LTC1052MN [Linear]
IC OP-AMP, 5 uV OFFSET-MAX, PDIP, 0.300 INCH, PLASTIC, DIP, Operational Amplifier;
| 型号： | LTC1052MN |
| 厂家： | 
Linear |
| 描述： | IC OP-AMP, 5 uV OFFSET-MAX, PDIP, 0.300 INCH, PLASTIC, DIP, Operational Amplifier 运算放大器 |
| 文件： | 总24页 (文件大小：846K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1052/LTC7652
Zero-Drift
Operational Amplifier
U
FEATURES
DESCRIPTIO
The LTC®1052 and LTC7652 are low noise zero-drift op
amps manufactured using Linear Technology’s enhanced
LTCMOSTM silicon gate process. Chopper-stabilization
constantlycorrectsoffsetvoltageerrors.Bothinitialoffset
and changes in the offset due to time, temperature and
common mode voltage are corrected. This, coupled with
picoampere input currents, gives these amplifiers
unmatched performance.
■
Guaranteed Max Offset: 5µV
■
Guaranteed Max Offset Drift: 0.05µV/°C
■
Typ Offset Drift: 0.01µV/°C
■
Excellent Long Term Stability: 100nV/√Month
■
Guaranteed Max Input Bias Current: 30pA
■
Over Operating Temperature Range:
Guaranteed Min Gain: 120dB
Guaranteed Min CMRR: 120dB
Guaranteed Min PSRR: 120dB
Low frequency (1/f) noise is also improved by the
chopping technique. Instead of increasing continuously
ata3dB/octaverate, theinternalchoppingcausesnoiseto
decrease at low frequencies.
■
Single Supply Operation: 4.75V to 16V
(Input Voltage Range Extends to Ground)
External Capacitors can be Returned to V– with No
■
Noise Degradation
The chopper circuitry is entirely internal and completely
transparent to the user. Only two external capacitors
are required to alternately sample-and-hold the offset
correction voltage and the amplified input signal. Control
circuitry is brought out on the 14-pin and 16-pin versions
to allow the sampling of the LTC1052 to be synchronized
with an external frequency source.
U
APPLICATIO S
■
Thermocouple Amplifiers
■
Strain Gauge Amplifiers
■
Low Level Signal Processing
■
Medical Instrumentation
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTCMOS is a trademark of Linear Technology Corporation.
Teflon is a trademark of DuPont.
U
TYPICAL APPLICATIO
Ultralow Noise, Low Drift Amplifier
Noise Spectrum
5V
160
140
120
100
80
3
7
+
6
LTC1052
2
8
–
4
1
0.1µF
0.1µF
0.1µF
–5V
5V
60
68k
5V
100k
3K
1
1.5k
3
2
5V
40
7
+
INPUT
8
LT®1007
OUTPUT
100k
20
6
–
4
– 5V
0
0
100
200
300
400
500
FREQUENCY (Hz)
V
V
OS = 3µV
OS∆T = 50nV/°C
100Ω
LTC1052/7652 • TA02
NOISE = 0.06µV 0.1Hz TO 10Hz
LTC1052/7652 • TA01
P-P
1052fa
1
LTC1052/LTC7652
W W
U W
ABSOLUTE AXI U RATI GS (Notes 1 and 2)
Total Supply Voltage (V+ to V–) ............................... 18V Operating Temperature Range
Input Voltage ........................ (V+ + 0.3V) to (V– – 0.3V)
Output Short Circuit Duration .......................... Indefinite
LTC1052C/LTC7652C ..........................–40°C to 85°C
LTC1052M (OBSOLETE).....................–55°C to 125°C
Storage Temperature Range .................. –55°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
EXTB
TOP VIEW
C
C
C
EXTB
INT/EXT
CLK IN
1
2
3
14
13
12
8
EXTA
+
C
V /CASE
1
EXTA
7
5
NC (GUARD)
CLK OUT
V+
–
+
– IN
+ IN
4
5
6
7
–
+
11
10
9
OUTPUT
2
6
– IN
OUTPUT
OUTPUT CLAMP
3
NC (GUARD)
V –
LTC1052 OUTPUT CLAMP
LTC7652 C
+ IN
4
RETURN
C
RETURN
8
–
V
N PACKAGE, 14-LEAD CERDIP
= 110°C, θ = 130°C/W
METAL CAN H PACKAGE
T
JMAX
JA
J PACKAGE, 14-LEAD CERDIP
OBSOLETE PACKAGE
OBSOLETE PACKAGE
Consider the N14 Package for Alternate Source
Consider the N8 Package for Alternate Source
ORDER PART NUMBER
LTC7652CH
REPLACES
ORDER PART NUMBER
REPLACES
ICL7652CTV
ICL7652ITV
ICL7650CTV-1
ICL7650ITV-1
ICL7650CTV
ICL7650ITV
ICL7650MTV
LTC1052CN
LTC1052CJ
LTC1052MJ
ICL7652CPD
ICL7650CPD
ICL7652IJD
ICL7650IJD
ICL7650MJD
LTC1052CH
LTC1052MH
TOP VIEW
TOP VIEW
C
1
2
3
4
5
6
7
8
16
EXTB
INT/EXT
CLK IN
C
C
EXTA
1
EXTB
8
7
6
15
14
13
12
11
10
9
C
EXTA
+
–
IN
–
+
V
2
3
CLK OUT
V+
NC (GUARD)
– IN
+ N
OUTPUT
OUTPUT
CLAMP
–
V
4
5
OUTPUT
OUTPUT CLAMP
+ IN
NC (GUARD)
V –
N8 PACKAGE
8-LEAD PDIP
C
RETURN
T
= 110°C, θ = 150°C/W
JMAX
JA
NC
NC
J8 PACKAGE, 8-LEAD CERDIP
SW PACKAGE
16-LEAD PLASTIC (WIDE) SO
OBSOLETE PACKAGE
T
= 110°C, θ = 150°C/W
JMAX JA
Consider the N8 Package for Alternate Source
ORDER PART NUMBER
REPLACES
ORDER PART NUMBER
LTC1052CSW
REPLACES
LTC1052CS
LTC1052CN8
LTC1052CJ8
LTC1052MJ8
ICL7650CPA
ICL7650IJA
Consult LTC Marketing for parts specified with wider operating temperature ranges.
1052fa
2
LTC1052/LTC7652
ELECTRICAL CHARACTERISTICS
The ■ denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, test circuit TC1, unless otherwise noted.
LTC1052M
TYP
LTC1052C/LTC7652C
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX MIN
TYP
MAX
UNITS
V
Input Offset Voltage
(Note 3)
(Note 3)
±0.5
±5
±0.5
±0.01
100
±5
µV
µV/°C
OS
∆V /∆Temp Average Input Offset Drift
■
±0.01 ±0.05
±0.05
OS
∆V /∆Time Long-Term Offset Voltage Stability
100
nV/√Month
OS
I
Input Offset Current
Input Bias Current
Input Noise Voltage
±30
±90
±2000
±30
±90
±350
pA
pA
OS
■
■
I
±1
±30
±1000
±1
±30
±175
pA
pA
B
e
R = 100Ω, DC to 10HZ, TC3
R = 100Ω, DC to 1HZ, TC3
S
1.5
0.5
1.5
0.5
µV
µV
nP-P
S
P-P
P-P
I
Input Noise Current
f = 10Hz (Note 5)
0.6
140
150
150
0.6
140
150
150
fA/√Hz
dB
n
–
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V
V
= V to 2.7V
■
■
■
■
120
120
120
120
120
CM
SUPPLY
= ±2.375V to ±8V
= ±4V
dB
A
V
R = 10k, V
OUT
120
dB
VOL
OUT
L
Maximum Output Voltage Swing
(Note 4)
R = 10k
±4.7 ±4.85
±4.95
±4.7
±4.85
±4.95
V
V
L
R = 100k
L
SR
Slew Rate
R = 10k, C = 50pF
4
4
V/µs
L
L
GBW
Gain Bandwidth Product
Supply Current
1.2
1.7
1.2
1.7
MHz
I
No Load
2.0
3.0
2.0
3.0
mA
mA
S
■
f
Internal Sampling Frequency
Clamp On Current
330
330
100
10
Hz
S
R = 100k
■
■
25
100
10
25
µA
L
Clamp Off Current
–4V < V
< 4V
100
2
100
1
pA
nA
OUT
Note 1: Absolute Maximum Ratings are those values beyond which the life
testing. V is measured to a limit determined by test equipment
OS
of a device may be impaired.
capability. Voltages on C
and C
, A , CMRR and PSRR are
EXTA
EXTB VOL
+
measured to insure proper operation of the nulling loop to ensure meeting
the V and V drift specifications. See Package-Induced V in the
Note 2: Connecting any terminal to voltages greater than V , or less than
–
V , may cause destructive latch-up. It is recommended that no sources
OS
OS
OS
Applications Information section.
Note 4: Output clamp not connected.
operating from external supplies be applied prior to power-up of the
LTC1052/LTC7652.
Note 3: These parameters are guaranteed by design. Thermocouple effects
1/2
Note 5: Current noise is calculated from the formula: i = (2q I ) , where
n
B
–19
preclude measurement of the voltage levels in high speed automatic
q = 1.6 • 10
coulomb.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input Noise Voltage
VS = ±5V, TEST CIRCUIT (TC3)
5µV
DC TO 1Hz
0
5µV
DC TO 10Hz
0
10 SEC.
1052fa
3
LTC1052/LTC7652
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Offset Voltage vs Sampling
Frequency
1OHzP-P Noise vs Sampling
Frequency
Input Bias Current vs
Temperature
1000
900
800
700
600
500
400
300
200
100
0
5
4
3
2
1
0
12
10
V
SUPPLY= ± 5V
V
SUPPLY= ±5V
GUARANTEED
8
6
4
2
0
GUARANTEED
100
1k
SAMPLING FREQUENCY, f (Hz)
10k
–50
0
25
50
75
125
0
500
1000
1500
2000
–25
100
SAMPLING FREQUENCY, f (Hz)
AMBIENT TEMPERATURE, T (°C)
S
S
A
LTC1052/7652 • TPC03
LTC1052/7652 • TPC01
LTC1052/7652 • TPC02
Common Mode Input Range vs
Supply Voltage
Overload Recovery
(Output Clamp Not Used)
Aliasing Error
8
6
VS = ±5V
AV = –1
VS = ±5V
TEST CIRCUIT TC2
4
2
0
– 2
– 4
– 6
– 8
–
V
= V
CM
50ms/DIV
OVERDRIVE
REMOVED
fI–fS
fS
fI
50Hz/DIV
A
V = –100
4
5
0
1
2
3
6
7
8
SUPPLY VOLTAGE (±V)
LTC1052/7652 • TPC04
Small-Signal Transient Response*
Large-Signal Transient Response*
Gain Phase vs Frequency
120
100
80
60
V = ± 5V
S
80
C = 100pF
L
100
120
140
160
180
200
220
PHASE
60
GAIN
40
20
0
AV = 1
2µs/DIV
AV = 1
2µs/DIV
–20
–40
RL = 10k
CL = 100pF
VS = ±5V
RL = 10k
CL = 100pF
VS = ±5V
3
4
5
6
100
10
10
10
10
107
*RESPONSE IS NOT DEPENDENT ON PHASE OF CLOCK
FREQUENCY (Hz)
LTC1052/LTC7652 • TPC06
1052fa
4
LTC1052/LTC7652
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Broadband Noise, CEXT = 0.1µF
Broadband Noise, CEXT = 1.0µF
Broadband Noise Test Circuit (TC2)
R2
1M
R1
5V
1k
2
7
–
6
R3
1k
LTC1052
3
8
+
4
1
C
C
EXTA
EXTB
AV = –1000
1ms/DIV
AV = –1000
1ms/DIV
– 5V
LTC1052/7652 • TPC07
Output Short-Circuit Current vs
Supply Voltage
Supply Current vs Supply Voltage
Supply Current vs Temperature
8
6
3.0
2.0
2.5
2.0
1.5
1.0
SUPPLY VOLTAGE = ± 5V
–
I
V
= V
SOURCE OUT
4
2
0
1.0
0
– 10
– 20
– 30
0.5
0
+
I
V
= V
SINK OUT
12
+
16
4
5
6
8
10
14
50
100 125
–50 –25
0
25
75
4
5
6
8
10
12
14
–
16
–
+
AMBIENT TEMPERATURE, T (°C)
TOTAL SUPPLY VOLTAGE, V TO V (V)
TOTAL SUPPLY VOLTAGE, V TO V (V)
A
LTC1052/LTC7652 • TPC08
LTC1052/LTC7652 • TPC10
LTC1052/LTC7652 • TPC09
Sampling Frequency vs
Temperature
Sampling Frequency vs Voltage
Comparator Operation
600
500
400
300
600
500
400
300
200
100
0
SUPPLY VOLTAGE = ± 5V
T
= 25°C
A
5V
5
1k
2
V
*
REF
–
7
6
LTC1052
1k
3
8
V
+
IN
4
1
0.1µF
0.1µF
200
100
0
* – 5V ≤ V
≤ 2.7V
– 5V
REF
LTC1052/7652 • TPC13
50
100 125
–50 –25
0
25
75
4
5
6
8
10
12
14
–
16
+
AMBIENT TEMPERATURE, T (°C)
TOTAL SUPPLY VOLTAGE, V TO V (V)
A
LTC1052/LTC7652 • TPC11
LT1052/LTC7652 • TPC12
1052fa
5
LTC1052/LTC7652
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Response Time vs Overdrive
VREF + OVERDRIVE
INPUT
{
VREF – 1mV
10µV
5V
50µV
5µV
OUTPUT
{
–5V
20ms/DIV
TEST CIRCUITS
Electrical Characteristics Test Circuit (TC1)
DC to 10Hz and DC to 1HZ Noise Test Circuit (TC3)
C2
C3
R2
1M
R2
R4
R1
1k
+
3
2
V
+
–
2
3
7
+
6
V
OUTPUT
(NOISE x 20,000)
–
C4
LT1001
34k
2
3
R3
6
7
OUTPUT
–
LTC1052
6
8
+
LTC1052
R1
R
4
L
8
1
+
4
1
0.1µF
0.1µF
34k
0.1µF
0.1µF
–
V
–
LTC1052/7652 • TC01
V
BANDWIDTH
10Hz
R1
16.2Ω
16.2Ω
R2
162k
162k
R3
16.2k
162k
R4
16.2k
162k
C2
0.1µF
1.0µF
C3
1.0µF
1.0µF
C4
1.0µF
1.0µF
1Hz
LTC1052/7652 • TC02
U
THEORY OF OPERATIO
DC OPERATION
The shaded portion of the LTC1052 block diagram
(Figure 1a) entirely determines the amplifier’s DC
characteristics. During the auto zero portion of the cycle,
the gm1 inputs are shorted together and a feedback path is
closed around the input stage to null its offset. Switch S2
and capacitor CEXTA act as a sample-and-hold to store the
nulling voltage during the next step—the sampling cycle.
stage. CEXTB and S2 act as a sample-and-hold to store the
amplified input signal during the auto zero cycle.
By switching between these two states at a frequency
much higher than the signal frequency, a continuous
output results.
Notice that during the auto zero cycle the gm1 inputs are
not only shorted together, but are also shorted to the
invertinginput.Thisforcesnullingwiththecommonmode
voltage present and accounts for the extremely high
In the sampling cycle, the zeroed amplifier is used to
amplify the differential input voltage. Switch S2 connects
the amplified input voltage to CEXTB and the output gain
CMRR of the LTC1052. In the same fashion, variations in
1052fa
6
LTC1052/LTC7652
U
THEORY OF OPERATIO
power supply are also nulled. For nulling to take place, the
offset voltage, common mode voltage and power supply
must not change at a frequency which is high compared to
the frequency response of the nulling loop.
For frequencies above this pole, I2 is:
1
SC2
I2 = VIN gm6
•
• SC1
and
C1
C2
I1 – I2 = VIN gm1 – VIN gm6
•
AC OPERATION AND ALIASING ERRORS
The LTC1052 is very carefully designed so that gm1 = gm6
and C1 = C2. Substituting these values in the above equa-
tion shows I1 – I2 = 0.
So far, the DC performance of the LTC1052 has been
explained. As the input signal frequency increases, the
problem of aliasing must be addressed. Aliasing is the
spurious formation of low and high frequency signals
caused by the mixing of the input signal with the sampling
frequency, fS. The frequency of the error signals, fE, is:
The gm6 input stage, with Cl and C2, not only filters the
input to the sampling loop, but also acts as a high
frequency path to give the LTC1052 good high frequency
response. The unity-gain cross frequencies for both the
DC path and high frequency path are identical
fE = fS ±fI
where fI = input signal frequency.
1
2π
1
2π
[f3dB =
(gm1/C1) =
(gm6/C2)]
Normally it is the difference frequency (fS – fI ) which is of
concern because the high frequency (fS + fI) can be easily
filtered. As the input frequency approaches the sampling
frequency, the difference frequency approaches zero and
willcauseDCerrors—theexactproblemthatthezero-drift
amplifier is meant to eliminate.
thereby making the frequency response smooth and con-
tinuous while eliminating sampling noise in the output as
the loop transitions from the high gain DC loop to the high
frequency loop.
The typical curves show just how well the amplifier works.
The output spectrum shows that the difference frequency
(fI–fS = 100Hz) is down by 80dB and the frequency
response curve shows no abnormalities or perturbations.
Also note the well-behaved small and large-signal step
responses and the absence of the sampling frequency in
the output spectrum. If the dynamics of the amplifier
(i.e., slew rate and overshoot), depend on the sampling
clock, the sampling frequency will appear in the output
spectrum.
Thesolutionissimple;filtertheinputsothesamplingloop
never sees any frequency near the sampling frequency.
At a frequency well below the sampling frequency, the
LTC1052 forces I1 to equal I2 (see Figure 1b). This makes
δ l zero, thus the gain of the sampling loop zero at this and
higher frequencies (i.e., a low pass filter). The corner
frequency of this low pass filter is set by the output stage
pole (1/RL4 gm5 RL5 C2).
C1
S3
V
REF
C2
+ IN
– IN
S2
S1
+
–
–
–
–
+
g
g
m2
g
+
g
+
V
m1
m5
m4
OUT
R
R
L2
C
C
L1
EXT B
R
R
L4
L5
EXT A
V
NULL
g
m3
V –
–
g
m6
LTC1052/7652 • TPC13
+
Figure 1a. LTC1052 Block Diagram
Auto Zero Cycle
1052fa
7
LTC1052/LTC7652
U
THEORY OF OPERATIO
C1
S3
V
REF
C2
R
l
2
+ IN
– IN
S2
S1
+
–
δl
–
+
–
–
g
g
m2
g
g
+
V
+
m1
m5
m4
OUT
l
R
R
L2
1
L1
C
EXT B
R
L4
L5
C
EXT A
g
m3
–
V
–
l
3
LTC1052/7652 • TO02
g
m6
+
Figure 1b. LTC1052 Block Diagram
Sampling Cycle
W U U
U
APPLICATIO S I FOR ATIO
EXTERNAL CAPACITORS
CEXTA and CEXTB are the holding elements of a sample-
and-hold circuit. The important capacitor characteristics
are leakage current and dielectric absorption. A high
qualityfilm-typecapacitorsuchasmylarorpolypropylene
provides excellent performance. However, low grade
capacitors such as ceramic are suitable in many
applications.
On competitive devices, connecting CEXTA and CEXTB to
V–causesanincreaseinamplifiernoise.Designchanges
have eliminated this problem on the LTC1052. On the
14-pin LTC1052 and 8-pin LTC7652, the capacitors can
be returned to V– or CRETURN with no change in noise
performance.
ACHIEVING PICOAMPERE/MICROVOLT PERFORMANCE
Picoamperes
Capacitors with very high dielectric absorption (ceramic)
can take several seconds to settle after power is first
turned on. This settling appears as clock ripple on the
output and, as the capacitor settles, the ripple gradually
disappears. If fast settling after power turn-on is
important, mylar or polypropylene is recommended.
In order to realize the picoampere level of accuracy of the
LTC1052, proper care must be exercised. Leakage
currents in circuitry external to the amplifier can
significantlydegradeperformance. Highqualityinsulation
should be used (e.g., Teflon, Kel-F); cleaning of all
insulating surfaces to remove fluxes and other residues
will probably be necessary—particularly for high
temperature performance. Surface coating may be
necessary to provide a moisture barrier in high humidity
environments.
Above 85°C, leakage, both from the holding capacitors
and the printed circuit board, becomes important. To
maintain the capabilities of the LTC1052 it may be
necessary to use Teflon™ capacitors and Teflon standoffs
when operating at 125°C (see Achieving Picoampere/
Microvolt Performance).
CEXTA and CEXTB are normally in the range of 0.1µF
to 1.0µF. All specifications are guaranteed with 0.1µF and
the broadband noise (refer to Typical Performance Char-
acteristics) is only very slightly degraded with 0.1µF.
Output clock ripple is not present for capacitors of 0.1µF
or greater at any temperature.
Board leakage can be minimized by encircling the input
connections with a guard ring operated at a potential
close to that of the inputs: in inverting configurations, the
guard ring should be tied to ground; in noninverting
Teflon is a trademark of Dupont.
1052fa
8
LTC1052/LTC7652
W U U
APPLICATIO S I FOR ATIO
U
connections, to the inverting input. Guarding both sides
of the printed circuit board is required. Bulk leakage
reduction depends on the guard ring width.
Figure 2 is an example of the introduction of an
unnecessary resistor to promote differential thermal
balance. Maintaining compensating junctions in close
physicalproximitywillkeepthematthesametemperature
and reduce thermal EMF errors.
NOMINALLY UNNECESSARY
RESISTOR USED TO
LEAD WIRE/SOLDER/COPPER
THERMALLY BALANCE OTHER
TRACE JUNCTION
INPUT RESISTOR
+
OUTPUT
LTC1052
–
RESISTOR LEAD, SOLDER,
COPPER TRACE JUNCTION
Microvolts
ThermocoupleeffectsmustbeconsiderediftheLTC1052’s
ultralow drift is to be fully utilized. Any connection
of dissimilar metals forms a thermoelectric junction
producing an electric potential which varies with
temperature (Seebeck effect). As temperature sensors,
thermocouples exploit this phenomenon to produce
useful information. In low drift amplifier circuits the effect
is a primary source of error.
LTC1052/7652 • AI03
Figure 2
When connectors, switches, relays and/or sockets are
necessary they should be selected for low thermal EMF
activity. The same techniques of thermally balancing and
coupling the matching junctions are effective in reducing
the thermal EMF errors of these components.
Connectors, switches, relay contacts, sockets, resistors,
solder, and even copper wire are all candidates for
thermal EMF generation. Junctions of copper wire from
different manufacturers can generate thermal EMFs of
200nV/°C—4 times the maximum drift specification of
the LTC1052. The copper/kovar junction, formed when
wire or printed circuit traces contact a package lead, has
a thermal EMF of approximately 35µV/°C–700 times the
maximum drift specification of the LTC1052.
Resistors are another source of thermal EMF errors.
Table 1 shows the thermal EMF generated for different
resistors. The temperature gradient across the resistor is
important, not the ambient temperature. There are two
junctions formed at each end of the resistor and if these
junctions are at the same temperature, their thermal EMFs
will cancel each other. The thermal EMF numbers are
approximate and vary with resistor value. High values give
higher thermal EMF.
Minimizing thermal EMF-induced errors is possible if
judicious attention is given to circuit board layout and
component selection. It is good practice to minimize the
number of junctions in the amplifier’s input signal path.
Avoid connectors, sockets, switches and relays where
possible. In instances where this is not possible, attempt
to balance the number and type of junctions so that
differential cancellation occurs. Doing this may involve
deliberately introducing junctions to offset unavoidable
junctions.
Table 1. Resistor Thermal EMF
RESISTOR TYPE
Tin Oxide
THERMAL EMF/°C GRADIENT
~mV/’C
Carbon Composition
Metal Film
~450µV/°C
~20µV/°C
Wire Wound
Evenohm
Manganin
~2µV/°C
~2µV/°C
1052fa
9
LTC1052/LTC7652
W U U
U
APPLICATIO S I FOR ATIO
When all of these errors are considered, it may seem
impossible to take advantage of the extremely low drift
specifications of the LTC1052. To show that this is not the
case, examine the temperature test circuit of Figure 3. The
lead lengths of the resistors connected to the amplifier’s
inputs are identical. The thermal capacity and thermal
resistance each input sees is balanced because of the
symmetrical connection of resistors and their identical
size. Thermal EMF-induced shifts are equal in phase and
amplitude, thus cancellation occurs.
Figure 4 shows the response of this circuit under
temperature transient conditions. Metal film resistors and
an 8-pin DIP socket were used. Care was taken in the
construction to thermally balance the inputs to the
amplifier. The units were placed in an oven and allowed to
stabilize at 25°C. The recording was started and after
100 seconds the oven, preset to 125°C, was switched on.
The test was first performed on an 8-pin plastic package
andthenwasrepeatedforaTO-5packagepluggedintothe
same test board. It is significant that the change in VOS,
even under these severe thermal transient conditions,
is quite good. As temperature stabilizes, note that the
steady-state change of VOS is well within the maximum
±0.05µV/°C drift specification.
50k
5V
2
3
7
4
–
6
100Ω
LTC1052
8
+
Very slight air currents can still affect even this
arrangement. Figure 5 shows strip charts of output noise
bothwiththecircuitcoveredandwithnocoverin“still”air.
This data illustrates why it is often prudent to enclose the
LTC1052 and its attendant components inside some form
of thermal baffle.
V
• 1000
OS
1
0.1µF
50k
0.1µF
0.1µF
–5V
LTC1052/7652 • AI04
Figure 3. Offset Drift Test Circuit
0 MIN
5 MIN
20 MIN
25 MIN
10
0
25°C TO 125°C
PLASTIC
±0.05µV/°C
10
0
25°C TO 125°C
METAL CAN
±0.05µV/°C
OVEN SWITCHED
ON (25°C)
OVEN STABILIZED
AT 12 MIN
100 SECONDS/IN
Figure 4. Transient Response of Offset Drift Test Circuit with 100°C Temperature Step
1052fa
10
LTC1052/LTC7652
W U U
APPLICATIO S I FOR ATIO
U
#1 COVERED
1µV
#1 UNCOVERED
#2 UNCOVERED
20 SEC
Figure 5. DC to 1Hz (Test Circuit TC3)
PACKAGE-INDUCED OFFSET VOLTAGE
CLOCK
Since the LTC1052 is constantly fixing its own offset, it
may be asked why there is any error at all, even under
transient temperature conditions. The answer is simple.
The LTC1052 can only fix offsets inside its own nulling
loop. There are many thermal junctions outside this loop
that cannot be distinguished from legitimate signals.
The LTC1052 has an internal clock, setting the nominal
sampling frequency at 330Hz. On 8-pin devices, there is
no way to control the clock externally. In some applica-
tions it may be desirable to control the sampling clock and
this is the function of the 14-pin device.
CLK IN, CLK OUT and INT/EXT are provided to accomplish
this.Withnoexternalconnection,aninternalpull-upholds
INT/EXT at the V+ supply and the 14-pin device self-
oscillates at 330Hz. In this mode there is a signal on the
CLK IN pin of 660Hz (2 times sampling frequency) with a
30% duty cycle. A divide-by-two drives the CLK OUT pin
and sets the sampling frequency.
To use an external clock, connect INT/EXT to V– and the
external clock to CLK IN. The logic threshold of CLK IN is
2.5V below the positive supply; this allows CMOS logic to
drive it directly with logic supplies of V+ and ground. CLK
IN can be driven from V+ to V– if desired. The duty cycle of
the external clock is not particularly critical but should be
kept between 30% and 60%.
Some have been discussed previously, but the package
thermal EMF effects are an important source of errors.
Notice the difference in the thermal response curves of
Figure 4. This can only be attributed to the package since
everything else is identical. In fact, the VOS specification is
set by the package-induced warm-up drift, not by the
LTC1052. TO-99 metal cans exhibit the worst warm-up
drift and Linear Technology sample tests TO-99 lots to
minimize this problem.
Two things make 100% screening costly: (1) The extreme
precision required on the LTC1052 and (2) the thermal
time constant of the package is 0.5 to 3 minutes, depend-
ing on package type. The first precludes the use of auto-
matic handling equipment and the second takes a long
time. Bench test equipment is available to 100% test for
warmed-up drift if offsets of less than ±5µV are required.
Capacitance between CLK IN and CLK OUT (pins 13 and
12) can cause the divide-by-two circuit to malfunction. To
avoid this, keep this capacitance below 5pF.
1052fa
11
LTC1052/LTC7652
W U U
U
APPLICATIO S I FOR ATIO
OUTPUT CLAMP
within approximately 1V of either supply rail. This switch
is in parallel with the amplifier’s feedback resistor. As the
output moves closer to the rail, the switch on
resistance decreases, reducing the closed loop gain. The
output swing is reduced when the clamp function is used.
If the LTC1052 is driven into saturation, the nulling loop,
attempting to force the differential input voltage to zero,
will drive CEXTA and CEXTB to a supply rail. After the
saturating drive is removed, the capacitors take a finite
time to recover—this is the overload recovery time. The
overload recovery is longest when the capacitors are
driven to the negative rail (refer to Overload Recovery in
the Typical Performance Characteristics section). The
overload recovery time in this case is typically 225ms. In
the opposite direction (i.e., CEXTA and CEXTB at positive
rail), it is about ten times faster (25ms). The overload
recovery time for the LTC1052 is much faster than com-
petitive devices; however, if a faster overload recovery
time is necessary, the output clamp function can be used.
How much current the output clamp leaks when off
is important because, when used, it is connected to the
amplifier’s negative input. Any current acts like input bias
current and will degrade accuracy. At the other extreme,
the maximum current the clamp conducts when on deter-
mines how much overdrive the clamp will take, and still
keep the amplifier from saturating. Both of these numbers
are guaranteed in the Electrical Characteristics section.
LOW SUPPLY OPERATION
The minimum supply voltage for proper operation of the
LTC1052 is typically 4.0V (±2.0V). In single supply
applications, PSRR is guaranteed down to 4.7V (±2.35V).
This assures proper operation down to the minimum TTL
specified voltage of 4.75V.
When the output clamp is connected to the negative input
it prevents the amplifier from saturating, thus keeping
CEXTA and CEXTB at their nominal voltages. The output
clamp is a switch that turns on when the output gets to
U
TYPICAL APPLICATIO S
5V Powered Ultraprecision Instrumentation Amplifier
Fast Precision Inverter
5V
5V
10k*
10k*
8pF
4
INPUT
3
2
7
+ IN
7
8
+
6
10k
V
LTC1052
OUT
8
–
11
12
1
1N4148
4
C1
C2
0.1µF
1µF
1µF
0.1µF
R2
100k
1000pF
300pF
R1
100
5V
2
3
13
6
7
– IN
5V
14
5
5V
7
+
–
6
2
3
LTC1043
0.22µF
+
OUTPUT
LT318A
6
LTC1052
4
10k
43k
8
10k
–
4
–5V
1
+
2
C4
1µF
10k
0.1µF
0.1µF
C3
1µF
1N914
3
– 5V
*1% METAL FILM
FULL POWER BANDWIDTH = 2MHz
≈ – 0.5V
18
17
15
16
SLEW RATE = 40V/µs
SETTLING (10V STEP) = 12µs TO 0.01%
BIAS CURRENT DC = 30pA
OFFSET DRIFT = 50nV/°C
0.0047µF
CIRCUITRY WITHIN DASHED LINES MAY BE DELETED IF OUTPUT
DOES NOT HAVE TO SWING ALL THE WAY TO GROUND
DRIFT = 50nV/°C
OFFSET VOLTAGE = 5µV
LTC1052/7652 • TA04
V
= 3µV
OS
R2
GAIN =
+ 1
R1
CMRR = >120dB DC – 20kHz
BANDWIDTH = 10Hz
LTC1052/7652 • TA03
1052fa
12
LTC1052/LTC7652
U
TYPICAL APPLICATIO S
Offset Stabilized Comparator
5V
4
5V
+
14
13
330Ω 150Ω
2k
8
2
3
+
–
12
11
6
COMPARATOR
INPUTS
7
COMPARATOR
OUTPUT (± 5V)
LT1011
5
1
4
10k
– 5V
1µF
8
5
7
6
–
GROUND OR
INPUT COMMON-
MODE VOLTAGE
5V
7
LTC1043
1M
2
3
+
6
LTC1052
8
–
4
2
3
1
0.1µF
0.1µF
– 5V
STATUS OUTPUT
OV = ZERO
5V
15
16
18
5V = COMPARE
ZERO COMMAND
5V = ZERO
– 5V = COMPARE
17
–5V
LTC1052/7652 • TA05
1HZ to 1.25MHz Voltage-to-Frequency Converter (5V Supply)
470Ω
5V
0.01µF
470Ω
10k
3
2
7
+
6
3.3k
Q1
2N2907
NC
2N3904
LTC1052
8
–
4
1
5V
74C04
330pF
0.1µF
0.1µF
10k
OUTPUT
1H to 1.25MHz
0.01µF
10k
5V
2k
3.3pF
FULL-SCALE TRIM
(1.25MHz)
5V
30.1k*
V
IN
OV TO 5V
10k
4
8
7
0.22µF
11
12
LT1004-1.2V
100pF**
0.1µF
*TRW MTR–5/ +1200ppm/°C
**POLYSTYRENE–WESCO #32–P/ – 120ppm/°C
± 0.05%
>120dB
0.01Hz/°C
20ppm/°C
LINEARITY
14
13
16
DYNAMIC RANGE
ZERO POINT DRIFT
GAIN DRIFT
1/2
LTC1043
17
LTC1052/7652 • TA06
1052fa
13
LTC1052/LTC7652
U
TYPICAL APPLICATIO S
No VOS Adjust* CMOS DAC Buffer—Single Supply
Air Flow Detector
15V
C *
F
10k
5V
5
15V
R
1k
FB
2
3
l
OUT1
+
7
100k
± 1%
6
12–BIT CMOS DAC
V
LTC1052
OUT
5
8
2
3
l
–
FOR HIGHER SPEED, REFER TO
“FAST PRECISION INVERTER”
UNDER TYPICAL APPLICATIONS
OUT2
+
4
7
1k
6
5V = NO AIR FLOW
0V = AIR FLOW
1
LT1004-1.2
LTC1052
15V
4
0.1µF
0.1µF
8
–
43.2Ω
± 1%
4
1
43k
0.1µF
0.1µF
6
5
–
AMBIENT
TEMPERATURE
STILL AIR
–
+
10k
240Ω
TYPE K
+
LTC1052/7652 • TA08
11
+
1µF
1N914
0.1µF
NON POLARIZED
*OFFSET VOLTAGE CAUSES
NONLINEARITY ERRORS.
SEE: “APPLICATION GUIDE
TO CMOS MULTIPLYING D/A
CONVERTERS,”
AIR FLOW
12
≈ – 0.5V
ANALOG DEVICES, INC.
LTC1052/7652 • TA07
1pF
1/2
16
LTC1043
17
1Hz to 30MHz Voltage-to-Frequency Converter
5V
120Ω
CURRENT
12k
SOURCE
STABILIZING
AMP
0.1µF
120Ω
3
7
+
7.5k
6
2N3906
LTC1052
2
8
NC
–
FET BUFFER
2N5486
4
1
RESET DIODE
2N3904
1Hz TO 30MHz
OUTPUT
0.1µF
0.1µF
5V
100pF
50Ω
74S132
0.0.1µF
– 5V
OUT
2k
30MHz
TRIM
2N5486
10k
0.22µF
16.2k*
5V
5V
IN
TRIGGER
HP5082-2810
50Ω
CHARGE
PUMP
OV TO 3V
2k
– 5V
8
7
100k
1000M
11
LT1004–1.2V
10k
1Hz TRIM
†
100pF
0.22µF
100k
– 5V
10
12
*TRW MTR-5/ + 120ppm/°C
†WESCO #32-P/ – 120ppm/°C
0.3Hz/°C ZERO-DRIFT
±0.08% LINEARITY
20ppm/°C GAIN DRIFT
150dB DYNAMIC RANGE
13
16
5V
5
5V
14
11
3
14
5
1/2
LTC1043
1/2 74S74
7
7490
10
12
1
LTC1052/7652 • TA09
1052fa
14
LTC1052/LTC7652
U
TYPICAL APPLICATIO S
±100mA Output Drive
Increasing Output Current
5V
100k
220pF
V
IN
74C04
5V
5V
100pF
1M
V
2
3
7
–
5V
10k
6
2
3
7
LTC1010
LTC1052
INPUT
–
OUT
8
OUTPUT
6
LTC1052
+
4
±100mA
8
1
+
– 5V
4
R
L
1
0.1µF
0.1µF
0.1µF
0.1µF
– 5V
100k
LOAD OUTPUT SWING
V
V
= 5µV
/∆T = 50µV/°C
OS
OS
100Ω
2000pF
GAIN = 10
10k
5k
2.5k
1k
± 4.92V
± 4.84V
± 4.65V
± 3.65V
FULL POWER BANDWIDTH = 1kHz
LTC1052/7652 • TA10
220Ω
LTC1052/7652 • TA11
Single 5V Thermocouple Amplifier with Cold Junction Compensation
5V
+
V
T
–
1k
100k
R1
LT1004-1.2
5V
4
1690Ω
†
5k AT 25°C
5V
3
2
7
7
8
–
6
R
R
F
V
= V 1 +
LTC1052
OUT
T
(
)
1820Ω
187Ω
l
8
+
4
11
12
1
1µF
1µF
0.1µF
0.1µF
R
C *
F
F
13
6
14
5
43k
5V
R
l
2
+
1µF
IN914
1µF
NONPOLARIZED
3
10k
≈ – 0.5V
18
16
15
LTC1052/7652 • TA12
THERMOCOUPLE
TYPE
R1
LTC1043
17
†
J
K
T
S
232k
301k
301k
2.1M
YELLOW SPRINGS INST. CO. PART #44007
*CHOOSE C TO FILTER NOISE
0.0047µF
F
1052fa
15
LTC1052/LTC7652
U
TYPICAL APPLICATIO S
Increasing Output Current and Voltage (VSUPPLY = ±15V)
DC Stabilized FET Probe
INPUT CAPACITANCE BOOTSTRAP
5V
FAST SOURCE
FOLLOWER
Q1
2N5486
INPUT
7V
2N3904
5V
15V
30k
6
33pF
1N4148
0.1µF
3k
NC
2
3
7
INPUT
LT1010
– 5V
OUTPUT
10M
–
3
6
7
LT318A
4
LTC1052
+
–
V+
10M
8
OUTPUT
±12V AT 20mA | LIMIT
+
7
4
3
2
DRAIN CURRENT SINK
10k
Q2
+
2
1
6
3k
0.1µF
LTC1052
0.1µF
0.1µF
2N2222
8
0.01µF
–
1
2N3904
NC
4
100Ω
–15V
– 7V
1k
0.1µF
0.1µF
0.1µF
– 5V
2000pF
DC STABILIZATION
STABLE FOR ALL GAINS, INVERTING
AND NONINVERTING, OBSERVE
LTC1052 COMMON MODE INPUT LIMITS
LTC1052/7652 • TA13
BANDWIDTH: 20MHz
: 100ns
1k
0.1µF
†
RISE
DELAY: 5ns
LTC1052/7652 • TA14
Precision Multiplexed Differential Thermocouple Amplifier
5V
COLD JUNCTION
COMPENSATOR
100k
4
R1
LT1004–1.2V
3
7
–
7
8
6
LTC1052
V
= 1001 • V
THERMOCOUPLE
OUT
5k AT
25°C
8
2
†
+
4
11
12
1690Ω
187Ω
1
1µF
1µF
0.1µF
0.1µF
0.1µF
1820Ω
1M
1k
– 5V
13
6
14
5
5V
16
12
13
3
2
3
1µF
1µF
1
†
14
5
YELLOW SPRINGS INST. CO. PART #44007
18
16
15
LTC1043
THERMOCOUPLE
TYPE
R1
15
2
J
K
T
S
232k
301k
301k
2.1M
0.0047µF
17
– 5V
11
4
9
ADDRESS
10
8
7
CD4052B
– 5V
LTC1052/7652 • TA15
1052fa
16
LTC1052/LTC7652
U
TYPICAL APPLICATIO S
Direct Thermocouple-to-Frequency Converter
R
T
COLD JUNCTION TEMPERATURE TRACKING
1N4148
–
+
TYPE K
THERMOCOUPLE 41.4µV/°C
STABILIZING AMP
470Ω
1.8k*
5V
7
3
+
A
10k
B
C
E
33k
D
6
LTC1052
1N914
100k
2
74C04
8
–
4
0.68µF
1µF
1
0.1µF
0.1µF
OPTIONAL INPUT
820pF
FILTER-AND-OVERLOAD
CLAMP
– 5V
3300pF
150k**
5V
5V
50k
60°C TRIM
74C04
OUTPUT
F
0Hz TO 600Hz
0°C TO 60°C
5V
16
– 5V
33k**
3k
†
74C903
A
LTC1043
4.75k*
1k*
5
6
1µF
*0.01% FILM-TRW MAR-6
**TRW/MTR/5/ + 120
0.1µF
LT1004–1.2V
2
R
= YELLOW SPRINGS INST. #44007
T
100pF = POLYSTYRENE
100pF
†
FOR GENERAL PURPOSE (1mV FULL-SCALE)
10-BIT A-TO-D, REMOVE THERMOCOUPLE—
COLD JUNCTION NETWORK, GROUND POINT A,
AND DRIVE LTC1052 POSITIVE INPUT
COLD JUNCTION BIAS
487Ω*
301k*
187Ω*
LTC1052/7652 • TA16
Direct 10-Bit Strain Gauge Digitizer
5V
74C00
5V
1000pF
1
– 5V
20Ω
STRAIN GAUGE
TRANSDUCER
28k
14k
CLOCK
0.003µF
20Ω
5V
Z
Z
= 350Ω
3
2
IN
+
= 350Ω
OUT
8
1k
6
INTEGRATOR
5V
LM301A
2N2905
5V
1000pF
FREQUENCY
OUT B
4
–
2
3
7
–
10k
5V
14
1
4 3
7
– 5V
1/2 74C903
470k*
6
2
5
LTC1052
1/2 74C74
5V
8
+
FREQUENCY
OUT A
7
6
4
1
3.3MΩ*
1/2 LTC1043
– 5V
– 5V
OUTPUT
GATING
0.01µF
0.01µF
BRIDGE DRIVE
7
8
– 5V
OUT A
OUT B
SW1
= 1000 COUNTS FULL-SCALE
DATA OUTPUT =
1N4148
1N4148
*0.1% METAL FILM TRW MAR-5
SW1 = MAIN CURRENT SWITCH
SW2 = CURRENT LOADING COMPENSATION SWITCH
11
12
16
14
– 5V
3.3M
CONNECT DIRECTLY
ACROSS BRIDGE
DRIVE POINTS
100k
SW2
CONNECT TO BRIDGE
END OF 470k RESISTOR
13
10k
(OPTIONAL)
TRANSDUCER ZERO NETWORK
LTC1052/7652 • TA17
+
22.3k*
33µF
1k*
1052fa
17
LTC1052/LTC7652
U
TYPICAL APPLICATIO S
16-Bit A/D Converter
74C00
5V
28k
14k
CLOCK
820pF
0.01µF
B
OUT
10k
5V
5V
7
1/3 74C903
95k*
E
2
IN
–
14
1
4 2
OV TO 5V
10pF
6
2
10k
FULL-SCALE
TRIM
5V
LTC1052
1/2 74C74
3
A2
+
1
A
OUT
7
5 6
8
INTEGRATOR
4
– 5V
0.1µF
0.1µF
5V
5V
– 5V
1k
16
13
4
3
7
14
+
6
2N4338
LTC1052
2
8
–
1
12
11
4
1µF
0.01µF
39pF
LT1009
0.1µF
0.1µF
– 5V
20k
75k*
7
8
LINEARITY
TRIM
18
15
CURRENT SINK
– 5V
3
A
B
OUT
OUT
DATA OUTPUT =
LTC1043
17
100,000 COUNTS FULL-SCALE
NO ZERO TRIM
20ppm/°C GAIN DRIFT
*VISHAY S-102 RESISTOR
– 5V
LTC1052/7652 • TA18
CURRENT SWITCH
1052fa
18
LTC1052/LTC7652
U
TYPICAL APPLICATIO S
Precision Isolation Amplifier
1k*
INPUT SIDE OUTPUT SIDE
10k
74C04
10k
20k
ZERO TRIM
– 15V
15V
4
4
5
1
–
+
100k*
2N5434
2N5434
30pF
2N5434
22M
1
100k
LTC1052
14–PIN
10
3
2
2
L2
+
8
2
6
STANCOR PCT-39
OUT
7
1000pF
LTC1052
4
1
–
5
2N5434
3
1k GAIN TRIM
INPUT
14
7
– 15V
6
100k
0.1µF
0.1µF
15V
13
10k
13.3k*
10k*
11
5
5
74C04
10k
IN4148
14 11
14
11
74C90
÷10
74C90
÷10
100pF
10M
2k
2k
(SELECT)
12
12
10
10
1
1
330Ω
15V
1.8k
68pF
1N4148 1N4148
NC
2N3904
1k
– 15V
25mA
7
1
74C04
2.2µF
+
FLOATING
SUPPLY
OUTPUTS
2N2222
2N3904
NC
L1
11k
POWER
DALE TC–10–11
8
DRIVER
2
– 15V
15V
25mA
20k
1000pF
1N4148
15V
+
4.3k
2.2µF
20k
FLOATING COMMON
68pF
1k
2N2222
9
3
LTC1052/7652 • TA19
1.8k
15V
250V ISOLATION
0.03% ACCURACY
*1% FILM RESISTOR
1052fa
19
LTC1052/LTC7652
U
PACKAGE DESCRIPTIO
H Package
8-Lead TO-5 Metal Can (.200 Inch PCD)
(Reference LTC DWG # 05-08-1320)
.335 – .370
(8.509 – 9.398)
DIA
.305 – .335
(7.747 – 8.509)
.040
(1.016)
MAX
.050
(1.270)
MAX
.165 – .185
(4.191 – 4.699)
REFERENCE
PLANE
SEATING
PLANE
GAUGE
PLANE
.500 – .750
(12.700 – 19.050)
.010 – .045*
(0.254 – 1.143)
.016 – .021**
(0.406 – 0.533)
.027 – .045
(0.686 – 1.143)
PIN 1
45°TYP
.028 – .034
(0.711 – 0.864)
.200
(5.080)
TYP
.110 – .160
(2.794 – 4.064)
INSULATING
STANDOFF
*LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE
AND THE SEATING PLANE
.016 – .024
(0.406 – 0.610)
**FOR SOLDER DIP LEAD FINISH, LEAD DIAMETER IS
H8(TO-5) 0.200 PCD 0801
OBSOLETE PACKAGE
1052fa
20
LTC1052/LTC7652
U
PACKAGE DESCRIPTIO
J Package
14-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
.785
(19.939)
MAX
.005
(0.127)
MIN
14
13
12
11
10
9
8
.220 – .310
.025
(5.588 – 7.874)
(0.635)
RAD TYP
2
3
4
5
6
1
7
.200
(5.080)
MAX
.300 BSC
(7.62 BSC)
.015 – .060
(0.381 – 1.524)
.008 – .018
(0.203 – 0.457)
0° – 15°
.045 – .065
(1.143 – 1.651)
.100
(2.54)
BSC
.125
(3.175)
MIN
.014 – .026
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
(0.360 – 0.660)
J14 0801
OBSOLETE PACKAGE
1052fa
21
LTC1052/LTC7652
U
PACKAGE DESCRIPTIO
J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
.405
(10.287)
MAX
CORNER LEADS OPTION
(4 PLCS)
.005
(0.127)
MIN
6
5
4
8
7
2
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION
.025
(0.635)
RAD TYP
.220 – .310
(5.588 – 7.874)
.045 – .068
(1.143 – 1.650)
FULL LEAD
OPTION
1
3
.200
.300 BSC
(5.080)
MAX
(7.62 BSC)
.015 – .060
(0.381 – 1.524)
.008 – .018
(0.203 – 0.457)
0° – 15°
.045 – .065
(1.143 – 1.651)
.125
3.175
MIN
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
.014 – .026
(0.360 – 0.660)
.100
(2.54)
BSC
J8 0801
OBSOLETE PACKAGE
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.400*
(10.160)
MAX
8
7
6
5
4
.255 ± .015*
(6.477 ± 0.381)
1
2
3
.130 ± .005
.300 – .325
.045 – .065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
.065
(1.651)
TYP
.008 – .015
(0.203 – 0.381)
.120
.020
(0.508)
MIN
(3.048)
MIN
+.035
.325
–.015
.018 ± .003
(0.457 ± 0.076)
.100
(2.54)
BSC
+0.889
8.255
(
)
N8 1002
–0.381
NOTE:
INCHES
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
1052fa
22
LTC1052/LTC7652
U
PACKAGE DESCRIPTIO
N Package
14-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.770*
(19.558)
MAX
14
13
12
11
10
9
8
7
.255 ± .015*
(6.477 ± 0.381)
1
2
3
5
6
4
.300 – .325
(7.620 – 8.255)
.045 – .065
(1.143 – 1.651)
.130 ± .005
(3.302 ± 0.127)
.020
(0.508)
MIN
.065
(1.651)
TYP
.008 – .015
(0.203 – 0.381)
+.035
.325
.005
(0.125)
MIN
–.015
.120
(3.048)
MIN
.018 ± .003
(0.457 ± 0.076)
.100
(2.54)
BSC
+0.889
8.255
(
)
–0.381
NOTE:
INCHES
MILLIMETERS
N14 1002
1. DIMENSIONS ARE
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
1052fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC1052/LTC7652
U
PACKAGE DESCRIPTIO
SW Package
16-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
.050 BSC .045 ±.005
.030 ±.005
.398 – .413
(10.109 – 10.490)
NOTE 4
TYP
15 14
12
10
9
N
16
N
13
11
.325 ±.005
.420
MIN
.394 – .419
(10.007 – 10.643)
NOTE 3
N/2
8
1
2
3
N/2
RECOMMENDED SOLDER PAD LAYOUT
2
3
5
7
1
4
6
.291 – .299
(7.391 – 7.595)
NOTE 4
.037 – .045
(0.940 – 1.143)
.093 – .104
(2.362 – 2.642)
.010 – .029
× 45°
(0.254 – 0.737)
.005
(0.127)
RAD MIN
0° – 8° TYP
.050
(1.270)
BSC
.004 – .012
.009 – .013
(0.102 – 0.305)
NOTE 3
(0.229 – 0.330)
.014 – .019
.016 – .050
(0.356 – 0.482)
TYP
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
INCHES
(MILLIMETERS)
S16 (WIDE) 0502
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
1052fa
LW/TP 1202 1K REV A • PRINTED IN USA
24 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
■
■
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 1985
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