LTC1063MJ8#TR_技术文档

LTC1063

DC Accurate, Clock-Tunable

5th Order Butterworth

Lowpass Filter

U

DESCRIPTIO

FEATURES

The LTC^®1063 is the first monolithic filter providing both

clock-tunability, low DC output offset and over 12-bit DC

accuracy. The frequency response of the LTC1063 closely

approximates a 5th order Butterworth polynomial. With

appropriate PCB layout techniques the output DC offset is

typically 1mV and is constant over a wide range of clock

frequencies. With ±5V supplies and ±4V input voltage

range, the CMR of the device is 80dB.

■

Clock-Tunable Cutoff Frequency

■

1mV DC Offset (Typical)

■

80dB CMRR (Typical)

Internal or External Clock

■

50µV_RMSClock Feedthrough

■

100:1 Clock-to-Cutoff Frequency Ratio

■

95µV_RMSTotal Wideband Noise

■

0.01% THD at 2V_RMSOutput Level

■

50kHz Maximum Cutoff Frequency

The filter cutoff frequency is controlled either by an inter-

nalorexternalclock. Theclock-to-cutofffrequencyratiois

100:1. The on-board clock is power supply independent,

and it is programmed via an external RC. The 50µV_RMS

clock feedthrough is considerably reduced over existing

monolithic filters.

■

Cascadable for Faster Roll-Off

■

Operates from ±2.375 to ±8V Power Supplies

■

Self-Clocking with 1 RC

■

Available in 8-Pin DIP and 16-Pin SO Wide Packages

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APPLICATIO S

The LTC1063 wideband noise is 95µV_RMS, and it can

process large AC input signals with low distortion. With

±7.5V supplies, for instance, the filter handles up to

4V_RMS(92dB S/N ratio) while the standard 1kHz THD is

below 0.02%; 80dB dynamic ranges (S/N +THD) is ob-

■

Audio

■

Strain Gauge Amplifiers

■

Anti-Aliasing Filters

■

Low Level Filtering

■

Digital Voltmeters

tained with input levels between 1V_RMSand 2.3V_RMS

.

■

60Hz Lowpass Filters

The LTC1063 is available in 8-pin miniDIP and 16-pin SO

wide packages. For a linear phase response, see LTC1065

data sheet.

■

Smoothing Filters

■

Reconstruction Filters

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

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TYPICAL APPLICATIO

Frequency Response

10

2.5kHz 5th Order Lowpass Filter

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

1

2

3

4

8

7

6

5

V

**

IN

V

OUT

LTC1063

*19.1k

5V

0.1µF

–5V

200pF*

0.1µF

*

SELF-CLOCKING SCHEME

+

** IF THE INPUT VOLTAGE CAN EXCEED V ,

CONNECT A SIGNAL DIODE BETWEEN PIN 1 AND V .

1

10

100

+

FREQUENCY (kHz)

1063 TA01

1063 TA02

1063fa

1

LTC1063

W W U W

ABSOLUTE MAXIMUM RATINGS _{(Note 1)}

Total Supply Voltage (V⁺to V^–) .......................... 16.5V

Power Dissipation............................................. 400mW

Voltage at Any Input .... (V^–– 0.3V) ≤ V_IN≤ (V⁺+ 0.3V)

Burn-In Voltage ...................................................... 16V

Operating Temperature Range ............... –40°C to 85°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

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/O

PACKAGE RDER I FOR ATIO

ORDER PART

TOP VIEW

NUMBER

NC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

ADJ

OS

V

1

2

3

4

8

7

6

5

V

ADJ

OS

IN

V

IN

NC

LTC1063CN8

LTC1063CSW

GND

OUT

+

GND

V

OUT

–

V

NC

CLK OUT

CLK IN

–

+

V

NC

N8 PACKAGE

8-LEAD PLASTIC DIP

T

JMAX

= 100°C, θ = 110°C/W (N)

JA

CLK OUT

CLK IN

J8 PACKAGE

8-LEAD CERAMIC DIP

LTC1063CJ8

LTC1063MJ8

SW PACKAGE

16-LEAD PLASTIC SO WIDE

= 100°C, θ = 85°C/W

T

JMAX

= 150°C, θ = 100°C/W (J)

JA

T

JMAX

JA

OBSOLETE PACKAGE

Consider the N8 Package for Alternate Source

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The

●

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at V = ±5V, f

= 500kHz, f = 5kHz, R = 10k, T = 25°C, unless otherwise specified.

S

CLK

C

L

A

PARAMETER

Clock-to-Cutoff Frequency Ratio (f /f )

CONDITIONS

±2.375V ≤ V ≤ ±7.5V

MIN

TYP

MAX

UNITS

100± 0.5

CLK

C

S

Maximum Clock Frequency (Note 2)

V = ±7.5V

5

4

3

MHz

S

V = ±5V

S

V = ±2.5V

S

Minimum Clock Frequency (Note 3)

Input Frequency Range

Filter Gain

±2.5V ≤ V ≤ ±7.5V, T < 85°C

30

Hz

S

A

0

0.9f

CLK

V = ±5V, f

= 25kHz, f = 250Hz

C

S

CLK

f

= 250Hz

– 3.5

– 3.6

– 3.0

–2.5

– 2.4

dB

IN

●

V = ±5V, f

IN

= 500kHz, f = 5kHz

C

S

CLK

f

= 100Hz

0

dB

f

= 1kHz = 0.2f

– 0.06

– 0.01

0.04

dB

IN

C

●

– 0.075

0.055

f

= 2.5kHz = 0.5f

– 0.09

– 0.14

0.16

0.41

0.46

dB

IN

C

= 4kHz = 0.8f

– 0.5

– 0.6

– 0.2

0.1

0.2

dB

IN

C

1063fa

2

LTC1063

ELECTRICAL CHARACTERISTICS

The

●

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at V = ±5V, f

= 500kHz, f = 5kHz, R = 10k, T = 25°C, unless otherwise specified.

S

CLK

C

L

A

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

f

= 5kHz = f

– 3.5

– 3.6

– 3.0

–2.5

–2.4

dB

IN

C

●

f

= 20kHz = 4f

– 57.5

– 57.0

– 60.0

–60.0

–62.0

–62.5

dB

C

Filter Gain

V = ±2.375V, f

= 500kHz, f = 5kHz

CLK C

S

f

IN

f

IN

f

IN

f

IN

= 1kHz

= 2.5kHz

= 4kHz

= 5kHz

– 0.066

– 0.081

0.004

0.074

0.089

dB

●

– 0.24

– 0.29

0.16

0.56

0.61

dB

– 0.6

– 0.7

– 0.2

0.2

0.3

dB

–3.5

–3.6

– 3.0

– 2.5

– 2.4

dB

Clock Feedthrough

±2.375 ≤ V ≤ ± 7.5V

50

µV

S

RMS

Wideband Noise (Note 4)

THD + Wideband Noise (Note 5)

±2.375 ≤ V ≤ ± 7.5V, 1Hz < f < f

100

–80

S

CLK

RMS

V = ±7.5V, f = 20kHz, f = 1kHz,

dB

S

C

IN

1V

RMS

≤ V ≤ 2.3V

IN RMS

Filter Output ± DC Swing

V = ±2.375V

1.6/–2.0

1.4/–1.8

1.7/–2.2

4.3/–4.8

6.8/–7.3

V

S

●

V = ±5V

S

4.0/–4.5

3.8/–4.3

V

V = ±7.5V

S

6.5/–7.0

6.3/–6.8

V

Input Bias Current

10

nA

Dynamic Input Impedance

Output DC Offset (Note 6)

800

MΩ

V = ±2.375V

S

V = ±7.5V

S

2

0

– 4

mV

S

V = ±5V

±5

Output DC Offset Drift

V = ±2.375V

S

V = ±7.5V

S

10

20

25

µV/°C

S

V = ±5V

Self-Clocking Frequency (f

)

R (Pin 4 to 5) = 20k, C (Pin 5 to GND) = 470pF

V = ±2.375V

OSC

99

95

105

103

112

114

kHz

S

●

V = ±5V

S

102

98

108

106

114

kHz

V = ±7.5V

S

104

101

110

109

116

kHz

External CLK Pin Logic Thresholds

V = ±2.375V

S

Min Logical “1”

Max Logical “0”

1.43

0.47

V

V = ±5V

S

Min Logical “1”

Max Logical “0”

3

1

V

V = ±7.5V

S

Min Logical “1”

Max Logical “0”

4.5

1.5

V

1063fa

3

LTC1063

ELECTRICAL CHARACTERISTICS

The

●

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at V = ±5V, f

= 500kHz, f = 5kHz, R = 10k, T = 25°C, unless otherwise specified.

S

CLK

C

L

A

PARAMETER

CONDITIONS

V = ±2.375V, f

MIN

TYP

MAX

UNITS

Power Supply Current

= 500kHz

CLK

2.7

4.0

5.5

mA

S

●

V = ±5V, f

= 500kHz

5.5

7.0

8

11

mA

S

CLK

V = ±7.5V, f

S

= 500kHz

CLK

11

14.5

mA

Note 4: The wideband noise specification does not include the clock

feedthrough.

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 5: To properly evaluate the filter’s harmonic distortion an inverting

output buffer is recommended as shown in the Test Circuit. An output

buffer is not necessarily needed when measuring output DC offset or

wideband noise.

Note 2: The maximum clock frequency criterion is arbitrarily defined as:

The frequency at which the filter AC response exhibits ≥ 1dB of gain

peaking.

Note 3: At limited temperature ranges (i.e., T ≤ 50°C) the minimum clock

A

Note 6: The output DC offset is optimized for ±5V supply. The output DC

offset shifts when the power supplies change; however this phenomenon

is repeatable and predictable.

frequency can be as low as 10Hz. The minimum clock frequency is

arbitrarily defined as: the clock frequency at which the output DC offset

changes by more than 1mV.

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TYPICAL PERFOR A CE CHARACTERISTICS

Output Offset vs Clock,

Low Clock Rates

Output Offset vs Clock,

Medium Clock Rates

Self-Clocking Frequency vs R

110

100

90

80

70

60

50

40

30

20

10

5

4

50

45

40

35

30

25

20

15

10

5

V

= ±5V

S

V

= ± 7.5V

LTC1063

S

3

5

4

A: T = 25°C

B: T = 85°C

A

2

R

C

C = 200pF

1

f

≅ 1/RC

OSC

V

= ±5V

S

0

–1

–2

–3

–4

–5

V

= ±2.5V

S

B

A

0

100

300

500

0

500

EXTERNAL CLOCK FREQUENCY (kHz)

1000

110

EXTERNAL CLOCK FREQUENCY (Hz)

210

10

FREQUENCY (kHz)

1063 G01

1063 G03

1063 G02

1063fa

4

LTC1063

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TYPICAL PERFOR A CE CHARACTERISTICS

Gain vs Frequency; V = ±2.5V

Gain vs Frequency; V = ±5V

Gain vs Frequency; V = ±7.5V

S

10

0

10

0

10

0

D

E

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10

–20

–30

–40

–50

–60

–70

–80

–90

A

B

C

A

B

C

B C

D

A. f

B. f

C. f

D. f

= 1MHz

= 2MHz

= 3MHz

= 4MHz

= 5MHz

CLK

A. f

CLK

B. f

CLK

C. f

CLK

D. f

CLK

= 1MHz

= 2MHz

= 3MHz

= 4MHz

A. f

B. f

C. f

= 0.5MHz

= 1MHz

= 2MHz

CLK

E. f

V

A

= 2.5V

RMS

V

A

= 1.5V

RMS

V

A

= 750mV

RMS

IN

T

= 25°C

T

= 25°C

T

= 25°C

1

10

INPUT FREQUENCY (kHz)

100 200

1

10

INPUT FREQUENCY (kHz)

100 200

1

10

INPUT FREQUENCY (kHz)

100 200

1063 G06

1063 G04

1063 G05

THD vs Frequency;

S

THD + Noise vs Input Voltage;

S

THD + Noise vs Input Voltage;

S

V = Single 5V

V = ±5V

1

0.1

1

0.1

1

0.1

f

= 1kHz, T = 25°C

A

V

f

= 0.75V

RMS

IN

f

= 1kHz, T = 25°C

A

IN

= 5kHz, f

IN

5 REPRESENTATIVE UNITS

= 500kHz

5 REPRESENTATIVE UNITS

C

CLK

S/N = 78dB, T = 25°C

A

5 REPRESENTATIVE UNITS

B

A

0.01

0.001

0.01

0.001

0.01

0.001

A. f = 5kHz, f

C

= 0.5MHz

= 1MHz

CLK

A. f = 10kHz, f

C

= 1MHz

= 2MHz

C

CLK

B. f = 10kHz, f

B. f = 20kHz, f

C

0.1

1

5

1

2

FREQUENCY (kHz)

5

3

4

0.1

1

5

INPUT (V

)

INPUT (V

)

RMS

1063 G07

1063 G08

1063 G09

THD + Noise vs Input Voltage;

S

THD vs Frequency;

S

V = ±7.5V

THD vs Frequency; V = ±5V

V = ±7.5V

S

1

0.1

1

0.1

1

0.1

V

f

= 1.5V

V

C

= 2.5V

IN RMS

f

= 1kHz, T = 25°C

A

IN

C

RMS

CLK

IN

= 10kHz, f

= 1MHz

f

= 10kHz, f = 1MHz

CLK

5 REPRESENTATIVE UNITS

S/N = 83.5dB, T = 25°C

S/N = 88dB, T = 25°C

A

5 REPRESENTATIVE UNITS

B

A

0.01

0.001

0.01

0.001

0.01

0.001

A. f = 10kHz, f

C

= 1MHz

= 2MHz

C

CLK

B. f = 20kHz, f

1

10

1

10

5

0.1

1

5

FREQUENCY (kHz)

INPUT (V

)

RMS

1063 G10

1063 G12

1063 G11

1063fa

5

LTC1063

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TYPICAL PERFOR A CE CHARACTERISTICS

Passband Gain and Phase

Phase Matching

vs Input Frequency

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1

0

±2.5V ≤ V ≤ ±7.5V, T = 25°C

V

= ± 7.5V

S

A

S

= 1V

IN

RMS

= 2MHz

–20

f

CLK

C

= 20kHz

–60

–1

–2

–3

–4

–5

–6

A

B

–100

–140

–180

–220

–260

PHASE

f

C

=100kHz

f

C

=1MHz

CLK

f =1kHz

CLK

f =10kHz

0

2

6

8

12 14 16 18 20 22 24

4

10

100

1k

10k

100k

INPUT FREQUENCY (kHz)

INPUT FREQUENCY (Hz)

1063 G14

1063 G13

Power Supply Current vs

Power Supply Voltage

Transient Response

10

9

8

7

6

5

4

3

2

1

0

–40°C

25°C

85°C

HORIZONTAL: 0.1ms/DIV, VERTICAL: 2V/DIV

_S= ±5V, f_C= 10kHz, V_IN= 1kHz ±3V_P

SQUARE WAVE

V

0

2

4

6

8

12 14 16

20

18

10

1063 G16

TOTAL POWER SUPPLY VOLTAGE (V)

1063 G15

1063fa

6

LTC1063

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PI FU CTIO S

DC level. The DC gain from the V_OSadjust pin to the filter

output pin equals two.

Power Supply Pins (Pins 6, 3, N Package)

The positive and negative supply pin should be bypassed

withahighquality0.1µFceramiccapacitor.Inapplications

where the clock pin (5) is externally swept to provide

several cutoff frequencies, the output DC offset variation

is minimized by connecting an additional 1µF solid tanta-

lum capacitor in parallel with the 0.1µF disc ceramic. This

technique was used to generate the graphs of the output

DC offset variation versus clock; they are illustrated in the

Typical Performance Characteristics section.

Any DC voltage applied to this pin will reflect at the output

pin of the filter multiplied by two.

If the V_OSadjust pin is not used, it should be shorted to the

groundpin.TheDCbiascurrentflowingintotheV_OSadjust

pin is typically 10pA.

Pin 8 should always be connected to an AC ground; AC

signals applied to this pin will degrade the filter response.

Whenthepowersupplyvoltageexceeds ±7V, andwhenV^–

is applied before V⁺, if V⁺is allowed to go below ground,

connect a signal diode between the positive supply pin and

ground to prevent latch-up (see Typical Applications).

Input Pin (Pin 1, N Package)

Pin 1 is the filter input and it is connected to an internal

switched-capacitor resistor. If the input pin is left floating,

the filter output will saturate. The DC input impedance of

pin 1 is very high; with ±5V supplies and 1MHz clock, the

DC input impedance is typically 1GΩ. A resistor, R_IN, in

series, with the input pin will not alter the value of the

filter’s DC output offset (Figure 1). R_INshould, however,

be limited to a maximum value (Table 1), otherwise the

filter’s passband flatness will be affected. Refer to the

Applications Information section for more details.

Ground Pin (Pin 2, N Package)

The ground pin merges the internal analog and digital

ground paths. The potential of the ground pin is the

reference for the internal switched-capacitor resistors,

and the reference for the external clock. The positive input

of the internal op amp is also tied to the ground pin.

For dual supply operation, the ground pin should be

connected to a high quality AC and DC ground. A ground

plane, if possible, should be used. A poor ground will

degrade DC offset and it will increase clock feedthrough,

noise and distortion.

R

IN

1

2

3

4

8

7

6

5

V

IN

V

OUT

LTC1063

–

+

V

f

CLK

1063 F01

A small amount of AC current flows out of the ground pin

whether or not the internal oscillator is used. The fre-

quency of the ground current equals the frequency of the

internalorexternalclock. Theaveragevalueofthiscurrent

is approximately 55µA, 110µA, 170µA for ±2.5V, ±5V and

±7.5V supplies respectively.

Figure 1.

Table 1. R

vs Clock and Power Supply

IN(MAX)

R

IN(MAX)

V = ±7.5V

V = ± 5V

S

V = ±2.5V

S

f

= 4MHz

2.2k

3.4k

–

CLK

For single supply operation, the ground pin should be

preferablybiasedathalfsupply(seeTypicalApplications).

= 3MHz

2.9k

f

= 2MHz

= 1MHz

= 500kHz

= 100kHz

5.5k

11k

24k

5k

11k

23k

120k

2.7k

9.2k

21k

CLK

V_OSAdjust Pin (Pin 8, N Package)

120k

110k

The V_OSadjust pin can be used to trim any small amount

ofoutputDCoffsetvoltageortointroduceadesiredoutput

1063fa

7

LTC1063

U

PI FU CTIO S

Output Pin (Pin 7, N Package)

Clock Output Pin (Pin 4, N Package)

Pin 7 is the filter output. This pin can typically source over

20mA and sink 2mA. Pin 7 should not drive long coax

cables, otherwise the filter’s total harmonic distortion will

degrade.

Any external clock applied to the clock input pin appears

at the clock output pin. The duty cycle of the clock output

equals the duty cycle of the external clock applied to the

clock input pin. The clock output pin swings to the power

supply rails. When the LTC1063 is used in a self-clocking

mode, the clock of the internal oscillator appears at the

clock output pin with a 30% duty cycle. The clock output

pin can be used to drive other LTC1063s or other ICs. The

maximum capacitance, C_L(MAX), the clock output pin can

drive is illustrated in Figure 2.

Clock Input Pin (Pin 5, N Package)

An external clock when applied to pin 5 tunes the filter

cutoff frequency. The clock-to-cutoff frequency ratio is

100:1. The high (V_HIGH) and low (V_LOW) clock logic

threshold levels are illustrated in Table 2. Square wave

clockswithdutycyclesbetween30%and50%arestrongly

recommended. Sinewave clocks are not recommended.

200

T

= 25°C

A

180

160

140

120

100

80

V

= ±2.5V

S

Table 2. Clock Pin Threshold Levels

POWER SUPPLY

V = ±2.5V

V = ±5V

S

V

1.5V

3V

V

LOW

0.5V

1V

HIGH

S

V

= ±5V

S

V

= ±7.5V

S

V = ±7.5V

4.5V

4.8V

4V

1.5V

1.6V

3V

S

60

V = ±8V

S

V = 5V, 0V

S

40

V = 12, 0V

V =15V, 0V

S

9.6V

12V

7.2V

9V

S

20

0

1

3

6

9 10

8

2

4

5

7

CLOCK FREQUENCY (MHz)

1063 F02

Figure 2. Maximum Load Capacitance at the Clock Output Pin

TEST CIRCUIT

+

V

LT1022

50k

OUT

–

1

8

7

6

5

V

IN

–

50k

2

LTC1063

3

+

V

20pF

0.1µF

4

0.1µF

CLOCK IN

1063 TC01

Figure 3. Test Circuit for THD

1063fa

8

LTC1063

W U U

APPLICATIO S I FOR ATIO

U

Note a 4pF parasitic capacitance is assumed in parallel

with the external 200pF timing capacitor. Figure 5 shows

the clock frequency variation from – 40°C to 85°C. The

200kHzclockofExample1willchangeby–1.75%at85°C.

Self-Clocking Operation

The LTC1063 features an internal oscillator which can be

tunedviaanexternalRC.TheLTC1063’sinternaloscillator

is primarily intended for generation of clock frequencies

below 500kHz. The first curve of the Typical Performance

Characteristics section shows how to quickly choose the

value of the RC for a given frequency. More precisely, the

frequency of the internal oscillator is equal to:

4

C = 200pF

T

A

= –40°C

3

2

V

S

= ±5V

V

S

= ±2.5V

1

V

S

= ±7.5V

f_CLK= K/RC

0

T

= 85°C

For clock frequencies (f_CLK) below 100kHz, K equals 1.07.

Figure 4b shows the variation of the parameter K versus

clock frequency and power supply. First choose the de-

sired clock frequency, (f_CLK< 500kHz), then through

Figure 4b pick the right value of K, setC = 200pF and solve

for R.

A

–1

–2

–3

–4

V

S

= ±7.5V

V

= ±5V

S

V

= ±2.5V

S

0

100

200

300

400

500

CLOCK FREQUENCY (kHz)

1063 F05

Example 1: f_CUTOFF= 2kHz, f_CLK= 200kHz, V_S= ±5V,

T_A= 25°C, K = 1.0, C = 200pF

Figure 5. f

vs Temperature

CLK

then,

R = (1.0)/(200kHz × 204pF) = 24.5k.

Foraverylimitedtemperaturerange,theinternaloscillator

of the LTC1063 can be used to generate clock frequencies

above 500kHz (Figures 6 and 7). The data of Figure 6 is

derived from several devices. For a given external (RC)

value,theobserveddevice-to-deviceclockfrequencyvaria-

tion was ±1% (V_S= ±5V), and ±1.25% for V_S= ±2.5V.

1

2

3

4

8

7

6

5

V

IN

V

OUT

+

LTC1063

–

V

Example 2: f_CUTOFF= 20kHz, f_CLK= 2MHz, V_S= ±7.5V,

T_A= 25°C, C = 10pF

R

C

from Figure 6, K = 0.575,

1063 F04a

Figure 4a.

and,

R = (0.575)/(2MHz × 14pF) = 20.5k.

0.80

0.75

0.70

0.65

0.60

0.55

0.50

0.45

0.40

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

0.75

f

= K/RC

F

= K/RC

CLK

C = 10pF

A

CLK

C = 200pF

= 25°C

T

= 25°C

T

A

V

= ±7.5V

S

V

= ±7.5V

= ±2.5V

300

S

V

= ±5V

V

S

= ±5V

S

V

S

V

S

= ±2.5V

0.5

1.0

1.5

2.0

2.5

3.0

100

400

500

200

CLOCK FREQUENCY (MHz)

INTERNAL CLOCK FREQUENCY (kHz)

1063 F06

1063 F04b

Figure 4b. f

vs K

Figure 6. f

vs K

CLK

1063fa

9

LTC1063

APPLICATIO S I FOR ATIO

W U U

U

0.80

Common Mode Rejection Ratio

f

= K/RC

CLK

0.75

0.70

0.65

0.60

0.55

0.50

0.45

0.40

C = 10pF

= 70°C

T

Thecommonmoderejectionratioisdefinedasthechange

oftheoutputDCoffsetwithrespecttotheDCchangeofthe

input voltage applied to the filter.

A

V

= ±7.5V

S

CMRR = 20log (∆V_{OS OUT}/∆V_IN)(dB)

V

= ±5V

S

Table 3 illustrates the common mode rejection for three

power supplies and three temperatures. The common

mode rejection improves if the output offset is adjusted to

approximately 0V. The output offset can be adjusted via

pin 8 (N package) (see Typical Applications).

V

= ±2.5V

S

0.5

1.0

1.5

2.0

2.5

3.0

CLOCK FREQUENCY (MHz)

1063 F07

Figure 7. f

vs K

Table 3. CMRR Data, f

= 100kHz

CLK

25°C

OS

A 4pF parasitic capacitance is assumed in parallel with the

external 10pF capacitor. A ±1% clock frequency variation

from device to device can be expected. The 2MHz clock

frequencydesignedabovewilltypicallydriftto1.74MHzat

70°C (Figure 7).

POWER SUPPLY ∆V

–40°C

76dB

74dB

70dB

25°C

85°C

76dB

75dB

74dB

(V Nulled)

IN

±2.5V

±5V

±1.8V

± 4V

78dB

79dB

72dB

85dB

82dB

76dB

±7.5V

± 6V

The above data is valid for clock frequencies up to 800kHz, 900kHz, 1MHz, for

V = ± 2.5V, ±5V, ±7.5V respectively.

The internal clock of the LTC1063 can be overridden by an

external clock provided that the external clock source can

drive the timing capacitor, C, which is connected from the

clock input pin to ground.

S

Clock Feedthrough

ClockfeedthroughisdefinedastheRMSvalueoftheclock

frequency and its harmonics which are present at the

filter’s output pin. The clock feedthrough is tested with the

filter input grounded and it depends on the quality of the

PC board layout and power supply decoupling. Any para-

sitic switching transients, during the rise and fall of the

incoming clock, are not part of the clock feedthrough

specifications; their amplitude strongly depends on scope

probing techniques as well as ground quality and power

supply bypassing. For a power supply V_S= ±5V, the clock

feedthrough of the LTC1063 is 50µV_RMS; for V_S= ±7.5V,

the clock feedthrough approaches 75µV_RMS. Figure 8

shows a typical scope photo of the LTC1063 output pin

when the input pin is grounded. The filter cutoff frequency

was 1kHz, while scope bandwidth was chosen to be 1MHz

such as switching transients above the 100kHz clock

frequency will show.

Output Offset

The DC output offset of the LTC1063 is trimmed to

typically less than ±1mV . The trimming is done at V_S=

±5V.ToobtainoptimumDCoffsetperformance,appropri-

ate PC layout techniques should be used and the filter IC

should be soldered to the PC board. A socket will degrade

theoutputDCoffsetbytypically1mV.TheoutputDCoffset

is sensitive to the coupling of the clock output pin 4 (N

package) to the negative power supply pin 3 (N package).

The negative supply pin should be well decoupled. When

the surface mount package is used, all the unused pins

should be grounded.

When the power supplies are fixed, the output DC offset

should not change by more than ±100µV over 10Hz to

1MHz clock frequency variation. When the filter clock

frequency is fixed, the output DC offset will typically

change by –4mV (2mV) when the power supply varies

from ±5V to ± 7.5V (±2.5V). See Typical Performance

Characteristics.

Wideband Noise

The wideband noise of the filter is the RMS value of the

device’s output noise spectral density. The wideband

noise data is used to determine the operating signal-to-

1063fa

10

LTC1063

W U U

APPLICATIO S I FOR ATIO

U

noise ratio at a given distortion level. The wideband noise

(µV_RMS) is nearly independent of the value of the clock

frequency and excludes the clock feedthrough. The

LTC1063’s typical wideband noise is 95µV_RMS. Figure 9

shows the same scope photo as Figure 8 but with a more

sensitive vertical scale: The clock feedthrough is imbed-

ded in the filter’s wideband noise. The peak-to-peak

wideband noise of the filter can be clearly seen; it is

approximately 500µV_P-P. Note that 500µV_P-Pequals the

95µV_RMSwideband noise of the part, multiplied by a crest

factor or 5.25.

Aliasing

Aliasingisaninherentphenomenonofsampleddatafilters

and it primarily occurs when the frequency of an input

signal approaches the sampling frequency. For the

LTC1063, an input signal whose frequency is in the range

of f_CLK±6% will generate an alias signal into the filter’s

passband and stopband. Table 4 shows details.

Example: LTC1063, f_CLK= 20kHz, f_C= 200kHz,

f_IN= (19.6kHz, 100mV_RMS

)

f_ALIAS= (400Hz, 3.16mV_RMS

)

An input RC can be used to attenuate incoming signals

closetothefilterclockfrequency(Figure10).AButterworth

passband response will be maintained if the value of the

input resistor follows Table 1.

Table 4. Aliasing Data

OUTPUT AMPLITUDE

REFERENCED TO

INPUT SIGNAL

INPUT FREQUENCY

OUTPUT FREQUENCY

0.9995f

0.995 f

0.0005 f

0.005 f

0

dB

CLK

0.99

f

0.01

f

– 3 dB

–10.2 dB

– 17.7 dB

– 24.3 dB

– 30 dB

– 40 dB

– 48 dB

– 54.5 dB

– 60.4 dB

– 65.5 dB

– 70.16 dB

– 78.25 dB

– 85.3 dB

–100.3 dB

2µs/DIV

0.9875f

0.985 f

0.9825f

0.0125 f

0.015 f

0.0175 f

1063 F08

f_CLK= 100kHz, f_C= 1kHz, V_S= ±5V, 1MHz SCOPE BW

Figure 8. LTC1063 Output Clock Feedthrough + Noise

0.98

0.975 f

0.97

0.965 f

0.96

0.955 f

f

0.02

0.025 f

0.03

0.035 f

0.04

0.045 f

f

0.95

0.94

0.93

0.9

f

0.05

0.06

0.07

0.1

f

R

1

2

3

4

8

7

6

5

V

IN

C

V

OUT

LTC1063

–

+

V

2µs/DIV

V

1063 F09

f_CLK= 100kHz, f_C= 1kHz, V_S= ±5V, 1MHz SCOPE BW

0.1µF

f

CLK

f

1

2πRC

f

CLK

10

CLK

20

Figure 9. LTC1063 Output Clock Feedthrough + Noise

≤

1063 F10

Figure 10. Adding an Input Anti-Aliasing RC

1063fa

11

LTC1063

W U U

U

APPLICATIO S I FOR ATIO

Group Delay

100

90

80

70

60

50

40

30

20

(A) LTC1063

The group delay of the LTC1063 closely approximates the

delay of an ideal 5-pole Butterworth lowpass filter (Figure

11, Curve A). To linearize the group delay of the LTC1063

(Figure 11, Curve B), use an input resistor about six times

higher than the maximum value of R_IN, shown in Table 1.

The passband response of the group delay corrected filter

approximates a 5-pole Bessel response while its transi-

tion band rolls off like a Butterworth.

BUTTERWORTH

(B) GROUP

DELAY

CORRECTED

0

2

3

4

5

6

8

10

1

7

9

INPUT FREQUENCY (kHz)

1063 F11

Figure 11. Group Delay

U

TYPICAL APPLICATIO S

7.5V

10k

Adjusting V

±7.5 Supply Operation

for

Single 5V Supply Operation (f = 3.4kHz)

OS(OUT)

C

5V

1

2

3

4

8

7

6

5

10k

V

IN

4.99k

4.53k

LT1009

V

OUT

1

2

3

4

8

7

6

5

0.1µF

+

LTC1063

13k

1µF

TANT

V

IN

≅2.5mV

5V

0.1µF

V

OUT

+

LTC1063

–

V

7.5V

–7.5V

200pF

+

f

CLK

0.1µF

1µF

TANT

0.1µF

*

1063 TA03

* OPTIONAL, 1N4148

1063 TA05

Cascading Two LTC1063s for Steeper Roll-Off

Sharing Clock for Multichannel Applications

1

2

3

4

8

7

6

5

V

*

IN

1

2

3

4

8

7

6

5

V

*

IN

LTC1063

V

OUT

5V

LTC1063

–5V

0.1µF

5V

–5V

0.1µF

R

C

0.1µF

R

C

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

V

*

IN

V

OUT

LTC1063

V

OUT

5V

LTC1063

–5V

5V

–5V

0.1µF

f

≅ (1/RC)(1/100)

C

WIDEBAND NOISE = 140µV

RMS

ATTENUATION AT f = 2f = 60dB

C

+

* IF THE INPUT VOLTAGE CAN EXCEED V ,

CONNECT A SIGNAL DIODE BETWEEN PIN 1 AND V . 1063 TA06

* IF THE INPUT VOLTAGE CAN EXCEED V ,

+

1063 TA04

CONNECT A SIGNAL DIODE BETWEEN PIN 1 AND V .

1063fa

12

LTC1063

U

PACKAGE DESCRIPTIO

J8 Package

8-Lead CERDIP (Narrow .300 Inch, Hermetic)

(Reference LTC DWG # 05-08-1110)

.405

(10.287)

MAX

CORNER LEADS OPTION

(4 PLCS)

.005

(0.127)

MIN

6

5

4

8

7

.023 – .045

(0.584 – 1.143)

HALF LEAD

OPTION

.025

.220 – .310

(5.588 – 7.874)

.045 – .068

(0.635)

RAD TYP

(1.143 – 1.650)

FULL LEAD

OPTION

1

2

3

.200

(5.080)

MAX

.300 BSC

(7.62 BSC)

.015 – .060

(0.381 – 1.524)

.008 – .018

(0.203 – 0.457)

0° – 15°

.045 – .065

(1.143 – 1.651)

.125

3.175

MIN

NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE

OR TIN PLATE LEADS

.014 – .026

(0.360 – 0.660)

.100

(2.54)

BSC

J8 0801

OBSOLETE PACKAGE

1063fa

13

LTC1063

U

PACKAGE DESCRIPTIO

N8 Package

8-Lead PDIP (Narrow .300 Inch)

(Reference LTC DWG # 05-08-1510)

.400*

(10.160)

MAX

8

7

6

5

4

.255 ± .015*

(6.477 ± 0.381)

1

2

3

.130 ± .005

.300 – .325

.045 – .065

(3.302 ± 0.127)

(1.143 – 1.651)

(7.620 – 8.255)

.065

(1.651)

TYP

.008 – .015

(0.203 – 0.381)

.120

.020

(0.508)

MIN

(3.048)

MIN

+.035

.325

–.015

.018 ± .003

(0.457 ± 0.076)

.100

(2.54)

BSC

+0.889

8.255

(

)

N8 1002

–0.381

NOTE:

INCHES

1. DIMENSIONS ARE

MILLIMETERS

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

1063fa

14

LTC1063

U

PACKAGE DESCRIPTIO

SW Package

16-Lead Plastic Small Outline (Wide .300 Inch)

(Reference LTC DWG # 05-08-1620)

.050 BSC .045 ±.005

.030 ±.005

.398 – .413

(10.109 – 10.490)

NOTE 4

TYP

15 14

12

10

9

N

16

N

13

11

.325 ±.005

.420

MIN

.394 – .419

(10.007 – 10.643)

NOTE 3

N/2

8

1

2

3

N/2

RECOMMENDED SOLDER PAD LAYOUT

2

3

5

7

1

4

6

.291 – .299

(7.391 – 7.595)

NOTE 4

.037 – .045

(0.940 – 1.143)

.093 – .104

(2.362 – 2.642)

.010 – .029

× 45°

(0.254 – 0.737)

.005

(0.127)

RAD MIN

0° – 8° TYP

.050

(1.270)

BSC

.004 – .012

.009 – .013

(0.102 – 0.305)

NOTE 3

(0.229 – 0.330)

.014 – .019

.016 – .050

(0.356 – 0.482)

TYP

(0.406 – 1.270)

NOTE:

1. DIMENSIONS IN

INCHES

(MILLIMETERS)

S16 (WIDE) 0502

2. DRAWING NOT TO SCALE

3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.

THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

1063fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

15

LTC1063

TYPICAL APPLICATIO S

U

Low Noise DC Accurate Clock-Tunable Notch

R1

10k ± 0.1%

–

+

1

2

3

4

8

7

6

5

V

R2

IN

LT1007

9.53k ± 0.1%

LTC1063

+

V

5V

–5V

0

–10

–20

–30

–40

–50

–60

–70

+

f

CLK

1µF

TANT

0.1µF

81Hz

f

CLK

119.04

• f

=

NOTCH

• NOTCH DEPTH > 50dB

f

= 100kHz

CLK

= 840Hz

(LTC1063)V

2

RMS

OS

• OUPUT DC OFFSET =

≅ 500µV

n

• OUTPUT NOISE = 50µV

NOTCH

f(–20dB)BW

215

340

465

590

715

1215 1340 1465

840

965 1090

INPUT FREQUENCY (Hz)

f

10.4

1

=

•

1063 TA07

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1065

Clock-Tunable 5th Order Bessel Lowpass Filter

650kHz Linear Phase Lowpass Filter

1mV Offset, 80dB CMR

LTC1565-31

LTC1566-1

LT1567

Continuous Time, Fully Differential In/Out

Single Ended to Differential Conv

Low Noise, 2.3MHz Lowpass Filter

Low Noise Op Amp and Inverter Building Block

Low Noise, 10MHz 4th Order Building Block

Linear Phase, DC Accurate, 10th Order Lowpass

Low Noise Differential Amp and 10MHz Lowpass

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LT1568

Lowpass or Bandpass, Differential Outputs

LTC1569-6

LTC1569-7

LT6600-2.5

LT6600-10

Resistor Set Clock, F < 64kHz

C

Resistor Set Clock, F < 300kHz

C

55µV

86µV

Noise 100kHz-10MHz 3V Supply

Noise 100kHz-20MHz 3V Supply

RMS

1063fa

LT/LT 0905 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

16

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1063MJ8#TR
厂家：	Linear
描述：	IC SWITCHED CAPACITOR FILTER, BUTTERWORTH, LOWPASS, CDIP8, 0.300 INCH, CERAMIC, DIP-8, Active Filter 时钟
文件：	总16页 (文件大小：271K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1063MJ8#TR [Linear]

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