LTC1064-7CN [Linear]
Linear Phase, 8th Order Lowpass Filter; 线性相位, 8阶低通滤波器型号: | LTC1064-7CN |
厂家: | Linear |
描述: | Linear Phase, 8th Order Lowpass Filter |
文件: | 总12页 (文件大小:299K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC1064-7
Linear Phase, 8th Order
Lowpass Filter
U
DESCRIPTIO
EATURE
S
F
■
■
■
■
■
Steeper Roll-Off Than 8th Order Bessel Filters
fCUTOFF up to 100kHz
Phase Equalized Filter in 14-Pin Package
Phase and Group Delay Response Fully Tested
Transient Response Exhibits 5% Overshoot and
No Ringing
Wide Dynamic Range
72dB THD or Better Throughout a 50kHz Passband
No External Components Needed
The LTC1064-7 is a clock-tunable monolithic 8th order
lowpass filter with linear passband phase and flat group
delay. The amplitude response approximates a maximally
flat passband whilte it exhibits steeper roll-off than an
equivalent8thorderBesselfilter. Forinstance, attwicethe
cutoff frequency the filter attains 34dB attenuation (vs
12dB for Bessel), while at three times the cutoff frequency
the filter attains 68dB attenuation (vs 30dB for Bessel).
The cutoff frequency of the LTC1064-7 is tuned via an
external TTL or CMOS clock.
■
■
■
O U
The LTC1064-7 features wide dynamic range. With single
5V supply, the S/N + THD is 76dB. Optimum 92dB S/N is
obtained with ±7.5V supplies.
PPLICATI
S
A
■
■
■
Data Communication Filters
Time Delay Networks
The clock-to-cutoff frequency ratio of the LTC1064-7 can
be set to 50:1 (pin 10 to V+) or 100:1 (pin 10 to V–).
Phase-Matched Filters
When the filter operates at clock-to-cutoff frequency ratio
of 50:1, the input is double-sampled to lower the risk of
aliasing.
The LTC1064-7 is pin-compatible with the LTC1064-X
series, LTC1164-7 and LTC1264-7.
U
O
TYPICAL APPLICATI
Eye Diagram
80kHz Linear Phase Lowpass Filter
1
2
3
4
5
6
7
14
13
12
11
10
9
V
IN
–7.5V
LTC1064-7
CLK = 4MHz
7.5V
7.5V
V
OUT
8
1064-7 TA01
NOTE: THE POWER SUPPLIES SHOULD BE BYPASSED BY A
0.1µF CAPACITOR CLOSE TO THE PACKAGE AND ANY PRINTED
CIRCUIT BOARD ASSEMBLY SHOULD MAINTAIN A DISTANCE
OF AT LEAST 0.2 INCHES BETWEEN ANY OUTPUT OR INPUT
1064-7 TA02
1µs/DIV
PIN AND THE f
LINE.
VS = ±7.5V
CLK
fCLK = 4MHz
RATIO = 50:1
1
LTC1064-7
W W W
U
ABSOLUTE AXI U RATI GS
Total Supply Voltage (V+ to V–) .......................... 16.5V
Power Dissipation............................................. 400mW
Burn-In Voltage ................................................... 16.5V
Voltage at Any Input ..... (V– – 0.3V) ≤ VIN ≤ (V+ + 0.3V)
Storage Temperature Range ................ –65°C to 150°C
Operating Temperature Range
LTC1064-7C ....................................... – 40°C to 85°C
LTC1064-7M .................................... – 55°C to 125°C
Lead Temperature (Soldering, 10 sec)................. 300°C
W
U
/O
PACKAGE RDER I FOR ATIO
TOP VIEW
TOP VIEW
ORDER PART
ORDER PART
NUMBER
NUMBER
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R
(A)
1
2
3
4
5
6
7
R
(A)
14
13
12
11
10
9
NC
IN
IN
V
NC
NC
V
IN
IN
–
–
GND
V
V
GND
+
LTC1064-7CN
LTC1064-7CJ
LTC1064-7MJ
LTC1064-7CS
+
V
NC
f
V
CLK
GND
NC
f
50/100
GND
LP (A)
INV (A)
CLK
50/100
NC
V
OUT
LP (A)
INV (A)
NC
8
V
OUT
J PACKAGE
N PACKAGE
14-LEAD CERAMIC DIP 14-LEAD PLASTIC DIP
S PACKAGE
16-LEAD PLASTIC SOL
TJMAX = 150°C, θJA = 65°C/W (J)
TJMAX = 110°C, θJA = 85°C/W
TJMAX = 110°C, θJA = 65°C/W (N)
ELECTRICAL CHARACTERISTICS
VS = ±7.5V, RL = 10k, TA = 25°C, fCUTOFF = 10kHz or 20kHz, fCLK = 1MHz, TTL or CMOS level (maximum clock rise and fall time ≤ 1µs)
and all gain measurements are referenced to passband gain, unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Passband Gain
0.1Hz ≤ f ≤ 0.25 f
CUTOFF
f
= 5kHz, (f /f ) = 50:1
●
–0.60
0.10
0.65
dB
TEST
CLK C
Gain at 0.5 f
(Note 4)
f
f
= 10kHz, (f /f ) = 50:1
●
●
–0.90
–1.30
–0.35
–0.35
0.15
1.25
dB
dB
CUTOFF
TEST
TEST
CLK C
= 5kHz, (f /f ) = 100:1
CLK
C
Gain at 0.75 f
(Note 1)
f
= 15kHz, (f /f ) = 50:1
●
–2.0
–1.0
–0.35
dB
CUTOFF
TEST
CLK C
Gain at f
f
f
= 20kHz, (f /f ) = 50:1
●
●
–4.50
–5.75
– 3.4
– 4.5
– 2.50
–3.75
dB
dB
CUTOFF
TEST
TEST
CLK C
= 10kHz, (f /f ) = 100:1
CLK
C
Gain at 2 f
f
f
= 40kHz, (f /f ) = 50:1
●
●
–36.5
–37.0
–34.0
–34.5
–31.75
–31.75
dB
dB
CUTOFF
TEST
TEST
CLK C
= 20kHz, (f /f ) = 100:1
CLK
C
Gain with f
Gain with f
= 20kHz
= 400kHz, V = ±2.375V
f
f
f
= 200Hz, (f /f ) = 100:1
– 6.5
–0.9
–4.5
– 4.3
– 0.3
–3.3
– 3.5
0.25
–2.00
dB
dB
dB
CLK
CLK
TEST
CLK C
= 4kHz, (f /f ) = 50:1
S
TEST
TEST
CLK C
= 8kHz, (f /f ) = 50:1
CLK
C
Phase Factor (F )
Phase = 180° – F (f/f )
(Note 1)
0.1Hz ≤ f ≤ f
CUTOFF
(f /f ) = 50:1
430 ± 2.0
421 ± 2.5
430
Deg
Deg
Deg
Deg
C
CLK C
(f /f ) = 100:1
CLK C
(f /f ) = 50:1
●
●
422
414
437
429
CLK
C
(f /f ) = 100:1
421
CLK
C
Phase Nonlinearity
(Notes 1, 3)
(f /f ) = 50:1
±1.0
±1.0
%
%
%
%
CLK
C
(f /f ) = 100:1
CLK
C
(f /f ) = 50:1
●
●
±2.0
±2.0
CLK
C
(f /f ) = 100:1
CLK
C
2
LTC1064-7
ELECTRICAL CHARACTERISTICS
VS = ±7.5V, RL = 10k, TA = 25°C, fCUTOFF = 10kHz or 20kHz, fCLK = 1MHz, TTL or CMOS level (maximum clock rise and fall time ≤ 1µs)
and all gain measurements are referenced to passband gain, unless otherwise specified.
PARAMETER
Group Delay (t )
CONDITIONS
(f /f ) = 50:1, f ≤ f
CUTOFF
MIN
TYP
MAX
UNITS
59.7 ± 0.5
117.0 ± 1.0
59.7
µs
µs
µs
µs
d
CLK
C
t = (F /360)(1/f )
(f /f ) = 100:1, f ≤ f
d
C
CLK C
CUTOFF
CUTOFF
(Note 2)
(f /f ) = 50:1, f ≤ f
●
●
58.6
115.0
60.7
119.0
CLK
C
(f /f ) = 100:1, f ≤ f
117.0
CLK
C
CUTOFF
Group Delay Deviation
(Notes 2, 3)
(f /f ) = 50:1, f ≤ f
±1.0
±1.0
%
%
%
%
CLK
C
CUTOFF
(f /f ) = 100:1, f ≤ f
CLK
C
CUTOFF
(f /f ) = 50:1, f ≤ f
●
●
±2.0
±2.0
CLK
C
CUTOFF
(f /f ) = 100:1, f ≤ f
CLK
C
CUTOFF
Input Frequency Range (Table 9)
(f /f ) = 50:1
<f
CLK
<f /2
CLK
kHz
kHz
CLK
C
(f /f ) = 100:1
CLK
C
Maximum f
V = 5V (AGND = 2V)
2.0
3.5
5.0
MHz
MHz
MHz
CLK
S
V = ±5V
S
V = ±7.5V
S
Clock Feedthrough (f ≥ f
)
CLK
50:1
200
µV
RMS
Wideband Noise
V = ±2.5V
95 ± 5%
105 ± 5%
115 ± 5%
µV
µV
µV
S
RMS
RMS
RMS
kΩ
(1Hz ≤ f ≤ f
)
CLK
V = ±5V
S
V = ±7.5V
S
Input Impedance
25
40
70
Output DC Voltage Swing
(Note 5)
V = ±2.375V
±1.0
±2.1
±3.0
±1.2
±3.2
±5.0
V
V
V
S
V = ±5V
●
●
S
V = ±7.5V
S
Output DC Offset
50:1, V = ±5V
±150
±150
±220
mV
mV
S
100:1, V = ±5V
S
Output DC Offset TempCo
Power Supply Current
50:1, V = ±5V
±200
±200
11
14
17
µV/°C
µV/°C
S
100:1, V = ±5V
S
V = ±2.375V, T = 25°C
S
22
22
26
28
28
32
mA
mA
mA
mA
mA
mA
A
●
●
●
V = ±5V, T = 25°C
S
A
V = ±7.5V, T = 25°C
S
A
Power Supply Range
±2.375
±8
V
The
Note 1: Input frequencies, f, are linearly phase shifted through the filter as long as f ≤
f ; f = cutoff frequency.
● denotes specifications which apply over the full operating temperature range.
180
f
= 1MHz
CLK
C
C
RATIO = 50:1
90
Figure 1 curve shows the typical phase response of an LTC1064-7 operating at f
=
CLK
1MHz, ratio = 50:1, f = 20kHz and it closely matches an ideal straight line. The phase
C
0
shift is described by: phase shift = 180° – F (f/f ); f ≤ f .
C
C
F is arbitrarily called the “phase factor” expressed in degrees. The phase factor allows
the calculation of the phase at a given frequency. Example: The phase shift at 14kHz of
the LTC1064-7 shown in Figure 1 is:
phase shift = 180° – 430° (14kHz/20kHz) ± nonlinearity = –121° ± 1% or
–121° ± 1.20°.
–90
–180
–270
–360
Note 2: Group delay and group delay deviation are calculated from the measured phase
factor and phase deviation specifications.
0
2
4
6
8
10 12 14 16 18 20
Note 3: Phase deviation and group delay deviation for LTC1064-7MJ is ±4%.
FREQUENCY (kHz)
1164-7 F01
Note 4: The filter cutoff frequency is abbreviated as f
or f .
C
CUTOFF
Note 5: The AC swing is typically 11V , 7V , 2.8V , with ±7.5V, ±5V, ±2.5V
Supply respectively. For more information refer to the THD + Noise vs Input graphs.
P-P
P-P
P-P
Figure 1. Phase Response in the Passband (Note 1)
3
LTC1064-7
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Phase Factor vs fCLK
(Typical Unit)
Phase Factor vs fCLK
(Typical Unit)
Gain vs Frequency
10
0
485
475
485
475
V
= ±5V
V = ±5V
S
(f /f ) = 100:1
CLK C
S
(f /f ) = 50:1
CLK
C
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
70°C
465
455
445
435
465
455
445
435
50:1
100:1
70°C
0°C
25°C
2.5
25°C
2.5
0°C
3.0
V
f
A
= ±5V
CLK
= 25°C
S
= 1MHz
425
415
425
415
T
0.1
1
10
100
0.5
3.5
0.5
3.5
1.0
1.5
2.0
1.0
1.5
2.0
3.0
f
(MHz)
f
(MHz)
FREQUENCY (kHz)
CLK
CLK
1064-7 G01
1064-7 G02
1064-7 G03
Phase Factor vs fCLK (Min and
Max Representative Units)
Phase Factor vs fCLK (Min and
Max Representative Units)
445
440
435
430
425
420
445
440
435
430
425
420
V
T
= 5V
V
T
= ±5V
S
A
S
A
= 25°C
= 25°C
PINS 3, 5 AT 2V
(f /f ) = 50:1
CLK
C
(f /f ) = 50:1
CLK
C
2.0
0.5
2.5
3.0
3.5
0.5
1.0
1.5
1.0
1.5
2.0
f
(MHz)
f
(MHz)
CLK
CLK
1064-7 G05
1064-7 G04
Passband Gain and Phase
Passband Gain and Phase
180
180
3
2
3
2
V
f
= ±5V
V
f
= ±5V
S
S
120
120
= 1MHz
= 2MHz
CLK
CLK
(f /f ) = 50:1
(f /f ) = 100:1
CLK
C
CLK
C
60
60
1
1
0
0
0
0
GAIN
–60
–120
–180
–240
–300
–360
–60
–120
–180
–240
–300
–360
–1
–2
–1
–2
GAIN
PHASE
PHASE
–3
–4
–3
–4
–5
–6
–5
–6
2
4
6
8
10 12 14 16 18 20 22
2
4
6
8
10 12 14 16 18 20 22
FREQUENCY (kHz)
FREQUENCY (kHz)
1064-7 G06
1064-7 G07
4
LTC1064-7
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Passband Gain vs Frequency and
Passband Gain vs Frequency
and fCLK
Passband Gain vs Frequency and
fCLK at TA = 85°C
fCLK at TA = 85°C
5
4
5
4
5
4
V
= ±7.5V
A. f
CLK
B. f
CLK
C. f
CLK
D. f
CLK
E. f
= 1MHz
= 2MHz
= 3MHz
= 4MHz
= 5MHz
V
T
= ±7.5V
= 25°C
V = ±5V
S
A. f
CLK
B. f
CLK
C. f
CLK
D. f
CLK
E. f
= 1MHz
= 2MHz
= 3MHz
= 4MHz
= 5MHz
A. f
CLK
B. f
CLK
C. f
CLK
D. f
CLK
= 0.5MHz
= 1.5MHz
= 2.5MHz
= 3.5MHz
S
S
(f /f ) = 50:1
(f /f ) = 50:1
CLK
C
A
CLK C
(f /f ) = 50:1
CLK
C
3
2
3
2
3
2
CLK
CLK
1
1
1
0
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
D
E
D
E
A
B
C
A
A
B
C D
B C
1
100
FREQUENCY (kHz)
1000
1
10
100
10
10
100
FREQUENCY (kHz)
1000
10
FREQUENCY (kHz)
1064-7 G09
1064-7 G10
1064-7 G08
Passband Gain vs Frequency
and fCLK
Passband Gain vs Frequency and
fCLK at TA = 85°C
Delay vs Frequency and fCLK
5
4
5
4
125
100
75
V
S
T
= SINGLE 5V
= 25°C
V = SINGLE 5V
S
A. f
CLK
B. f
CLK
C. f
CLK
D. f
CLK
= 0.5MHz
A. f
CLK
B. f
CLK
C. f
CLK
D. f
CLK
= 0.5MHz
= 1.0MHz
= 1.5MHz
= 2.0MHz
V
T
= ±5V
S
A
A
(f /f ) = 50:1
= 1.0MHz
= 1.5MHz
= 2.0MHz
A
CLK C
= 25°C
(f /f ) = 50:1
CLK
C
(f /f ) = 50:1
3
2
3
2
CLK
C
A. f
= 0.5MHz
= 1.5MHz
= 2.5MHz
= 3.5MHz
CLK
CLK
CLK
CLK
B. f
C. f
D. f
1
1
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
50
25
0
B
A
A
B
C
D
B
C D
C
D
1
10
100
1
10
100
2
12
22
32
42
52
62
72
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
1064-7 G11
1064-7 G12
1064-7 G13
THD + Noise vs Frequency
Delay vs Frequency and fCLK
THD + Noise vs Frequency
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
250
200
150
–40
–45
V
T
= ±5V
V
V
f
= ±7.5V
= 1V
RMS
CLK
V
V
f
= ±7.5V
= 2V
CLK
S
A
S
IN
S
IN
A
= 25°C
RMS
(f /f ) = 100:1
= 2.5MHz
= 1MHz
–50
–55
–60
–65
–70
–75
–80
–85
–90
CLK
C
(f /f ) = 50:1
(f /f ) = 50:1
CLK
C
CLK
C
(100k RESISTOR
(100k RESISTOR
A. f
= 0.5MHz
CLK
CLK
CLK
CLK
–
–
PIN 9 TO V )
PIN 9 TO V )
B. f
C. f
D. f
= 1.5MHz
= 2.5MHz
= 3.5MHz
100
50
0
B
C
D
1
10
20
1
10
FREQUENCY (kHz)
50
1
6
11
16
21
26
31
36
FREQUENCY (kHz)
FREQUENCY (kHz)
1064-7 G15
1064-7 G16
1064-7 G14
5
LTC1064-7
TYPICAL PERFOR A CE CHARACTERISTICS
U W
THD + Noise vs Frequency
THD + Noise vs Frequency
THD + Noise vs Frequency
–40
–40
–45
–40
–45
V
V
f
= SINGLE 5V
V
V
f
= ±5V
= 1V
CLK
S
V
V
f
= SINGLE 5V
S
IN
S
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
= 0.5V
IN
RMS
= 1MHz
= 0.5V
RMS
IN
CLK
RMS
= 1MHz
–50
–55
–60
–65
–70
–75
–80
–85
–90
CLK
–50
–55
–60
–65
–70
–75
–80
–85
–90
= 500kHz
(f /f ) = 50:1
(f /f ) = 50:1
(f /f ) = 100:1
CLK
C
CLK
C
CLK C
(100k RESISTOR
(PINS 3, 5 AT 2V)
(PINS 3, 5 AT 2V)
–
PIN 9 TO V )
1
10
20
1
10
20
1
2
3
4
5
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
1064-7 G18
1064-7 G17
1064-7 G19
THD + Noise vs Input
THD + Noise vs Input
THD + Noise vs Input
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–40
–45
f
f
= 1kHz
A. V = ±5V
f
f
= 1kHz
A. V = ±5V
IN
S
IN
S
V
= SINGLE 5V
= 1kHz
S
= 2MHz
B. V = ±7.5V
S
= 1MHz
B. V = ±7.5V
S
CLK
CLK
f
IN
A
B
(f /f ) = 100:1
(f /f ) = 50:1
CLK
C
CLK
C
–50
–55
–60
–65
–70
–75
–80
–85
–90
f
= 1MHz
CLK
(100k PIN 9
TO V )
A
B
B
A
(f /f ) = 50:1
CLK
C
–
A. PINS 3, 5 AT 2V
B. PINS 3, 5 AT 2.5V
0.1
1
5
0.1
1
2
0.1
1
5
INPUT (V
)
INPUT (V
)
RMS
INPUT (V
)
RMS
RMS
1064-7 G21
1064-7 G22
1064-7 G20
Power Supply Current vs
Power Supply Voltage
THD + Noise vs Input
Phase Matching vs Frequency
48
44
40
36
32
28
24
20
16
12
8
–40
–45
5
PHASE DIFFERENCE BETWEEN
ANY TWO UNITS (SAMPLE OF
50 REPRESENTATIVE UNITS)
f
= 1MHz
V
= SINGLE 5V
= 1kHz
CLK
S
f
IN
A
B
–50
–55
–60
–65
–70
–75
–80
–85
–90
f
= 500kHz
4
3
2
1
0
CLK
V
CLK
≥ ±5V
S
(f /f ) = 100:1
CLK
C
f
≤ 2.5MHz
(f /f ) = 50:1 OR 100:1
CLK
C
T
= 0°C TO 70°C
A
–55°C
25°C
125°C
A. PINS 3, 5 AT 2V
B. PINS 3, 5 AT 2.5V
4
0
0
2
4
6
8
10 12 14 16 18 20 22 24
0.1
1
2
0
0.2
0.4
0.6
0.8
1.0
TOTAL POWER SUPPLY VOLTAGE (V)
INPUT (V
)
RMS
FREQUENCY (f
/FREQUENCY)
CUTOFF
1064-7 G23
1064-7 G25
1064-7 G24
6
LTC1064-7
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Table 1. Passband Gain and Phase
VS = ±7.5V, (fCLK/fC) = 50:1, TA = 25°C
FREQUENCY (kHz)
GAIN (dB)
PHASE (DEG)
FREQUENCY (kHz)
GAIN (dB)
PHASE (DEG)
f
f
f
f
f
= 1MHz (Typical Unit)
f
= 4MHz (Typical Unit)
CLK
CLK
0.000
5.000
10.000
15.000
20.000
– 0.086
– 0.086
– 0.334
– 1.051
– 3.316
180.00
73.54
–33.60
–140.81
–249.30
0.000
10.000
20.000
30.000
40.000
– 0.116
– 0.116
– 0.436
– 1.171
– 3.353
180.00
72.49
–35.21
–142.33
–250.12
= 2MHz (Typical Unit)
f
= 5MHz (Typical Unit)
CLK
CLK
0.000
10.000
20.000
30.000
40.000
– 0.131
– 0.131
– 0.442
– 1.108
– 3.115
180.00
72.88
–34.71
–141.99
–250.45
0.000
12.500
25.000
37.500
50.000
– 0.097
– 0.097
– 0.351
– 0.951
– 2.999
180.00
71.00
–38.08
–146.51
–256.13
= 3MHz (Typical Unit)
CLK
CLK
CLK
0.000
15.000
30.000
45.000
60.000
– 0.156
– 0.156
– 0.459
– 0.941
– 2.508
180.00
72.54
–35.01
–141.95
–250.53
Table 3. Passband Gain and Phase
VS = ±5V, (fCLK/fC) = 50:1, TA = 25°C
FREQUENCY (kHz)
GAIN (dB)
PHASE (DEG)
f
f
f
f
f
f
= 0.5MHz (Typical Unit)
CLK
= 4MHz (Typical Unit)
0.000
2.500
5.000
7.500
10.000
– 0.081
– 0.081
– 0.345
– 1.063
– 3.283
180.00
73.71
–33.31
–140.36
–248.52
0.000
20.000
40.000
60.000
80.000
– 0.121
– 0.121
– 0.292
– 0.476
– 1.539
180.00
72.12
–35.75
–142.92
–252.63
= 1MHz (Typical Unit)
CLK
= 5MHz (Typical Unit)
0.000
5.000
10.000
15.000
20.000
– 0.071
– 0.071
– 0.322
– 1.036
– 3.284
180.00
73.44
–33.83
–141.13
–249.68
0.000
25.000
50.000
75.000
100.000
– 0.045
– 0.045
– 0.006
0.185
180.00
70.85
–38.25
–146.77
–259.27
–0.356
= 1.5MHz (Typical Unit)
CLK
CLK
CLK
CLK
0.000
7.500
15.000
22.500
30.000
– 0.095
– 0.095
– 0.392
– 1.075
– 3.155
180.00
73.03
–34.53
–141.89
–250.45
Table 2. Passband Gain and Phase
VS = ±7.5V, (fCLK/fC) = 100:1, TA = 25°C
FREQUENCY (kHz)
GAIN (dB)
PHASE (DEG)
= 2MHz (Typical Unit)
f
f
f
= 1MHz (Typical Unit)
CLK
CLK
CLK
0.000
10.000
20.000
30.000
40.000
– 0.127
– 0.127
– 0.447
– 1.041
– 2.856
180.00
72.81
–34.70
–141.77
–250.24
0.000
2.500
5.000
7.500
10.000
– 0.203
– 0.203
– 0.741
– 1.831
– 4.451
180.00
74.07
–31.71
–136.47
–240.17
= 2MHz (Typical Unit)
= 2.5MHz (Typical Unit)
0.000
5.000
10.000
15.000
20.000
– 0.152
– 0.152
– 0.575
– 1.501
– 3.973
180.00
73.79
–32.47
–138.11
–243.84
0.000
12.500
25.000
37.500
50.000
– 0.126
– 0.126
– 0.411
– 0.864
– 2.397
180.00
72.61
–34.91
–141.88
–250.62
= 3MHz (Typical Unit)
= 3MHz (Typical Unit)
0.000
7.500
15.000
22.500
30.000
– 0.123
– 0.123
– 0.481
– 1.312
– 3.654
180.00
73.32
–33.64
–140.14
–247.11
0.000
15.000
30.000
45.000
60.000
– 0.102
– 0.102
– 0.292
– 0.546
– 1.769
180.00
72.23
–35.64
–142.96
–252.73
7
LTC1064-7
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Table 3. Passband Gain and Phase
VS = ±5V, (fCLK/fC) = 50:1, TA = 25°C
Table 5. Passband Gain and Phase
VS = Single 5V, (fCLK/fC) = 50:1, TA = 25°C
FREQUENCY (kHz)
GAIN (dB)
PHASE (DEG)
FREQUENCY (kHz)
GAIN (dB)
PHASE (DEG)
f
= 3.5MHz (Typical Unit)
f
= 0.5MHz (Typical Unit)
CLK
CLK
0.000
17.500
35.000
52.500
70.000
– 0.054
– 0.054
– 0.108
– 0.137
– 1.104
180.00
71.07
–38.00
–146.68
–258.97
0.000
2.500
5.000
7.500
10.000
– 0.134
– 0.134
– 0.391
– 1.109
– 3.351
180.00
73.52
–33.67
–140.92
–249.32
f
= 1MHz (Typical Unit)
CLK
Table 4. Passband Gain and Phase
0.000
5.000
10.000
15.000
20.000
– 0.148
– 0.148
– 0.423
– 1.111
– 3.241
180.00
73.07
–34.63
–142.25
–251.03
VS = ±5V, (fCLK/fC) = 100:1, TA = 25°C
FREQUENCY (kHz)
GAIN (dB)
PHASE (DEG)
f
= 0.5MHz (Typical Unit)
CLK
CLK
CLK
CLK
CLK
0.000
1.250
2.500
3.750
5.000
– 0.186
– 0.186
– 0.726
– 1.805
– 4.402
180.00
74.10
–31.65
–136.48
–240.33
f
f
= 1.5MHz (Typical Unit)
CLK
CLK
0.000
7.500
– 0.157
– 0.157
– 0.456
– 0.981
– 2.687
180.00
72.73
–34.83
–142.08
–251.09
15.000
22.500
30.000
f
= 1MHz (Typical Unit)
= 2MHz (Typical Unit)
0.000
2.500
5.000
7.500
10.000
– 0.184
– 0.184
– 0.712
– 1.785
– 4.387
180.00
74.02
–31.80
–136.61
–240.43
0.000
10.000
20.000
30.000
40.000
– 0.188
– 0.188
– 0.304
– 0.513
– 1.824
180.00
71.37
–37.52
–146.11
–257.46
f
f
f
f
f
= 1.5MHz (Typical Unit)
0.000
3.750
7.500
– 0.145
– 0.145
– 0.596
– 1.556
– 4.047
180.00
73.84
–32.32
–137.73
–242.95
Table 6. Passband Gain and Phase
VS = Single 5V, (fCLK/fC) = 100:1, TA = 25°C
11.250
15.000
= 2MHz (Typical Unit)
0.000
5.000
10.000
15.000
20.000
FREQUENCY (kHz)
GAIN (dB)
PHASE (DEG)
f
f
f
f
= 0.5MHz (Typical Unit)
CLK
0.000
1.250
2.500
3.750
5.000
– 0.243
– 0.243
– 0.776
– 1.861
– 4.483
180.00
73.91
–31.98
–136.98
–240.90
– 0.116
– 0.116
– 0.494
– 1.361
– 3.761
180.00
73.64
–32.93
–139.03
–245.57
= 1MHz (Typical Unit)
CLK
= 2.5MHz (Typical Unit)
0.000
2.500
5.000
7.500
10.000
– 0.208
– 0.208
– 0.678
– 1.679
– 4.221
180.00
73.76
–32.47
–137.87
–242.65
0.000
6.250
12.500
18.750
25.000
– 0.101
– 0.101
– 0.452
– 1.273
– 3.611
180.00
73.17
–33.93
–140.58
–247.80
= 1.5MHz (Typical Unit)
= 3MHz (Typical Unit)
CLK
CLK
CLK
CLK
0.000
7.500
15.000
22.500
30.000
– 0.105
– 0.105
– 0.445
– 1.228
– 3.509
180.00
72.36
–35.47
–142.70
–250.58
0.000
3.750
– 0.115
– 0.115
– 0.473
– 1.314
– 3.715
180.00
73.26
–33.73
–140.40
–247.66
7.500
11.250
15.000
= 3.5MHzMHz (Typical Unit)
= 2MHz (Typical Unit)
0.000
8.750
17.500
26.250
35.000
– 0.104
– 0.104
– 0.437
– 1.188
– 3.478
180.00
70.81
–38.39
–146.85
–256.10
0.000
5.000
10.000
15.000
20.000
– 0.209
– 0.209
– 0.499
– 1.281
– 3.695
180.00
71.18
–37.85
–146.27
–255.38
8
LTC1064-7
U
U
U
PI FU CTIO S
Power Supply Pins (4, 12)
for the filter should be connected to clock’s ground at a
single point only. Table 7 shows the clock’s low and high
levelthresholdvaluesforadualorsinglesupplyoperation.
A pulse generator can be used as a clock source provided
thehighlevelONtimeisgreaterthan0.1µs.Sinewavesare
not recommended for clock input frequencies less than
100kHz, since excessively slow clock rise or fall times
generate internal clock jitter (maximum clock rise or fall
time ≤ 1µs). The clock signal should be routed from the
rightsideoftheICpackageandperpendiculartoittoavoid
couplingtoanyinputoroutputanalogsignalpath. A200Ω
resistor between clock source and pin 11 will slow down
the rise and fall times of the clock to further reduce charge
coupling (Figures 2 and 3).
TheV+ (pin4)andtheV – (pin12)shouldbebypassedwith
a 0.1µF capacitor to an adequate analog ground. The
filter’s power supplies should be isolated from other
digital or high voltage analog supplies. A low noise linear
supply is recommended. Using a switching power supply
will lower the signal-to-noise ratio of the filter. The supply
during power-up should have a slew rate less than 1V/µs.
When V+ is applied before V– and V– is allowed to go
above ground, a signal diode should clamp V– to prevent
latch-up. Figures 2 and 3 show typical connections for
dual and single supply operation.
–
V
1
2
3
4
5
6
7
14
13
12
11
10
9
Table 7. Clock Source High and Low Threshold Levels
V
V
0.1µF
IN
POWER SUPPLY
HIGH LEVEL
LOW LEVEL
200Ω
+
LTC1064-7
CLOCK SOURCE
Dual Supply = ±7.5V
Dual Supply = ±5V
Dual Supply = ±2.5V
Single Supply = 12V
Single Suppl = 5V
≥ 2.18V
≥ 1.45V
≥ 0.73V
≥ 7.80V
≥ 1.45V
≤ 0.5V
≤ 0.5V
≤ –2.0V
≤ 6.5V
≤ 0.5V
+
V
0.1µF
+
GND
DIGITAL SUPPLY
8
V
OUT
1064-7 F02
Analog Ground Pins (3, 5)
Figure 2. Dual Supply Operation for an fCLK/fCUTOFF = 50:1
The filter performance depends on the quality of the
analog signal ground. For either dual or single supply
operation, an analog ground plane surrounding the pack-
age is recommended. The analog ground plane should be
connected to any digital ground at a single point. For dual
supply operation, pin 3 should be connected to the analog
ground plane. For single supply operation pin 3 should be
biased at 1/2 supply and should be bypassed to the analog
ground plane with at least a 1µF capacitor (Figure 3). For
single 5V operation at the highest fCLK of 2MHz, pin 3
should be biased at 2V. This minimizes passband gain and
phase variations.
1
2
3
4
5
6
7
14
13
12
11
10
9
V
IN
200Ω
+
V
LTC1064-7
CLOCK SOURCE
+
0.1µF
V
+
GND
DIGITAL SUPPLY
10k
10k
8
+
1µF
V
OUT
1064-7 F03
Figure 3. Single Supply Operation for an fCLK/fCUTOFF = 50:1
Ratio Input Pin (10)
The DC level at this pin determines the ratio of the clock
frequency to the cutoff frequency of the filter. Pin 10 at V+
gives a 50:1 ratio and pin 10 at V– gives a 100:1 ratio. For
single supply operation the ratio is 50:1 when pin 10 is at
V+ and 100:1 when pin 10 is at ground. When pin 10 is not
tied to ground, it should be bypassed to analog ground
Clock Input Pin (11)
Any TTL or CMOS clock source with a square-wave output
and 50% duty cycle (±10%) is an adequate clock source
for the device. The power supply for the clock source
should not be the filter’s power supply. The analog ground
9
LTC1064-7
U
U
U
PI FU CTIO S
with a 0.1µF capacitor. If the DC level at pin 10 is switched
mechanically or electrically at slew rates greater than
1V/µs while the device is operating, a 10k resistor should
be connected between pin 10 and the DC source.
External Connection Pins (7, 14)
Pins 7 and 14 should be connected together. In a printed
circuit board the connection should be done under the IC
package through a short trace surrounded by the analog
ground plane.
Filter Input Pin (2)
The input pin is connected internally through a 40k resis-
tor tied to the inverting input of an op amp.
NC Pins (1, 5, 8, 13)
Pins 1, 5, 8 and 13 are not connected to any internal circuit
point on the device and should preferably be tied to analog
ground.
Filter Output Pins (9, 6)
Pin 9 is the specified output of the filter; it can typically
source 3mA and sink 1mA. Driving coaxial cables or
resistive loads less than 20k will degrade the total har-
monicdistortion ofthefilter. When evaluating thedevice’s
distortion an output buffer is required. A noninverting
buffer, Figure 4, can be used provided that its input
common-mode range is well within the filter’s output
swing. Pin 6 is an intermediate filter output providing an
unspecified 6th order lowpass filter. Pin 6 should not be
loaded.
–
LT1220
1k
+
1064-7 F04
Figure 4. Buffer for Filter Output
O U
W
U
PPLICATI
A
S I FOR ATIO
Clock Feedthrough
amplitude strongly depends on scope probing techniques
as well as grounding and power supply bypassing. The
clock feedthrough, if bothersome, can be greatly reduced
by adding a simple R/C lowpass network at the output of
the filter pin (9). This R/C will completely eliminate any
switching transients.
ClockfeedthroughisdefinedastheRMSvalueoftheclock
frequency and its harmonics that are present at the filter’s
output pin (9). The clock feedthrough is tested with the
input pin (2) grounded and it depends on PC board layout
and on the value of the power supplies. With proper layout
techniques the values of the clock feedthrough are shown
in Table 8.
Wideband Noise
The wideband noise of the filter is the total RMS value of
the device’s noise spectral density and it is used to
determine the operating signal-to-noise ratio. Most of its
frequency contents lie within the filter passband and it
cannot be reduced with post filtering. For instance, the
Table 8. Clock Feedthrough
V
50:1
90µV
100:1
S
Single 5V
±5V
±7.5V
100µV
RMS
RMS
RMS
RMS
100µV
120µV
300µV
650µV
RMS
RMS
LTC1064-7 wideband noise at ±5V supply is 105µVRMS
,
Note: The clock feedthrough at single 5V is imbedded in the
wideband noise of the filter. Clock waveform is a square wave.
95µVRMS of which have frequency contents from DC up to
the filter’s cutoff frequency. The total wideband noise
(µVRMS) is nearly independent of the value of the clock.
The clock feedthrough specifications are not part of the
wideband noise.
Any parasitic switching transients during the rise and fall
edges of the incoming clock are not part of the clock
feedthroughspecifications. Switchingtransientshavefre-
quency contents much higher than the applied clock; their
10
LTC1064-7
O U
W
U
PPLICATI
A
S I FOR ATIO
Speed Limitations
Transient Response
To avoid op amp slew rate limiting at maximum clock
frequencies, the signal amplitude should be kept below a
specified level as shown in Table 9.
Table 9. Maximum VIN vs VS and Clock
POWER SUPPLY
MAXIMUM f
MAXIMUM V
IN
CLK
±7.5V
5.0MHz
4.5MHz
4.0MHz
1.8V
2.3V
2.7V
1.4V
(f > 80kHz)
RMS IN
(f > 80kHz)
RMS IN
(f > 80kHz)
RMS IN
≥ 3.5MHz
(f > 500kHz)
RMS IN
±5V
3.5MHz
≥ 3.0MHz
2.0MHz
1.6V
(f > 80kHz)
RMS IN
1064-7 F05
50µs/DIV
0.7V
(f > 400kHz)
(f > 250kHz)
RMS IN
VS = ±7.5V, fIN = 2kHz ± 3V
CLK = 1MHz, RATIO = 50:1
f
Single 5V
0.5V
RMS IN
Figure 5.
Table 10. Transient Response of LTC Lowpass Filters
DELAY
TIME*
(SEC)
RISE SETTLING OVER-
t
s
TIME** TIME***
(SEC) (SEC)
SHOOT
(%)
OUTPUT
INPUT
LOWPASS FILTER
LTC1064-3 Bessel
LTC1164-5 Bessel
LTC1164-6 Bessel
LTC1264-7 Linear Phase
LTC1164-7 Linear Phase
LTC1064-7 Linear Phase
LTC1164-5 Butterworth
LTC1164-6 Elliptic
90%
50%
10%
0.50/f
0.43/f
0.43/f
0.34/f
0.34/f
0.34/f
0.36/f
0.39/f
0.39/f
0.48/f
0.54/f
0.54/f
0.54/f
0.80/f
0.85/f
1.15/f
2.05/f
0.5
0
1
5
5
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
t
d
1.15/f
1.20/f
1.20/f
0.80/f
0.85/f
0.90/f
0.85/f
2.2/f
2.2/f
2.4/f
4.3/f
4.5/f
C
5
C
C
C
C
11
18
20
20
t
r
LTC1064-4 Elliptic
LTC1064-1 Elliptic
6.5/f
0.39
CUTOFF
C
RISE TIME (t ) =
±5%
r
f
* To 50% ±5%, ** 10% to 90% ±5%, *** To 1% ±0.5%
2.2
SETTLING TIME (t ) =
s
±5%
f
CUTOFF
(TO 1% of OUTPUT)
Table 11. Aliasing (fCLK = 100kHz)
1.2
CUTOFF
DELAY TIME (t ) = GROUP DELAY ≈
(TO 50% OF OUTPUT)
d
1064-7 F06
f
INPUT FREQUENCY
OUTPUT LEVEL
OUTPUT FREQUENCY
(Aliased Frequency
(V = 1V
IN CLK OUT
,
(Relative to Input,
IN
RMS
f
= f ± f
)
0dB = 1V
(dB)
)
f
= ABS [f ± f ])
Figure 6.
RMS
OUT
CLK IN
(kHz)
(kHz)
Aliasing
50:1, f
= 2kHz
CUTOFF
190 (or 210)
195 (or 205)
196 (or 204)
197 (or 203)
198 (or 202)
–76.1
–51.9
–36.3
–18.4
–3.0
10.0
5.0
4.0
3.0
2.0
Aliasing is an inherent phenomenon of sampled data
systems and it occurs when input frequencies close to the
sampling frequency are applied. For the LTC1064-7 case
at 100:1, an input signal whose frequency is in the range
offCLK ±3%, willbealiasedbackintothefilter’spassband.
If, for instance, an LTC1064-7 operating with a 100kHz
clock and 1kHz cutoff frequency receives a 98kHz, 10mV
input signal, a 2kHz, 143µVRMS alias signal will appear at
its output. When the LTC1064-7 operates with a clock-to-
cutoff frequency of 50:1, aliasing occurs at twice the clock
frequency. Table 11 shows details.
199.5 (or 200.5)
–0.2
0.5
100:1, f = 1kHz
CUTOFF
97 (or 103)
–74.2
–53.2
–36.9
–19.6
–5.2
3.0
2.5
2.0
1.5
1.0
97.5 (or 102.5)
98 (or 102)
98.5 (or 101.5)
99 (or 101)
99.5 (or 100.5)
–0.7
0.5
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LTC1064-7
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
J Package
14-Lead Ceramic DIP
0.785
0.200
(5.080)
MAX
(19.939)
MAX
0.005
(0.127)
MIN
0.290 – 0.320
(7.366 – 8.128)
14
13
12
11
10
9
8
0.015 – 0.060
(0.381 – 1.524)
0.220 – 0.310
0.025
(5.588 – 7.874)
(0.635)
RAD TYP
0.008 – 0.018
0° – 15°
(0.203 – 0.460)
2
3
4
5
6
1
7
0.098
(2.489)
MAX
0.385 ± 0.025
0.038 – 0.068
0.100 ± 0.010
(2.540 ± 0.254)
0.125
(3.175)
MIN
(9.779 ± 0.635)
(0.965 – 1.727)
0.014 – 0.026
J14 0392
(0.360 – 0.660)
N Package
14-Lead Plastic DIP
0.770
0.065
(19.558)
MAX
(1.651)
TYP
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.015
(0.380)
MIN
14
13
12
11
10
9
8
0.130 ± 0.005
(3.302 ± 0.127)
0.260 ± 0.010
(6.604 ± 0.254)
0.009 – 0.015
(0.229 – 0.381)
+0.025
1
2
3
5
6
7
4
0.325
–0.015
0.075 ± 0.015
(1.905 ± 0.381)
0.018 ± 0.003
(0.457 ± 0.076)
0.125
(3.175)
MIN
+0.635
8.255
(
)
–0.381
0.100 ± 0.010
(2.540 ± 0.254)
N14 0392
S Package
16-Lead Plastic SOL
0.398 – 0.413
(10.109 – 10.490)
0.291 – 0.299
(7.391 – 7.595)
15 14
12
10
9
16
13
11
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.005
0.010 – 0.029
(0.254 – 0.737)
× 45°
(0.127)
RAD MIN
0° – 8° TYP
0.394 – 0.419
(10.007 – 10.643)
SEE NOTE
0.050
(1.270)
TYP
0.004 – 0.012
(0.102 – 0.305)
0.009 – 0.013
(0.229 – 0.330)
SEE NOTE
0.014 – 0.019
0.016 – 0.050
(0.406 – 1.270)
(0.356 – 0.482)
TYP
NOTE:
PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
2
3
5
7
8
1
4
6
SOL16 0392
LT/GP 1292 10K REV 0
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
12
●
●
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
LINEAR TECHNOLOGY CORPORATION 1992
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