LTC1068IG-25 [Linear]
Clock-Tunable, Quad Second Order, Filter Building Blocks; 时钟可调，四阶，过滤积木
| 型号： | LTC1068IG-25 |
| 厂家： | 
Linear |
| 描述： | Clock-Tunable, Quad Second Order, Filter Building Blocks |
| 文件： | 总28页 (文件大小：538K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1068 Series
Clock-Tunable, Quad
Second Order, Filter Building Blocks
U
DESCRIPTIO
EATURE
Four Identical 2nd Order Filter Sections in an
S
F
The LTC®1068 product family consists of four monolithic
clock-tunablefilterbuildingblocks.Eachproductcontains
fourmatched,lownoise,highaccuracy2ndorderswitched-
capacitorfiltersections. Anexternalclocktunesthecenter
frequency of each 2nd order filter section. The LTC1068
products differ only in their clock-to-center frequency
ratio. The clock-to-center frequency ratio is set to 200:1
(LTC1068-200), 100:1 (LTC1068), 50:1 (LTC1068-50) or
25:1 (LTC1068-25). External resistors can modify the
clock-to-center frequency ratio. High performance, quad
2nd order, dual 4th order or 8th order filters can be
designed with an LTC1068 family product. Designing
filters with an LTC1068 product is fully supported by
FilterCADTM filter design software for Windows®.
■
SSOP Package
■
■
2nd Order Section Center Frequency Error:
±
0.3% Typical and
±0.8% Maximum
Low Noise per 2nd Order Section, Q ≤ 5:
LTC1068-200 50µV
LTC1068-50 75µV
, LTC1068 50µV
RMS RMS
, LTC1068-25 90µV
RMS
RMS
■
■
Low Power Supply Current: 4.5mA, Single 5V,
LTC1068-50
Operation with ±5V Power Supply, Single 5V
Supply or Single 3.3V Supply
O U
PPLICATI
A
S
■
Lowpass or Highpass Filters:
The LTC1068 products are available in a 28-pin SSOP
surface mount package. A customized version of an
LTC1068 family product can be obtained in a 16-lead SO
package with internal thin-film resistors. Please contact
LTC Marketing for details.
LTC1068-200, 0.5Hz to 25kHz; LTC1068, 1Hz to
50kHz; LTC1068-50, 2Hz to 50kHz; LTC1068-25,
4Hz to 200kHz
Bandpass or Bandreject (Notch) Filters:
LTC1068-200, 0.5Hz to 15kHz; LTC1068, 1Hz to
30kHz; LTC1068-50, 2Hz to 30kHz; LTC1068-25,
4Hz to 140kHz
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
FilterCAD is a trademark of Linear Technology Corporation.
Windows is a registered trademark of Microsoft Corporation.
U
O
TYPICAL APPLICATI
Dual, Matched, 4th Order Butterworth Lowpass Filters, Clock-Tunable
Up to 200kHz f – 3dB = fCLK/25, 4th Order Filter Noise = 60µVRMS
R12 14k
R11 20k
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
INV B
HPB/NB
BPB
INV C
HPC/NC
BPC
IN1
R21 14k
R31 20k
R22 20k
R32 10k
Gain vs Frequency
3
10
0
4
V
LPB
LPC
OUT1
5
–10
–20
–30
–40
–50
–60
–70
–80
SB
SC
LTC1068-25
6
–
–5V
NC
V
1µF
7
AGND
NC
CLK
8
+
5V
f
= (25)(f – 3dB)
CLK
V
0.1µF
9
NC
NC
10
11
12
13
14
SA
SD
V
LPA
LPD
OUT2
R33 20k
R23 14k
R34 10k
R24 20k
BPA
HPA/NA
INVA
BPD
0.1
1
10
RELATIVE FREQUENCY [f /(f – 3dB)]
IN
HPD/ND
INVD
R13 20k
1068 TA20b
V
IN2
R14 14k
1068 TA20a
1
LTC1068 Series
W W W
U
ABSOLUTE AXI U RATI GS (Note 1)
Total Supply Voltage (V+ to V–) .............................. 12V
Power Dissipation............................................. 500mW
Input Voltage at Any Pin .... V– – 0.3V ≤ VIN ≤ V+ + 0.3V
Storage Temperature Range ................. –65°C to 150°C
Operating Temperature Range
LTC1068C................................................ 0°C to 70°C
LTC1068I........................................... –40°C to 85°C
Lead Temperature (Soldering, 10 sec).................. 300°C
W
U
/O
PACKAGE RDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
ORDER PART
1
2
INV C
HPC/NC
BPC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INV B
HPB/NB
BPB
NUMBER
TOP VIEW
INV B
1
2
INV C
HPC/NC
BPC
LTC1068CN
LTC1068IN
24
23
22
21
20
19
3
LTC1068CG
HPB/NB
BPB
4
LPC
LPB
LTC1068CG-200
LTC1068CG-50
LTC1068CG-25
LTC1068IG
3
5
SC
SB
LPB
4
LPC
–
6
V
NC
SB
5
SC
–
7
NC
AGND
AGND
6
V
+
+
8
CLK
NC
V
V
7
18 CLK
LTC1068IG-200
LTC1068IG-50
LTC1068IG-25
SA
LPA
8
SD
17
16
15
14
13
9
NC
SA
9
LPD
10
11
12
13
14
SD
BPA
10
11
12
BPD
LPD
BPD
HPD/ND
INV D
LPA
HPA/NA
INV A
HPD/ND
INV D
BPA
HPA/NA
INV A
N PACKAGE
24-LEAD PDIP
TJMAX = 110°C, θJA = 65°C/W
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 110°C, θJA = 95°C/W
Consult factory for Military grade parts.
LTC1068 (Internal Op Amps) VS = ±5V, TA = 25°V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Supply Voltage Range
Voltage Swings
3.14
±5.5
V
V = 3.14V, R = 5k (Note 2)
●
●
●
1.2
2.6
±3.4
1.6
3.2
±4.1
V
V
S
L
P-P
V = 4.75V, R = 5k (Note 3)
S
L
P-P
V
V = ±5V, R = 5k
S
L
Output Short-Circuit Current (Source/Sink)
V = ±4.75V
V = ±5V
S
17/6
20/15
mA
mA
S
DC Open-Loop Gain
GBW Product
R = 5k
85
dB
MHz
V/µs
V
L
V = ±5V
S
6
10
Slew Rate
V = ±5V
S
Analog Ground Voltage (Note 4)
V = 5V, Voltage at AGND
S
2.5V ±2%
2
LTC1068 Series
ELECTRICAL CHARACTERISTICS
LTC1068 (Complete Filter) VS = ±5V, TA = 25°V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Clock-to-Center Frequency Ratio (Note 5)
V = 4.75V, f
= 1MHz, Mode 1 (Note 3),
CLK
100 ±0.3
100 ±0.8
100 ±0.9
%
%
S
f = 10kHz, Q = 5, V = 0.5V
,
●
●
O
IN
RMS
R1 = R3 = 49.9k, R2 = 10k
V = ±5V, f = 1MHz, Mode 1,
100 ±0.3
100 ±0.8
100 ±0.9
%
%
S
CLK
f = 10kHz, Q = 5, V = 1V
,
O
IN
RMS
R1 = R3 = 49.9k, R2 = 10K
Clock-to-Center Frequency Ratio,
Side-to-Side Matching (Note 5)
V = 4.75V, f = 1MHz, Q = 5 (Note 3)
●
●
±0.25
±0.25
±0.9
±0.9
%
%
S
CLK
V = ±5V, f
= 1MHz, Q = 5
S
CLK
Q Accuracy (Note 5)
V = 4.75V, f
= 1MHz, Q = 5 (Note 3)
CLK
= 1MHz, Q = 5
●
●
±1
±1
±3
±3
%
%
S
V = ±5V, f
S
CLK
f Temperature Coefficient
±1
±5
0
ppm/°C
ppm/°C
mV
O
Q Temperature Coefficient
DC Offset Voltage (Note 5)
(See Table 1)
V = ±5V, f
= 1MHz, V
●
●
●
±15
±25
±40
S
CLK
OS1
(DC Offset of Input Inverter)
V = ±5V, f = 1MHz, V
OS2
±2
±5
mV
mV
S
CLK
(DC Offset of First Integrator)
V = ±5V, f = 1MHz, V
S
CLK
OS3
(DC Offset of Second Integrator)
Clock Feedthrough
V = ±5V, f = 1MHz
0.1
5.6
mV
RMS
S
CLK
Max Clock Frequency (Note 6)
Power Supply Current
V = ±5V, Q ≤ 2.0, Mode 1
S
MHz
V = 3.14V, f
V = 4.75V, f
S
= 1MHz (Note 2)
= 1MHz (Note 3)
●
●
●
3.5
6.5
9.5
8
11
15
mA
mA
mA
S
CLK
CLK
V = ±5V, f
= 1MHz
S
CLK
LTC1068-200 (Internal Op Amps) VS = ±5V, TA = 25°V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Supply Voltage Range
Voltage Swings
3.14
±5.5
V
V = 3.14V, R = 5k (Note 2)
●
●
●
1.2
2.6
±3.4
1.6
3.2
±4.1
V
V
S
L
P-P
V = 4.75V, R = 5k (Note 3)
S
L
P-P
V
V = ±5V, R = 5k
S
L
Output Short-Circuit Current (Source/Sink)
V = ±4.75V
V = ±5V
S
17/6
20/15
mA
mA
S
DC Open-Loop Gain
GBW Product
R = 5k
85
dB
MHz
V/µs
V
L
V = ±5V
S
6
10
Slew Rate
V = ±5V
S
Analog Ground Voltage (Note 4)
V = 5V, Voltage at AGND
S
2.5V ±2%
LTC1068-200 (Complete Filter) VS = ±5V, TA = 25°V, unless otherwise noted.
PARAMETER
CONDITIONS
V = 4.75V, f
MIN
TYP
MAX
UNITS
Clock-to-Center Frequency Ratio (Note 5)
= 1MHz, Mode 1 (Note 3),
CLK
200 ±0.3
200 ±0.8
200 ±0.9
%
%
S
f = 5kHz, Q = 5, V = 0.5V
,
●
●
O
IN
RMS
R1 = R3 = 49.9k, R2 = 10k
V = ±5V, f = 1MHz, Mode 1,
200 ±0.3
200 ±0.8
200 ±0.9
%
%
S
CLK
f = 5Hz, Q = 5, V = 1V
,
RMS
O
IN
R1 = R3 = 49.9k, R2 = 10K
3
LTC1068 Series
ELECTRICAL CHARACTERISTICS
LTC1068-200 (Complete Filter) VS = ±5V, TA = 25°V, unless otherwise noted.
PARAMETER
CONDITIONS
V = 4.75V, f
MIN
TYP
MAX
UNITS
Clock-to-Center Frequency Ratio,
Side-to-Side Matching (Note 5)
= 1MHz, Q = 5 (Note 3)
CLK
= 1MHz, Q = 5
●
●
±0.25
±0.25
±0.9
±0.9
%
%
S
V = ±5V, f
S
CLK
Q Accuracy (Note 5)
V = 4.75V, f
= 1MHz, Q = 5 (Note 3)
CLK
= 1MHz, Q = 5
●
●
±1
±1
±3
±3
%
%
S
V = ±5V, f
S
CLK
f Temperature Coefficient
±1
±5
0
ppm/°C
ppm/°C
mV
O
Q Temperature Coefficient
DC Offset Voltage (Note 5)
(See Table 1)
V = ±5V, f
= 1MHz, V
●
●
●
±15
±25
±40
S
CLK
OS1
(DC Offset of Input Inverter)
V = ±5V, f = 1MHz, V
OS2
±2
±5
mV
mV
S
CLK
(DC Offset of First Integrator)
V = ±5V, f = 1MHz, V
S
CLK
OS3
(DC Offset of Second Integrator)
Clock Feedthrough
V = ±5V, f = 1MHz
0.1
5.6
mV
RMS
S
CLK
Max Clock Frequency (Note 6)
Power Supply Current
V = ±5V, Q ≤ 2.0, Mode 1
S
MHz
V = 3.14V, f
V = 4.75V, f
S
= 1MHz (Note 2)
= 1MHz (Note 3)
●
●
●
3.5
6.5
9.5
8
11
15
mA
mA
mA
S
CLK
CLK
V = ±5V, f
= 1MHz
S
CLK
LTC1068-50 (Internal Op Amps) VS = ±5V, TA = 25°V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Supply Voltage Range
Voltage Swings
3.14
±5.5
V
V = 3.14V, R = 5k (Note 2)
●
●
●
1.2
2.6
±3.4
1.8
3.6
±4.1
V
V
S
L
P-P
V = 4.75V, R = 5k (Note 3)
S
L
P-P
V
V = ±5V, R = 5k
S
L
Output Short-Circuit Current (Source/Sink)
V = ±3.14V
V = ±5V
S
17/6
20/15
mA
mA
S
DC Open-Loop Gain
GBW Product
R = 5k
85
dB
MHz
V/µs
V
L
V = ±5V
S
4
Slew Rate
V = ±5V
S
7
Analog Ground Voltage (Note 4)
V = 5V, Voltage at AGND
S
2.175V ±2%
LTC1068-50 (Complete Filter) VS = ±5V, TA = 25°V, unless otherwise noted.
PARAMETER
CONDITIONS
V = 3.14V, f
MIN
TYP
MAX
UNITS
Clock-to-Center Frequency Ratio (Note 5)
= 250kHz, Mode 1 (Note 2),
CLK
50 ±0.3
50 ±0.8
50 ±0.9
%
%
S
f = 5kHz, Q = 5, V = 0.34V
,
●
●
O
IN
RMS
R1 = R3 = 49.9k, R2 = 10k
V = ±5V, f = 500kHz, Mode 1,
50 ±0.3
50 ±0.8
50 ±0.9
%
%
S
CLK
f = 10kHz, Q = 5, V = 1V
,
O
IN
RMS
R1 = R3 = 49.9k, R2 = 10K
Clock-to-Center Frequency Ratio,
Side-to-Side Matching (Note 5)
V = 3.14V, f = 250kHz, Q = 5 (Note 2)
●
●
±0.25
±0.25
±0.9
±0.9
%
%
S
CLK
V = ±5V, f
= 500kHz, Q = 5
S
CLK
Q Accuracy (Note 5)
V = 3.14V, f
= 250kHz, Q = 5 (Note 2)
CLK
= 500kHz, Q = 5
●
●
±1
±1
±3
±3
%
%
S
V = ±5V, f
S
CLK
4
LTC1068 Series
ELECTRICAL CHARACTERISTICS
LTC1068-50 (Complete Filter) VS = ±5V, TA = 25°V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
±1
±5
0
MAX
UNITS
ppm/°C
ppm/°C
mV
f Temperature Coefficient
O
Q Temperature Coefficient
DC Offset Voltage (Note 5)
(See Table 1)
V = ±5V, f
= 500kHz, V
OS1
●
●
●
±15
±25
±40
S
CLK
(DC Offset of Input Inverter)
V = ±5V, f = 500kHz, V
OS2
–2
–5
mV
mV
S
CLK
(DC Offset of First Integrator)
V = ±5V, f = 500kHz, V
OS3
S
CLK
(DC Offset of Second Integrator)
Clock Feedthrough
V = ±5V, f = 500kHz
0.16
3.4
mV
RMS
S
CLK
Max Clock Frequency (Note 6)
Power Supply Current
V = ±5V, Q ≤ 1.6, Mode 1
S
MHz
V = 3.14V, f
V = 4.75V, f
S
= 250kHz (Note 2)
= 250kHz (Note 3)
●
●
●
3.0
4.3
6.0
5
8
11
mA
mA
mA
S
CLK
CLK
V = ±5V, f
= 500kHz
S
CLK
LTC1068-25 (Internal Op Amps) VS = ±5V, TA = 25°V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Supply Voltage Range
Voltage Swings
3.14
±5.5
V
V = 3.14V, R = 5k (Note 2)
●
●
●
1.2
2.6
±3.4
1.6
3.4
±4.1
V
V
S
L
P-P
V = 4.75V, R = 5k (Note 3)
S
L
P-P
V
V = ±5V, R = 5k
S
L
Output Short-Circuit Current (Source/Sink)
V = ±4.75V
V = ±5V
S
17/6
20/15
mA
mA
S
DC Open-Loop Gain
GBW Product
R = 5k
85
dB
MHz
V/µs
V
L
V = ±5V
S
6
10
Slew Rate
V = ±5V
S
Analog Ground Voltage (Note 4)
V = 5V, Voltage at AGND
S
2.5V ±2%
LTC1068-25 (Complete Filter) VS = ±5V, TA = 25°V, unless otherwise noted.
PARAMETER
CONDITIONS
V = 4.75V, f
MIN
TYP
MAX
UNITS
Clock-to-Center Frequency Ratio (Note 5)
= 500kHz, Mode 1 (Note 3),
CLK
25 ±0.3
25 ±0.8
25 ±0.9
%
%
S
f = 20kHz, Q = 5, V = 0.5V
,
●
●
O
IN
RMS
R1 = R3 = 49.9k, R2 = 10k
V = ±5V, f = 1MHz, Mode 1,
25 ±0.3
25 ±0.8
25 ±0.9
%
%
S
CLK
f = 40kHz, Q = 5, V = 1V
,
O
IN
RMS
R1 = R3 = 49.9k, R2 = 10K
Clock-to-Center Frequency Ratio,
Side-to-Side Matching (Note 5)
V = 4.75V, f = 500kHz, Q = 5 (Note 3)
●
●
±0.25
±0.25
±0.9
±0.9
%
%
S
CLK
V = ±5V, f
= 1MHz, Q = 5
S
CLK
Q Accuracy (Note 5)
V = 4.75V, f
= 500kHz, Q = 5 (Note 3)
CLK
= 1MHz, Q = 5
●
●
±1
±1
±3
±3
%
%
S
V = ±5V, f
S
CLK
f Temperature Coefficient
±1
±5
ppm/°C
ppm/°C
O
Q Temperature Coefficient
5
LTC1068 Series
ELECTRICAL CHARACTERISTICS LTC1068-25 (Complete Filter) VS = ±5V, TA = 25°V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC Offset Voltage (Note 5)
(See Table 1)
V = ±5V, f
= 1MHz, V
OS1
●
●
●
0
±15
mV
S
CLK
(DC Offset of Input Inverter)
V = ±5V, f = 1MHz, V
OS2
–2
–5
±25
±40
mV
mV
S
CLK
(DC Offset of First Integrator)
V = ±5V, f = 1MHz, V
S
CLK
OS3
(DC Offset of Second Integrator)
Clock Feedthrough
V = ±5V, f = 1MHz
0.25
5.6
mV
RMS
S
CLK
Max Clock Frequency (Note 6)
Power Supply Current
V = ±5V, Q ≤ 1.6, Mode 1
S
MHz
V = 3.14V, f
V = 4.75V, f
S
= 1MHz (Note 2)
= 1MHz (Note 3)
●
●
●
3.5
6.5
9.5
8
11
15
mA
mA
mA
S
CLK
CLK
V = ±5V, f
= 1MHz
S
CLK
The
●
denotes specifications which apply over the full operating
Note 4: Pin 7 (AGND) is the internal analog ground of the device. For
single supply applications this pin should be bypassed with a 1µF
capacitor. The biasing voltage of AGND is set with an internal resistive
divider from Pin 8 to Pin 23 (see Block Diagram).
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Production testing for single 3.14V supply is achieved by
using the equivalent dual supplies of ±1.57V.
Note 5: Side D is guaranteed by design.
Note 6: See Typical Performance Characteristics.
Note 3: Production testing for single 4.75V supply is achieved by
using the equivalent dual supplies of ±2.375V.
Table 1. Output DC Offsets One 2nd Order Section
MODE
V
V
V
V
V
OSN
OSBP
OSLP
1
1b
2
[(1/Q) + 1 + ||HOLP||] – V /Q
V
V
– V
OSN OS2
OS1
OS1
OS3
OS3
OS3
OS3
[(1/Q) + 1 + R2/R1] – V /Q
V
~(V
– V )(1 + R5/R6)
OSN OS2
OS3
[V (1 + R2/R1 + R2/R3 + R2/R4) – V (R2/R3)X
[R4/(R2 + R4)] + V [R2/(R2 + R4)]
V
V
V
– V
OSN OS2
OS1
OS3
OS2
3
V
V
[1 + R4/R1 + R4/R2 + R4/R3] – V (R4/R2) – V (R4/R3)
OS1 OS2 OS3
OS2
OS3
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
LTC1068
Maximum Q vs Center Frequency
(Modes 1, 1b, 2)
LTC1068-200
Maximum Q vs Center Frequency
(Modes 1, 1b, 2)
LTC1068
Maximum Q vs Center Frequency
(Modes 2, 3)
55
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
A: V = 3.3V, f
S
= 1.2MHz
= 3.2MHz
= 6.1MHz
CLK(MAX)
A. V = 3.3V, f
S
= 1.5MHz
= 3.4MHz
= 5.6MHz
CLK(MAX)
A. V = 3.3V, f
S
= 1MHz
= 3MHz
= 5MHz
CLK(MAX)
CLK(MAX)
CLK(MAX)
CLK(MAX)
B: V = 5V, f
B. V = 5V, f
B. V = 5V, f
S
S
CLK(MAX)
S
S
CLK(MAX)
S
S
CLK(MAX)
C: V = ±5V, f
C. V = ±5V, f
C. V = ±5V, f
(FOR MODE 2 R4 ≥ 10R2)
(FOR MODE 2 R4 < 10R2)
(FOR MODE 2, R4 ≥ 10R2)
A
B
C
A
B
C
A
B
C
0
0
0
0
20
30
40
50
60
70
16
CENTER FREQUENCY, f (kHz)
32
10
40
CENTER FREQUENCY, f (kHz)
0
8
12
20 24 28
0
20
30
50
60
4
10
CENTER FREQUENCY, f (kHz)
O
O
O
1068 G01
1068 G03
1068 G02
6
LTC1068 Series
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
LTC1068-200
Maximum Q vs Center Frequency
(Modes 2, 3)
LTC1068-50
Maximum Q vs Center Frequency
(Modes 1, 1b, 2)
LTC1068-50
Maximum Q vs Center Frequency
(Modes 2, 3)
55
50
45
40
35
30
25
20
15
10
5
55
50
45
40
35
30
25
20
15
10
5
55
50
45
40
35
30
25
20
15
10
5
A: V = 3.3V, f
S
= 1.2MHz
= 3.2MHz
= 6.1MHz
A: V = 3.3V, f
= 1.1MHz
CLK(MAX)
A: V = 3.3V, f
S
= 1.1MHz
= 2.1MHz
= 3.6MHz
CLK(MAX)
CLK(MAX)
S
CLK(MAX)
B: V = 5V, f
B: V = 5V, f
= 2.1MHz
= 3.6MHz
B: V = 5V, f
S
S
CLK(MAX)
CLK(MAX)
S
S
CLK(MAX)
CLK(MAX)
S
S
CLK(MAX)
C: V = ±5V, f
C: V = ±5V, f
C: V = ±5V, f
(FOR MODE 2, R4 < 10R2)
(FOR MODE 2, R4 ≥ 10R2)
(FOR MODE 2, R4 < 10R2)
C
B
C
B
A
B
C
A
A
0
0
0
0
8
12 16 20 24 28 32
0
8
12 16 20 24 28 32
0
8
12 16 20 24 28 32
4
4
4
CENTER FREQUENCY, f (kHz)
CENTER FREQUENCY, f (kHz)
CENTER FREQUENCY, f (kHz)
O
O
O
1068 G04
1068 G05
1068 G06
LTC1068-25
Maximum Q vs Center Frequency
(Modes 1, 1b, 2)
LTC1068-25
Maximum Q vs Center Frequency
(Modes 2, 3)
LTC1068 Center Frequency
Variation vs Clock Frequency
55
50
45
40
35
30
25
20
15
10
5
55
50
45
40
35
30
25
20
15
10
5
1.2
1.0
V
= ±5V
A: V = 3.3V, f
S
= 1.2MHz
= 3.4MHz
= 6.1MHz
CLK(MAX)
S
A: V = 3.3V, f
S
= 1MHz
= 3MHz
= 5MHz
CLK(MAX)
CLK(MAX)
CLK(MAX)
Q = 5, REFERENCE
B: V = 5V, f
B: V = 5V, f
S
S
CLK(MAX)
S
S
CLK(MAX)
CENTER FREQUENCY
WITH f
C: V = ±5V, f
C: V = ±5V, f
0.8
= 0.75MHz
(FOR MODE 2, R4 ≥ 10R2)
CLK
(FOR MODE 2, R4 < 10R2)
MODE 3
0.6
0.4
MODE 1
0.2
0
–0.2
–0.4
–0.6
B
B
C
C
A
A
0
0
0
64
96 128 160 192 224
0
64
96 128 160 192 224
32
32
0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25
CLOCK FREQUENCY (MHz)
CENTER FREQUENCY, f (kHz)
FREQUENCY, f (kHz)
O
O
1068 G07
1068 G08
1068 G09
LTC1068-200 Center Frequency
Variation vs Clock Frequency
LTC1068-50 Center Frequency
Variation vs Clock Frequency
LTC1068-25 Center Frequency
Variation vs Clock Frequency
0.4
0.3
0.20
0.15
1.8
1.3
0.8
0.3
V
= ±5V
S
MODE 1
MODE 3
Q = 5, REFERENCE
CENTER FREQUENCY
WITH f
0.10
= 0.5MHz
CLK
0.05
0.2
MODE 3
0
0.1
–0.05
–0.10
–0.15
–0.20
–0.25
MODE 1
MODE 1
0
V
= ±5V
V
= ±5V
S
S
Q = 5, REFERENCE
Q = 5, REFERENCE
MODE 3
1.5
–0.1
–0.2
CENTER FREQUENCY
CENTER FREQUENCY
WITH f
WITH f
= 0.5MHz
= 0.75MHz
CLK
CLK
0
0.5
1.0
1.25
1.5
1.75
2.0
0.5
1.0
2.0
2.5
3.0
3.5
0.75
0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25
CLOCK FREQUENCY (MHz)
CLOCK FREQUENCY (MHz)
CLOCK FREQUENCY (MHz)
1068 G11
1068 G12
1068 G10
7
LTC1068 Series
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
LTC1068/LTC1068-200
Noise vs Q
LTC1068-50 Noise vs Q
LTC1068-25 Noise vs Q
300
250
200
150
100
50
300
250
200
150
100
50
300
250
200
150
100
50
±5V
5V
±5V
5V
3.3V
3.3V
±5V
5V
3.3V
0
0
0
25 30
25 30
0
5
10 15 20
Q
35 40
0
5
10 15 20
Q
35 40
25 30
0
5
10 15 20
Q
35 40
1068 G14
1068 G13
1068 G15
Noise Increase vs R2/R4 Ratio
(Mode 3)
Noise Increase vs R5/R6 Ratio
(Mode 1b)
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
0
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
0
0.2
0.6
0.8 0.9
0
1.0 1.5 2.0
R5/R6 RATIO
2.5 3.0 3.5
0.3 0.4 0.5
0.7
1.0
0.5
R2/R4 RATIO
1068 G16
1068 G17
LTC1068/LTC1068-200/
LTC1068-25 Power Supply
Current vs Power Supply
LTC1068-50 Power Supply
Current vs Power Supply
10.5
9.5
8.5
8
7
6
5
70°C
25°C
70°C
25°C
–20°C
–20°C
7.5
6.5
5.5
4.5
4
3
2
7
9
10
7
9
10
3
4
5
6
8
3
4
5
6
8
TOTAL POWER SUPPLY (V)
TOTAL POWER SUPPLY (V)
LT1027 • TPCXX
1068 G19
8
LTC1068 Series
U
U
U
PIN FUNCTIONS
Power Supply Pins
Clock Input Pin
The V+ and V– pins should each be bypassed with a 0.1µF
capacitor to an adequate analog ground. The filter’s power
supplies should be isolated from other digital or high
voltage analog supplies. A low noise linear supply is
recommended. Using a switching power supply will lower
the signal-to-noise ratio of the filter. Figures 1 and 2 show
typical connections for dual and single supply operation.
Any TTL or CMOS clock source with a square-wave output
and 50% duty cycle (±10%) is an adequate clock source
for the device. The power supply for the clock source
should not be the filter’s power supply. The analog ground
for the filter should be connected to clock’s ground at a
single point only. Table 2 shows the clock’s low and high
level threshold values for dual or single supply operation.
Table 2. Clock Source High and Low Threshold Levels
Analog Ground Pin
POWER SUPPLY
HIGH LEVEL
≥ 1.53V
LOW LEVEL
≤ 0.53V
The filter’s performance depends on the quality of the
analog signal ground. For either dual or single supply
operation, an analog ground plane surrounding the pack-
age is recommended. The analog ground plane should be
connectedtoanydigitalgroundatasinglepoint.Forsingle
supply operation, AGND should be bypassed to the analog
ground plane with at least a 0.47µF capacitor (Figure 2).
Dual Supply = ±5V
Single Supply = 5V
Single Supply = 3.3V
≥ 1.53V
≤ 0.53V
≥ 1.20V
≤ 0.53V
Apulsedgeneratorcanbeusedasaclocksourceprovided
the high level ON time is at least 25% of the pulse period.
Sine waves are not recommended for clock input frequen-
cies less than 100kHz, since excessively slow clock rise or
fall times generate internal clock jitter (maximum clock
rise or fall time ≤ 1µs). The clock signal should be routed
from the right side of the IC package and perpendicular to
it to avoid coupling to any input or output analog signal
Two internal resistors bias the analog ground pin. For the
LTC1068, LTC1068-200 and LTC1068-25, the voltage at
the analog ground pin (AGND) for single supply is 0.5 × V+
and for the LTC1068-50 it is 0.435 × V+.
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ANALOG
GROUND
PLANE
ANALOG
GROUND
PLANE
3
3
DEVICE
LTC1068
LTC1068-200 10k 10k
LTC1068-25
LTC1068-50 11.3k 8.6k
R
R
B
A
4
4
–
V
5
5
LTC1068
0.1µF
6
6
+
V
7
7
AGND
V
LTC1068
R
R
B
A
0.1µF
8
8
+
V
0.1µF
9
9
0.47µF
10
11
12
13
14
10
11
12
13
14
(1µF FOR
STOPBAND
FREQUENCIES
≤1kHz)
STAR
SYSTEM
GROUND
STAR
SYSTEM
GROUND
200Ω
200Ω
CLOCK
SOURCE
CLOCK
SOURCE
DIGITAL GROUND
DIGITAL GROUND
FOR MODE 3, THE S NODE
SHOULD BE TIED TO PIN 7 (AGND)
1068 F01
1068 F02
Figure 1. Dual Supply Ground Plane Connections
Figure 2. Single Supply Ground Plane Connections
9
LTC1068 Series
U
U
U
PIN FUNCTIONS
path.A200ΩresistorbetweenclocksourceandPin11will
slow down the rise and fall times of the clock to further
reduce charge coupling (Figures 1 and 2).
–
LT®1354
1k
+
Output Pins
1068 F03
Each 2nd order section of an LTC1068 device has three
outputs that typically source 17mA and sink 6mA. Driving
coaxial cables or resistive loads less than 20k will degrade
the total harmonic distortion performance of any filter
design. When evaluating the distortion or noise perfor-
mance of a particular filter design implemented with a
LTC1068 device, the final output of the filter should be
buffered with a wideband, noninverting high slew rate
amplifier (Figure 3).
Figure 3. Wideband Buffer
In a printed circuit layout any signal trace, clock source
trace or power supply trace should be at least 0.1 inches
away from any inverting input pins
Summing Input Pins
Thesearevoltageinputpins.Ifused,theyshouldbedriven
with a source impedance below 5k. When they are not
used, they should be tied to the analog ground pin.
Inverting Input Pins
Thesepinsaretheinvertinginputsofinternalopampsand
are susceptible to stray capacitive coupling from low
impedance signal outputs and power supply lines.
Thesummingpinconnectionsdeterminethecircuittopol-
ogy (mode) of each 2nd order section. Please refer to
Modes of Operation.
W
BLOCK DIAGRAM
HPA/NA
(13)
BPA
(12)
LPA
(11)
DEVICE
LTC1068
LTC1068-200 10k 10k
LTC1068-25
LTC1068-50 11.3k 8.6k
R
R
B
A
INV A
(14)
–
+
+
+
+
+
+
Σ
–
∫
∫
∫
∫
∫
∫
∫
∫
AGND
(7)
+
*THE RATIO R /R VARIES ±2%
A
B
BPB
(3)
LPB
(4)
HPB/NB
(2)
SA
(10)
+
V
(8)
INV B
(1)
–
+
+
+
+
+
+
Σ
–
R *
A
CLK (21)
–
+
HPC/NC
(27)
LPC
(25)
BPC
(26)
R *
B
V
(23)
AGND (7)
SB
(5)
INV C
(28)
NC (6)
NC (9)
–
+
Σ
–
LPD
(18)
HPD/ND
(16)
BPD
(17)
NC (20)
NC (22)
SC
(24)
INV D
(15)
–
+
Σ
–
PIN 28-LEAD SSOP PACKAGE
1068 BD
SD
(19)
10
LTC1068 Series
W
U
MODES OF OPERATION
Linear Technology’s universal switched-capacitor filters
are designed for a fixed internal, nominal fCLK/fO ratio. The
fCLK/fO ratio is 100 for the LTC1068, 200 for the LTC1068-
200, 50 for the LTC1068-50 and 25 for the LTC1068-25.
FilterdesignsoftenrequirethefCLK/fO ratioofeachsection
to be different from the nominal ratio and in most cases
different from each other. Ratios other than the nominal
valuearepossiblewithexternalresistors.Operatingmodes
use external resistors, connected in different arrange-
ments to realize different fCLK/fO ratios. By choosing the
proper mode, the fCLK/fO ratio can be increased or de-
creased from the part’s nominal ratio.
Mode 1
In Mode 1, the ratio of the external clock frequency to the
center frequency of each 2nd order section is internally
fixed at the part’s nominal ratio. Figure 4 illustrates Mode
1 providing 2nd order notch, lowpass and bandpass
outputs. Mode 1 can be used to make high order Butter-
worth lowpass filters; it can also be used to make low Q
notches and for cascading 2nd order bandpass functions
tuned at the same center frequency. Mode 1 is faster than
Mode 3.
Please refer to the Operating Limits paragraph under Appli-
cations Information for a guide to the use of capacitor CC.
The choice of operating mode also effects the transfer
function at the HP/N pins. The LP and BP pins always give
thelowpassandbandpasstransferfunctionsrespectively,
regardless of the mode utilized. The HP/N pins have a
different transfer function depending on the mode used.
Mode 1 yields a notch transfer function. Mode 3 yields a
highpass transfer function. Mode 2 yields a highpass
notch transfer function (i.e., a highpass with a stopband
notch). Morecomplextransferfunctions, suchaslowpass
notch, allpassorcomplexzeros, areachievedbysumming
two or more of the LP, BP or HP/N outputs. This is
illustrated in sections Mode 2n and Mode 3a.
C
C
R3
R2
N
S
LP
BP
R1
V
–
IN
–
+
Σ
∫
∫
+
f
AGND
CLK
DEVICE
RATIO
f
=
; f = f
O
O
n
RATIO
LTC1068
100
R2
R1
R3
R1
R3
R2
LTC1068-200 200
Q = ; H = –
ON
; H
OBP
= –
LTC1068-50
LTC1068-25
50
25
H
= H
ON
OLP
1068 F04
Choosing the proper mode(s) for a particular application
is not trivial and involves much more than just adjusting
the fCLK/fO ratio. Listed here are four of the nearly twenty
modes available. To make the design process simpler and
quicker, Linear Technology has developed the FilterCAD
for Widows design software. FilterCAD is an easy-to-use,
powerful and interactive filter design program. The de-
signercanenterafewfilterspecificationsandtheprogram
producesafullschematic.FilterCADallowsthedesignerto
concentrate on the filter’s transfer function and not get
bogged down in the details of the design. Alternatively,
those who have experience with the Linear Technology
familyofpartscancontrolallofthedetailsthemselves. For
a complete listing of all the operating modes, consult the
appendices of the FilterCAD manual or the Help files in
FilterCAD. FilterCAD can be obtained free of charge on the
LinearTechnologywebsite(www.linear-tech.com)oryou
can order the FilterCAD CD-ROM by contacting Linear
Technology Marketing.
Figure 4. Mode 1, 2nd Order Filter Providing Notch,
Bandpass and Lowpass Outputs
Mode 1b
Mode 1b is derived from Mode 1. In Mode 1b (Figure 5)
two additional resistors R5 and R6 are added to lower the
amount of voltage fed back from the lowpass output into
the input of the SA (or SB) switched-capacitor summer.
This allows the filter’s clock-to-center frequency ratio to
be adjusted beyond the part’s nominal ratio. Mode 1b
maintains the speed advantages of Mode 1 and should be
consideredanoptimummodeforhighQdesignswithfCLK
to fCUTOFF (or fCENTER) ratios greater than the part’s
nominal ratio.
The parallel combination of R5 and R6 should be kept
below 5k.
Please refer to the Operating Limits paragraph under Appli-
cations Information for a guide to the use of capacitor CC.
11
LTC1068 Series
W
U
MODES OF OPERATION
C
C
C
C
R4
R3
R2
R6
N
R5
R3
R2
HP
S
LP
BP
S
LP
BP
R1
R1
V
–
+
O
IN
V
–
–
IN
–
+
+
Σ
∫
∫
Σ
∫
∫
+
1/4 LTC1068
DEVICE
RATIO
f
1
CLK
R2
R4
R2
R4
R3
R2
LTC1068
100
AGND
f
=
; Q = 1.005
AGND
(
)
RATIO
√
R3
√
LTC1068-200 200
1 –
(
)
(RATIO)(0.32)(R4)
LTC1068-50
LTC1068-25
50
25
f
CLK
R6
(R6 + R5)
f
=
;=f f
n O
O
RATIO
√
R3
R1
1
R2
= – ; H
R4
R1
1068 F05
H
= –
; H
= –
OHP
OBP
OLP
R2
R1
R3
= –
R3
R6
R1
R3
Q =
; H = – ; H
ON
OBP
1 –
(
)
R1
R2 (R6 + R5)
√
(RATIO)(0.32)(R4)
R2 R6 + R5
R1
DEVICE
RATIO
H
= –
OLP
(
)
R6
LTC1068
LTC1068-200 200
100
LTC1068-50
LTC1068-25
50
25
Figure 5. Mode 1b, 2nd Order Filter Providing Notch,
Bandpass and Lowpass Outputs
1068 F06
Figure 6. Mode 3, 2nd Order Section Providing
Highpass, Bandpass and Lowpass Outputs
Mode 3
In Mode 3, the ratio of the external clock frequency to the
center frequency of each 2nd order section can be ad-
justed above or below the parts nominal ratio. Figure 6
illustrates Mode 3, the classical state variable configura-
tion, providing highpass, bandpass and lowpass 2nd
orderfilterfunctions. Mode3isslowerthanMode1. Mode
3 can be used to make high order all-pole bandpass,
lowpass and highpass filters.
C
C
R4
R3
R2
HPN
S
LP
BP
R1
V
–
+
IN
–
+
Σ
∫
∫
Please refer to the Operating Limits paragraph under Appli-
cations Information for a guide to the use of capacitor CC.
DEVICE
RATIO
AGND
LTC1068
100
LTC1068-200 200
Mode 2
LTC1068-50
LTC1068-25
50
25
f
f
CLK
RATIO
CLK
R2
R4
f
=
; f =
n
1 +
O
RATIO
Mode 2 is a combination of Mode 1 and Mode 3, shown in
Figure7.WithMode2,theclock-to-centerfrequencyratio,
fCLK/fO, is always less than the part’s nominal ratio. The
advantage of Mode 2 is that it provides less sensitivity to
resistor tolerances than does Mode 3. Mode 2 has a
highpass notch output where the notch frequency de-
pends solely on the clock frequency and is therefore less
than the center frequency, fO.
√
1068 F07
R3
R2
R4
1
R3
Q = 1.005
1 +
(
)
R2
√
1–
(
)
(RATIO)(0.32)(R4)
R2
R1
1
R2
H
H
= –
(AC GAIN, f >> f ); H
O
= –
OHPN
(DC GAIN)
OHPN
R1
R2
1 +
(
)
R4
1
R3
R1
1
R2
R4
R2
R1
= –
; H
= –
OLP
OBP
R3
1 +
1–
(RATIO)(0.32)(R4)
Please refer to the Operating Limits paragraph under Appli-
cations Information for a guide to the use of capacitor CC.
Figure 7. Mode 2, 2nd Order Filter Providing Highpass
Notch, Bandpass and Lowpass Outputs
12
LTC1068 Series
U
W U U
APPLICATIONS INFORMATION
Operating Limits
mine the operating signal-to-noise ratio. Most of its fre-
quency contents lie within the filter passband and cannot
be reduced with post filtering. For a notch filter the noise
of the filter is centered at the notch frequency.
The Maximum Q vs Center Frequency (fO) graphs, under
Typical Performance Characteristics, define an upper limit
of operating Q for eachLTC1068 device2nd ordersection.
These graphs indicate the power supply, fO and Q value
conditions under which a filter implemented with an
LTC1068 device will remain stable when operated at
temperatures of 70°C or less. For a 2nd order section, a
bandpass gain error of 3dB or less is arbitrarily defined as
a condition for stability.
Thetotalwidebandnoise(µVRMS)isnearlyindependentof
the value of the clock. The clock feedthrough specifica-
tions are not part of the wideband noise.
For a specific filter design, the total noise depends on the
Q of each section and the cascade sequence. Please refer
to the Noise vs Q graphs under the Typical Performance
Characteristics.
When the passband gain error begins to exceed 1dB, the use
of capacitor CC will reduce the gain error (capacitor CC is
connected from the lowpass node to the inverting node of a
2nd order section). Please refer to Figures 4 through 7. The
value of CC can be best determined experimentally, and as a
guideitshouldbeabout5pFforeach1dBofgainerrorandnot
toexceed15pF. Whenoperatingan LTC1068 devicenearthe
limits defined by the Maximum Q vs Frequency graphs,
passbandgainvariationsof2dBormoreshouldbeexpected.
Aliasing
Aliasingisaninherentphenomenonofswitched-capacitor
filters and occurs when the frequency of the input signals
that produce the strongest aliased components have a
frequency, fIN, such as (fSAMPLING – fIN) that falls into the
filter’s passband. For an LTC1068 device the sampling
frequency is twice fCLK. If the input signal spectrum is not
band-limited, aliasing may occur.
Clock Feedthrough
Demonstration Circuit 104
ClockfeedthroughisdefinedastheRMSvalueoftheclock
frequency and its harmonics that are present at the filter’s
output pins. The clock feedthrough is tested with the
filter’s input grounded and depends on PC board layout
and on the value of the power supplies. With proper layout
techniques, the typical values of clock feedthrough are
listed under Electrical Characteristics.
DC104 is a surface mount printed circuit board for the
evaluation of Linear Technology’s LTC1068 product fam-
ily in a 28-lead SSOP package. The LTC1068 product
family consists of four monolithic clock-tunable filter
building blocks.
Demo Board 104 is available in four assembled versions:
Assembly104-AfeaturesthelownoiseLTC1068CG(clock-
to-centerfrequencyratio=100), assembly104-Bfeatures
thelownoiseLTC1068CG-200(clock-to-centerfrequency
ratio = 200), assembly 104-C features the high frequency
LTC1068CG-25(clock-to-centerfrequencyratio=25)and
assembly 104-D features the low power LTC1068CG-50
(clock-to-center frequency ratio = 50).
Any parasitic switching transients during the rising and
fallingedgesoftheincomingclockarenotpartoftheclock
feedthroughspecifications. Switchingtransientshavefre-
quency contents much higher than the applied clock; their
amplitude strongly depends on scope probing techniques
as well as grounding and power supply bypassing. The
clock feedthrough, can be greatly reduced by adding a
simple RC lowpass network at the final filter output. This
RC will completely eliminate any switching transients.
All DC104 boards are assembled with input, output and
power supply test terminals, a 28-lead SSOP filter device
(LTC1068CG Series), a dual op amp in an SO-8 for input
or output buffers and decoupling capacitors for the filter
and op amps. The filter and dual op amps share the power
Wideband Noise
The wideband noise of the filter is the total RMS value of
the device’s noise spectral density and is used to deter-
13
LTC1068 Series
U
W U U
APPLICATIONS INFORMATION
surface mount resistors. The printed circuit layout of
DC104 is arranged so that most of the resistor connec-
tions for one 8th order filter or two 4th order filters are
available on the board. A resistor makes a connection
between two filter nodes on the board and for most filter
designs, no wiring is required.
supply inputs to the board. Jumpers JPA to JPD on the
board configure the filter’s second order circuit modes,
jumper JP1 configures the filter for dual or single supply
operation and jumpers JP2 (A-D) to JP3 (A-D) configure
the op amp buffers as inverting or noninverting. Surface
mount pads are available on the board for 1206 size
DC104 Component Side Silkscreen
DC104 Component Side
DC104 Solder Side
14
LTC1068 Series
U
W U U
APPLICATIONS INFORMATION
15
LTC1068 Series
U
W U U
APPLICATIONS INFORMATION
A Surface Mount Printed Circuit Layout
the folowing figures for an 8th order elliptic bandpass
filter. The total board area of this 8th order filter is 1" by
0.8". No attempt was made to design the smallest possible
printed circuit layout.
A very compact surface mount printed circuit layout can
be designed with 0603 size surface mount resistors,
capacitors and a 28-pin SSOP of the LTC1068 product
family. An example of a printed circuit layout is shown in
70kHz Elliptic Bandpass Filter, fCENTER = fCLK/25 (Maximum fCENTER is 80kHz, VS = ±5V)
R
28k
R
R
23.2k
11.3k
H1
L2
H2
1
2
28
27
INV B
INV C
R22 4.99k
R32 107k
R21 4.99k
HPB/NB
HPC/NC
R11 29.4k
R31 24.9k
R41 20.5k
3
4
26
25
BPB
LPB
BPC
LPC
V
IN
R52
R51
4.99k
5
6
7
8
24
23
22
21
4.99k R62 56.2k
U1
LTC1068-25
SB
SC
–
V
–5V
NC
R61 11.3k
C2
NC
AGND
0.1µF
+
1.75MHz
CLK
5V
V
C1
0.1µF
9
20
19
R64 10k
NC
SA
NC
SD
10
R54
4.99k
R43 43.2k
R33 59k
11
12
13
14
18
LPA
LPD
BPD
R44 17.4k
R34 63.4k
R24 7.5k
17
16
15
BPA
R23 4.99k
HPA/NA
INV A
HPD/ND
INV D
R
L3
R
15.4k
H3
45.3K
V
OUT
1068 TA07a
Gain vs Frequency
FilterCAD Custom Inputs for fC = 70kHz
10
0
2nd ORDER SECTION
f (kHz)
O
Q
f (kHz)
TYPE
HPN
LPN
LPN
BP
MODE
2b
N
B
C
A
D
67.7624
67.0851
73.9324
73.3547
5.7236
20.5500
15.1339
16.3491
58.3011
–10
–20
–30
–40
–50
–60
–70
–80
–90
81.6810
81.0295
1bn
2n
2b
20
60
FREQUENCY (kHz)
80 90
30 40 50
70
100
1068 TA07b
16
LTC1068 Series
U
W U U
APPLICATIONS INFORMATION
Surface Mount Components
(Board Area = 1" × 0.8")
R
R11
H1
R21
R31
R22
R32
R51
R61
U1
R52
R41
R62
R64
C2
C1
R43
R33
R44
R34
R54
R23
R24
R
H2
R
L3
R
R
H3
L2
1068 TA08
Component Side
Solder Side
V
IN
R
H1
R11
R51
R61
R21
R31
R41
R22
R52
R32
GND
GND
–
R62
V
R64
R43
R33
R44
+
V
R54
R34
R24
R23
R
L3
R
H2
R
R
H3
L2
V
OUT
1068 TA09
1068 TA10
17
LTC1068 Series
U
TYPICAL APPLICATIONS
LTC1068-200 8th Order Linear Phase Lowpass, fCUTOFF = fCLK/400
for Ultralow Frequency Applications
R
R
L2
14.3k
L1
23.2k
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INV B
INV C
HPC/NC
BPC
R21 12.4k
R31 10k
R22 15.4k
R32 10k
R11
14.3k
HPB/NB
BPB
Gain and Group Delay
vs Frequency
3
V
IN
R41 15.4k
R52 5.11k
4
10
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
LPB
LPC
R62 9.09k
5
SB
SC
GAIN
–10
–20
–30
–40
–50
–60
–70
–80
–90
LTC1068-200
6
–
–5V
NC
V
7
AGND
NC
CLK
0.1µF
8
+
5V
400kHz
V
0.1µF
R64 9.09k
R54 5.11k
9
GROUP
DELAY
NC
NC
10
11
12
13
14
SA
SD
R43 12.4k
LPA
LPD
V
OUT
R33 12.4k
R23 10k
R34 10k
BPA
HPA/NA
INV A
BPD
R24 15.4k
0.1
1
10
HPD/ND
INV D
FREQUENCY (Hz)
1068 TA11b
R
L3
R
23.2k
B3
23.2k
1068 TA11a
FilterCAD Custom Inputs for fC = 1Hz
2nd ORDER SECTION
f (Hz)
O
Q
Q
TYPE
MODE
N
B
C
A
D
1.7947
1.6002
1.7961
1.6070
0.7347
0.5195
1.1369
0.5217
LP
LP
3
1b
3s
1b
1.0159
LPBP
LP
18
LTC1068 Series
U
TYPICAL APPLICATIONS
LTC1068-50 8th Order Linear Phase Lowpass, fCUTOFF = fCLK/50
for Single Supply Low Power Applictions. Maximum fCUTOFF is
20kHz with a 3.3V Supply and 40kHz with a 5V Supply
R
R
L2
A1
9.09k
56.2k
R
R
H2
34k
B1
13.3k
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INV B
INV C
HPC/NC
BPC
R21 20.5k
R31 10k
R22 43.2k
R32 43.2k
R42 196k
R11
22.6k
HPB/NB
BPB
Gain and Group Delay
vs Frequency
150
3
V
IN
R41 22.6k
4
10
0
LPB
LPC
5
140
SB
SC
GAIN
LTC1068-50
6
–
–10
–20
–30
–40
–50
–60
–70
–80
130
120
NC
V
7
AGND
NC
CLK
8
110
+
3.3V
500kHz
V
GROUP
DELAY
0.1µF
9
100
NC
NC
10
11
12
13
14
90
80
70
60
SA
SD
R43 48.7k
R44 34.8k
R34 14.3k
R24 16.9k
LPA
LPD
R33 12.7k
R23 10.7k
1µF
BPA
HPA/NA
INV A
BPD
HPD/ND
INV D
1
10
100
FREQUENCY (kHz)
1068 TA12b
R
L3
R
24.9k
B3
26.7k
V
OUT
1068 TA12a
FilterCAD Custom Inputs for fC = 10kHz
2nd ORDER SECTION
f (kHz)
Q
f (kHz)
Q
N
TYPE
MODE
4a3
2n
O
N
B
C
A
D
9.5241
11.0472
11.0441
6.9687
0.5248
1.1258
1.3392
0.6082
0.5248
AP
LPN
LPBP
LP
21.7724
1.5781
2s
3
19
LTC1068 Series
TYPICAL APPLICATIONS
U
LTC1068-25 8th Order Lowpass, fCUTOFF = fCLK/32,
Attenuation –50dB at (1.25)(fCUTOFF)and –60dB at
(1.5)(fCUTOFF). Maximum fCUTOFF = 120kHz
R
18.2k
R
R
40.2k
36.5k
H1
L2
R
L1
26.7k
H2
1
2
28
27
INV B
INV C
R22 10k
R21 10k
R31 10k
HPB/NB
HPC/NC
R11 32.4k
R32 32.4k
3
4
26
25
BPB
LPB
BPC
LPC
V
IN
Gain vs Frequency
R52
R61
2.21k
R51
4.99k
10
0
5
6
7
8
24
23
22
21
4.99k R62 5.9k
SB
SC
LTC1068-25
–
V
–5V
NC
0.1µF
–10
–20
–30
–40
–50
–60
–70
–80
NC
AGND
+
3.2MHz
CLK
5V
V
0.1µF
9
20
19
R64 3.16k
NC
SA
NC
SD
R63 8.45k
10
R54
4.99k
R53
4.99k
11
12
13
14
18
LPA
LPD
BPD
R33 118k
R34 15k
R24 10k
17
16
15
BPA
R23 10k
HPA/NA
INV A
HPD/ND
INV D
20
100
500
FREQUENCY (kHz)
1069 TA13b
R
L3
20.5K
R
H3
53.6k
V
OUT
1068 TA13a
FilterCAD Custom Inputs for fC = 100kHz
2nd ORDER SECTION
f (kHz)
Q
f (kHz)
TYPE
LPN
LPN
LPN
LP
MODE
1bn
1bn
1bn
1b
O
N
B
C
A
D
70.9153
94.2154
101.4936
79.7030
0.5540
2.3848
9.3564
0.9340
127.2678
154.1187
230.5192
20
LTC1068 Series
U
TYPICAL APPLICATIONS
LTC1068 8th Order Linear Phase Bandpass, fCENTER = fCLK/128,
Passband –3dB at (0.88)(fCENTER) and (1.12)(fCENTER). Maximum
fCENTER = 40kHz with ±5V Supplies
R
L1
63.4k
R
R
B2
16.2k
H1
7.5k
1
2
24
23
INV B
INV C
R21
R22
4.99k
4.99k
HPB/NB
BPB
HPC/NC
R11
R31
19.6k
R32
21.5k
26.1k
Gain vs Frequency
3
4
22
21
V
IN
BPC
LPC
R41
12.1k
10
0
LPB
R52
4.99k
R62
7.5k
LTC1068
–10
–20
–30
–40
–50
–60
–70
–80
–90
5
6
20
19
SB
AGND
SC
–
–5V
0.1µF
V
7
+
5V
V
0.1µF
18
17
CLK
SD
1.28MHz
R64 17.8k
8
9
SA
R43
10.7k
R54
4.99k
16
15
LPA
LPD
BPD
V
OUT
R33
14.7k
R34
28.7k
10
BPA
R23
4.99k
R24
4.99k
1
10
100
11
12
14
13
FREQUENCY (kHz)
HPA/NA
INV A
HPD/ND
INV D
1068 TA14b
R
R
L3
H3
14.7k
40.2k
24-Lead Package
1068 TA14a
FilterCAD Custom Inputs for fC = 10kHz
2nd ORDER SECTION
f (kHz)
Q
f (kHz)
TYPE
HPN
BP
MODE
O
N
B
C
A
D
8.2199
9.9188
8.7411
11.3122
2.6702
3.3388
2.1125
5.0830
4.4025
3a
1b
3a
1b
21.1672
LPN
BP
21
LTC1068 Series
U
TYPICAL APPLICATIONS
LTC1068 8th Order Linear Phase Bandpass, fCENTER = fCLK/100,
Passband –3dB at (0.88)(fCENTER) and (1.12)(fCENTER). Maximum
fCENTER = 50kHz with ±5V Supplies
R
R
B2
14.3k
L1
24.9k
R
H1
51.1k
1
2
24
23
INV B
INV C
R21
10k
R22
10k
HPB/NB
BPB
HPC/NC
BPC
R31
25.5k
R32
32.4k
R11
24.3k
Gain vs Frequency
3
4
22
21
V
IN
R42
26.1k
R41
107k
10
0
LPB
LPC
SC
5
6
7
20
19
–10
–20
–30
–40
–50
–60
–70
–80
–90
SB
–
AGND
V
–5V
0.1µF
+
5V
V
LTC1068
18
17
0.1µF
R63
2.32k
f
1MHz
CLK
8
9
SA
SD
R53
4.99k
R44
12.1k
R43
16.9k
16
15
LPA
BPA
LPD
BPD
R33
17.4k
R34
19.1k
10
R23
7.32k
R24
10k
1
10
100
11
12
14
13
HPA/NA
INV A
HPD/ND
INV D
FREQUENCY (kHz)
1068 TA15b
R
B3
24-Lead Package
V
OUT
18.7k
1068 TA15a
FilterCAD Custom Inputs for fC = 10kHz
2nd ORDER SECTION
f (kHz)
Q
f (kHz)
TYPE
LPN
BP
MODE
O
N
B
C
A
D
10.4569
11.7607
8.6632
9.0909
2.6999
3.9841
2.1384
1.8356
17.4706
2n
2
BP
2b
3
BP
22
LTC1068 Series
U
TYPICAL APPLICATIONS
LTC1068 8th Order Linear Phase Bandpass, fCENTER = fCLK/100,
Passband –3dB at (0.7)(fCENTER) and (1.3)(fCENTER), Superior Sinewave
Burst Response, Maximum fCENTER = 60kHz with ±5V Supplies
R
R
L2
10k
L1
348k
R
R
H2
200k
H1
11k
1
2
24
23
INV B
INV C
R21
R22
14.7k
18.2k
HPB/NB
BPB
HPC/NC
BPC
R31
10k
R32
10k
R11
11k
3
4
22
21
Gain vs Frequency
V
IN
R42
18.7k
R41
14.3k
10
0
LPC
SC
LPB
5
6
7
20
19
SB
–10
–20
–30
–40
–50
–60
–70
–80
–90
–
AGND
V
–5V
0.1µF
+
5V
V
LTC1068
18
17
0.1µF
f
1MHz
CLK
8
SA
SD
R43
R44
21.5k
10k
9
16
15
LPA
BPA
LPD
BPD
R33
11.3k
R34
17.8k
10
R23
21k
R24
15.4k
1
10
100
11
12
14
13
HPA/NA
INV A
HPD/ND
INV D
FREQUENCY (kHz)
1068 TA16b
R
H3
V
OUT
95.3k
R
L3
24-Lead Package
12.4k
1068 TA16a
FilterCAD Custom Inputs for fC = 10kHz
2nd ORDER SECTION
f (kHz)
Q
f (kHz)
Q
N
TYPE
HPN
LPN
LPN
BP
MODE
3a
O
N
B
C
A
D
10.1389
9.8654
9.8830
12.4097
0.7087
0.5540
0.5434
1.5264
1.7779
44.7214
27.7227
3a
3a
3
23
LTC1068 Series
U
TYPICAL APPLICATIONS
LTC1068-50 8th Order Linear Phase Bandpass, fCENTER = fCLK/40,
Passband –3dB at (0.8)(fCENTER) and (1.2)(fCENTER) for Single Supply
Low Power Applicaions. Maximum fCENTER = 25kHz with a Single 5V Supply
R
18.2k
R
17.8k
84.5k
H1
L2
R
H2
1
2
28
27
INV B
INV C
R22 11.3k
R21 10k
HPB/NB
HPC/NC
R11 36.5k
R31 30.1k
R41 10.7k
R32 29.4k
R42 10k
Gain vs Frequency
3
4
26
25
BPB
LPB
BPC
LPC
V
IN
10
0
R51
4.99k
R61
1.74k
5
6
7
8
24
23
SB
SC
LTC1068-50
–10
–20
–30
–40
–50
–60
–70
–
V
NC
22
21
NC
AGND
+
CLK
400kHz
5V
V
1µF
0.1µF
9
20
19
NC
SA
NC
SD
10
R44 22.1k
R43 12.1k
R33 26.7k
R23 10k
11
12
13
14
18
LPA
LPD
BPD
R34 28k
R24 10k
17
16
15
BPA
–80
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (kHz)
HPA/NA
INV A
HPD/ND
INV D
1068 TA17b
R
L3
R
H3
47.5k
15.8K
V
OUT
1068 TA17a
FilterCAD Custom Inputs for fC = 10kHz
2nd ORDER SECTION
f (kHz)
Q
f (kHz)
TYPE
HPN
LPN
LPN
BP
MODE
2b
O
N
B
C
A
D
8.7384
11.6756
10.8117
9.6415
4.0091
4.6752
4.2066
3.6831
4.0678
19.1786
16.0127
2n
2n
2
24
LTC1068 Series
U
TYPICAL APPLICATIONS
LTC1068-25 8th Order Bandpass, fCENTER = fCLK/32,
Passband –3dB at (0.965)(fCENTER) and (1.35)(fCENTER).
Maximum fCENTER = 80kHz with ±5V Supplies
R
118k
R
47.5k
B2
H1
1
2
28
27
INV B
INV C
R22 4.99k
R32 130k
R21 4.99k
R31 97.6k
HPB/NB
HPC/NC
R11 121k
3
4
26
25
Gain vs Frequency
BPB
LPB
BPC
LPC
V
IN
10
0
R52
R61
8.87k
R51
4.99k
5
6
7
8
24
23
22
21
4.99k R62 9.53k
SB
SC
LTC1068-25
–
–10
–20
–30
–40
–50
–60
–70
–5V
V
NC
0.1µF
NC
AGND
+
CLK
320kHz
5V
V
0.1µF
9
20
19
R64 6.98k
NC
SA
NC
SD
R63 6.49k
10
R54
4.99k
R53
4.99k
11
12
13
14
18
LPA
LPD
BPD
R33 124k
R34 102k
R24 4.99k
17
16
15
BPA
7.5
8
8.5
9 9.5 10 10.5 11
FREQUENCY (kHz)
11.5
12 12.5
R23 4.99k
HPA/NA
INV A
HPD/ND
INV D
1068 TA18b
R
L3
78.7K
V
OUT
1068 TA18a
FilterCAD Custom Inputs for fC = 10kHz
2nd ORDER SECTION
f (kHz)
Q
TYPE
BP
MODE
1b
O
B
C
A
D
10.2398
10.3699
9.6241
9.7744
15.6469
21.1060
18.6841
15.6092
BP
1b
LP
1b
LP
1b
25
LTC1068 Series
TYPICAL APPLICATIONS
U
LTC1068-200 8th Order Highpass, fCENTER = fCLK/200,
Attenuation –60dB at (0.6)(fCENTER).
Maximum fCUTOFF = 20kHz with ±5V Supplies
R
H1
11.8k
R
249k
L2
R
L1
66.5k
R
H2
20.5k
1
2
28
27
INV B
INV C
R22 21.5k
R21 10k
R31 16.5k
R41 11.3k
HPB/NB
HPB/NC
BPC
Gain vs Frequency
R11 18.2k
R32 10.2k
R42 18.7k
3
4
26
25
BPB
LPB
V
IN
10
0
LPC
5
6
7
8
24
23
SB
SC
–10
–20
–30
–40
–50
–60
–70
–80
LTC1068-200
–
V
–5V
NC
0.1µF
22
21
NC
AGND
+
CLK
200kHz
5V
V
0.1µF
9
20
19
R63 2.55k
NC
SA
NC
SD
10
R53
4.99k
R44 21k
R34 14.3k
R24 20.5k
R43 20.5k
11
12
13
14
18
LPA
LPD
BPD
R33 36.5k
R23 10k
17
16
15
BPA
0.2
1
10
FREQUENCY (kHz)
HPA/NA
INV A
HPD
1068TA19b
INV D
R
H3
10k
V
OUT
C23 [1/(2π • R23 • C23) = (160)(f
)]
CUTOFF
1068 TA19a
FilterCAD Custom Inputs for fC = 1kHz
2nd ORDER SECTION
f (kHz)
Q
f (kHz)
TYPE
HPN
HPN
HPN
HP
MODE
3a
O
N
B
C
A
D
0.9407
1.0723
0.9088
0.9880
1.5964
0.5156
3.4293
0.7001
0.4212
0.2869
0.5815
0.0000
3a
2b
3
26
LTC1068 Series
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.397 – 0.407*
(10.07 – 10.33)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
0.301 – 0.311
(7.65 – 7.90)
5
7
8
1
2
3
4
6
9 10 11 12 13 14
0.205 – 0.212**
(5.20 – 5.38)
0.068 – 0.078
(1.73 – 1.99)
0° – 8°
0.0256
(0.65)
BSC
0.005 – 0.009
(0.13 – 0.22)
0.022 – 0.037
(0.55 – 0.95)
0.002 – 0.008
(0.05 – 0.21)
0.010 – 0.015
(0.25 – 0.38)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
G28 SSOP 0694
N Package
24-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.265*
(32.131)
MAX
24
23
22
21
20
19
18
17
16
15
10
14
11
13
12
0.255 ± 0.015*
(6.477 ± 0.381)
3
4
5
6
7
8
9
1
2
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.020
(0.508)
MIN
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.325
–0.015
0.100 ± 0.010
(2.540 ± 0.254)
+0.889
8.255
N24 1197
(
)
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC1068 Series
TYPICAL APPLICATION
U
LTC1068-200 8th Order Notch, fNOTCH = fCLK/256, f – 3dB at (0.9) (fNOTCH) and (1.05)(fNOTCH),
Attenuation at fNOTCH Greater Than 70dB for fNOTCH in the Frequency Range 200Hz to 5kHz
C22 470pF
R
5.11k
H1
C21
R
5.11k
H2
470pF
1
2
28
27
INV B
INV C
R22 6.34k
R32 84.3k
R21 5.11k
HPB/NB
HPB/NC
R11 51.1k
R31 51.1k
R41 100k
3
4
26
25
BPB
LPB
BPC
LPC
V
IN
R
66.5k
R52
L2
R51
5.11k
R61
8.06k
5
6
7
8
24
23
22
21
5.11k R62 5.76k
SB
SC
LTC1068-200
–
V
–5V
CLK
NC
0.1µF
NC
AGND
+
CLK
f
= (256)(f
)
NOTCH
5V
V
0.1µF
9
20
19
R64 7.87k
NC
SA
R63
NC
SD
8.06k
10
R54
R53
5.11k
R43
178k
5.11k
11
12
13
14
18
LPA
LPD
BPD
R34 75k
17
16
15
BPA
R
G
R33 124k
R24 7.32k
15k
HPA/NA
INV A
HPD
R23 10k
INV D
R
5.11k
475k
H4
–
+
C23 470pF
R
H3
5.11k
R
L4
LT1354
V
OUT
1068 TA01
Gain vs Frequency
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0.8
0.9
1.0
1.1
IN NOTCH
1.2
)
RELATIVE FREQUENCY (f /f
1068 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
50:1 and 100:1 Clock-to-f Ratios, f to 100kHz, V = Up to ±7.5V
LTC1064
Universal Filter, Quad 2nd Order
O
O
S
LTC1067/LTC1067-50
LTC1164
Low Power, Dual 2nd Order
Rail-to-Rail, V = 3V to ±5V
S
Low Power Universal Filter, Quad 2nd Order
High Speed Universal Filter, Quad 2nd Order
50:1 and 100:1 Clock-to-f Ratios, f to 20kHz, V = Up to ±7.5V
O O S
LTC1264
20:1 Clock-to-f Ratio, f to 200kHz, V = Up to ±7.5V
O
O
S
1068fa LT/TP 0998 2K REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
LINEAR TECHNOLOGY CORPORATION 1996
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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