LTC1090AMJ_技术文档

LTC1090

Single Chip 10-Bit Data

Acquisition System

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FEATURES

DESCRIPTIO

The LTC^®1090 is a data acquisition component which

contains a serial I/O successive approximation A/D con-

verter. It uses LTCMOS^TMswitched capacitor technology

to perform either 10-bit unipolar, or 9-bit plus sign bipolar

A/D conversions. The 8-channel input multiplexer can be

configured for either single ended or differential inputs (or

combinations thereof). An on-chip sample and hold is

included for all single ended input channels.

■

Software Programmable Features:

Unipolar/Bipolar Conversions

4 Differential/8 Single Ended Inputs

MSB or LSB First Data Sequence

Variable Data Word Length

■

Built-In Sample and Hold

Single Supply 5V, 10V or ±5V Operation

Direct 4 Wire Interface to Most MPU Serial Ports and

All MPU Parallel Ports

30kHz Maximum Throughput Rate

■

The serial I/O is designed to be compatible with industry

standard full duplex serial interfaces. It allows either

MSB or LSB first data and automatically provides 2’s

complement output coding in the bipolar mode. The

output data word can be programmed for a length of 8, 10,

12 or 16 bits. This allows easy interface to shift registers

and a variety of processors.

■

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KEY SPECIFICATIO S

■

Resolution: 10 Bits

■

Total Unadjusted Error (LTC1090A): ±1/2LSB Max

■

Conversion Time: 22µs

The LTC1090A is specified with total unadjusted error

(including the effects of offset, linearity and gain errors)

less than ±0.5LSB.

■

Supply Current: 2.5mA Max, 1.0mA Typ

, LTC and LT are registered trademarks of Linear Technology Corporation.

LTCMOS is a trademark of Linear Technology Corp.

TheLTC1090isspecifiedwithoffsetandlinearitylessthan

±0.5LSB but with a gain error limit of ±2LSB for

applications where gain is adjustable or less critical.

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TYPICAL APPLICATIO

FOR 8051 CODE SEE

APPLICATIONS INFORMATION

SECTION

LTC1090

MPU

(e.g., 8051)

Linearity Plot

DIFFERENTIAL

INPUT

1.0

5V

BIPOLAR INPUT

0.5

0.0

5V

–5V

D

P1.1

P1.2

P1.3

P1.4

OUT

D

IN

T

SCLK

CS

–0.5

–1.0

UNIPOLAR

INPUTS

SERIAL DATA

LINK

0

512

1024

OUTPUT CODE

LTC1090 • TA02

(+)

(–)

– UNIPOLAR

INPUT

LTC1090 • TA01

–5V

1090fc

1

LTC1090

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ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Notes 1 and 2)

TOP VIEW

ORDER PART

Supply Voltage (V_CC) to GND or V^–................................ 12V

Negative Supply Voltage (V^–) ..................... –6V to GND

Voltage:

1

2

V

CC

20

19

18

17

16

15

14

13

12

11

CH0

CH1

NUMBER

ACLK

SCLK

3

CH2

LTC1090ACN

LTC1090CN

LTC1090CSW

Analog and Reference

4

D

IN

CH3

Inputs .................................... (V^–) –0.3V to V_CC0.3V

Digital Inputs ......................................... –0.3V to 12V

Digital Outputs ..............................– 0.3V to V_CC0.3V

Power Dissipation.............................................. 500mW

Operating Temperature Range

5

D

OUT

CH4

6

CS

CH5

+

7

REF

CH6

–

8

REF

CH7

–

9

V

COM

DGND

10

AGND

LTC1090AC/LTC1090C........................–40°C to 85°C

LTC1090AM/LTC1090M (OBSOLETE) ......–55°C to 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

SW PACKAGE

20-LEAD PLASTIC SO WIDE

N PACKAGE

20-LEAD PDIP

T

= 150°C, θ = 70°C/W

JA

JMAX

= 110°C, θ = 90°C/W

JA

LTC1090AMJ

LTC1090MJ

LTC1090ACJ

LTC1090CJ

J PACKAGE

20-LEAD CERDIP

T

= 150°C θ = 70° C/W

JMAX

JA

OBSOLETE PACKAGE

Consider the SW or N Package for Alternate Source

LTC1090 • POI01

Consult LTC Marketing for parts specified with wider operating temperature

ranges.

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RECO E DED OPERATI G CO DITIO S

LTC1090/LTC1090A

SYMBOL PARAMETER

CONDITIONS

MIN

MAX

UNITS

V

–

V

Positive Supply Voltage

Negative Supply Voltage

Shift Clock Frequency

A/D Clock Frequency

V = 0V

4.5

–5.5

0

10

CC

–

V

= 5V

0

V

CC

f

1.0

MHz

SCLK

ACLK

25°C

85°C

125°C

0.01

0.05

0.25

2.0

t

Total Cycle Time

See Operating Sequence

10 SCLK +

48 ACLK

Cycles

CYC

↓

t

Hold Time, CS Low After Last SCLK

V

= 5V

0

ns

hCS

hDI

CC

↑

Hold Time, D After SCLK

150

IN

↓

Setup Time CS Before Clocking in First Address Bit (Note 9)

2 ACLK Cycles

suCS

1µs

↑

t

Setup Time, D Stable Before SCLK

V

= 5V

400

127

200

44

ns

suDI

IN

CC

ACLK High Time

WHACLK

WLACLK

WHCS

ACLK Low Time

CS High Time During Conversion

ACLK

Cycles

1090fc

2

LTC1090

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CO VERTER A D ULTIPLEXER CHARACTERISTICS

The ■ denotes specifications which

apply over the full operating temperature range, otherwise specifications are T_A= 25°C. (Note 3)

LTC1090A

LTC1090

TYP

PARAMETER

Offset Error

CONDITIONS

(Note 4)

MIN

TYP

MAX

±0.5

±1.0

MIN

MAX

±0.5

±2.0

UNITS

LSB

■

Linearity Error

Gain Error

(Notes 4 and 5)

(Note 4)

LSB

Total Unadjusted Error

V

= 5.000V

LSB

REF

(Notes 4 and 6)

Reference Input Resistance

Analog and REF Input Range

10

kΩ

V

–

(Note 7)

(V ) – 0.05V to V 0.05V

CC

On Channel Leakage Current

(Note 8)

On Channel = 5V

Off Channel = 0V

■

1

–1

1

–1

1

µA

On Channel = 0V

Off Channel = 5V

µA

Off Channel Leakage Current

(Note 8)

On Channel = 5V

Off Channel = 0V

On Channel = 0V

Off Channel = 5V

AC ELECTRICAL CHARACTERISTICS

The ■ denotes specifications which apply over the full operating

temperature range, otherwise specification are T_A= 25°C. (Note 3)

LTC1090/LTC1090A

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

↓

t

Delay Time From CS to D

Analog Input Sample Time

Conversion Time

Data Valid

(Note 9)

2

ACLK Cycles

ACC

SMPL

CONV

dDO

dis

OUT

See Operating Sequence

See Test Circuits

5

SCLK Cycles

44

ACLK Cycles

↓

Delay Time, SCLK to D

Data Valid

■

250

300

400

50

450

ns

OUT

↑

Delay Time, CS to D

Hi-Z

140

150

OUT

↓

Delay Time, 2nd CLK to D

Enabled

ns

en

OUT

↓

Time Output Data Remains Valid After SCLK

hDO

f

D

OUT

D

OUT

Fall Time

See Test Circuits

■

90

60

300

ns

Rise Time

r

C

Input Capacitance

Analog Inputs

On Channel

Off Channel

65

5

pF

IN

Digital Inputs

1090fc

3

LTC1090

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DIGITAL A DDCELECTRICALCHARACTERISTICS

The ■ denotes specifications which apply

over the full operating temperature range, otherwise specification are T_A= 25°C. (Note 3)

LTC1090/LTC1090A

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

High Level lnput Voltage

Low Level Input Voltage

High Level lnput Current

Low Level Input Current

High Level Output Voltage

V

= 5.25V

= 4.75V

■

2.0

IH

IL

CC

IN

0.8

2.5

V

I

= V

µA

IH

IL

CC

= 0V

–2.5

IN

V

= 4.75V, l = 10µA

= 4.75V, l = 360µA

4.7

4.0

V

OH

CC

O

■

2.4

V

Low Level Output Voltage

Hi-Z Output Leakage

V

= 4.75V, l = 1.6mA

0.4

V

OL

CC

O

I

V

= V , CS High

■

3

–3

µA

OZ

OUT

CC

= 0V, CS High

I

Output Source Current

Output Sink Current

Positive Supply Current

Reference Current

V

= 0V

–10

10

mA

µA

SOURCE

SINK

CC

OUT

= V

CC

+

CS High, REF Open

= 5V

■

1.0

0.5

1

2.5

1.0

50

V

REF

–

REF

–

Negative Supply Current

CS High, V = –5V

–

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

below V or one diode drop above V . Be careful during testing at low

CC

V

levels (4.5V), as high level reference or analog inputs (5V) can cause

CC

Note 2: All voltage values are with respect to ground with DGND, AGND

this input diode to conduct, especially at elevated temperatures, and cause

errors for inputs near full-scale. This spec allows 50mV forward bias of

either diode. This means that as long as the reference or analog input does

not exceed the supply voltage by more than 50mV, the output code will be

correct. To achieve an absolute 0V to 5V input voltage range will therefore

require a minimum supply voltage of 4.950V over initial tolerance,

temperature variations and loading.

–

and REF wired together (unless otherwise noted).

–

Note 3: V = 5V, V + = 5V, V – = 0V, V = 0V for unipolar mode and

CC

REF

–5V for bipolar mode, ACLK = 2.0MHz, SCLK = 0.5MHz unless otherwise

specified.

Note 4: These specs apply for both unipolar and bipolar modes. In bipolar

mode, one LSB is equal to the bipolar input span (2V ) divided by 1024.

REF

For example, when V = 5V, 1LSB (bipolar) = 2(5V)/1024 = 9.77mV.

Note 5: Linearity error is specified between the actual end points of the

A/D transfer curve.

Note 6: Total unadjusted error includes offset, gain, linearity, multiplexer

and hold step errors.

Note 7: Two on-chip diodes are tied to each reference and analog input

which will conduct for reference or analog input voltages one diode drop

REF

Note 8: Channel leakage current is measured after the channel selection.

Note 9: To minimize errors caused by noise at the chip select input, the

internal circuitry waits for two ACLK falling edges after a chip select falling

edge is detected before responding to control input signals. Therefore, no

attempt should be made to clock an address in or data out until the

minimum chip select setup time has elapsed.

1090fc

4

LTC1090

TEST CIRCUITS

On and Off Channel Leakage Current

Voltage Waveforms for D_OUTDelay Time, t_dDO

SCLK

0.8V

5V

I

t

ON

dDO

2.4V

0.4V

ON CHANNELS

A

D

OUT

I

OFF

A

Voltage Waveforms for D_OUTRise and Fall Times, t_r, t_f

OFF

CHANNELS

POLARITY

2.4V

D

OUT

0.4V

LTC1090 • TC01

t

f

r

LTC1090 • TC02

Voltage Waveforms for t_enand t_dis

1

2

ACLK

2.0V

CS

D

OUT

90%

2.4V

0.4V

WAVEFORM 1

(SEE NOTE 1)

t

dis

en

D

OUT

WAVEFORM 2

(SEE NOTE 2)

10%

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT

IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL

NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT

IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL

LTC1090 • TC03

Load Circuit for t_disand t_en

Load Circuit for t_dDO, t_r, and t_f

1.4V

TEST

POINT

5V WAVEFORM 2

3k

100pF

D

OUT

D

TEST POINT

100pF

OUT

WAVEFORM 1

LTC1090 • TC04

LTC1090 • TC05

1090fc

5

LTC1090

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PI FU CTIO S

#

FUNCTION

DESCRIPTION

1-8

9

CH0 to CH7

COM

Analog Inputs

Common

The analog inputs must be free of noise with respect to AGND.

The common pin defines the zero reference point for all single ended inputs. It must be free

of noise and is usually tied to the analog ground plane.

10

11

12

13,14

15

16

17

18

19

DGND

AGND

DigitalGround

This is the ground for the internal logic. Tie to the ground plane.

AGND should be tied directly to the analog ground plane.

Tie V to most negative potential in the circuit. (Ground in single supply applications.)

The reference inputs must be kept free of noise with respect to AGND.

A logic low on this input enables data transfer.

The A/D conversion result is shifted out of this output.

The A/D configuration word is shifted into this input.

This clock synchronizes the serial data transfer.

This clock controls the A/D conversion process.

This supply must be kept free of noise and ripple by bypassing directly to the analog ground

plane.

Analog Ground

Negative Supply

Reference Inputs

Chip Select Input

Digital Data Output

Data Input

Shift Clock

A/D Conversion Clock

Positive Supply

–

V

–

+

REF , REF

CS

D

OUT

D

IN

SCLK

ACLK

20

V

CC

W

BLOCK DIAGRA

20

18

V

SCLK

CC

OUTPUT

16

INPUT SHIFT

REGISTER

17

SHIFT

D

OUT

IN

REGISTER

1

2

3

4

5

6

7

8

9

SAMPLE

AND HOLD

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

COMP

10-BIT

SAR

ANALOG

INPUT

MUX

10-BIT

CAPACITIVE

DAC

19

15

ACLK

10

11

AGND

12

13

–

14

+

CONTROL

AND

TIMING

–

DGND

V

REF

CS

LTC1090 • BD01

1090fc

6

LTC1090

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TYPICAL PERFOR A CE CHARACTERISTICS

Supply Current vs Supply Voltage

Supply Current vs Temperature

Reference Current vs Temperature

6

5

4

3

2

1

0

1.4

1.2

1.0

0.8

0.6

0.5

0.4

0.3

+

V

= 5V

REF OPEN

REF

ACLK = 2MHz

CS = V

= 25°C

CC

T

A

0.6

0.4

0.2

0.1

0

+

REF OPEN

ACLK = 2MHz

CS = 5V

V

= 5V

CC

4

6

7

8

9

10

50

100 125

50

100 125

5

–50 –25

0

25

75

–50 –25

0

25

75

SUPPLY VOLTAGE, V (V)

AMBIENT TEMPERATURE, T (°C)

CC

A

LTC1090 • TPC01

LTC1090 • TPC02

LTC1090 • TPC03

Unadjusted Offset Error vs

Reference Voltage

Linearity Error vs Reference

Voltage

Change in Gain Error vs

Reference Voltage

1.25

1.0

1.25

1.0

10

9

8

7

6

5

4

3

2

1

0

V

= 5V

V

= 5V

V

= 5V

CC

0.75

0.5

0.75

0.5

V

= 1mV

OS

0.25

0

0.25

0

V

= 0.5mV

OS

0

1

2

3

4

5

0

1

2

3

4

5

0.2

1.0

5.0

REFERENCE VOLTAGE, V

(V)

REFERENCE VOLTAGE, V

(V)

REF

REFERENCE VOLTAGE, V

(V)

REF

LTC1090 • TPC04

LTC1090 • TPC05

LTC1090 • TPC06

Change in Gain Error vs Supply

Voltage

Offset Error vs Supply Voltage

Linearity Error vs Supply Voltage

1.25

1.0

1.25

1.0

0.5

0.25

0

V

= 4V

V

= 4V

V

= 4V

REF

ACLK = 2MHz

= 1.25mV AT V = 5V

ACLK = 2MHz

V

OS

CC

0.75

0.5

0.75

0.5

–0.25

–0.5

0.25

0

0.25

0

4

6

7

8

9

10

4

6

7

8

9

10

4

6

7

8

9

10

5

SUPPLY VOLTAGE, V (V)

CC

LTC1090 • TPC07

LTC1090 • TPC08

LTC1090 • TPC09

1090fc

7

LTC1090

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TYPICAL PERFOR A CE CHARACTERISTICS

Change in Offset Error

vs Temperature

Change in Gain Error

vs Temperature

Change in Linearity Error

vs Temperature

0.6

0.5

0.4

0.3

0.6

0.5

0.4

0.3

0.6

0.5

0.4

0.3

V

= 5V

V

= 5V

CC

V

= 5V

CC

REF

ACLK = 2MHz

0.2

0.1

0

0.2

0.1

0

0.2

0.1

0

50

100 125

–50 –25

0

25

75

50

100 125

–50 –25

0

25

75

50

100 125

–50 –25

0

25

75

AMBIENT TEMPERATURE, T (°C)

A

LTC1090 • TPC11

LTC1090 • TPC10

LTC1090 • TPC12

Maximum Conversion Clock Rate

vs Temperature

Maximum Conversion Clock Rate

vs Supply Voltage

Maximum Conversion Clock Rate

vs Reference Voltage

7

6

5

4

3

2

1

0

5

6

5

4

3

V

= 5V

= 25°C

V

= 4V

= 25°C

CC

REF

T

A

4

3

2

1

0

2

1

0

V

= 5V

CC

= 5V

REF

8

10

0

1

2

3

4

5

4

5

6

7

9

50

100 125

–50 –25

0

25

75

REFERENCE VOLTAGE, V

(V)

SUPPLY VOLTAGE, V (V)

CC

AMBIENT TEMPERATURE, T (°C)

REF

A

LTC1090 • TPC14

LTC1090 • TPC15

LTC1090 • TPC13

Maximum Filter Resistor vs Cycle

Time

Sample-and-Hold Acquisition

Time vs Source Resistance

Maximum Conversion Clock Rate

vs Source Resistance

10

5

4

3

2

1

0

100k

V

T

= 5V

REF

CC

V

T

= 5V

= 25°C

R

CC

FILTER

= 5V

V

+

_

IN

REF

= 25°C

A

C

≥ 1µF

A

FILTER

10k

1k

0 TO 5V INPUT STEP

1

V

+

–

INPUT

IN

+

R

IN

SOURCE

V

+

_

INPUT

–

100

R

SOURCE

0.1

100

10

1k

10k

10

100

1k

(Ω)

10k

10

100

CYCLE TIME, t

1000

10k

+

R

(Ω)

(µs)

SOURCE

CYC

–

R

SOURCE

LTC1090 • TPC18

LTC1090 • TPC16

LTC1090 • TPC17

**MAXIMUM R_FILTERREPRESENTS THE FILTER RESISTOR VALVE AT WHICH A 0.1LSB SHIFT

CHANGE IN FULL SCALE ERROR FROM ITS VALUE AT R = 0 IS FIRST DETECTED.

*MAXIMUM ACLK FREQUENCY REPRESENTS THE ACLK FREQUENCY AT WHICH A 0.1LSB

SHIFT IN THE ERROR AT ANY CODE TRANSITION FROM ITS 2MHz VALVE IS FIRST DETECTED.

FILTER

1090fc

8

LTC1090

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TYPICAL PERFOR A CE CHARACTERISTICS

Digital Input Logic Threshold vs

Supply Voltage

Input Channel Leakage Current

vs Temperature

Noise Error vs Reference Voltage

2.0

1.75

1.5

1000

900

800

700

600

500

400

300

200

100

4

3

2

1

LTC1090 NOISE = 200µV PEAK-TO-PEAK

T

= 25°C

A

GUARANTEED

1.25

1.0

0.75

0.5

ON CHANNEL

OFF CHANNELS

0.25

0

0.2

1

5

–50

0

25

50

75 100 125

–25

4

5

6

7

8

9

10

REFERENCE VOLTAGE, V

(V)

SUPPLY VOLTAGE, V (V)

AMBIENT TEMPERATURE, T (°C)

REF

CC

A

LTC1090 • TPC21

LTC1090 • TPC20

LTC1090 • TPC19

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APPLICATIO S I FOR ATIO

The LTC1090 is a data acquisition component which

contains the following functional blocks:

DIGITAL CONSIDERATIONS

1. Serial Interface

1. 10-bit successive approximation capacitive

A/D converter

The LTC1090 communicates with microprocessors and

other external circuitry via a synchronous, full duplex,

four wire serial interface (see Operating Sequence). The

shift clock (SCLK) synchronizes the data transfer with

each bit being transmitted on the falling SCLK edge

and captured on the rising SCLK edge in both transmit-

ting and receiving systems. The data is transmitted and

received simultaneously (full duplex).

2. Analog multiplexer (MUX)

3. Sample and hold (S/H)

4. Synchronous, full duplex serial interface

5. Control and timing logic

Operating Sequence

(Example: Differential Inputs (CH3 to CH2), Bipolar, MSB First and 10-Bit Word Length)

t

CYC

1

5

8

10

SCLK

CS

DON’T CARE

t

CONV

SMPL

SGL/

DIFF

D

ODD/

SIGN

IN

MSBF

DON’T CARE

SEL1 SEL0 UNI

WL1 WL0

D

OUT

B9

(SB)

B8

B7

B6 B5

B4 B3

B2

B1

B0

SHIFT CONFIGURATION

WORD IN

SHIFT A/D RESULT OUT AND

NEW CONFIGURATION WORD IN

LTC1090 • AI01

1090fc

9

LTC1090

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APPLICATIO S I FOR ATIO

Datatransferisinitiatedbyafallingchipselect(CS)signal.

After the falling CS is recognized, an 8-bit input word

is shiftedintotheD_INinputwhichconfigurestheLTC1090

for the next conversion. Simultaneously, the result of the

previous conversion is output on the D_OUTline. At the end

of the data exchange the requested conversion begins and

CS should be brought high. After t_CONV, the conversion is

complete and the results will be available on the next data

transfer cycle. As shown below, the result of a conversion

is delayed by one CS cycle from the input word requesting

it.

Multiplexer (MLIX) Address

The first four bits of the input word assign the MUX

configuration for the requested conversion. For a given

channel selection, the converter will measure the voltage

between the two channels indicated by the + and – signs

in the selected row of Table 1. Note that in differential

mode (SGL/DIFF = O) measurements are limited to four

adjacent input pairs with either polarity. In single ended

mode, all input channels are measured with respect to

COM. Figure 1 shows some examples of multiplexer

assignments.

Table 1. Multiplexer Channel Selection

D

Word 1

Word 0

D

Word 2

Word 1

D

Word 3

Word 2

OUT

IN

MUX ADDRESS

SGL/ ODD SELECT

DIFFERENTIAL CHANNEL SELECTION

OUT

t

CONV

A/D

CONV

A/D

Data

Transfer

Data

Transfer

DIFF SIGN

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

+

–

7

–

+

Conversion

LTC1090 • AI02

0

1

+

–

+

–

2. Input Data Word

+

–

The LTC1090 8-bit input data word is clocked into the D_IN

input on the first eight rising SCLK edges after chip select

is recognized. Further inputs on the D_INpin are then

ignored until the next CS cycle. The eight bits of the input

word are defined as follows:

–

+

–

+

–

+

Unipolar/

Bipolar

Word Length

Data Input (D ) Word:

IN

MUX ADDRESS

SGL/ ODD/ SELECT

SINGLE ENDED CHANNEL SELECTION

SGL/

DIFF

ODD/

SIGN

SELECT

1

SELECT

0

UNI

MSBF

WL1

WL0

DIFF SIGN

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7 COM

1

0

1

+

–

MUX Address

MSB First/

LSB First

+

LTC1090• AI03

+

–

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4 Differential

8 Single Ended

Combinations of Differential and Single Ended

CHANNEL

0,1

CHANNEL

+

0

1

2

3

4

5

6

7

+( – )

–( + )

+

–

0,1

+( – )

–( + )

–

2,3

4,5

6,7

2,3

+

+( – )

–( + )

4

5

6

7

+

+( – )

–( + )

+

COM ( – )

COM (

)

–

LTC1090 • AI04B

LTC1090 • AI04C

LTC1090 • AI04A

Changing the MUX Assignment “On the Fly”

+

–

4,5

6,7

5,4

+

–

+

6

7

COM (UNUSED)

COM (

)

–

1ST CONVERSION

2ND CONVERSION

LTC1090 • AI04E

LTC1090 • AI04D

Figure 1. Examples of Multiplexer Options on the LTC1090

Unipolar/Bipolar (UNI)

input voltage. When UNI is a logical zero, a bipolar conver-

sion will result. The input span and code assignment for

each conversion type are shown in the figures below.

The fifth input bit (UNI) determines whether the conver-

sion will be unipolar or bipolar. When UNI is a logical one,

a unipolar conversion will be performed on the selected

Unipolar Transfer Curve (UNI = 1)

1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 0

0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0

V

IN

V

– 2LSB

V

REF

OV 1LSB

REF

LTC1090 • AI05

V

– 1LSB

REF

Bipolar Transfer Curve (UNI = 0)

0 1 1 1 1 1 1 1 1 1

0 1 1 1 1 1 1 1 1 0

–V +1LSB

REF

0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0

1LSB

–V

REF

V

IN

V

– 2LSB

V

1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 0

REF

–1LSB

V

– 1LSB

REF

–2LSB

1 0 0 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0 0 0

LTC1090 • AI06

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Unipolar Output Code (UNI = 1)

control the length of the present, not the next, D_OUTword.

WL1andWL0arenever“don’tcares”andmustbesetfor

the correct D_OUTword length even when a “dummy” D_IN

wordissent. Onanytransfercycle, thewordlengthshould

be made equal to the number of SCLK cycles sent by the

MPU.

INPUT VOLTAGE

(V = 5V)

OUTPUT CODE

INPUT VOLTAGE

REF

1111111111

V

– 1LSB

4.9951V

REF

1111111110

– 2LSB

4.9902V

•

WL1

WL0

OUTPUT WORD LENGTH

0000000001

0000000000

1LSB

0V

0.0049V

0V

0

1

0

1

0

1

8 Bits

10 Bits

12 Bits

16 Bits

Bipolar Output Code (UNI = 0)

INPUT VOLTAGE

OUTPUT CODE

INPUT VOLTAGE

(V

REF

= 5V)

Figure 2 shows how the data output (D_OUT) timing can be

controlled with word length selection and MSB/LSB first

format selection.

0111111111

V

– 1LSB

4.9902V

REF

0111111110

– 2LSB

4.9805V

•

3. Deglitcher

0000000001

0000000000

1111111111

1111111110

•

1LSB

0.0098V

0V

A deglitching circuit has been added to the Chip Select

input of the LTC1090 to minimize the effects of errors

causedbynoiseonthatinput.Thiscircuitignoreschanges

in state on the CS input that are shorter in duration than 1

ACLK cycle. After a change of state on the CS input, the

LTC1090 waits for two falling edges of the ACLK before

recognizing a valid chip select. One indication of CS low

recognition is the D_OUTline becoming active (leaving the

Hi-Z state). Note that the deglitching applies to both the

rising and falling CS edges.

–1LSB

–0.0098V

–2LSB

–0.0195V

•

1000000001

1000000000

– (V ) + 1LSB

–4.9902V

–5.000V

REF

– (V

)

REF

MSB First/LSB First Format (MSBF)

The output data of the LTC1090 is programmed for MSB

first or LSB first sequence using the MSBF bit. For MSB

first output data the input word clocked to the LTC1090

should always contain a logical one in the sixth bit location

(MSBF bit). Likewise for LSB first output data, the input

wordclockedtotheLTC1090shouldalwayscontainazero

in the MSBF bit location. The MSBF bit in a given D_INword

will control the order of the next D_OUTword. The MSBF bit

affects only the order of the output data word. The order

of the input word is unaffected by this bit.

ACLK

CS

HIGH Z

D

VALID OUTPUT

OUT

LOW CS RECOGNIZED

INTERNALLY

MSBF

OUTPUT FORMAT

LSB First

0

1

ACLK

CS

MSB First

Word Length (WL1, WL0)

The last two bits of the input word (WL1 and WL0) program

the output data word length of the LTC1090. Word lengths

of 8, 10, 12 or 16 bits can be selected according to the

following table. The WL1 and WL0 bits in a given D_INword

HIGH Z

D

OUT

HIGH CS RECOGNIZED

INTERNALLY

LTC1090 • AI07

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8-Bit Word Length

t

CONV

SMPL

CS

SCLK

1

8

(SB)

D

THE LAST TWO BITS

ARE TRUNCATED

OUT

B9 B8 B7

B6 B5

B3 B4

B4

B5

B3 B2

MSB FIRST

D

OUT

LSB FIRST

B0 B1 B2

B6 B7

LTC1090 • AI08A

10-Bit Word Length

t

SMPL

CONV

CS

SCLK

10

1

(SB)

D

OUT

MSB FIRST

B9 B8 B7

B6 B5

B4

B5

B3 B2 B1 B0

(SB)

B9

D

OUT

LSB FIRST

B0 B1 B2

B3 B4

B6 B7

B8

LTC1090 • AI08B

12-Bit Word Length

t

CONV

SMPL

CS

SCLK

10

12

1

(SB)

FILL

ZEROES

D

OUT

MSB FIRST

B9 B8 B7

B6 B5

B4

B5

B3 B2 B1 B0

(SB)

B9

D

OUT

B0 B1 B2

B3 B4

B6 B7

B8

*

LSB FIRST

LTC1090 • AI08C

16-Bit Word Length

t

CONV

SMPL

CS

SCLK

16

1

10

(SB)

FILL

ZEROES

D

OUT

MSB FIRST

B9 B8 B7

B6 B5

B3 B4

B4

B5

B3 B2 B1 B0

(SB)

B9

D

OUT

LSB FIRST

B0 B1 B2

B6 B7

B8

*

*IN UNIPOLAR MODE, THESE BITS ARE FILLED WITH ZEROES.

IN BIPOLAR MODE, THE SIGN BIT IS EXTENDED INTO THESE LOCATIONS

LTC1090 • AI08D

Figure 2. Data Output (D_OUT)Timing with Different Word Lengths

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4. CS Low During Conversion

In the normal mode of operation, CS is brought high

during the conversion time (see Figure 3). The serial port

ignores any SCLK activity while CS is high. The LTC1090

will also operate with CS low during the conversion. In this

mode, SCLK must remain low during the conversion as

shown in Figure 4. After the conversion is complete, the

D

_OUTline will become active with the first output bit. Then

the data transfer can begin as normal.

5. Microprocessor Interfaces

The LTC1090 can interface directly (without external hard-

ware) to most popular microprocessor (MPU) synchronous

t

SHIFT

MUX

ADDRESS

IN

SMPL

SAMPLE

ANALOG

INPUT

SHIFT RESULT OUT

AND NEW ADDRESS IN

40 TO 44 ACLK CYCLES

CS

SCLK

SEL SEL

SEL

1

SGL/

DIFF

SGL/

DIFF

ODD/

SIGN

ODD/

SIGN

SEL

0

D

UNI MSBF WL1 WL0

DON’T CARE

IN

1

0

D

OUT

B9

B8

B7

B6 B5

B4 B3

B2

B1

B0

B9

B8

B7

B6 B5

B4 B3

B2

B1

B0

LTC1090 • AI09

Figure 3. CS High During Conversion

t

SHIFT

MUX

ADDRESS

IN

SMPL

SAMPLE

ANALOG

INPUT

SHIFT RESULT OUT

AND NEW ADDRESS IN

40 TO 44 ACLK CYCLES

CS

SCLK

D

SCLK MUST REMAIN LOW

DON’T CARE

SEL SEL

SEL

1

SGL/

DIFF

SGL/

DIFF

ODD/

SIGN

ODD/

SIGN

SEL

0

UNI MSBF WL1 WL0

IN

1

0

D

OUT

B9

B8

B7

B6 B5

B4 B3

B2

B1

B0

B9

B8

B7

B6 B5

B4 B3

B2

B1

B0

LTC1090 • AI10

Figure 4. CS Low During Conversion

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serial formats (see Table 2). If an MPU without a serial

interfaceisused,then4oftheMPU’sparallelportlinescan

be programmed to form the serial link to the LTC1090.

Included here are three serial interface examples and one

example showing a parallel port programmed to form the

serial interface.

National MICROWIRE (COP420)

The COP420 transfers data MSB first and in 4-bit incre-

ments (nibbles). This is easily accommodated by setting

the LTC1090 to MSB first format and 12-bit word length.

The data output word is then received by the COP420 in

three 4-bit blocks with the final two unused bits filled with

zeroes by the LTC1090.

Table 2. Microprocessors with Hardware Serial Interfaces

Compatible with the LTC1090**

PART NUMBER

Motorola

TYPE OF INTERFACE

Hardware and Software Interface to National Semiconductor

COP420 Processor

MC6805S2, S3

MC68HC11

MC68HC05

SPI

LTC1090

CS

COP420

GO

SK

SO

SCLK

RCA

ANALOG

INPUTS

CDP68HC05

Hitachi

SPI

D

IN

D

SI

OUT

HD6305

HD63705

HD6301

HD63701

HD6303

SCI Synchronous

D

OUT

from LTC1090 stored in COP420 RAM

MSB*

National Semiconductor

COP400 Family

COP800 Family

NS8050U

MICROWIRE^†

MICROWIRE/PLUS

B9 B8 B7 B6

Location A

first 4 bits

†

HPC16000 Family

second 4 bits

third 4 bits

Location A + 1

Location A + 2

B5 B4 B3 B2

Texas Instruments

LSB

TMS7002

TMS7042

TMS70C02

TMS70C42

TMS32011*

TMS32020*

Serial Port

B1 B0 B0 B0

LTC1090 • AI11

*B9 is MSB in unipolar or sign bit in bipolar

*Requires external hardware

MNEMONIC

DESCRIPTION

**Contact LTC Marketing for interface information for processors not on

this list

MICROWIRE and MlCROWIRE/PLUS are trademarks of National

LEI

SC

Enable SlO

Set Carry flag

G0 is set to (CS goes low)

Load first 4 bits of D to ACC

Swap ACC with SIO reg. Starts SK Clk

Load 2nd 4 bits of D to ACC

Timing

Swap first 4 bits from A/D with ACC. SK continues.

Put first 4 bits in RAM (location A)

Timing

Swap 2nd 4 bits from A/D with ACC. SK continues.

Put 2nd 4 bits in RAM (location A + 1)

Clear Carry

†

OGI

LDD

XAS

LDD

NOP

XAS

XIS

NOP

XAS

XIS

RC

NOP

XAS

XIS

OGI

LEI

Semiconductor Corp.

IN

Serial Port Microprocessors

IN

Most synchronous serial formats contain a shift clock

(SCLK)andtwodatalines,onefortransmittingandonefor

receiving. In most cases data bits are transmitted on the

falling edge of the clock (SCLK) and captured on the rising

edge. However, serial port formats vary among MPU

manufacturers as to the smallest number of bits that can

be sent in one group (e.g., 4-bit, 8-bit or 16-bit transfers).

They also vary as to the order in which the bits are

transmitted (LSB or MSB first). The following examples

showhowtheLTC1090accommodatesthesedifferences.

Timing

Swap 3rd 4 bits from A/D with ACC. SK off

Put 3rd 4 bits in RAM (location A + 2)

G0 is set to 1 (CS goes high)

Disable SlO

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Motorola SPI (MC68HC05C4)

Hitachi Synchronous SCI (HD63705)

The MC68HC05C4 transfers data MSB first and in 8-bit

increments. Programming the LTC1090 for MSB first

format and 16-bit word length allows the 10-bit data

output to be received by the MPU as two 8-bit bytes with

the final 6 unused bits filled with zeroes by the LTC1090.

The HD63705 transfers serial data in 8-bit increments,

LSB first. To accommodate this, the LTC1090 is

programmed for 16-bit word length and LSB first format.

The 10-bit output data is received by the processor as two

8-bit bytes, LSB first. The LTC1090 fills the final 6 unused

bits (after the MSB) with zeroes in unipolar mode and with

the sign bit in bipolar mode.

Hardware and Software Interface to Motorola MC68HC05C4

Processor

Hardware and Software Interface to Hitachi HD63705 Processor

LTC1090

CS

MC68HCO5C4

CO

LTC1090

CS

HD63705

C0

SCK

SCLK

ANALOG

INPUTS

D

MOSI

CK

IN

SCLK

ANALOG

INPUTS

D

T

X

MISO

OUT

IN

D

R

X

OUT

D

OUT

from LTC1090 stored in MC68HCO5C4 RAM

MSB*

D

OUT

from LTC1090 stored in HD63705 RAM

LSB

B9 B8 B7 B6 B5 B4 B3 B2

LSB

Location A

byte 1

B7 B6 B5 B4 B3 B2 B1 B0

Sign

Location A

byte 1

Location A + 1

B1 B0

0

byte 2

Location A + 1

B9 B9 B9 B9 B9 B9 B9 B8 byte 2

LTC1090 • AI12

*B9 is MSB in unipolar or sign bit in bipolar

Bipolar

LSB

MNEMONIC

DESCRIPTION

C0 is cleared (CS goes Low)

B7 B6 B5 B4 B3 B2 B1 B0

MSB

Location A

byte 1

byte 2

BCLR n

LDA

STA

↑

NOP

↓

LDA

STA

↑

NOP

↓

BSET n

LDA

STA

Load D for LTC1090 into ACC

IN

0

0 0

0

0 B9 B8

Location A + 1

Load D from ACC to SPI data reg. Start SCK

IN

Unipolar

LTC1090 • AI13

8 NOPs for timing

MNEMONIC

DESCRIPTION

Load contents of SPI status reg. into ACC

Load LTC1090 D

from SPI data reg. into ACC (byte 1)

into RAM (location A)

OUT

LDA

BCLR n

STA

Load D word for LTC1090 into ACC from RAM

C0 cleared (CS goes low)

Load D word for LTC1090 into SCI data reg. from ACC

and start clocking data (LSB first)

IN

OUT

Start next SPl cycle

IN

6 NOPs for timing

↑

NOP

↓

6 NOPs for timing

C0 is set (CS goes high)

Load contents of SPI status reg. into ACC

LDA

Load contents of SCI data reg. into ACC (byte 1)

Start next SCI cycle

Load LTC1090 D

from SPI data reg. into ACC (byte 2)

into RAM (location A + 1)

OUT

STA

Load LTC1090 D

word into RAM (Location A)

OUT

NOP

BSET n

LDA

Timing

C0 set (CS goes high)

Load contents of SCI data reg. into ACC (byte 2)

Load LTC1090 D word into RAM (Location A + 1)

STA

OUT

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8051 Code

DESCRIPTION

Parallel Port Microprocessors

MNEMONIC

When interfacing the LTC1090 to an MPU which has a

parallel port, the serial signals are created on the port with

software. Three MPU port lines are programmed to create

the CS, SCLK and D_INsignals for the LTC1090. A fourth

port line reads the D_OUTline. An example is made of the

Intel 8051/8052/80C252 family.

MOV PI,#02H

Initialize port 1 (bit 1 is made

an input)

SCLK goes low

CS goes high

D word for the LTC1090 is

placed in ACC.

CS goes low

Load counter

CLR P1.3

SETB P1.4

CONTINUE: MOV A,#0DH

IN

CLR P1.4

MOV R4,#08

NOP

MOV C, P1.1

RLC A

MOV P1.2, C

SETB P1.3

CLR P1.3

DJNZ R4, LOOP

MOV R2, A

MOV C, P1.1

CLR A

RLC A

SETB P1.3

CLR P1.3

MOV C, P1.1

RRC A

Intel 8051

Delay for deglitcher

Read data bit into carry

Rotate data bit into ACC

LOOP:

To interface to the 8051, the LTC1090 is programmed for

MSB first format and 10-bit word length. The 8051 gener-

ates CS, SCLK and D_INon three port lines and reads D_OUT

on the fourth.

Output D bit to LTC1090

IN

SCLK goes high

SCLK goes low

Next bit

Store MSBs in R2

Read data bit into carry

CIear ACC

Rotate data bit into ACC

SCLK goes high

SCLK goes low

Read data bit into carry

Rotate right into ACC

Store LSBs in R3

SCLK goes high

SCLK goes low

Hardware and Software Interface to Intel 8051 Processor

LTC1090

8051

D

P1.1

OUT

D

P1.2

P1.3

IN

ANALOG

INPUTS

SCLK

CS

P1.4

ALE

MOV R3, A

SETB P1.3

CLR P1.3

ACLK

SETB P1.4

MOV R5,#07H

DJNZ R5, DELAY

CS goes high

Load counter

Delay for LTC1090 to perform

conversion

Repeat program

D

from LTC1090 stored in 8051 RAM

OUT

DELAY:

MSB*

AJMP CONTINUE

R2

R3

B9 B8 B7 B6 B5 B4 B3 B2

LSB

B1 B0

0

*B9 is MSB in unipolar or sign bit in bipolar

2

1 0

OUTPUT PORT

SERIAL DATA

3-WIRE SERIAL

3

INTERFACE TO OTHER

PERIPHERALS OR LTC1090s

3

MPU

CS

LTC1090

8 CHANNELS

LTC1090 • AI14

Figure 5. Several LTC1090’s Sharing One 3-Wire Serial Interface

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6. Sharing the Serial Interface

V

CC

4.7µF TANTALUM

The LTC1090 can share the same 3-wire serial interface

withotherperipheralcomponentsorotherLTC1090s(see

Figure 5). In this case, the CS signals decide which

LTC1090 is being addressed by the MPU.

1

20

ANALOG CONSIDERATIONS

1. Grounding

The LTC1090 should be used with an analog ground plane

and single point grounding techniques.

Pin11(AGND)shouldbetieddirectlytothisgroundplane.

Pin 10 (DGND) can also be tied directly to this ground

plane because minimal digital noise is generated within

the chip itself.

V –

ANALOG

GROUND

PLANE

10

11

Pin 20 (V_CC) should be bypassed to the ground plane with

a 4.7µF tantalum with leads as short as possible. Pin 12

(V^–) should be bypassed with a 0.1µF ceramic disk. For

single supply applications, V^–can be tied to the ground

plane.

0.1µF CERAMIC DISK

LTC1090 • AI15

Figure 6. Example Ground Plane for the LTC1090

Itisalsorecommendedthatpin13(REF^–)andpin9(COM)

be tied directly to the ground plane. All analog inputs

should be referenced directly to the single point ground.

Digital inputs and outputs should be shielded from and/or

routed away from the reference and analog circuitry.

Figure6showsanexampleofanidealgroundplanedesign

for a two sided board. Of course this much ground plane

will not always be possible, but users should strive to get

as close to this ideal as possible.

HORIZONTAL: 10µs/DIV

Figure 7. Poor V_CCBypassing. Noise and Ripple

can Cause A/D Errors

2. Bypassing

For good performance, V_CCmust be free of noise and

ripple. Any changes in the V_CCvoltage with respect to

analog ground during a conversion cycle can induce

errorsornoiseintheoutputcode. V_CCnoiseandripplecan

bekeptbelow1mVbybypassingtheV_CCpindirectlytothe

analog ground plane with a 4.7µF tantalum with leads as

shortaspossible. Figures7and8showtheeffectsofgood

and poor V_CCbypassing.

HORIZONTAL: 10µs/DIV

Figure 8. Good V_CCBypassing Keeps Noise and Ripple

on V_CCBelow 1mV

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“+” Input Settling

3. Analog Inputs

This input capacitor is switched onto the “+” input during

the sample phase (t_SMPL, see Figure 10). The sample

phasestartsatthe4thSCLKcycleandlastsuntilthefalling

edge of the last SCLK (the 8th, 10th, 12th or 16th SCLK

cycle depending on the selected word length). The voltage

on the “+” input must settle completely within this sample

time. Minimizing R_SOURCE⁺and C1 will improve the input

settling time. If large “+” input source resistance must be

used, the sample time can be increased by using a slower

SCLK frequency or selecting a longer word length. With

the minimum possible sample time of 4µs, R_SOURCE⁺< 2k

and C1 < 20pF will provide adequate settling.

Because of the capacitive redistribution A/D conversion

techniques used, the analog inputs of the LTC1090 have

capacitive switching input current spikes. These current

spikes settle quickly and do not cause a problem.

However, if large source resistances are used or if slow

settling op amps drive the inputs, care must be taken to

insure that the transients caused by the current spikes

settle completely before the conversion begins.

Source Resistance

The analog inputs of the LTC1090 look like a 60pF capaci-

tor (C_IN) in series with a 500Ω resistor (R_ON) as shown in

Figure 9. C_INgets switched between the selected “+” and

“–” inputs once during each conversion cycle. Large

external source resistors and capacitances will slow the

settling of the inputs. It is important that the overall RC

time constants be short enough to allow the analog inputs

to completely settle within the allowed time.

“–” Input Settling

Attheendofthesamplephasetheinputcapacitor switches

to the “–” input and the conversion starts (see Figure 10).

During the conversion, the “+” input voltage is effectively

“held” by the sample and hold and will not affect the

conversion result. However, it is critical that the “–” input

voltage be free of noise and settle completely during the

first four ACLK cycles of the conversion time. Minimizing

“

+

”

+

INPUT

R

SOURCE

+

V

IN

4TH SCLK

= 500Ω

R

C1

ON

–

R_SOURCEand C2 will improve settling time. If large

“

–

”

–

C

= 60pF

INPUT

“–”inputsourceresistancemustbeused,thetimeallowed

for settling can be extended by using a slower ACLK

R

IN

SOURCE

LAST SCLK

LTC1090

–

V

IN

C2

–

frequency. At the maximum ACLK rate of 2MHz, R_SOURCE

< 1kΩ and C2 < 20pF will provide adequate settling.

LTC1090 • AI16

Figure 9. Analog Input Equivalent Circuit

SAMPLE

“ + ” INPUT MUST

SETTLE DURING THIS TIME

HOLD

MUX ADDRESS

SHIFTED IN

t

SMPL

CS

SCLK

ACLK

LAST SCLK (8TH, 10TH, 12TH OR 16TH DEPENDING ON WORK LENGTH)

1

2

3

4

1

2

3

4

1ST BIT

TEST

“ – ” INPUT MUST SETTLE

DURING THIS TIME

“ + ” INPUT

“ – ” INPUT

LTC1090 • AI17

Figure 10. “+” and “–” Input Settling Windows

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19

LTC1090

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APPLICATIO S I FOR ATIO

Input Op Amps

When driving the analog inputs with an op amp it is

important that the op amp settle within the allowed time

(see Figure 10). Again, the “+” and “–” input sampling

times can be extended as described above to accommo-

date slower op amps. Most op amps including the LT1006

and LT1013 single supply op amps can be made to settle

well even with the minimum settling windows of 4µs (“+”

input) and 2µs (“–” input) which occur at the maximum

clock rates (ACLK = 2MHz and SCLK = 1MHz). Figures 11

and 12 show examples of adequate and poor op amp

settling.

eliminated by increasing the cycle time as shown in the

typical curve of Maximum Filter Resistor vs Cycle Time.

I

DC

R

FILTER

V

“ + ”

IN

LTC1090

C

FILTER

–

“

”

LTC1090 • AI18

Figure 13. RC Input Filtering

Input Leakage Current

Input leakage currents can also create errors if the source

resistancegetstoolarge.Forinstance,themaximuminput

leakage specification of 1µA (at 125°C) flowing through a

source resistance of 1kΩ will cause a voltage drop of 1mV

or 0.2LSB. This error will be much reduced at lower

temperatures because leakage drops rapidly (see typical

curve of Input Channel Leakage Current vs Temperature).

HORIZONTAL: 1µs/DIV

Figure 11. Adequate Settling of Op Amp Driving Analog Input

Noise Coupling into Inputs

High source resistance input signals (>500Ω) are more

sensitivetocouplingfromexternalsources.Itispreferable

to use channels near the center of the package (i.e., CH2 to

CH7) for signals which have the highest output resistance

because they are essentially shielded by the pins on the

package ends (DGND and CH0). Grounding any unused

inputs (especially the end pin, CH0) will also reduce

outside coupling into high source resistances.

HORIZONTAL: 20µs/DIV

Figure 12. Poor Op Amp Settling can Cause A/D Errors

RC Input Filtering

It is possible to filter the inputs with an RC network as

shown in Figure 13. For large values of C_F(e.g., 1µF), the

capacitive input switching currents are averaged into a net

DC current. Therefore, a filter should be chosen with a

small resistor and large capacitor to prevent DC drops

across the resistor. The magnitude of the DC current is

approximatelyl_DC=60pFxV_IN/t_CYCandisroughlypropor-

tional to V_IN. When running at the minimum cycle time of

33µs, theinputcurrentequals9µAatV_IN=5V. Inthiscase,

afilterresistorof50Ωwillcause0.1LSBoffull-scaleerror.

If a larger filter resistor must be used, errors can be

4. Sample-and-Hold

Single Ended Inputs

The LTC1090 provides a built-in sample and hold (S&H)

function for all signals acquired in the single ended mode

(COM pin grounded). This sample and hold allows the

LTC1090 to convert rapidly varying signals (see typical

curveofS&HAcquisitionTimevsSourceResistance). The

input voltage is sampled during the t_SMPLtime as shown

in Figure 10. The sampling interval begins after the fourth

1090fc

20

LTC1090

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APPLICATIO S I FOR ATIO

U

MUX address bit is shifted in and continues during the When driving the reference inputs, three things should be

remainder of the data transfer. On the falling edge of the kept in mind:

final SCLK, the S&H goes into hold mode and the conver-

1. The source resistance (R_OUT) driving the reference

sion begins. The voltage will be held on either the 8th,

inputs should be low (less than 1Ω) to prevent DC

10th, 12th or 16th falling edge of the SCLK depending on

the word length selected.

(I_REF).

drops caused by the 1mA maximum reference current

Differential Inputs

2. Transients on the reference inputs caused by the

capacitive switching currents must settle completely

during each bit test (each 4 ACLK cycles). Figures 15

and 16 show examples of both adequate and poor

settling. Using a slower ACLK will allow more time for

the reference to settle. However, even at the maximum

ACLK rate of 2MHz most references and op amps can

be made to settle within the 2µs bit time.

With differential inputs or when the COM pin is not tied to

ground, the A/D no longer converts just a single voltage

but rather the difference between two voltages. In these

cases,thevoltageontheselected“+” inputisstillsampled

and held and therefore may be rapidly time varying just as

in single ended mode. However, the voltage on the se-

lected “–” input must remain constant and be free of noise

and ripple throughout the conversion time. Otherwise, the 3. It is recommended that the REF^–input be tied directly

differencing operation may not be performed accurately.

The conversion time is 44 ACLK cycles. Therefore, a

change in the “–” input voltage during this interval can

“–” input this error would be:

totheanaloggroundplane.IfREF^–isbiasedatavoltage

other than ground, the voltage must not change during

a conversion cycle. This voltage must also be free of

noise and ripple with respect to analog ground.

V_{ERROR (MAX)}= V_PEAKx 2 x π x f(“–”) x 44/f_ACLK

+

REF

Where f(“–”) is the frequency of the “–” input voltage,

V_PEAKis its peak amplitude and f_ACLKis the frequency of

theACLK. InmostcasesV_ERRORwillnotbesignificant. For

a 60Hz signal on the “–” input to generate a 1/4LSB error

(1.25mV) with the converter running at ACLK = 2MHz, its

peak value would have to be 150mV.

14

EVERY 4 ACLK CYCLES

R

OUT

ON

10k

TYP

V

–

REF

13

5pF – 30pF

LTC1090

LTC1090 • AI19

Figure 14. Reference Input Equivalent Circuit

5. Reference Inputs

The voltage between the reference inputs of the LTC1090

defines the voltage span of the A/D converter. The refer-

ence inputs look primarily like a 10kΩ resistor but will

have transient capacitive switching currents due to the

switched capacitor conversion technique (see Figure 14).

During each bit test of the conversion (every 4 ACLK

cycles), a capacitive current spike will be generated on the

reference pins by the A/D. These current spikes settle

quickly and do not cause a problem. However, if slow

settling circuitry is used to drive the reference inputs, care

must be taken to insure that transients caused by these

current spikes settle completely during each bit test of the

conversion.

HORIZONTAL: 1µs/DIV

Figure 15. Adequate Reference Settling

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21

LTC1090

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APPLICATIO S I FOR ATIO

voltage. The offset (which is typically a fixed voltage)

becomes a larger fraction of an LSB as the size of the LSB

is reduced. The typical curve of Unadjusted Offset Error vs

Reference Voltage shows how offset in LSBs is related to

reference voltage for a typical value of V_OS. For example,

a V_OSof 0.5mV which is 0.1LSB with a 5V reference

becomes 0.5LSB with a 1V reference and 2.5LSBs with a

0.2V reference. If this offset is unacceptable, it can be

corrected digitally by the receiving system or by offsetting

the “–” input to the LTC1090.

HORIZONTAL: 1µs/DIV

Figure 16. Poor Reference Settling Can Cause A/D Errors

6. Reduced Reference Operation

Noise with Reduced V_REF

The effective resolution of the LTC1090 can be increased

by reducing the input span of the converter. The LTC1090

exhibits good linearity and gain over a wide range of

reference voltages (see typical curves of Linearity and

Gain Error vs Reference Voltage). However, care must be

taken when operating at low values of V_REFbecause of the

reduced LSB step size and the resulting higher accuracy

requirementplacedontheconverter.Thefollowingfactors

must be considered when operating at low V_REFvalues:

The total input referred noise of the LTC1090 can be

reduced to approximately 200µV peak-to-peak using a

ground plane, good bypassing, good layout techniques

and minimizing noise on the reference inputs. This noise

isinsignificantwitha5Vreferencebutwillbecomealarger

fraction of an LSB as the size of the LSB is reduced. The

typical curve of Noise Error vs Reference Voltage shows

the LSB contribution of this 200µV of noise.

1. Conversion speed (ACLK frequency)

For operation with a 5V reference, the 200µV noise is only

0.04LSB peak-to-peak. In this case, the LTC1090 noise

will contribute virtually no uncertainty to the output code.

However, for reduced references, the noise may become

asignificantfractionofanLSBandcauseundesirablejitter

in the output code. For example, with a 1V reference, this

same 200µV noise is 0.2LSB peak-to-peak. This will

reduce the range of input voltages over which a stable

output code can be achieved by 0.2LSB. If the reference is

further reduced to 200mV, the 200µV noise becomes

equal to one LSB and a stable code may be difficult to

achieve.Inthiscaseaveragingreadingsmaybenecessary.

2. Offset

3. Noise

Conversion Speed with Reduced V_REF

With reduced reference voltages, the LSB step size is

reducedandtheLTC1090internalcomparatoroverdriveis

reduced. With less overdrive, more time is required to

perform a conversion. Therefore, the maximum ACLK

frequency should be reduced when low values of V_REFare

used. This is shown in the typical curve of Maximum

Conversion Clock Rate vs Reference Voltage.

This noise data was taken in a very clean setup. Any setup

induced noise (noise or ripple on V_CC, V_REF, V_INor V^–) will

add to the internal noise. The lower the reference voltage

to be used, the more critical it becomes to have a clean,

noise-free setup.

Offset with Reduced V_REF

The offset of the LTC1090 has a larger effect on the output

code when the A/D is operated with reduced reference

1090fc

22

LTC1090

U

TYPICAL APPLICATIO

A “Quick Look” Circuit for the LTC1090

SNEAK-A-BIT^TM

The LTC1090’s unique ability to software select the polar-

ity of the differential inputs and the output word length is

used to achieve one more bit of resolution. Using the

circuit below with two conversions and some software, a

2’s complement 10-bit + sign word is returned to memory

inside the MPU. The MC68HC05C4 was chosen as an

example; however, any processor could be used.

Users can get a quick look at the function and timing of the

LTC1090 by using the following simple circuit. REF⁺and

D_INare tied to V_CCselecting a 5V input span, CH7 as a

single ended input, unipolar mode, MSB first format and

16-bit word length. ACLK and SCLK are tied together and

driven by an external clock. CS is driven at 1/64 the clock

rate by the CD4520 and D_OUToutputs the data. All other

pins are tied to a ground plane. The output data from the

Two 10-bit unipolar conversions are performed: the first

over a 0 to 5V span and the second over a 0 to –5V span

(by reversing the polarity of the inputs). The sign of the

input is determined by which of the two spans contained

it.Thentheresultingnumber(rangingfrom–1023to1023

decimal) is converted to 2’s complement notation and

stored in RAM.

D

_OUTpin can be viewed on an oscilloscope which is set up

to trigger on the falling edge of CS.

A “Quick Look” Circuit for the LTC1090

5V

4.7µF

f/64

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

DGND

V

CC

Scope Trace of LTC1090 “Quick Look” Circuit

V

DD

ACLK

SCLK

CLK

EN

0.1

Showing A/D Output of 0101010101 (155_HEX

)

f

RESET

D

Q1

Q4

Q3

IN

D

Q2

OUT

CS

+

LTC1090

Q3

Q2

Q1

REF

V

Q4

CS

V

–

IN

RESET

EN

V

CLK

SS

D

AGND

OUT

CLOCK IN

1MHz MAX

MSB

(B9)

LSB

(B0)

DEGLITCHER

TIME

FILLS

ZERO

TO OSCILLOSCOPE

LTC1090 • TA03

SNEAK-A-BIT Circuit

10µF

LT1021-5

9V

2MHz

CLOCK

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

V

CC

ACLK

SCLK

MC68HC05C4

OTHER CHANNELS

OR SNEAK-A-BIT

INPUTS

SCK

D

MOSI

MISO

CO

IN

D

OUT

LTC1090

CS

V

IN

–5V TO 5V

+

REF

–

REF

–

V

DGND

AGND

0.1µF

–5V

LTC1090 • TA04

SNEAK-A-BIT is a trademark of Linear Technology Corp.

1090fc

23

LTC1090

U

TYPICAL APPLICATIO

Sneak-A-Bit Code for the LTC1090 Using the MC68HC05C4

SNEAK-A-BIT

V

IN

MNEMONIC

DESCRIPTION

5V

V

( + ) CH6

( – ) CH7

IN

READ–/+: LDA #$3F

Load D word for LTC1090 into ACC

IN

1ST CONVERSION

1024 STEPS

JSR TRANSFER Read LTC1090 routine

LDA $60

STA $71

LDA $61

Load MSBs from LTC1090 into ACC

Store MSBs in $71

Load LSBs from LTC1090 into ACC

Store LSBs in $72

SOFTWARE

1ST CONVERSION

2047 STEPS

0V

STA $72

2ND CONVERSION

1024 STEPS

RTS

Return

V

( – ) CH6

( + ) CH7

IN

READ+/–: LDA #$7F

Load D word for LTC1090 into ACC

IN

JSR TRANSFER Read LTC1090 routine

LDA $60

STA $73

–5V

Load MSBs from LTC1090 into ACC

Store MSBs in $73

2ND CONVERSION

LDA $61

STA $74

Load LSBs from LTC1090 into ACC

Store LSBs in $74

SNEAK-A-BIT Code

RTS

Return

TRANSFER:BCLR 0, $02

STA $0C

LOOP 1: TST $0B

BPL LOOP 1

LDA $0C

STA $0C

STA $60

LOOP 2: TST $0B

BPL LOOP 2

BSET 0, $02

LDA $0C

CS goes low

D

from LTC1090 in MC68HC05C4 RAM

Sign

OUT

Load D into SPI. Start transfer

IN

Test status of SPlF

Loop to previous instruction if not done

Load contents of SPI data reg into ACC

Start next cycle

Store MSBs in $60

Test status of SPlF

Loop to previous instruction if not done

CS goes high

Load contents of SPI data reg into ACC

Location $77

B10 B9 B8 B7 B6 B5 B4 B3

LSB

B2 B1 B0

filled with 0s

Location $87

D

words for LTC1090

IN

MSBF

STA $61

RTS

CHK SIGN: LDA $73

Store LSBs in $61

Return

MUX Addr.

(ODD/SIGN)

UNI

Word

Length

Load MSBs of +/–read into ACC

Or ACC (MSBs) with LSBs of +/–read

If result is 0 goto minus

Clear carry

Rotate right $73 through carry

Rotate right $74 through carry

Load MSBs of +/–read into ACC

Store MSBs in RAM location $77

Load LSBs of +/–read into ACC

Store LSBs in RAM location $87

Goto end of routine

ORA $74

BEQ MINUS

CLC

ROR $73

ROR $74

LDA $73

STA $77

LDA $74

STA $87

D

1

2

3

0

1

IN

1

0

1

LTC1090 • TA05

BRA END

CLC

Sneak-A-Bit Code for the LTC1090 Using the MC68HC05C4

MINUS:

Clear carry

ROR $71

ROR $72

COM $71

COM $72

LDA $72

ADD #$01

STA $72

CLRA

ADC $71

STA $71

STA $77

LDA $72

STA $87

RTS

Shift MSBs of – /+ read right

Shift LSBs of – /+ read right

1’s complement of MSBs

1’s complement of LSBs

Load LSBs into ACC

Add 1 to LSBs

Store ACC in $72

Clear ACC

Add with carry to MSBs. Result in ACC

Store ACC in $71

Store MSBs in RAM location $77

Load LSBs in ACC

Store LSBs in RAM location $87

MNEMONIC

DESCRIPTION

LDA #$50

Configuration data for SPCR

Load configuration data into $0A

Configuration data for port C DDR

Load configuration data into port C DDR

Make sure CS is high

STA

LDA #$FF

STA $06

BSET 0, $02

$0A

JSR

READ–/+

Dummy read configures LTC1090 for next

read

JSR

READ+/–

READ–/+

CHK SIGN

Read CH6 with respect to CH7

Read CH7 with respect to CH6

Determines which reading has valid data,

converts to 2’s complement and stores in

RAM

END:

Return

1090fc

24

LTC1090

U

PACKAGE DESCRIPTIO

J Package

20-Lead CERDIP (Narrow .300 Inch, Hermetic)

(Reference LTC DWG # 05-08-1110)

1.060

(26.924)

MAX

CORNER LEADS OPTION

(4 PLCS)

20

19

18

17

16

15

14

13

12

11

10

0.023 – 0.045

(0.584 – 1.143)

HALF LEAD

OPTION

0.025

(0.635)

RAD TYP

0.220 – 0.310

(5.588 – 7.874)

0.045 – 0.068

(1.143 – 1.727)

FULL LEAD

OPTION

1

2

3

4

5

6

7

8

9

0.005

(0.127)

MIN

0.200

(5.080)

MAX

0.300 BSC

(0.762 BSC)

0.015 – 0.060

(0.381 – 1.524)

0.008 – 0.018

(0.203 – 0.457)

0° – 15°

0.125

(3.175)

MIN

0.045 – 0.065

(1.143 – 1.651)

0.100

(2.54)

BSC

NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE

OR TIN PLATE LEADS

0.014 – 0.026

J20 1298

(0.356 – 0.660)

OBSOLETE PACKAGE

1090fc

25

LTC1090

U

PACKAGE DESCRIPTIO

N Package

20-Lead PDIP (Narrow .300 Inch)

(Reference LTC DWG # 05-08-1510)

1.040*

(26.416)

MAX

20

19

18

17

16

15

14

13

12

11

10

0.255 ± 0.015*

(6.477 ± 0.381)

3

4

5

6

7

8

9

1

2

0.300 – 0.325

0.045 – 0.065

0.130 ± 0.005

(7.620 – 8.255)

(1.143 – 1.651)

(3.302 ± 0.127)

0.020

(0.508)

MIN

0.065

(1.651)

TYP

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325

0.005

(0.127)

MIN

0.100

(2.54)

BSC

–0.015

0.125

(3.175)

MIN

0.018 ± 0.003

(0.457 ± 0.076)

+0.889

8.255

(

)

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

N20 1098

1090fc

26

LTC1090

U

PACKAGE DESCRIPTIO

SW Package

20-Lead Plastic Small Outline (Wide .300 Inch)

(Reference LTC DWG # 05-08-1620)

0.496 – 0.512*

(12.598 – 13.005)

19 18

16

14 13 12 11

20

17

15

0.394 – 0.419

(10.007 – 10.643)

NOTE 1

0.291 – 0.299**

(7.391 – 7.595)

2

3

5

7

8

9

10

1

4

6

0.037 – 0.045

(0.940 – 1.143)

0.093 – 0.104

(2.362 – 2.642)

0.010 – 0.029

(0.254 – 0.737)

× 45°

0° – 8° TYP

0.050

(1.270)

BSC

0.004 – 0.012

0.009 – 0.013

(0.102 – 0.305)

NOTE 1

0.016 – 0.050

(0.406 – 1.270)

(0.229 – 0.330)

0.014 – 0.019

S20 (WIDE) 1098

(0.356 – 0.482)

TYP

NOTE:

1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.

THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

1090fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

27

LTC1090

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1290

8-Channel Configurable, 5V, 12-Bit ADC

Serial-Controlled 8-to-1 Analog Multiplexer

4-/8-Channel, 3V Micropower 12-Bit ADC

10-Bit/12-Bit,8-Channel,1.25MspsADCs

10-Bit/12-Bit,8-Channel,400kspsADCs

24-Bit, 4-/8-Channel, No Latency ∆Σ^TMADC

20-Bit, 4-/8-Channel, No Latency ∆Σ ADC

Pin-CompatiblewithLTC1090

LTC1391

Low R , Low Power, 16-Pin SO and SSOP Package

ON

LTC1594L/LTC1598L

LTC1850/LTC1851

LTC1852/LTC1853

LTC2404/LTC2408

LTC2424/LTC2428

LowPower, SmallSize

5V, Programmable MUX and Sequencer

3V or 5V, Programmable MUX and Sequencer

4ppm INL, 10ppm Total Unadjusted Error, 200µA

1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408

No Latency ∆Σ is a trademark of Linear Technology Corporation.

1090fc

LW/TP 0902 1K REV C • PRINTED IN USA

28 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

■

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

 LINEAR TECHNOLOGY CORPORATION 1990


型号：	LTC1090AMJ
厂家：	Linear
描述：	Single Chip 10-Bit Data Acquisition System 单芯片10位数据采集系统转换器模数转换器
文件：	总28页 (文件大小：343K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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