LTC1096IS8-PBF [Linear]
Micropower Sampling 8-Bit Serial I/O A/D Converters; 微功耗采样8位串行I / OA / D转换器
| 型号： | LTC1096IS8-PBF |
| 厂家： | 
Linear |
| 描述： | Micropower Sampling 8-Bit Serial I/O A/D Converters |
| 文件： | 总32页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1096/LTC1096L
LTC1098/LTC1098L
Micropower Sampling
8-Bit Serial I/O A/D Converters
FEATURES
DESCRIPTION
The LTC®1096/LTC1096L/LTC1098/LTC1098L are
micropower, 8-bit A/D converters that draw only 80μA of
supplycurrentwhenconverting.Theyautomaticallypower
down to 1nA typical supply current whenever they are not
performing conversions. They are packaged in 8-pin SO
packages and have both 3V (L) and 5V versions. These
8-bit,switched-capacitor,successiveapproximationADCs
include sample-and-hold. The LTC1096/LTC1096L have a
n
80μA Maximum Supply Current
n
1nA Typical Supply Current in Shutdown
n
5V Operation (LTC1096/LTC1098)
n
3V Operation (LTC1096L/LTC1098L)(2.65V Min)
n
Sample-and-Hold
n
16μs Conversion Time
n
33kHz Sample Rate
n
0.5LSꢀ Total Unadjusted Error Over Temp
n
Direct 3-Wire Interface to Most MPU Serial Ports and
All MPU Parallel I/O Ports
single differential analog input. The LTC1098/LTC1098L
offer a software selectable 2-channel MUX.
n
8-Pin SO Plastic Package
On-chip serial ports allow efficient data transfer to a wide
rangeofmicroprocessorsandmicrocontrollersoverthree
wires.This,coupledwithmicropowerconsumption,makes
remote location possible and facilitates transmitting data
through isolation barriers.
APPLICATIONS
n
ꢀattery-Operated Systems
n
Remote Data Acquisition
n
ꢀattery Monitoring
ꢀattery Gas Gauges
Temperature Measurement
Isolated Data Acquisition
These circuits can be used in ratiometric applications or
with an external reference. The high impedance analog
inputs and the ability to operate with reduced spans (be-
low 1V full scale) allow direct connection to sensors and
transducers in many applications, eliminating the need
for gain stages.
n
n
n
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
10μW, S8 Package, 8-Bit A/D
Supply Current vs Sample Rate
Samples at 200Hz and Runs Off a 5V Battery
1000
T
= 25°C
= V
A
1μF
5V
V
= 5V
CC
REF
MPU
100
10
1
(e.g., 8051)
CS/
SHUTDOWN
V
P1.4
P1.3
P1.2
CC
+IN
CLK
ANALOG INPUT
0V TO 5V RANGE
LTC1096
–IN
D
OUT
GND
V
REF
10968 TA01
0.1
1
SAMPLE FREQUENCY, f
10
100
(kHz)
SMPL
10968 TA02
10968fc
1
LTC1096/LTC1096L
LTC1098/LTC1098L
ABSOLUTE MAXIMUM RATINGS
(Notes 1 and 2)
Supply Voltage (V ) to GND ...................................12V
Operating Temperature
CC
Voltage
LTC1096AC/LTC1096C/LTC1096LC/
Analog and Reference ................ –0.3V to V + 0.3V
LTC1098AC/LTC1098C/LTC1098LC.......... 0°C to 70°C
LTC1096AI/LTC1096I/LTC1096LI/
LTC1098AI/LTC1098I/LTC1098LI .........–40°C to 85°C
Lead Temperature (Soldering, 10 sec.) ................. 300°C
CC
Digital Inputs ........................................ –0.3V to 12V
Digital Outputs ........................... –0.3V to V + 0.3V
CC
Power Dissipation...............................................500mW
Storage Temperature Range...................–65°C to 150°C
PIN CONFIGURATION (Note 3)
LTC1096
TOP VIEW
CS/
LTC1098
TOP VIEW
CS/
1
2
3
4
V
1
2
3
4
V (V
CC REF)
8
7
6
5
8
7
6
5
CC
SHUTDOWN
+IN
SHUTDOWN
CLK
D
CLK
D
CH0
CH1
GND
–IN
OUT
OUT
V
D
IN
GND
REF
N8 PACKAGE
8-LEAD PLASTIC DIP
S8 PACKAGE
8-LEAD PLASTIC SOIC
N8 PACKAGE
8-LEAD PLASTIC DIP
S8 PACKAGE
8-LEAD PLASTIC SOIC
T
= 150°C, θ = 130°C/W (N8)
T
= 150°C, θ = 130°C/W (N8)
JMAX
JA
JMAX JA
T
= 150°C, θ = 175°C/W (S8)
T
= 150°C, θ = 175°C/W (S8)
JMAX JA
JMAX
JA
ORDER INFORMATION
LEAD FREE FINISH
LTC1096ACN8#PꢀF
LTC1096ACS8#PꢀF
LTC1096AIN8#PꢀF
LTC1096AIS8#PꢀF
LTC1096CN8#PꢀF
LTC1096CS8#PꢀF
LTC1096IN8#PꢀF
LTC1096IS8#PꢀF
LTC1096LCS8#PꢀF
LTC1096LIS8#PꢀF
LTC1098ACN8#PꢀF
LTC1098ACS8#PꢀF
LTC1098CN8#PꢀF
LTC1098CS8#PꢀF
LTC1098IN8#PꢀF
LTC1098IS8#PꢀF
LTC1098LCS8#PꢀF
LTC1098LIS8#PꢀF
TAPE AND REEL
PART MARKING*
LTC1096ACN8
1096A
PACKAGE DESCRIPTION
8-Lead Plastic DIP
8-Lead Plastic SOIC
8-Lead Plastic DIP
8-Lead Plastic SOIC
8-Lead Plastic DIP
8-Lead Plastic SOIC
8-Lead Plastic DIP
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic DIP
8-Lead Plastic SOIC
8-Lead Plastic DIP
8-Lead Plastic SOIC
8-Lead Plastic DIP
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic SOIC
TEMPERATURE RANGE
0°C to 70°C
LTC1096ACN8#TRPꢀF
LTC1096ACS8#TRPꢀF
LTC1096AIN8#TRPꢀF
LTC1096AIS8#TRPꢀF
LTC1096CN8#TRPꢀF
LTC1096CS8#TRPꢀF
LTC1096IN8#TRPꢀF
LTC1096IS8#TRPꢀF
LTC1096LCS8#TRPꢀF
LTC1096LIS8#TRPꢀF
LTC1098ACN8#TRPꢀF
LTC1098ACS8#TRPꢀF
LTC1098CN8#TRPꢀF
LTC1098CS8#TRPꢀF
LTC1098IN8#TRPꢀF
LTC1098IS8#TRPꢀF
LTC1098LCS8#TRPꢀF
LTC1098LIS8#TRPꢀF
0°C to 70°C
LTC1096AIN8
1096AI
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
LTC1096CN8
1096
0°C to 70°C
LTC1096IN8
1096I
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
1096L
1096LI
–40°C to 85°C
0°C to 70°C
LTC1098ACN8
1098A
0°C to 70°C
LTC1098CN8
1098
0°C to 70°C
0°C to 70°C
LTC1098IN8
1098I
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
1098L
1098LI
–40°C to 85°C
10968fc
2
LTC1096/LTC1096L
LTC1098/LTC1098L
ORDER INFORMATION
LEAD BASED FINISH
LTC1096ACN8
LTC1096ACS8
LTC1096AIN8
LTC1096AIS8
LTC1096CN8
LTC1096CS8
LTC1096IN8
TAPE AND REEL
LTC1096ACN8#TR
LTC1096ACS8#TR
LTC1096AIN8#TR
LTC1096AIS8#TR
LTC1096CN8#TR
LTC1096CS8#TR
LTC1096IN8#TR
LTC1096IS8#TR
LTC1096LCS8#TR
LTC1096LIS8#TR
LTC1098ACN8#TR
LTC1098ACS8#TR
LTC1098CN8#TR
LTC1098CS8#TR
LTC1098IN8#TR
LTC1098IS8#TR
LTC1098LCS8#TR
LTC1098LIS8#TR
PART MARKING*
LTC1096ACN8
1096A
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
8-Lead Plastic DIP
8-Lead Plastic SOIC
8-Lead Plastic DIP
8-Lead Plastic SOIC
8-Lead Plastic DIP
8-Lead Plastic SOIC
8-Lead Plastic DIP
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic DIP
8-Lead Plastic SOIC
8-Lead Plastic DIP
8-Lead Plastic SOIC
8-Lead Plastic DIP
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic SOIC
0°C to 70°C
LTC1096AIN8
1096AI
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
LTC1096CN8
1096
0°C to 70°C
LTC1096IN8
1096I
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
LTC1096IS8
LTC1096LCS8
LTC1096LIS8
LTC1098ACN8
LTC1098ACS8
LTC1098CN8
LTC1098CS8
LTC1098IN8
1096L
1096LI
–40°C to 85°C
0°C to 70°C
LTC1098ACN8
1098A
0°C to 70°C
LTC1098CN8
1098
0°C to 70°C
0°C to 70°C
LTC1098IN8
1098I
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
LTC1098IS8
LTC1098LCS8
LTC1098LIS8
1098L
1098LI
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
RECOMMENDED OPERATING CONDITIONS
LTC1096/LTC1098
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Supply Voltage
LTC1096
LTC1098
3.0
3.0
9
6
V
V
CC
V
= 5V Operation
CC
CLK
CYC
f
t
Clock Frequency
Total Cycle Time
V
CC
= 5V
25
500
kHz
LTC1096, f
LTC1098, f
= 500kHz
= 500kHz
29
29
μs
μs
CLK
CLK
t
t
V
= 5V
150
ns
Hold Time, D After CLK↑
hDI
CC
IN
V
V
= 5V, LTC1096
= 5V, LTC1098
500
500
ns
ns
Setup Time CS↓ ꢀefore First CLK↑ (See Operating Sequence)
suCS
CC
CC
t
V
= 5V, LTC1096
10
μs
Wake-Up Time CS↓ ꢀefore First CLK↓ After First CLK↑
(See Figure 1 LTC1096 Operating Sequence)
WAKEUP
CC
V
= 5V, LTC1098
10
μs
Wake-Up Time CS↓ ꢀefore MSꢀF ꢀit CLK↓
(See Figure 2 LTC1098 Operating Sequence)
CC
t
t
t
V
CC
V
CC
V
CC
= 5V
= 5V
= 5V
400
0.8
0.8
ns
μs
μs
Setup Time, D Stable ꢀefore CLK↑
suDI
IN
CLK High Time
CLK Low Time
WHCLK
WLCLK
10968fc
3
LTC1096/LTC1096L
LTC1098/LTC1098L
RECOMMENDED OPERATING CONDITIONS
LTC1096/LTC1098
SYMBOL
PARAMETER
CONDITIONS
= 5V
MIN
TYP
MAX
UNITS
t
t
CS High Time ꢀetween Data Transfer Cycles
CS Low Time During Data Transfer
V
1
μs
WHCS
WLCS
CC
LTC1096, f
LTC1098, f
= 500kHz
= 500kHz
28
28
μs
μs
CLK
CLK
V
= 3V Operation
CC
CLK
CYC
f
t
Clock Frequency
Total Cycle Time
V
CC
= 3V
25
250
kHz
LTC1096, f
LTC1098, f
= 250kHz
= 250kHz
58
58
μs
μs
CLK
CLK
t
t
V
= 3V
450
ns
Hold Time, D After CLK↑
hDI
CC
IN
V
V
= 3V, LTC1096
= 3V, LTC1098
1
1
μs
μs
Setup Time CS↓ ꢀefore First CLK↑ (See Operating Sequence)
suCS
CC
CC
t
V
= 3V, LTC1096
10
μs
Wake-Up Time CS↓ ꢀefore First CLK↓ After First CLK↑
(See Figure 1 LTC1096 Operating Sequence)
WAKEUP
CC
V
= 3V, LTC1098
10
μs
Wake-Up Time CS↓ ꢀefore MSꢀF ꢀit CLK↓
(See Figure 2 LTC1098 Operating Sequence)
CC
t
t
t
t
t
V
V
V
V
= 3V
= 3V
= 3V
= 3V
1
μs
μs
μs
μs
Setup Time, D Stable ꢀefore CLK↑
suDI
CC
CC
CC
CC
IN
CLK High Time
1.6
1.6
2
WHCLK
WLCLK
WHCS
WLCS
CLK Low Time
CS High Time ꢀetween Data Transfer Cycles
CS Low Time During Data Transfer
LTC1096, f
LTC1098, f
= 250kHz
= 250kHz
56
56
μs
μs
CLK
CLK
LTC1096L/LTC1098L
SYMBOL
PARAMETER
CONDITIONS
MIN
2.65
25
TYP
MAX
4.0
UNITS
V
V
Supply Voltage
Clock Frequency
Total Cycle Time
CC
CLK
CYC
f
t
V
CC
= 2.65V
250
kHz
LTC1096L, f
LTC1098L, f
= 250kHz
= 250kHz
58
58
μs
μs
CLK
CLK
t
t
V
= 2.65V
450
ns
Hold Time, D After CLK↑
hDI
CC
IN
V
V
= 2.65V, LTC1096L
= 2.65V, LTC1098L
1
1
μs
μs
Setup Time CS↓ ꢀefore First CLK↑ (See Operating Sequence)
suCS
CC
CC
t
V
= 2.65V, LTC1096L
10
μs
Wake-Up Time CS↓ ꢀefore First CLK↓ After First CLK↑
(See Figure 1 LTC1096L Operating Sequence)
WAKEUP
CC
V
= 2.65V, LTC1098L
10
μs
Wake-Up Time CS↓ ꢀefore MSꢀF ꢀit CLK↓
(See Figure 2 LTC1098L Operating Sequence)
CC
t
t
t
t
t
V
V
V
V
= 2.65V
= 2.65V
= 2.65V
= 2.65V
1
μs
μs
μs
μs
Setup Time, D Stable ꢀefore CLK↑
suDI
CC
CC
CC
CC
IN
CLK High Time
1.6
1.6
2
WHCLK
WLCLK
WHCS
WLCS
CLK Low Time
CS High Time ꢀetween Data Transfer Cycles
CS Low Time During Data Transfer
LTC1096L, f
LTC1098L, f
= 250kHz
= 250kHz
56
56
μs
μs
CLK
CLK
10968fc
4
LTC1096/LTC1096L
LTC1098/LTC1098L
CONVERTER AND MULTIPLEXER CHARACTERISTICS
LTC1096/LTC1098
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V, VREF = 5V, fCLK = 500kHz, unless otherwise noted.
LTC1096A/LTC1098A
MIN TYP MAX
LTC1096/LTC1098
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
ꢀits
LSꢀ
LSꢀ
LSꢀ
LSꢀ
V
l
l
l
l
l
Resolution (No Missing Code)
Offset Error
8
8
0.5
0.5
0.5
0.5
0.5
0.5
1.0
1.0
Linearity Error
(Note 4)
Full Scale Error
Total Unadjusted Error (Note 5)
Analog Input Range
REF Input Range (Notes 6, 7)
V
REF
= 5.000V
(Notes 6, 7)
–0.05V to V + 0.05V
CC
4.5 ≤ V ≤ 6V
–0.05V to V + 0.05V
V
V
CC
CC
6V < V ≤ 9V, LTC1096
–0.05V to 6V
CC
l
Analog Input Leakage Current
(Note 8)
1.0
1.0
μA
LTC1096/LTC1098
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 3V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
LTC1096A/LTC1098A
MIN TYP MAX
LTC1096/LTC1098
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
ꢀits
LSꢀ
LSꢀ
LSꢀ
LSꢀ
V
l
l
l
l
l
Resolution (No Missing Code)
Offset Error
8
8
0.75
0.5
1.0
1.0
1.0
1.0
1.0
1.5
Linearity Error
(Notes 4, 9)
Full-Scale Error
Total Unadjusted Error (Notes 5, 9)
Analog Input Range
V
REF
= 2.500V
(Notes 6, 7)
–0.05V to V + 0.05V
CC
REF Input Range (Notes 6, 7, 9)
Analog Input Leakage Current
3V ≤ V ≤ 6V
–0.05V to V + 0.05V
V
CC
CC
l
(Notes 8, 9)
1.0
1.0
μA
LTC1096L/LTC1098L
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
LTC1096A/LTC1098A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ꢀits
LSꢀ
LSꢀ
LSꢀ
LSꢀ
V
l
l
l
l
l
Resolution (No Missing Code)
Offset Error
8
1.0
1.0
1.0
1.5
Linearity Error
(Note 4)
Full-Scale Error
Total Unadjusted Error (Note 5)
Analog Input Range
REF Input Range (Note 6)
Analog Input Leakage Current
V
REF
= 2.5V
(Notes 6, 7)
–0.05V to V + 0.05V
CC
2.65V ≤ V ≤ 4.0V
–0.05V to V + 0.05V
V
CC
CC
l
(Note 8)
1.0
μA
10968fc
5
LTC1096/LTC1096L
LTC1098/LTC1098L
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
LTC1096/LTC1098
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V, VREF = 5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
l
l
l
l
V
IH
V
IL
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 5.25V
= 4.75V
2.0
CC
CC
IN
0.8
2.5
V
I
I
= V
μA
μA
IH
IL
CC
= 0V
–2.5
IN
l
l
V
OH
V
CC
V
CC
= 4.75V, I = 10μA
= 4.75V, I = 360μA
4.5
2.4
4.74
4.72
V
V
O
O
l
l
V
Low Level Output Voltage
Hi-Z Output Leakage
Output Source Current
Output Sink Current
Reference Current
V
= 4.75V, I = 1.6mA
0.4
3.0
V
μA
OL
CC
O
I
I
I
I
CS ≥ V
IH
OZ
V
OUT
V
OUT
= 0V
–25
45
mA
mA
SOURCE
SINK
= V
CC
l
l
l
CS = V
0.001
3.500
35.000
2.5
7.5
50.0
μA
μA
μA
REF
CC
t
t
≥ 200μs, f
≤ 50kHz
CYC
CYC
CLK
= 29μs, f
= 500kHz
CLK
l
I
Supply Current
CS = V
0.001
3.0
μA
CC
CC
l
l
LTC1096, t
LTC1096, t
≥ 200μs, f
≤ 50kHz
40
120
80
180
μA
μA
CYC
CYC
CLK
= 29μs, f
= 500kHz
CLK
l
l
LTC1098, t
LTC1098, t
≥ 200μs, f
≤ 50kHz
44
155
88
230
μA
μA
CYC
CYC
CLK
= 29μs, f
= 500kHz
CLK
LTC1096/LTC1098
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 3V, VREF = 2.5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
l
l
l
l
V
IH
V
IL
High Level Input Voltage
V
V
V
V
= 3.6V
= 3V
1.9
CC
CC
IN
Low Level Input Voltage
0.45
2.5
V
I
I
High Level Input Current (Note 9)
Low Level Input Current (Note 9)
High Level Output Voltage
= V
μA
μA
IH
IL
CC
= 0V
–2.5
IN
l
l
V
V
CC
V
CC
= 3V, I = 10μA
2.3
2.1
2.69
2.64
V
V
OH
O
= 3V, I = 360μA
O
l
l
V
Low Level Output Voltage
V
= 3V, I = 400μA
0.3
3.0
V
μA
OL
CC
O
I
I
I
I
Hi-Z Output Leakage (Note 9)
Output Source Current (Note 9)
Output Sink Current (Note 9)
Reference Current (Note 9)
CS ≥ V
IH
OZ
V
OUT
V
OUT
= 0V
–10
15
mA
mA
SOURCE
SINK
= V
CC
l
l
l
CS = V
0.001
3.500
35.000
2.5
7.5
50.0
μA
μA
μA
REF
CC
t
t
≥ 200μs, f
≤ 50kHz
CYC
CYC
CLK
= 58μs, f
= 250kHz
CLK
l
I
Supply Current (Note 9)
CS = V
0.001
3.0
μA
CC
CC
l
l
LTC1096, t
LTC1096, t
≥ 200μs, f
≤ 50kHz
40
120
80
180
μA
μA
CYC
CYC
CLK
= 58μs, f
= 250kHz
CLK
l
l
LTC1098, t
LTC1098, t
≥ 200μs, f
≤ 50kHz
44
155
88
230
μA
μA
CYC
CYC
CLK
= 58μs, f
= 250kHz
CLK
10968fc
6
LTC1096/LTC1096L
LTC1098/LTC1098L
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
LTC1096L/LTC1098L
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
l
l
l
l
V
IH
V
IL
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 3.6V
1.9
CC
CC
IN
= 2.65V
0.45
2.5
V
I
IH
I
IL
= V
μA
μA
CC
= 0V
–2.5
IN
l
l
V
OH
V
CC
V
CC
= 2.65V, I = 10μA
= 2.65V, I = 360μA
2.3
2.1
2.64
2.50
V
V
O
O
l
l
V
Low Level Output Voltage
Hi-Z Output Leakage
Output Source Current
Output Sink Current
Reference Current
V
= 2.65V, I = 400μA
0.3
3.0
V
μA
OL
CC
O
I
I
I
I
CS ≥ High
OZ
V
OUT
V
OUT
= 0V
–10
15
mA
mA
SOURCE
SINK
= V
CC
l
l
l
CS = V
0.001
3.500
35.000
2.5
7.5
50.0
μA
μA
μA
REF
CC
t
t
≥ 200μs, f
≤ 50kHz
CYC
CYC
CLK
= 58μs, f
= 250kHz
CLK
l
I
Supply Current
CS = V
0.001
3.0
μA
CC
CC
l
l
LTC1096L, t
LTC1096L, t
≥ 200μs, f
≤ 50kHz
40
120
80
180
μA
μA
CYC
CYC
CLK
= 58μs, f
= 250kHz
CLK
l
l
LTC1098L, t
LTC1098L, t
≥ 200μs, f
≤ 50kHz
44
155
88
230
μA
μA
CYC
CYC
CLK
= 58μs, f
= 250kHz
CLK
AC CHARACTERISTICS
LTC1096/LTC1098
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V, VREF = 5V, fCLK = 500kHz, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
f
t
t
t
t
t
t
t
Analog Input Sample Time
Maximum Sampling Frequency
Conversion Time
See Operating Sequence
1.5
CLK Cycles
SMPL
l
33
kHz
SMPL(MAX)
See Operating Sequence
See Test Circuits
8
CLK Cycles
CONV
dDO
dis
en
l
l
l
200
170
60
450
450
250
ns
ns
ns
ns
ns
ns
Delay Time, CLK↓ to D
Delay Time, CS↑ to D
Data Valid
OUT
See Test Circuits
Hi-Z
OUT
See Test Circuits
Delay Time, CLK↓ to D
Enable
OUT
C
LOAD
= 100pF
180
70
Time Output Data Remains Valid After CLK↓
hDO
f
l
l
D
OUT
D
OUT
Fall Time
See Test Circuits
See Test Circuits
250
100
Rise Time
25
r
C
IN
Input Capacitance
Analog Inputs On Channel
Analog Inputs Off Channel
25
5
pF
pF
Digital Input
5
pF
10968fc
7
LTC1096/LTC1096L
LTC1098/LTC1098L
AC CHARACTERISTICS
LTC1096/LTC1098
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 3V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
f
t
t
t
t
t
t
t
Analog Input Sample Time
Maximum Sampling Frequency
Conversion Time
See Operating Sequence
1.5
CLK Cycles
SMPL
l
16.5
kHz
SMPL(MAX)
See Operating Sequence
See Test Circuits (Note 9)
See Test Circuits (Note 9)
See Test Circuits (Note 9)
8
CLK Cycles
CONV
dDO
dis
en
l
l
l
500
220
160
400
70
1000
800
ns
ns
ns
ns
ns
ns
Delay Time, CLK↓ to D
Delay Time, CS↑ to D
Data Valid
OUT
Hi-Z
OUT
480
Delay Time, CLK↓ to D
Enable
OUT
C
LOAD
= 100pF
Time Output Data Remains Valid After CLK↓
hDO
f
l
l
D
OUT
D
OUT
Fall Time
See Test Circuits (Note 9)
See Test Circuits (Note 9)
250
150
Rise Time
50
r
C
IN
Input Capacitance
Analog Inputs On Channel
Analog Inputs Off Channel
25
5
pF
pF
Digital Input
5
pF
LTC1096L/LTC1098L
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
f
t
t
t
t
t
t
t
Analog Input Sample Time
Maximum Sampling Frequency
Conversion Time
See Operating Sequence
1.5
CLK Cycles
SMPL
l
16.5
kHz
SMPL(MAX)
See Operating Sequence
See Test Circuits
8
CLK Cycles
CONV
dDO
dis
en
l
l
l
500
220
160
400
70
1000
800
ns
ns
ns
ns
ns
ns
Delay Time, CLK↓ to D
Delay Time, CS↑ to D
Data Valid
OUT
See Test Circuits
Hi-Z
OUT
See Test Circuits
480
Delay Time, CLK↓ to D
Enable
OUT
C
LOAD
= 100pF
Time Output Data Remains Valid After CLK↓
hDO
f
l
l
D
OUT
D
OUT
Fall Time
See Test Circuits
See Test Circuits
250
200
Rise Time
50
r
C
IN
Input Capacitance
Analog Inputs On Channel
Analog Inputs Off Channel
25
5
pF
pF
Digital Input
5
pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: For the 8-lead PDIP, consult the factory.
Note 4: Linearity error is specified between the actual and points of the
A/D transfer curve.
Note 5: Total unadjusted error includes offset, full scale, linearity,
multiplexer and hold step errors.
analog input does not exceed the supply voltage by more than 50mV, the
output code will be correct. To achieve an absolute 0V to 5V input voltage
range will therefore require a minimum supply voltage of 4.950V over
initial tolerance, temperature variations and loading. For 5.5V < V ≤ 9V,
CC
reference and analog input range cannot exceed 5.55V. If reference and
analog input range are greater than 5.55V, the output code will not be
guaranteed to be correct.
Note 7: The supply voltage range for the LTC1096L/LTC1098L is from
2.65V to 4V. The supply voltage range for the LTC1096 is from 3V to 9V,
but the supply voltage range for the LTC1098 is only from 3V to 6V.
Note 8: Channel leakage current is measured after the channel selection.
Note 9: These specifications are either correlated from 5V specifications or
guaranteed by design.
Note 6: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode
drop below GND or one diode drop above V . This spec allows 50mV
CC
forward bias of either diode. This means that as long as the reference or
10968fc
8
LTC1096/LTC1096L
LTC1098/LTC1098L
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Clock Rate
for Active and Shutdown Modes
Supply Current vs Supply Voltage
Active and Shutdown Modes
Supply Current vs Sample
Frequency LTC1096
1000
250
200
150
100
50
100
80
T
= 25°C
T
= 25°C
= V
T
= 25°C
REF
A
A
CC
A
CS = 0V
V
= 5V
REF
V
= 2.5V
V
= 9V
CC
100
10
1
V
= 5V
CC
60
40
“ACTIVE” MODE CS = 0
10
20
0.001
0
0.002
“SHUTDOWN” MODE CS = V
CS = V
CC
CC
0
1
10
100
1000
0.1
1
SAMPLE FREQUENCY, f
10
100
0
1
2
3
4
5
6
7
8
9
(kHz)
FREQUENCY (kHz)
SUPPLY VOLTAGE,V (V)
SMPL
CC
10968 G01
10968 G02
10968 G03
Change in Offset vs
Reference Voltage LTC1096
Change in Offset vs
Supply Voltage
Change in Linearity vs
Reference Voltage LTC1096
0.5
0.4
0.50
0.25
0
0.50
0.25
0
T
= 25°C
T
V
F
= 25°C
= 5V
T
V
F
= 25°C
A
CC
A
A
CC
V
F
= 2.5V
= 5V
REF
= 100kHz
= 500kHz
= 500kHz
CLK
CLK
CLK
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.25
–O.50
–0.25
–0.50
0
1
2
3
4
5
6
7
8
9
10
0
1
3
4
5
2
0
1
2
3
4
5
SUPPLY VOLTAGE, V (V)
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
CC
10968 G05
10968 G06
10968 G04
Change in Linearity vs
Supply Voltage
Change in Gain vs
Change in Gain vs Supply Voltage
Reference Voltage LTC1096
0.5
0.4
0.5
0.4
0.50
0.25
0
T
= 25°C
T
V
F
= 25°C
A
T
V
F
= 25°C
CC
A
A
V
F
= 2.5V
= 2.5V
= 5V
REF
REF
= 100kHz
= 100kHz
= 500kHz
CLK
CLK
CLK
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
–0.25
–O.50
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
0
1
3
4
5
2
SUPPLY VOLTAGE, V (V)
SUPPLY VOLTAGE, V (V)
VOLTAGE REFERENCE (V)
CC
CC
10968 G07
10968 G08
10968 G09
10968fc
9
LTC1096/LTC1096L
LTC1098/LTC1098L
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Clock Frequency vs
Source Resistance
Maximum Clock Frequency vs
Supply Voltage
Digital Input Logic Threshold
vs Supply Voltage
1
0.75
0.50
0.25
0
1.5
5
4
3
2
1
0
T
= 25°C
T
= 25°C
T = 25°C
A
A
A
V
IN
+ INPUT
– INPUT
V
= V
= 5V
V
= 2.5V
REF
CC
REF
1.25
–
R
SOURCE
1.0
0.75
0.5
0.25
0
1
10
100
0
2
4
6
8
10
0
2
4
6
8
10
–
R
(kΩ)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE, V (V)
SOURCE
CC
10968 G10
10968 G11
10968 G12
Minimum Wake-Up Time
vs Source Resistance
Input Channel Leakage Current
vs Temperature
Wake-Up Time vs Supply Voltage
4
3
2
1
0
10
7.5
5.0
2.5
0
1000
100
10
T
V
= 25°C
= 5V
T
= 25°C
REF
V
V
= 5V
REF
A
REF
A
V
= 2.5V
= 5V
CC
ON CHANNEL
1
0.1
+
OFF CHANNEL
R
SOURCE
V
IN
+
–
0.01
1
10
100
–60 –40 –20
0
20
60 80 100 120 140
40
0
2
4
6
8
10
R
(kΩ)
TEMPERATURE (°C)
SUPPLY VOLTAGE, V (V)
SOURCE
CC
10968 G14
10968 G15
10968 G13
Minimum Clock Frequency for
0.1LSB Error† vs Temperature
ENOBs vs Frequency
FFT Plot
200
180
160
140
120
10
9
0
T
= 25°C
V
V
= 5V
A
REF
CC
–10
V
f
= V
= 5V
= 5V
CC
REF
= 31.25kHz
8
SMPL
IN
–20
–30
–40
–50
–60
–70
–80
–90
–100
f
= 5.8kHz
7
6
5
4
3
2
1
0
100
80
60
T
= 25°C
40
20
A
V
= V
= 5V
CC
REF
= 31.25kHz
f
SMPL
0
–60 –40 –20
0
20
60 80 100 120 140
1
10
FREQUENCY (kHz)
100
40
0
4
6
10 12
2
8
14
16
TEMPERATURE (°C)
FREQUENCY (kHz)
10968 G17
10968 G16
10968 G18
*Maximum CLK frequency represents the clock frequency at which a 0.1LSꢀ shift in the error at any code
transition from its 0.75MHz value is first detected.
†
As the CLK frequency is decreased from 500kHz, minimum CLK frequency (Δerror ≤ 0.1LSꢀ) represents
the frequency at which a 0.1LSꢀ shift in any code transition from its 500kHz value is first detected.
10968fc
10
LTC1096/LTC1096L
LTC1098/LTC1098L
PIN FUNCTIONS
LTC1096/LTC1096L
LTC1098/LTC1098L
CS/SHDN (Pin 1): Chip Select Input. A logic low on this
input enables the LTC1096/LTC1096L. A logic high on this
inputdisablestheLTC1096/LTC1096Landdisconnectsthe
power to the LTC1096/LTC1096L.
CS/SHDN (Pin 1): Chip Select Input. A logic low on this
input enables the LTC1098/LTC1098L. A logic high on this
inputdisablestheLTC1098/LTC1098Landdisconnectsthe
power to the LTC1098/LTC1098L.
+
IN (Pin 2): Analog Input. This input must be free of noise
CH0(Pin2):AnalogInput. Thisinputmustbefreeofnoise
with respect to GND.
with respect to GND.
–
IN (Pin 3): Analog Input. This input must be free of noise
CH1(Pin3):AnalogInput. Thisinputmustbefreeofnoise
with respect to GND.
with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
V
(Pin 5): Reference Input. The reference input defines
D
(Pin 5): Digital Data Input. The multiplexer address
REF
IN
the span of the A/D converter and must be kept free of
is shifted into this pin.
noise with respect to GND.
D
(Pin 6): Digital Data Output. The A/D conversion
OUT
D
(Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
OUT
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the se-
rial data transfer.
CLK (Pin 7): Shift Clock. This clock synchronizes the se-
rial data transfer.
V (V )(Pin8):PowerSupplyVoltage.Thispinprovides
CC REF
V (Pin8):PowerSupplyVoltage.Thispinprovidespower
power and defines the span of the A/D converter. It must
be free of noise and ripple by bypassing directly to the
analog ground plane.
CC
to the A/D converter. It must be free of noise and ripple by
bypassing directly to the analog ground plane.
10968fc
11
LTC1096/LTC1096L
LTC1098/LTC1098L
BLOCK DIAGRAM
LTC1096/LTC1096L
V
(V /V
CC CC REF
)
CS (D ) CLK
IN
ꢀIAS AND
SHUTDOWN CIRCUIT
SERIAL PORT
D
OUT
+
IN (CH0)
C
SAMPLE
–
+
SAR
–
IN (CH1)
MICROPOWER
COMPARATOR
CAPACITIVE DAC
10968 ꢀD
GND
PIN NAMES IN PARENTHESES
REFER TO THE LTC1098/LTC1098L
V
REF
TEST CIRCUITS
On and Off Channel Leakage Current
Load Circuit for tdDO, tr and tf
5V
I
ON
A
1.4V
3kΩ
ON CHANNEL
I
OFF
A
D
TEST POINT
OUT
OFF
CHANNEL
100pF
•
•
•
•
10968 TC02
POLARITY
10968 TC01
10968fc
12
LTC1096/LTC1096L
LTC1098/LTC1098L
TEST CIRCUITS
Voltage Waveforms for DOUT Delay Time, tdDO
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
CLK
V
IL
V
OH
D
OUT
t
dDO
V
OL
V
V
OH
OL
D
OUT
t
t
10968 TC04
r
f
10968 TC03
Load Circuit for tdis and ten
Voltage Waveforms for tdis
2.0V
CS
TEST POINT
3k
D
OUT
90%
10%
WAVEFORM 1
(SEE NOTE 1)
5V t WAVEFORM 2, t
dis
en
t
dis
D
OUT
D
OUT
t
WAVEFORM 1
dis
WAVEFORM 2
(SEE NOTE 2)
100pF
10968 TC05
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISAꢀLED ꢀY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISAꢀLED ꢀY THE OUTPUT CONTROL.
10968 TC06
10968fc
13
LTC1096/LTC1096L
LTC1098/LTC1098L
TEST CIRCUITS
Voltage Waveforms for ten
LTC1096/LTC1096L
CS
t
WAKEUP
1
CLK
ꢀ7
D
OUT
V
OL
t
en
10968 TC07
LTC1098/LTC1098L
CS
START
D
IN
1
2
3
4
5
CLK
ꢀ7
D
OUT
V
OL
t
en
10968 TC08
10968fc
14
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
OVERVIEW
wake-up time must be provided from CS falling to the
first falling clock (CLK) after the first rising CLK for the
LTC1096(L) and from CS falling to the MSꢀF bit CLK fall-
ing for the LTC1098(L) (see Operating Sequence). If the
LTC1096(L)/LTC1098(L) are running with clock frequency
less than or equal to 100kHz, the wake-up time is inher-
ently provided.
The LTC1096/LTC1096L/LTC1098/LTC1098L are 8-bit
micropower, switched-capacitor A/D converters. These
sampling ADCs typically draw 120μA of supply current
when sampling up to 33kHz. Supply current drops linearly
as the sample rate is reduced (see Supply Current vs
SampleRateonthefirstpageofthisdatasheet). TheADCs
automatically power down when not performing conver-
sion, drawing only leakage current. They are packaged in
8-pin SO packages. The LTC1096L/LTC1098L operate on
a single supply ranging from 2.65V to 4V. The LTC1096
operates on a single supply ranging from 3V to 9V while
the LTC1098 operates from 3V to 6V supplies.
Example
Two cases are shown at right to illustrate the relationship
among wake-up time, setup time and CLK frequency for
the LT1096(L).
In Case 1 the clock frequency is 100kHz. One clock cycle
is 10μs which can be the wake-up time, while half of that
can be the setup time. In Case 2 the clock frequency is
50kHz, half of the clock cycle plus the setup time (=1μs)
can be the wake-up time. If the CLK frequency is higher
than 100kHz, Figure 1 shows the relationship between the
wake-up time and setup time.
The LTC1096/LTC1096L/LTC1098/LTC1098L comprise an
8-bit, switched-capacitor ADC, a sample-and-hold and a
serial port (see ꢀlock Diagram). Although they share the
same basic design, the LTC1096(L) and LTC1098(L) differ
in some respects. The LTC1096(L) has a differential input
and has an external reference input pin. It can measure
signals floating on a DC common mode voltage and can
operate with reduced spans down to 250mV. Reducing the
span allows it to achieve 1mV resolution. The LTC1098(L)
has a 2-channel input multiplexer and can convert either
channel with respect to ground or the difference between
the two.
t
WAKEUP
CS
t
su
CLK
D
OUT
NULL ꢀIT
ꢀ7
Case 1. Timing Diagram
SERIAL INTERFACE
t
WAKEUP
TheLTC1098(L)communicateswithmicroprocessorsand
other external circuitry via a synchronous, half duplex,
4-wire serial interface while the LTC1096(L) uses a 3-wire
interface (see Operating Sequence in Figures 1 and 2).
CS
t
su
10μs
CLK
D
Power Down and Wake-Up Time
OUT
10968 AI Ex
The LTC1096(L)/LTC1098(L) draw power when the CS
pin is low and shut themselves down when that pin is
high. In order to have a correct conversion result, a 10μs
Case 2. Timing Diagram
10968fc
15
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
t
CYC
CS
POWER
DOWN
CLK
t
suCS
NULL
ꢀIT
t
WAKEUP
Hi-Z
D
OUT
ꢀ7
(MSꢀ)
ꢀ6
ꢀ5
ꢀ4 ꢀ3
ꢀ2 ꢀ1 ꢀ0
HI-Z
t
CONV
t
CYC
CS
POWER
DOWN
CLK
t
suCS
NULL
ꢀIT
t
WAKEUP
Hi-Z
ꢀ0
ꢀ7
ꢀ5
ꢀ4 ꢀ3
ꢀ2 ꢀ1
ꢀ1
ꢀ2
ꢀ3
ꢀ5 ꢀ6 ꢀ7*
ꢀ6
ꢀ4
D
OUT
Hi-Z
(MSꢀ)
10968 F01
t
CONV
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.
Figure 1. LTC1096(L) Operating Sequence
Thewake-uptimeisinherentlyprovidedfortheLTC1098(L)
with setup time = 1μs (see Figure 2).
CS
D
1
D
2
IN
IN
D
1
D
2
OUT
OUT
Data Transfer
SHIFT MUX
ADDRESS IN
TheCLKsynchronizesthedatatransferwitheachbitbeing
transmitted on the falling CLK edge and captured on the
rising CLK edge in both transmitting and receiving sys-
tems. The LTC1098(L) first receives input data and then
transmits back the A/D conversion result (half duplex).
1 NULL ꢀIT SHIFT A/D CONVERSION
RESULT OUT
10968 AI01
is output on the D
line. At the end of the data exchange
OUT
CS should be brought high. This resets the LTC1098(L) in
preparation for the next data exchange.
ꢀecause of the half duplex operation, D and D
may
IN
OUT
be tied together allowing transmission over just three
wires: CS, CLK and DATA (D /D ).
The LTC1096(L) does not require a configuration input
IN OUT
word and has no D pin. A falling CS initiates data trans-
IN
Datatransferisinitiatedbyafallingchipselect(CS)signal.
After CS falls the LTC1098(L) looks for a start bit. After the
start bit is received, the 3-bit input word is shifted into the
feras shown in the LTC1096(L) operating sequence. After
CS falls, the first CLK pulse enables D . After one null
OUT
bit, the A/D conversion result is output on the D
line.
OUT
D input which configures the LTC1098(L) and starts the
IN
ꢀringing CS high resets the LTC1096(L) for the next data
conversion. After one null bit, the result of the conversion
exchange.
10968fc
16
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
MSB-FIRST DATA (MSBF = 1)
t
CYC
CS
POWER
DOWN
t
WAKEUP
CLK
t
suCS
ODD/
SIGN
START
D
D
DON'T CARE
ꢀ4 ꢀ3
IN
MSꢀF
SGL/
DIFF
NULL
HI-Z
Hi-Z
OUT
ꢀ5
t
ꢀ2 ꢀ1 ꢀ0*
ꢀIT ꢀ7
ꢀ6
(MSꢀ)
t
SMPL
CONV
MSB-FIRST DATA (MSBF = 0)
t
CYC
CS
POWER
DOWN
t
WAKEUP
CLK
t
suCS
ODD/
SIGN
START
D
D
DON'T CARE
ꢀ1 ꢀ2
IN
MSꢀF
SGL/
DIFF
NULL
HI-Z
Hi-Z
ꢀ6
ꢀ0
ꢀIT ꢀ7
ꢀ5
t
ꢀ4 ꢀ3
ꢀ2 ꢀ1
ꢀ3
ꢀ5 ꢀ6 ꢀ7*
OUT
ꢀ4
(MSꢀ)
t
10968 F02
SMPL
CONV
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.
Figure 2. LTC1098(L) Operating Sequence Example: Differential Inputs (CH+, CH–)
Input Data Word
Start Bit
The LTC1096(L) requires no D word. It is permanently
The first “logical one” clocked into the D input after CS
IN
IN
configured to have a single differential input. The conver-
goes low is the start bit. The start bit initiates the data
transfer.TheLTC1098(L)willignoreallleadingzeroswhich
precede this logical one. After the start bit is received,
the remaining bits of the input word will be clocked in.
sion result, in which output on the D
line is MSꢀ-first
OUT
sequence, followed by LSꢀ sequence providing easy
interface to MSꢀ- or LSꢀ-first serial ports.
Further inputs on the D pin are then ignored until the
IN
The LTC1098(L) clocks data into the D input on the ris-
IN
next CS cycle.
ing edge of the clock. The input data words are defined
as follows:
SGL/ ODD/
DIFF SIGN
START
MSꢀF
MUX MSꢀ-FIRST/
ADDRESS LSꢀ-FIRST
10968 AI02
10968fc
17
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
Multiplexer (MUX) Address
Unipolar Transfer Curve
The bits of the input word following the START bit assign
the MUX configuration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the followintg tables.
In single-ended mode, all input channels are measured
with respect to GND.
The LTC1096(L)/LTC1098(L) are permanently configured
for unipolar only. The input span and code assignment for
this conversion type are shown in the following figures
for a 5V reference.
Unipolar Transfer Curve
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0
LTC1098(L) Channel Selection
•
•
•
MUX ADDRESS
SGL/DIFF ODD/SIGN
CHANNEL #
0
1
GND
–
–
1
1
0
0
0
1
0
1
+
SINGLE-ENDED MUX MODE
DIFFERENTIAL MUX MODE
+
–
+
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
V
IN
+
–
10968 AI03
10968 AI04
MSB-First/LSB-First (MSBF)
The output data of the LTC1098(L) is programmed for
MSꢀ-first or LSꢀ-first sequence using the MSꢀF bit.
When the MSꢀF bit is a logical one, data will appear on
Unipolar Output Code
INPUT VOLTAGE
(V = 5.000V)
OUTPUT CODE
INPUT VOLTAGE
REF
4.9805V
the D
line in MSꢀ-first format. Logical zeros will be
1 1 1 1 1 1 1 1
V
V
– 1LSꢀ
REF
REF
OUT
4.9609V
1 1 1 1 1 1 1 0
– 2LSꢀ
•
filled in indefinitely following the last data bit. When the
MSꢀF bit is a logical zero, LSꢀ-first data will follow the
•
•
•
•
•
•
•
•
0.0195V
0V
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
1LSꢀ
normal MSꢀ-first data on the D
Sequence)
line. (see Operating
0V
OUT
10968 AI05
Operation with D and D
Tied Together
IN
OUT
The LTC1098(L) can be operated with D and D
tied
IN
OUT
together. This eliminates one of the lines required to com-
municate to the microprocessor (MPU). Data is transmit-
ted in both directions on a single wire. The processor pin
connectedtothisdatalineshouldbeconfigurableaseither
an input or an output. The LTC1098(L) will take control of
10968fc
18
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
MSꢀF ꢀIT LATCHED
ꢀY LTC1098(L)
CS
1
2
3
4
CLK
DATA (D /D
)
START
SGL/DIFF
ODD/SIGN
MSꢀF
ꢀ7
ꢀ6
• • •
IN OUT
MPU CONTROLS DATA LINE AND SENDS
MUX ADDRESS TO LTC1098(L)
LTC1098(L) CONTROLS DATA LINE AND SENDS
A/D RESULT ꢀACK TO MPU
PROCESSOR MUST RELEASE
DATA LINE AFTER 4TH RISING CLK
AND ꢀEFORE THE 4TH FALLING CLK
LTC1098(L) TAKES CONTROL OF
DATA LINE ON 4TH FALLING CLK
10968 F03
Figure 3. LTC1098(L) Operation with DIN and DOUT Tied Together
the data line and drive it low on the 4th falling CLK edge
after the start bit is received (see Figure 3). Therefore the
processor port line must be switched to an input before
this happens, to avoid a conflict.
its normal operating power continuously. Figure 5 shows
that the typical current varies from 40μA at clock rates
below 50kHz to 100μA at 500kHz. Several things must
be taken into account to achieve such a low power
consumption.
In the Typical Applications section, there is an example of
interfacingtheLTC1098(L)withD andD
tiedtogether
IN
OUT
SUPPLY CURRENT vs CLOCK RATE FOR
ACTIVE AND SHUTDOWN MODES
140
to the Intel 8051 MPU.
T
= 25°C
CC
A
120
100
80
V
= 5V
ACHIEVING MICROPOWER PERFORMANCE
With typical operating currents of 40μA and automatic
shutdown between conversions, the LTC1096/LTC1098
achieves extremely low power consumption over a wide
range of sample rates (see Figure 4). In systems that
convert continuously, the LTC1096/LTC1098 will draw
60
ACTIVE (CS LOW)
40
20
0.002
0
SHUTDOWN (CS HIGH)
1000
T
= 25°C
= 5V
A
100
1k
10k
100k
1M
V
CC
CLOCK FREQUENCY (Hz)
10968 F05
Figure 5. After a Conversion, When the Microprocessor
Drives CS High, the ADC Automatically Shuts Down Until the
Next Conversion. The Supply Current, Which Is Very Low
During cConversions, Drops to Zero in Shutdown
100
10
1
Shutdown
Figures 1 and 2 show the operating sequence of the
LTC1096/LTC1098. The converter draws power when the
CS pin is low and powers itself down when that pin is high.
If the CS pin is not taken to ground when it is low and not
taken to supply voltage when it is high, the input buffers
0.1
1
10
(kHz)
100
Sample Rate, f
SAMPLE
10968 F04
Figure 4. Automatic Power Shutdown Between Conversions
Allows Power Consumption to Drop with Sample Rate
10968fc
19
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
of the converter will draw current. This current may be
larger than the typical supply current. It is worthwhile to
bring the CS pin all the way to ground when it is low and
all the way to supply voltage when it is high to obtain the
lowest supply current.
Wake-Up Time
A 10μs wake-up time must be provided for the ADCs
to convert correctly on a 5V supply. The wake-up time
is typically less than 3μs over the supply voltage range
(see typical curve of Wake-Up Time vs Supply Voltage).
With 10μs wake-up time provided over the supply range,
the ADCs will have adequate time to wake up and acquire
input signals.
When the CS pin is high (= supply voltage), the converter
is in shutdown mode and draws only leakage current. The
status of the D and CLK input have no effect on supply
IN
current during this time. There is no need to stop D and
IN
Input Logic Levels
CLK with CS = high, except the MPU may benefit.
The input logic levels of CS, CLK and D are made to meet
IN
Minimize CS Low Time
TTL on 5V supply. When the supply voltage varies, the
input logic levels also change. For the LTC1096/LTC1098
to sample and convert correctly, the digital inputs have
to meet logic low and high levels relative to the operating
supply voltage (see typical curve of Digital Input Logic
Threshold vs Supply Voltage). If achieving micropower
consumption is desirable, the digital inputs must go rail-
to-railbetweensupplyvoltageandground(seeACHIEVING
MICROPOWER PERFORMANCE section).
Insystemsthathavesignificanttimebetweenconversions,
lowest power drain will occur with the minimum CS low
time. ꢀringing CS low, waiting 10μs for the wake-up time,
transferring data as quickly as possible, and then bringing
it back high will result in the lowest current drain. This
minimizes the amount of time the device draws power.
Even though the device draws more power at high clock
rates, the net power is less because the device is on for
a shorter time.
Clock Frequency
D
OUT
Loading
The maximum recommended clock frequency is 500kHz
fortheLTC1096/LTC1098runningoffa5Vsupply.Withthe
supply voltage changing, the maximum clock frequency
for the devices also changes (see the typical curve of
Maximum Clock Rate vs Supply Voltage). If the maximum
clock frequency is used, care must be taken to ensure that
the device converts correctly.
Capacitive loading on the digital output can increase
power consumption. A 100pF capacitor on the D pin
OUT
can more than double the 100μA supply current drain at a
500kHz clock frequency. An extra 100μA or so of current
goesintocharginganddischargingtheloadcapacitor. The
same goes for digital lines driven at a high frequency by
any logic. The CxVxf currents must be evaluated and the
troublesome ones minimized.
Mixed Supplies
It is possible to have a microprocessor running off a 5V
supply and communicate with the LTC1096/LTC1098 op-
erating on 3V or 9V supplies. The requirement to achieve
Lower Supply Voltage
For lower supply voltages, LTC offers the LTC1096L/
LTC1098L. These pin compatible devices offer specified
this is that the outputs of CS, CLK and D from the MPU
IN
performance to 2.65V
supply.
have to be able to trip the equivalent inputs of the ADCs
MIN
and the output of D
from the ADCs must be able to
OUT
toggle the equivalent input of the MPU (see typical curve
OPERATING ON OTHER THAN 5V SUPPLIES
of Digital Input Logic Threshold vs Supply Voltage). With
The LTC1096 operates from 3V to 9V supplies and the
LTC1098 operates from 3V to 6V supplies. To operate the
LTC1096/LTC1098 on other than 5V supplies, a few things
must be kept in mind.
the LTC1096 operating on a 9V supply, the output of D
OUT
may go between 0V and 9V. The 9V output may damage
the MPU running off a 5V supply. The way to get around
this possibility is to have a resistor divider on D
OUT
10968fc
20
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
(Figure 6) and connect the center point to the MPU input.
The V pin should be bypassed to the ground plane with
CC
It should be noted that to get full shutdown, the CS input
a 1μF tantalum with leads as short as possible. If power
supplyisclean,theLTC1096(L)/LTC1098(L)canalsooper-
ate with smaller 0.1μF surface mount or ceramic bypass
capacitors. All analog inputs should be referenced directly
tothesinglepointground.Digitalinputsandoutputsshould
be shielded from and/or routed away from the reference
and analog circuitry.
of the LTC1096/LTC1098 must be driven to the V volt-
CC
age. This would require adding a level shift circuit to the
CS signal in Figure 6.
9V
OPTIONAL
LEVEL SHIFT
4.7μF
9V
SAMPLE-AND-HOLD
MPU
5V
ꢀoththeLTC1096(L)andtheLTC1098(L)provideabuilt-in
sample-and-hold (S&H) function to acquire signals. The
S&H of the LTC1096(L) acquires input signals from “+”
(e.g. 8051)
CS
V
CC
P1.4
DIFFERENTIAL INPUTS
+IN
–IN
GND
CLK
P1.3
P1.2
50k
6V
COMMON MODE RANGE
0V TO 6V
D
OUT
input relative to “–” input during the t
time (see
WAKEUP
V
REF
50k
Figure1).However,theS&HoftheLTC1098(L)cansample
inputsignalsinthesingle-endedmodeorinthedifferential
LTC1096
10968 F06
inputs during the t
time (see Figure 7).
SMPL
Figure 6. Interfacing a 9V Powered LTC1096 to a 5V System
BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
Single-Ended Inputs
Thesample-and-holdoftheLTC1098(L)allowsconversion
of rapidly varying signals. The input voltage is sampled
during the t
time as shown in Figure 7. The sampling
SMPL
TheLTC1096(L)/LTC1098(L)shouldbeusedwithananalog
ground plane and single point grounding techniques. The
GND pin should be tied directly to the ground plane.
interval begins as the bit preceding the MSꢀF bit is shifted
SAMPLE
HOLD
"+" INPUT MUST
SETTLE DURING
THIS TIME
CS
t
t
CONV
SMPL
CLK
D
START
SGL/DIFF
MSꢀF
DON'T CARE
IN
D
OUT
ꢀ7
1ST ꢀIT TEST "–" INPUT MUST
SETTLE DURING THIS TIME
"+" INPUT
"–" INPUT
10968 F07
Figure 7. LTC1098(L) “+” and “–” Input Settling Windows
10968fc
21
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
in and continues until the falling CLK edge after the MSꢀF
bit is received. On this falling edge, the S&H goes into hold respectively.MinimizingR
mode and the conversion begins.
t
or t
for the LTC1096(L) or the LTC1098(L)
WAKEUP
SMPL
+
andC1willimprovethe
SOURCE
input settling time. If a large “+” input source resistance
must be used, the sample time can be increased by using
a slower CLK frequency.
Differential Inputs
With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two volt-
“–” Input Settling
ages. In this case, the voltage on the selected “+” input At the end of the t
or t
, the input capacitor
SMPL
WAKEUP
is still sampled and held and therefore may be rapidly switches to the “–” input and conversion starts (see
time varying just as in single-ended mode. However, the Figures 1 and 7). During the conversion the “+” input
voltage on the selected “–” input must remain constant voltage is effectively “held” by the sample-and-hold and
and be free of noise and ripple throughout the conver- will not affect the conversion result. However, it is criti-
sion time. Otherwise, the differencing operation may not cal that the “–” input voltage settles completely during
be performed accurately. The conversion time is 8 CLK the first CLK cycle of the conversion time and be free of
–
cycles. Therefore, a change in the “–” input voltage during noise. Minimizing R
and C2 will improve settling
SOURCE
this interval can cause conversion errors. For a sinusoidal time. If a large “–” input source resistance must be used,
voltage on the “–” input this error would be:
= V • 2 • π • f(“–”) • 8/f
CLK
the time allowed for settling can be extended by using a
slower CLK frequency.
V
ERROR (MAX)
PEAK
Where f(“–”) is the frequency of the “–” input voltage,
is its peak amplitude and f is the frequency of
Input Op Amps
V
PEAK
CLK
When driving the analog inputs with an op amp it is im-
portant that the op amp settle within the allowed time (see
Figure 7). Again, the “+” and “–” input sampling times can
be extended as described above to accommodate slower
opamps. Mostopamps, includingtheLT1006andLT1413
single supply op amps, can be made to settle well even
with the minimum settling windows of 3μs (“+” input)
which occur at the maximum clock rate of 500kHz.
the CLK. In most cases V
will not be significant. For
ERROR
a 60Hz signal on the “–” input to generate a 1/4LSꢀ error
(5mV) with the converter running at CLK = 500kHz, its
peak value would have to be 750mV.
ANALOG INPUTS
ꢀecause of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1096(L)/
LTC1098(L)havecapacitiveswitchinginputcurrentspikes.
These current spikes settle quickly and do not cause a
problem. However, if large source resistances are used
or if slow settling op amps drive the inputs, care must be
taken to ensure that the transients caused by the current
spikes settle completely before the conversion begins.
Source Resistance
TheanaloginputsoftheLTC1096/LTC1098looklikea25pF
capacitor (C ) in series with a 500Ω resistor (R ) as
IN
ON
shown in Figure 8. C gets switched between the selected
IN
“+” and “–” inputs once during each conversion cycle.
“+”
+
INPUT
R
SOURCE
“+” Input Settling
LTC1096
LTC1098
V
+
–
IN
IN
C1
The input capacitor of the LTC1096(L) is switched onto
“+” input during the wake-up time (see Figure 1) and
samples the input signal within that time. However, the
input capacitor of the LTC1098(L) is switched onto “+”
R
= 500Ω
ON
“–”
C
= 25pF
IN
–
INPUT
R
SOURCE
V
C2
input during the sample phase (t
, see Figure 7). The
10968 F08
SMPL
sample phase is 1.5 CLK cycles before conversion starts.
Figure 8. Analog Input Equivalent Circuit
The voltage on the “+” input must settle completely within
10968fc
22
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
Largeexternalsourceresistorsandcapacitanceswillslow
the settling of the inputs. It is important that the overall
RC time constants be short enough to allow the analog
inputs to completely settle within the allowed time.
capacitive current spike will be generated on the reference
pin by the ADC. These current spikes settle quickly and do
not cause a problem.
Using a slower CLK will allow more time for the reference
to settle. Even at the maximum CLK rate of 500kHz most
references and op amps can be made to settle within the
RC Input Filtering
It is possible to filter the inputs with an RC network as
+
shown in Figure 9. For large values of C (e.g., 1μF), the
REF
F
LTC1096
EVERY CLK CYCLE
5
capacitive input switching currents are averaged into a
net DC current. Therefore, a filter should be chosen with
a small resistor and large capacitor to prevent DC drops
across the resistor. The magnitude of the DC current is
R
OUT
R
ON
V
5pF TO 30pF
REF
GND
4
approximately I = 25pF(V /t ) and is roughly pro-
DC
IN CYC
10968 F10
portional to V . When running at the minimum cycle time
IN
Figure 10. Reference Input Equivalent Circuit
of 29μs, the input current equals 4.3μA at V = 5V. In this
IN
case, a filter resistor of 390Ω will cause 0.1LSꢀ of full-
scale error. If a larger filter resistor must be used, errors
can be eliminated by increasing the cycle time.
2μs bit time.
Reduced Reference Operation
The minimum reference voltage of the LTC1098 is limited
I
DC
R
FILTER
“+”
LTC1098
“–”
V
to 3V because the V supply and reference are internally
IN
CC
tied together. However, the LTC1096 can operate with
reference voltages below 1V.
C
FILTER
The effective resolution of the LTC1096 can be increased
by reducing the input span of the converter. The LTC1096
exhibits good linearity and gain over a wide range of ref-
erence voltages (see typical curves of Linearity and Full
Scale Error vs Reference Voltage). However, care must be
10968 F09
Figure 9. RC Input Filtering
Input Leakage Current
taken when operating at low values of V because of the
REF
Input leakage currents can also create errors if the source
resistancegetstoolarge.Forinstance,themaximuminput
leakage specification of 1μA (at 125°C) flowing through a
sourceresistanceof3.9kwillcauseavoltagedropof3.9mV
or 0.2LSꢀ. This error will be much reduced at lower tem-
peraturesbecauseleakagedropsrapidly(seetypicalcurve
of Input Channel Leakage Current vs Temperature).
reduced LSꢀ step size and the resulting higher accuracy
requirementplacedontheconverter.Thefollowingfactors
must be considered when operating at low V values.
REF
1. Offset
2. Noise
3. Conversion speed (CLK frequency)
Offset with Reduced V
REF
REFERENCE INPUTS
The offset of the LTC1096 has a larger effect on the output
code when the ADC is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSꢀ as the size of the
LSꢀ is reduced. The typical curve of Unadjusted Offset
Error vs Reference Voltage shows how offset in LSꢀs is
The voltage on the reference input of the LTC1096 defines
the voltage span of the A/D converter. The reference
input transient capacitive switching currents due to the
switched-capacitor conversion technique (see Figure 10).
During each bit test of the conversion (every CLK cycle), a
10968fc
23
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
related to reference voltage for a typical value of V . For
to settle within the bit time at which the clock is running.
Whenusingalargervalueresistordivideronthereference
input the “–” input should be matched with an equivalent
resistance.
OS
example,aV of2mVwhichis0.1LSꢀwitha5Vreference
OS
becomes 0.5LSꢀ with a 1V reference and 2.5LSꢀs with
a 0.2V reference. If this offset is unacceptable, it can be
corrected digitally by the receiving system or by offsetting
the “–” input of the LTC1096.
Bypassing Reference Input with Divider
ꢀypassing the reference input with a divider is also pos-
sible. However, care must be taken to make sure that the
DC voltage on the reference input will not drop too much
below the intended reference voltage.
Noise with Reduced V
REF
ThetotalinputreferrednoiseoftheLTC1096canbereduced
toapproximately1mVpeak-to-peakusingagroundplane,
good bypassing, good layout techniques and minimizing
noise on the reference inputs. This noise is insignificant
with a 5V reference but will become a larger fraction of
an LSꢀ as the size of the LSꢀ is reduced.
AC PERFORMANCE
Two commonly used figures of merit for specifying the
dynamic performance of the ADCs in digital signal pro-
cessing applications are the signal-to-noise ratio (SNR)
and the effective number of bits (ENOꢀs).
For operation with a 5V reference, the 1mV noise is only
0.05LSꢀ peak-to-peak. In this case, the LTC1096 noise
will contribute virtually no uncertainty to the output code.
However, for reduced references, the noise may become
a significant fraction of an LSꢀ and cause undesirable jit-
ter in the output code. For example, with a 1V reference,
this same 1mV noise is 0.25LSꢀ peak-to-peak. This will
reduce the range of input voltages over which a stable
output code can be achieved by 1LSꢀ. If the reference is
further reduced to 200mV, the 1mV noise becomes equal
to 1.25LSꢀs and a stable code may be difficult to achieve.
In this case averaging readings may be necessary.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency to
the RMS amplitude of all other frequency components at
the A/D output. This includes distortion as well as noise
products and for this reason it is sometimes referred to as
signal-to-noise+distortion[S/(N+D)].Theoutputisband
limited to frequencies from DC to one half the sampling
frequency. Figure 11 shows spectral content from DC to
15.625kHz which is 1/2 the 31.25kHz sampling rate.
This noise data was taken in a very clean setup. Any setup-
induced noise (noise or ripple on V , V
add to the internal noise. The lower the reference voltage
to be used, the more critical it becomes to have a clean,
noise free setup.
or V ) will
CC REF
IN
0
–10
–20
f
f
= 31.25kHz
SAMPLE
IN
= 11.8kHz
–30
–40
–50
Conversion Speed with Reduced V
REF
–60
–70
With reduced reference voltages the LSꢀ step size is
reduced and the LTC1096 internal comparator overdrive
is reduced. Therefore, it may be necessary to reduce
the maximum CLK frequency when low values of V
are used.
–80
–90
–100
–110
–120
REF
8
10
0
2
4
6
12 14 16
FREQUENCY (kHz)
10968 F11
Input Divider
Figure 11. This Clean FFT of an 11.8kHz Input Shows
Remarkable Performance for an ADC That Draws Only 100μA
When Sampling at the 31.25kHz Rate
It is OK to use an input divider on the reference input of
the LTC1096 as long as the reference input can be made
10968fc
24
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
Effective Number of Bits
8
7
6
5
f
= 31.25kHz
SAMPLE
The effective number of bits (ENOꢀs) is a measurement
of the resolution of an A/D and is directly related to the
S/(N + D) by the equation:
4
3
ENOꢀ = [S/(N + D) –1.76]/6.02
where S/(N + D) is expressed in dꢀ. At the maximum sam-
pling rate of 33kHz the LTC1096 maintains 7.5 ENOꢀs or
betterto40kHz.Above40kHztheENOꢀsgraduallydecline,
as shown in Figure 12, due to increasing second harmonic
distortion. The noise floor remains approximately 70dꢀ.
2
1
0
20
40
0
INPUT FREQUENCY (kHz)
10968 F12
Figure 12. Dynamic Accuracy Is Maintained Up to an Input
Frequency of 40kHz
TYPICAL APPLICATIONS
MICROPROCESSOR INTERFACES
Table 1. Microprocessor with Hardware Serial Interfaces
Compatible with the LTC1096(L)/LTC1098(L)
TheLTC1096(L)/LTC1098(L)caninterfacedirectly(without
externalhardwaretomostpopularmicroprocessor(MPU)
synchronousserialformats(seeTable1).IfanMPUwithout
a dedicated serial port is used, then three or four of the
MPU’s parallel port lines can be programmed to form the
serial link to the LTC1096(L)/LTC1098(L). Included here
is one serial interface example and one example showing
a parallel port programmed to form the serial interface.
PART NUMBER
Motorola
TYPE OF INTERFACE
MC6805S2,S3
MC68HC11
MC68HC05
SPI
SPI
SPI
RCA
CDP68HC05
Hitachi
SPI
HD6305
HD63705
HD6301
HD63701
HD6303
HD64180
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
CSI/O
Motorola SPI (MC68HC05C4,CM68HC11)
The MC68HC05C4 has been chosen as an example of
an MPU with a dedicated serial port. This MPU transfer
data MSꢀ-first and in 8-bit increments. With two 8-bit
transfers, the A/D result is read into the MPU. The first
National Semiconductor
COP400 Family
COP800 Family
NS8050U
MICROWIRE™
MICROWIRE/PLUS™
MICROWIRE/PLUS
MICROWIRE/PLUS
8-bit transfer sends the D word to the LTC1098(L) and
IN
clocksintotheprocessor. Thesecond8-bittransferclocks
HPC16000 Family
the A/D conversion result, ꢀ7 through ꢀ0, into the MPU.
Texas Instruments
TMS7002
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
ANDing the first MUP received byte with 00Hex clears the
first byte. Notice how the position of the start bit in the
first MPU transmit word is used to position the A/D result
right-justified in two memory locations.
TMS7042
TMS70C02
TMS70C42
TMS32011*
TMS32020
*Requires external hardware
MICROWIRE and MICROWIRE/PLUS are trademarks of
National Semiconductor Corp.
10968fc
25
LTC1096/LTC1096L
LTC1098/LTC1098L
TYPICAL APPLICATIONS
Data Exchange Between LTC1098(L) and MC68HC05C4
START
ꢀIT
ꢀYTE 1
MSꢀF
ꢀYTE 2 (DUMMY)
MPU TRANSMIT
WORD
SGL/ ODD/
DIFF SIGN
0
0
0
1
X
X
X
X
X
X
X
X
X
X = DON'T CARE
CS
START
SGL/
DIFF
ODD/
SIGN
D
IN
DON'T CARE
MSꢀF
CLK
D
ꢀ7
ꢀ7
ꢀ6
ꢀ6
ꢀ5
ꢀ5
ꢀ4
ꢀ4
ꢀ3
ꢀ3
ꢀ2
ꢀ2
ꢀ1
ꢀ1
ꢀ0
ꢀ0
OUT
MPU RECEIVED
WORD
?
?
?
?
?
?
?
0
1ST TRANSFER
2ND TRANSFER
10968 TA03
Hardware and Software Interface to Motorola MC68HC05C4
LABEL
MNEMONIC COMMENTS
START
ꢀCLRn
LDA
ꢀit 0 Port C goes low (CS goes low)
C0
CS
Load LTC1098(L) D word into Acc.
IN
STA
Load LTC1098(L) D word into SPI from Acc.
IN
SCK
MC68HC05C4
MISO
CLK
Transfer begins.
Test status of SPIF
ANALOG
INPUTS
LTC1098
TST
ꢀPL
D
IN
Loop to previous instruction if not done
with transfer
Load contents of SPI data register
D
MOSI
OUT
LDA
10968 TA04
into Acc. (D
MSꢀs)
OUT
STA
AND
STA
TST
ꢀPL
Start next SPI cycle
Clear the first D
word
OUT
Store in memory location A (MSꢀs)
Test status of SPIF
DOUT from LTC1098(L) Stored in MC68HC05C4
Loop to previous instruction if not done
with transfer
LOCATION A
0
0
0
0
0
0
0
0
ꢀYTE 1
ꢀYTE 2
ꢀSETn
LDA
Set ꢀ0 of Port C (CS goes high)
Load contents of SPI data register into
LSꢀ
LOCATION A + 1
ꢀ7
ꢀ6
ꢀ5
ꢀ4
ꢀ3
ꢀ2
ꢀ1
ꢀ0
Acc. (D
LSꢀs)
OUT
STA
Store in memory location A + 1 (LSꢀs)
10968 TA05
10968fc
26
LTC1096/LTC1096L
LTC1098/LTC1098L
TYPICAL APPLICATIONS
Interfacing to the Parallel Port of the
LABEL
MNEMONIC
OPERAND COMMENTS
Intel 8051 Family
MOV
SETꢀ
CLR
MOV
RLC
CLR
MOV
SETꢀ
DJNZ
MOV
CLR
MOV
MOV
RLC
SETꢀ
CLR
A, #FFH
P1.4
D word for LTC1098(L)
IN
Make sure CS is high
CS goes low
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1098(L) and parallel port mi-
croprocessors. Normally the CS, CLK and D signals
wouldbegeneratedonthreeportlinesandtheD
read on a fourth port line. This works very well. However,
we will demonstrate here an interface with the D and
P1.4
LOOP 1
R4, #04
A
Load counter
Rotate D bit into Carry
IN
IN
OUT
P1.3
CLK goes low
signal
P1.2, C
P1.3
Output D bit to LTC1098(L)
IN
CLK goes high
R4, LOOP 1 Next bit
IN
P1, #04
P1.3
ꢀit 2 becomes an input
CLK goes low
D
of the LTC1098(L) tied together as described in the
OUT
LOOP
R4, #09
C, P1.2
A
Load counter
SERIAL INTERFACE section. This saves one wire.
Read data bit into Carry
Rotate data bit into Acc.
CLK goes high
CLK goes low
The 8051 first sends the start bit and MUX address to the
LTC1098(L) over the data line connected to P1.2. Then
P1.2 is reconfigured as an input (by writing to it a one) and
the 8051 reads back the 8-bit A/D result over the same
data line.
P1.3
P1.3
DJNZ
MOV
SETꢀ
R4, LOOP
R2, A
P1.4
Next bit
Store MSꢀs in R2
CS goes high
CS
CLK
P1.4
P1.3
P1.2
DOUT from LTC1098(L) Stored in 8051 RAM
ANALOG
INPUTS
LTC1098(L)
8051
D
MSꢀ
LSꢀ
OUT
D
MUX ADDRESS
A/D RESULT
IN
R2 ꢀ7
ꢀ6
ꢀ5
ꢀ4
ꢀ3
ꢀ2
ꢀ1
ꢀ0
10968 TA06
10968 TA07
MSꢀF ꢀIT LATCHED
ꢀY LTC1098(L)
CS
1
2
3
4
CLK
SGL/
DIFF
ODD/
SIGN
DATA (D /D
)
ꢀ7
ꢀ6
ꢀ5
ꢀ4
ꢀ3
ꢀ2
ꢀ1
ꢀ0
START
MSꢀF
IN OUT
8051 P1.2 OUTPUTS DATA
TO LTC1098(L)
10968 TA08
LTC1098(L) SENDS A/D RESULT
ꢀACK TO 8051 P1.2
8051 P1.2 RECONFIGURED
AS AN INPUT AFTER THE 4TH RISING
CLK AND ꢀEFORE THE 4TH FALLING CLK
LTC1098(L) TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK
10968fc
27
LTC1096/LTC1096L
LTC1098/LTC1098L
A “Quick Look” Circuit for the LTC1096
CS
Users can get a quick look at the function and timing of
the LT1096 by using the following simple circuit (Figure
13). V is tied to V . V is applied to the +IN input and
REF
CC IN
CLK
the –IN input is tied to the ground. CS is driven at 1/16
the clock rate by the 74C161 and D outputs the data.
OUT
The output data from the D
pin can be viewed on an
OUT
oscilloscope that is set up to trigger on the falling edge
of CS (Figure 14). Note the LSꢀ data is partially clocked
out before CS goes high.
D
OUT
10968 F14
NULL
ꢀIT
MSꢀ
(ꢀ7)
LSꢀ
(ꢀ0)
LSꢀ DATA
(ꢀ1)
5V
4.7μF
VERTICAL: 5V/DIV
HORIZONTAL: 10μs/DIV
+
CLR
CLK
A
V
5V
CC
RC
Figure 14. Scope Trace the LTC1096 “Quick Look” Circuit
CS
V
CC
Showing A/D Output 10101010 (AAHEX
)
QA
Qꢀ
QC
QD
T
V
CH0
CH1
GND
CLK
ꢀ
C
IN
74C161
LTC1096
D
3V
D
P
GND
OUT
V
REF
LOAD
0.1μF
LM134
75k
678Ω
V
CC
CLOCK IN 150kHz MAX
TO OSCILLOSCOPE
+IN
CS
13.5k
10968 F13
TO μP
–IN LTC1096 CLK
182k
Figure 13. “Quick Look” Circuit for the LTC1096
V
D
OUT
REF
GND
LT1004-1.2
Figure 15 shows a temperature measurement system.
The LTC1096 is connected directly to the low cost silicon
0.01μF
0.01μF
63.4k
10968 F15
temperature sensor. The voltage applied to the V
pin
REF
adjusts the full scale of the A/D to the output range of the
sensor. The zero point of the converter is matched to the
zero output voltage of the sensor by the voltage on the
LTC1096’s negative input.
Figure 15. The LTC1096’s High Impedance Input Connects
Directly to This Temperature Sensor, Eliminating Signal
Conditioning Circuitry in This 0°C to 70°C Thermometer
10968fc
28
LTC1096/LTC1096L
LTC1098/LTC1098L
Remote or Isolated Systems
and the optoisolators draw power only when data is being
transferred. The system consumes only 50μA at a sample
rate of 10Hz (1ms on-time and 99ms off-time). This is
easily within the current supplied by the charge pump
running at 5MHz. If a truly isolated system is required,
the system’s low power simplifies generating an isolated
supply or powering the system from a battery.
Figure 16 shows a floating system that sends data to a
grounded host system. The floating circuitry is isolated by
twooptoisolatorsandpoweredbyasimplecapacitordiode
chargepump.Thesystemhasverylowpowerrequirements
because the LTC1096 shuts down between conversions
FLOATING SYSTEM
1N5817
+
0.001μF
0.1μF
47μF
2kV
2N3904
75k
1N5817
V
CC
V
REF
0.022μF
100k
20k
LT1004-2.5
CS
5MHz
300Ω
LTC1096
+IN
–IN
ANALOG
INPUT
1N5817
CLK
D
OUT
100k
GND
CLK
1k
10k
500k
DATA
10968 F16
Figure 16. Power for This Floating A/D System Is Provided by a Simple Capacitor Diode Charge Pump. The Two Optoisolators
Draw No Current Between Samples, Turning On Only to Send the Clock and Receive Data
10968fc
29
LTC1096/LTC1096L
LTC1098/LTC1098L
PACKAGE DESCRIPTION
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.400*
(10.160)
MAX
8
7
6
5
4
.255 .015*
(6.477 0.381)
1
2
3
.130 .005
.300 – .325
.045 – .065
(3.302 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
.065
(1.651)
TYP
.008 – .015
(0.203 – 0.381)
.120
.020
(0.508)
MIN
(3.048)
MIN
+.035
.325
–.015
.018 .003
(0.457 0.076)
.100
(2.54)
BSC
+0.889
8.255
(
)
N8 1002
–0.381
NOTE:
INCHES
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
10968fc
30
LTC1096/LTC1096L
LTC1098/LTC1098L
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 .005
.050 BSC
7
5
8
6
.245
MIN
.160 .005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 .005
TYP
1
3
4
2
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
SO8 0303
10968fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC1096/LTC1096L
LTC1098/LTC1098L
TYPICAL APPLICATION
A/D Conversion for 3V Systems
and sends it to the microprocessor in serial format. The
LT1004 provides the full-scale reference for the ADC. The
other half of the LTC1178 is used to provide low battery
detection. The circuit’s 70μA supply current is dominated
by the op amps and the reference. The circuit can be
located near the battery and data transmitted serially to
the microprocessor.
The LTC1096/LTC1098 are ideal for 3V systems. Figure
17 shows a 3V to 6V battery current monitor that draws
only 70μA from the battery it monitors. The battery cur-
rent is sensed with the 0.02Ω resistor and amplified by
the LT1178. The LTC1096 digitizes the amplifier output
0.1μF
0.1μF
3V TO 6V
73.2k
470k
750k
24.9k
+
CS
+
V
CC
CLK
L
O
A
D
1/2 LT1178
0.02Ω FOR 2A FULL SCALE
0.2Ω FOR 0.2A FULL SCALE
LTC1096
D
–
OUT
–
TO μP
GND
V
REF
20M
+
LO ꢀATTERY
1/2 LT1178
470k
LT1004-1.2
–
10968 F17
Figure 17. This 0A to 2A Battery Current Monitor Draws Only 70μA from a 3V Battery
RELATED PARTS
PART NUMBER
LTC1196/LTC1198
LTC1286/LTC1298
LTC1285/LTC1298
LTC1400
DESCRIPTION
COMMENTS
8-Pin SO, 1Msps, 8-ꢀit ADCs
Low Power, Small Size, Low Cost
1- or 2-Channel, Auto Shutdown
1- or 2-Channel, Auto Shutdown
8-Pin SO, 5V Micropower, 12-ꢀit ADCs
8-Pin SO, 3V Micropower, 12-ꢀit ADCs
5V High Speed,Serial 12-ꢀit ADC
400ksps, Complete with V , CLK, Sample-and-Hold
REF
LTC1594/LTC1598
LTC1594L/LTC1598L
4- and 8-Channel, 5V Micropower, 12-ꢀit ADCs
4- and 8-Channel, 3V Micropower, 12-ꢀit ADCs
Low Power, Small Size, Low Cost
Low Power, Small Size, Low Cost
10968fc
LT 0708 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy ꢀlvd., Milpitas, CA 95035-7417
32
●
●
© LINEAR TECHNOLOGY CORPORATION 1994
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明