LTC1148LCS#TRPBF [Linear]
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| 型号： | LTC1148LCS#TRPBF |
| 厂家： | 
Linear |
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LTC1148
LTC1148-3.3/LTC1148-5
High Efficiency Synchronous
Step-Down Switching Regulators
U
DESCRIPTIO
EATURE
S
F
The LTC®1148 series is a family of synchronous step-
down switching regulator controllers featuring automatic
Burst ModeTM operation to maintain high efficiencies at
low output currents. These devices drive external comple-
mentary power MOSFETs at switching frequencies up to
250kHz using a constant off-time current-mode architec-
ture providing constant ripple current in the inductor.
■
Ultrahigh Efficiency: Over 95% Possible
Current-Mode Operation for Excellent Line and Load
Transient Response
High Efficiency Maintained Over Three Decades of
Output Current
■
■
■
■
■
■
■
■
■
■
■
Low 160µA Standby Current at Light Loads
Logic Controlled Micropower Shutdown: IQ < 20µA
Wide VIN Range: 3.5V* to 20V
The operating current level is user-programmable via an
external current sense resistor. Wide input supply range
allows operation from 3.5V* to 18V (20V maximum).
Constantoff-timearchitectureprovideslowdropoutregu-
lation limited by only the RDS(ON) of the external MOSFET
and resistance of the inductor and current sense resistor.
Short-Circuit Protection
Very Low Dropout Operation: 100% Duty Cycle
Synchronous FET Switching for High Efficiency
Adaptive Nonoverlap Gate Drives
Output Can Be Externally Held High in Shutdown
Available in 14-Pin Narrow SO Package
The LTC1148 series combines synchronous switching for
maximum efficiency at high currents with an automatic low
currentoperatingmode,calledBurstModeoperation,which
reducesswitchinglosses.Standbypowerisreducedtoonly
2mWatVIN =10V(atIOUT =0). LoadcurrentsinBurstMode
operation are typically 0mA to 300mA.
O U
PPLICATI
S
A
■
■
■
■
■
■
Notebook and Palmtop Computers
Portable Instruments
Battery-Operated Digital Devices
Cellular Telephones
DC Power Distribution Systems
GPS Systems
For operation up to 48V input, see the LTC1149 and
LTC1159 data sheets and Application Note 54.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Modeis a trademark of Linear Technology Corporation.
* LTC1148L and LTC1148L-3.3 only.
U
O
TYPICAL APPLICATI
LTC1148-5 Efficiency
V
IN
(5.2V TO 18V)
100
V
= 6V
IN
+
+
C
IN
100µF
1µF
V
IN
P-DRIVE
LTC1148HV-5
SHUTDOWN
95
90
85
80
P-CHANNEL
Si4431DY
V
IN
= 10V
L*
62µH
R
**
SENSE
0.05Ω
V
OUT
0V = NORMAL
>1.5V = SHUTDOWN
5V/2A
+
SENSE
1000pF
I
C
TH
–
SENSE
+
T
C
R
C
OUT
390µF
D1
MBRS140T3
N-CHANNEL
Si4412DY
N-DRIVE
PGND
1k
C
T
SGND
470pF
C
C
3300pF
LT1148 • TA01
0.02
0.2
LOAD CURRENT (A)
2
*COILTRONICS CTX62-2-MP
**KRL SL-1-C1-0R050J
LTC1148 • TA01
Figure 1. High Efficiency Step-Down Converter
1
LTC1148
LTC1148-3.3/LTC1148-5
W W W
W
U
U
ABSOLUTE AXI U RATI GS
/O
PACKAGE RDER I FOR ATIO
(Note 1)
Input Supply Voltage (Pin 3)
ORDER PART
NUMBER
LTC1148 and LTC1148L Series ............ 16V to –0.3V
LTC1148HV Series ............................... 20V to –0.3V
Continuous Output Current (Pins 1, 14) .............. 50mA
Sense Voltages (Pins 7, 8)
TOP VIEW
LTC1148CN
1
2
3
4
5
6
7
N-DRIVE
NC
14
13
12
11
10
9
P-DRIVE
NC
LTC1148HVCN
LTC1148CN-3.3
LTC1148HVCN-3.3
LTC1148CN-5
PGND
V
LTC1148HV (Adjustable Only)
IN
SGND
C
T
VIN ≥ 12.7V ...................................... 13V to –0.3V
VIN < 12.7V ......................... (VIN + 0.3V) to –0.3V
Operating Ambient Temperature Range ...... 0°C to 70°C
Extended Commercial
Temperature Range ............................... –40°C to 85°C
Junction Temperature (Note 2)............................ 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
SHUTDOWN
INTV
I
CC
LTC1148HVCN-5
LTC1148CS
LTC1148HVCS
LTC1148LCS
V
*
FB
TH
–
+
SENSE
8
SENSE
N PACKAGE
14-LEAD PDIP
S PACKAGE
14-LEAD PLASTIC SO
*FIXED OUTPUT VERSIONS = NC
LTC1148CS-3.3
LTC1148HVCS-3.3
LTC1148LCS-3.3
LTC1148CS-5
TJMAX = 125°C, θJA = 70°C/ W (N)
TJMAX = 125°C, θJA = 110°C/ W (S)
LTC1148HVCS-5
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
TA = 25°C, VIN = 10V, VSHUTDOWN = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Feedback Voltage (LTC1148, LTC1148L,
LTC1148HV)
V
IN
= 9V
●
●
1.21
1.25
1.29
V
9
I
Feedback Current (LTC1148, LTC1148L,
LTC1148HV)
0.2
1
µA
9
V
OUT
Regulated Output Voltage
LTC1148-3.3, LTC1148HV-3.3, LTC1148L-3.3
LTC1148-5, LTC1148HV-5
V
= 9V
= 700mA
= 700mA
IN
I
I
●
●
3.23
4.90
3.33
5.05
3.43
5.20
V
V
LOAD
LOAD
∆V
OUT
Output Voltage Line Regulation
Output Voltage Load Regulation
V
IN
= 7V to 12V, I = 50mA
LOAD
–40
0
40
mV
LTC1148-3.3, LTC1148HV-3.3, LTC1148L-3.3 5mA < I
< 2A
< 2A
●
●
40
60
65
100
mV
mV
LOAD
LOAD
LTC1148-5, LTC1148HV-5
5mA < I
Output Ripple (Burst Mode)
I
= 0A
50
mV
P-P
LOAD
I
Input DC Supply Current (Note 3)
LTC1148 Series
Normal Mode
(Note 7)
Q
4V < V < 12V
1.6
160
160
10
2.1
230
230
20
mA
µA
µA
µA
IN
Sleep Mode
Sleep Mode (LTC1148-5)
Shutdown
LTC1148HV Series
Normal Mode
Sleep Mode
4V < V < 12V
IN
6V < V < 12V
IN
SHUTDOWN
V
= 2.1V, 4V < V < 12V
IN
4V < V < 18V
1.6
160
160
10
2.3
250
250
22
mA
µA
µA
µA
IN
4V < V < 18V
IN
Sleep Mode (LTC1148HV-5)
Shutdown
6V < V < 18V
IN
SHUTDOWN
V
= 2.1V, 4V < V < 18V
IN
LTC1148L Series
Normal Mode
Sleep Mode
3.5V < V < 12V
1.6
160
10
2.1
230
20
mA
µA
µA
IN
3.5V < V < 12V
IN
Shutdown
V = 2.1V, 3.5V < V < 12V
SHUTDOWN IN
2
LTC1148
LTC1148-3.3/LTC1148-5
ELECTRICAL CHARACTERISTICS
TA = 25°C, VIN = 10V, VSHUTDOWN = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V – V
Current Sense Threshold Voltage
LTC1148, LTC1148HV, LTC1148L
8
7
–
V
V
= 5V, V = V /4 + 25mV (Forced)
25
150
mV
mV
SENSE
SENSE
9
OUT
–
= 5V, V = V /4 – 25mV (Forced)
●
●
●
130
130
170
170
9
OUT
–
–
LTC1148-3.3, LTC1148HV-3.3
LTC1148L-3.3
V
SENSE
V
SENSE
= V
= V
+ 100mV (Forced)
– 100mV (Forced)
25
150
mV
mV
OUT
OUT
–
–
LTC1148-5, LTC1148HV-5
V
SENSE
V
SENSE
= V
= V
+ 100mV (Forced)
– 100mV (Forced)
25
150
mV
mV
OUT
OUT
130
0.5
170
2
V
10
Shutdown Pin Threshold
0.8
1.2
V
I
I
Shutdown Pin Input Current
0V < V
< 8V, V = 16V
5
µA
10
SHUTDOWN
IN
–
C Pin Discharge Current
T
V
OUT
V
OUT
in Regulation, V
= 0V
= V
OUT
50
4
70
2
90
10
µA
µA
4
SENSE
t
Off Time (Note 5)
C = 390pF, I = 700mA
LOAD
5
6
µs
OFF
T
t , t
R
Driver Output Transition Times
C = 3000pF (Pins 1, 14), V = 6V
100
200
ns
F
L
IN
–40°C ≤ TA ≤ 85°C (Note 5), VIN = 10V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
9
Feedback Voltage (LTC1148, LTC1148HV
LTC1148L)
V
IN
= 9V
1.20
1.25
1.30
V
∆V
Regulated Output Voltage
LTC1148-3.3, LTC1148HV-3.3, LTC1148L-3.3
LTC1148-5, LTC1148HV-5
V
= 9V
= 700mA
= 700mA
OUT
IN
I
I
3.17
4.85
3.33
5.05
3.43
5.20
V
V
LOAD
LOAD
I
Input DC Supply Current (Note 3)
LTC1148 Series
Normal Mode
Sleep Mode
(Note 7)
Q
4V < V < 12V
1.6
160
160
10
2.4
260
260
22
mA
µA
µA
µA
IN
4V < V < 12V
IN
Sleep Mode
Shutdown
LTC1148HV Series
Normal Mode
Sleep Mode
Sleep Mode
Shutdown
6V < V < 12V
V
IN
= 2.1V, 4V < V < 12V
SHUTDOWN IN
4V < V < 18V
1.6
160
160
10
2.6
280
280
24
mA
µA
µA
µA
IN
4V < V < 18V
IN
6V < V < 18V
IN
= 2.1V, 4V < V < 18V
SHUTDOWN IN
V
LTC1148L Series
Normal Mode
Sleep Mode
3.5V < V < 12V
1.6
160
10
2.4
260
22
mA
µA
µA
IN
3.5V < V < 12V
IN
Shutdown
V
= 2.1V, 3.5V < V < 12V
SHUTDOWN
IN
V – V
Current Sense Threshold Voltage
LTC1148, LTC1148HV, LTC1148L (Note 4)
8
7
–
V
V
= 5V, V = V /4 – 25mV (Forced)
25
150
mV
mV
SENSE
SENSE
9
OUT
–
= 5V, V = V /4 + 25mV (Forced)
125
125
175
175
9
OUT
–
–
LTC1148-3.3, LTC1148HV-3.3, LTC1148L-3.3
LTC1148-5, LTC1148HV-5
V
SENSE
V
SENSE
= V
= V
+ 100mV (Forced)
– 100mV (Forced)
25
150
mV
mV
OUT
OUT
–
–
V
SENSE
V
SENSE
= V
= V
+ 100mV (Forced)
– 100mV (Forced)
25
150
mV
mV
OUT
OUT
125
0.55
3.8
175
2
V
10
Shutdown Pin Threshold
Off Time (Note 5)
0.8
5
V
t
C = 390pF, I = 700mA
LOAD
6
µs
OFF
T
3
LTC1148
LTC1148-3.3/LTC1148-5
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications which apply over the full operating
Note 4: The LTC1148 and LTC1148HV versions are tested with external
feedback resistors resulting in a nominal output voltage of 5V. The
LTC1148L version is tested with external feedback resistors resulting in a
nominal output voltage of 2.5V.
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 5: In applications where R
time increases approximately 40%.
is placed at ground potential, the off
Note 2: T is calculated from the ambient temperature T and power
SENSE
J
A
dissipation P according to the following formulas:
D
LTC1148CN, LTC1148CN-3.3, LTC1148CN-5: T = T + (P × 70°C/W)
Note 6: The LTC1148, LTC1148HV and LTC1148L series are not tested
and not quality assurance sampled at –40°C and 85°C. These
specifications are guaranteed by design and/or correlation.
J
A
D
LTC1148CS, LTC1148CS-3.3, LTC1148CS-5: T = T + (P × 110°C/W)
J
A
D
Note 3: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 7: The LTC1148L and LTC1148L-3.3 allow operation to V = 3.5V.
IN
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Input Voltage
Line Regulation
Load Regulation
100
98
96
94
92
90
88
86
84
82
80
40
30
20
0
FIGURE 1 CIRCUIT
FIGURE 1 CIRCUIT
FIGURE 1 CIRCUIT
I
= 1A
LOAD
R
= 0.05Ω
SENSE
I
= 1A
20
LOAD
–20
–40
V
= 6V
10
IN
0
–10
–20
–30
–40
V
IN
= 12V
I
= 100mA
LOAD
–60
–80
–100
0
4
8
12
16
20
8
12
0
4
16
20
0
0.5
1
1.5
2
2.5
INPUT VOLTAGE (V)
LOAD CURRENT (A)
INPUT VOLTAGE (V)
LTC1148 • TPC01
LTC1148 • TPC02
LTC1148 • TPC03
Operating Frequency
vs (VIN – VOUT
DC Supply Current
Supply Current in Shutdown
)
2.1
20
18
16
14
12
10
8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
NOT INCLUDING
GATE CHARGE CURRENT
V
= 2V
SHUTDOWN
V
= 5V
OUT
1.8
1.5
1.2
0.9
0.6
0.3
0°C
ACTIVE MODE
70°C
25°C
6
4
SLEEP MODE
2
0
0
0
0
2
4
6
8
10 12 14 16 18 20
0
2
6
8
10 12 14 16 18 20
4
4
0
2
6
8
10
12
INPUT VOLTAGE (V)
INPUT VOLTAGE
(V – V ) VOLTAGE (V)
IN OUT
LTC1148 • TPC05
LTC1148 • TPC04
LTC1148 • TPC06
4
LTC1148
LTC1148-3.3/LTC1148-5
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Off Time vs VOUT
Gate Charge Supply Current
Current Sense Threshold Voltage
28
24
20
16
12
8
175
80
70
60
50
40
30
20
10
0
–
V
= V
OUT
MAXIMUM
THRESHOLD
SENSE
150
125
100
75
Q
+ Q = 100nC
P
N
50
Q
N
+ Q = 50nC
P
MINIMUM
THRESHOLD
4
25
LTC1148-5
3
LTC1148-3.3
0
0
20
80
140
200
260
0
20
40
60
80
100
2
0
1
4
5
OPERATING FREQUENCY (kHz)
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
LTC1148 • TPC07
LTC1148 • TPC09
LTC1148 • TPC08
U
U
U
PI FU CTIO S
P-DRIVE (Pin 1): High Current Drive for Top P-Channel
VFB (Pin 9): For the LTC1148 adjustable version, Pin 9
serves as the feedback pin from an external resistive
divider used to set the output voltage. On LTC1148-3.3
and LTC1148-5 versions this pin is not used.
MOSFET. Voltage swing at this pin is from VIN to ground.
NC (Pin 2): No Connection. Can connect to power ground.
VIN (Pin 3): Main Supply Pin. Must be closely decoupled
to power ground Pin 12.
SHUTDOWN (Pin 10): When grounded, the LTC1148
series operates normally. Pulling Pin 10 high holds both
MOSFETs off and puts the LTC1148 series in micropower
shutdown mode. Requires CMOS logic signal with tR,
tF < 1µs, should not be left floating.
CT (Pin 4): External capacitor CT from Pin 4 to ground sets
the operating frequency. The actual frequency is also
dependent upon the input voltage.
INTVCC (Pin 5): Internal Supply Voltage, Nominally 3.3V.
Can be decoupled to signal ground. Do not externally load
this pin.
SGND (Pin 11): Small-Signal Ground. Must be routed
separately from other grounds to the (–) terminal of COUT
.
PGND (Pin 12): Driver Power Ground. Connects to source
of N-channel MOSFET and the (–) terminal of CIN.
ITH (Pin 6): Gain Amplifier Decoupling Point. The current
comparator threshold increases with the Pin 6 voltage.
SENSE– (Pin 7): Connects to internal resistive divider
which sets the output voltage in LTC1148-3.3 and
LTC1148-5 versions. Pin 7 is also the (–) input for the
current comparator.
NC(Pin13):NoConnection.Canconnecttopowerground.
N-DRIVE (Pin 14): High Current Drive for Bottom
N-Channel MOSFET. Voltage swing at Pin 14 is from
ground to VIN.
SENSE+ (Pin 8): The (+) Input to the Current Comparator.
A built-in offset between Pins 7 and 8 in conjunction with
RSENSE sets the current trip threshold.
5
LTC1148
LTC1148-3.3/LTC1148-5
U
U
W
FU CTIO AL DIAGRA
Pin 9 connection shown for LTC1148-3.3 and LTC1148-5; changes create LTC1148.
3
1
V
IN
+
–
P-DRIVE
SGND
11
SENSE
8
SENSE
7
ADJUSTABLE
VERSION
V
FB
14 N-DRIVE
12 PGND
9
–
+
V
SLEEP
–
25mV TO 150mV
R
S
C
Q
+
–
+
+
–
5pF
S
V
OS
–
+
–
+
V
V
TH1
TH2
13k
T
I
6
G
TH
100k
1.25V
V
IN
OFF-TIME
CONTROL
–
SENSE
REFERENCE
4
SHUTDOWN 10
5 INTV
CC
V
FB
C
T
LTC1148 • FD
TEST CIRCUIT
+
+
330µF
IRF9Z34
V
IN
1N5818
IRFZ34
1
2
3
4
5
6
7
14
13
12
11
10
9
N-DRIVE
P-DRIVE
NC
NC
PGND
50µH
1µF
+
LTC1148
V
IN
C
T
SGND
V
10
+
100pF
SHUTDOWN
25k
75k
INTV
CC
NC (V
)
I
TH
FB
440µF
+
390pF
10nF
3300pF
8
+
–
SENSE
SENSE
+
R
SENSE
0.05Ω
V
1k
7
+
V
7
1000pF
TO
V
8
V
OUT
6
LTC1148
LTC1148-3.3/LTC1148-5
U
OPERATIO
The LTC1148 series uses a current mode, constant off-
time architecture to synchronously switch an external
pair of complementary power MOSFETs. Operating fre-
quency is set by an external capacitor at the timing
capacitor Pin 4.
(Pin 6) to increase the current comparator threshold, thus
tracking the load current.
The sequence of events for Burst Mode operation is very
similar to continuous operation with the cycle interrupted
by the voltage comparator. When the output voltage is at
orabovethedesiredregulatedvalue,theP-channelMOSFET
is held off by comparator V and the timing capacitor
continues to discharge below VTH1. When the timing
capacitor discharges past VTH2, voltage comparator S
trips, causing the internal sleep line to go low and the N-
channel MOSFET to turn off.
The output voltage is sensed by an internal voltage
divider connected to SENSE– Pin 7 (LTC1148-3.3 and
LTC1148-5) or external divider returned to VFB Pin 9
(LTC1148). A voltage comparator V, and a gain block G,
compare the divided output voltage with a reference
voltage of 1.25V. To optimize efficiency, the LTC1148
series automatically switches between two modes of
operation, burst and continuous. The voltage compara-
tor is the primary control element when the device is in
Burst Modeoperation, while the gain block controls the
output voltage in continuous mode.
The circuit now enters sleep mode with both power
MOSFETs turned off. In sleep mode, a majority of the
circuitry is turned off, dropping the quiescent current
from 1.6mA to 160µA. The load current is now being
supplied from the output capacitor. When the output
voltage has dropped by the amount of hysteresis in
comparator V, the P-channel MOSFET is again turned on
and the process repeats.
During the switch “ON” cycle in continuous mode, current
comparator C monitors the voltage between Pins 7 and 8
connected across an external shunt in series with the
inductor. When the voltage across the shunt reaches its
threshold value, the P-drive output is switched to VIN,
turning off the P-channel MOSFET. The timing capacitor
connected to Pin 4 is now allowed to discharge at a rate
determined by the off-time controller. The discharge cur-
rent is made proportional to the output voltage (measured
by Pin 7) to model the inductor current, which decays at
a rate which is also proportional to the output voltage.
While the timing capacitor is discharging, the N-drive
output goes to VIN, turning on the N-channel MOSFET.
To avoid the operation of the current loop interfering with
Burst Mode operation, a built-in offset (VOS) is incorpo-
ratedinthegainstage. Thispreventsthecurrentcompara-
tor threshold from increasing until the output voltage has
dropped below a minimum threshold.
To prevent both the external MOSFETs from ever being
turned on at the same time, feedback is incorporated to
sense the state of the driver output pins. Before the
N-drive output can go high, the P-drive output must also
be high. Likewise, the P-drive output is prevented from
going low while the N-drive output is high.
When the voltage on the timing capacitor has discharged
past VTH1, comparator T trips, setting the flip-flop. This
causes the N-drive output to go low (turning off the N-
channel MOSFET) and the P-drive output to also go low
(turning the P-channel MOSFET back on). The cycle
then repeats.
Using constant off-time architecture, the operating fre-
quency is a function of the input voltage. To minimize the
frequencyvariationasdropoutisapproached, theoff-time
controller increases the discharge current as VIN drops
below VOUT + 1.5V. In dropout the P-channel MOSFET is
turned on continuously (100% duty cycle), providing
extremely low dropout operation.
As the load current increases, the output voltage de-
creases slightly. This causes the output of the gain stage
7
LTC1148
LTC1148-3.3/LTC1148-5
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0.20
0.15
0.10
0.05
0
The basic LTC1148 series application circuit (fixed
output versions) is shown in Figure 1. External compo-
nent selection is driven by the load requirement, and
begins with the selection of R
. Once R
is
SENSE
SENSE
known, C and L can be chosen. Next, the power
T
MOSFETsandD1areselected. Finally, C andC
are
IN
OUT
selected and the loop is compensated. The circuit
shown in Figure 1 can be configured for operation up to
an input voltage of 20V. If the application requires
higher input voltage, then the LTC1149 or LTC1159
should be used.
0
1
2
3
4
5
MAXIMUM OUTPUT CURRENT (A)
LTC1148 • F02
RSENSE Selection for Output Current
Figure 2. Selecting RSENSE
RSENSE is chosen based on the required output current.
The LTC1148 series current comparator has a threshold
range which extends from a minimum of 25mV/RSENSE to
a maximum of 150mV/RSENSE. The current comparator
threshold sets the peak of the inductor ripple current,
yielding a maximum output current IMAX equal to the peak
value less half the peak-to-peak ripple current. For proper
Burst Mode operation, IRIPPLE(P-P) must be less than or
equal to the minimum current comparator threshold.
The LTC1148 series automatically extends tOFF during a
short circuit to allow sufficient time for the inductor
current to decay between switch cycles. The resulting
ripple current causes the average short-circuit current
ISC(AVG) to be reduced to approximately IMAX
.
L and CT Selection for Operating Frequency
The LTC1148 series uses a constant off-time architecture
with tOFF determined by an external timing capacitor CT.
Each time the P-channel MOSFET switch turns on, the
voltageonCT isresettoapproximately3.3V. Duringtheoff
time, CT is discharged by a current which is proportional
to VOUT. The voltage on CT is analogous to the current in
inductor L, which likewise decays at a rate proportional to
VOUT. Thus the inductor value must track the timing
capacitor value.
Since efficiency generally increases with ripple current,
the maximum allowable ripple current is assumed, i.e.,
IRIPPLE(P-P) = 25mV/RSENSE (See CT and L Selection for
Operating Frequency). Solving for RSENSE and allowing
a margin for variations in the LTC1148 series and
external component values yields:
100mV
MAX
R
=
SENSE
I
The value of CT is calculated from the desired continuous
mode operating frequency, f:
A graph for selecting R
versus maximum output
SENSE
current is given in Figure 2.
The load current below which Burst Modeoperation com-
mences(IBURST)andthepeakshort-circuitcurrent(ISC(PK)
bothtrackIMAX.OnceRSENSE hasbeenchosen,IBURST and
ISC(PK) can be predicted from the following:
1
C =
T
4
2.6(10 )f
)
Assumes VIN = 2VOUT, Figure 1 circuit.
A graph for selecting CT versus frequency including the
effects of input voltage is given in Figure 3.
15mV
SENSE
I
≈
BURST
As the operating frequency is increased the gate charge
losses will be higher, reducing efficiency (see Efficiency
Considerations). The complete expression for operating
frequency of the circuit in Figure 1 is given by:
R
150mV
SENSE
I
=
SC(PK)
R
8
LTC1148
LTC1148-3.3/LTC1148-5
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1000
Inductor Core Selection
–
V
= V
= 5V
OUT
SENSE
Once the minimum value for L is known, the type of
inductor must be selected. The highest efficiency will be
obtained using ferrite, Kool Mµ® on molypermalloy (MPP)
cores. Lower cost powdered iron cores provide suitable
performance but cut efficiency by 3% to 7%. Actual core
loss is independent of core size for a fixed inductor value,
but it is very dependent on inductance selected. As induc-
tance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses increase.
800
600
400
V
= 12V
200
IN
V
IN
= 7V
200
0
V
= 10V
IN
0
300
100
FREQUENCY (kHz)
LTC1148 • F03
Ferrite designs have very low core loss, so design goals
canconcentrateoncopperlossandpreventingsaturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple which can cause Burst Mode operation to be falsely
triggered. Do not allow the core to saturate!
Figure 3. Timing Capacitor Value
V
V
1
OFF
OUT
f =
1 –
)
)
t
IN
where:
V
REG
OUT
4
t
= 1.3(10 )C
OFF
T
)
V
)
Kool Mµ (from Magnetics, Inc.) is a very good, low loss
core material for toroids, with a “soft” saturation charac-
teristic. Molypermalloy is slightly more efficient at high
(>200kHz) switching frequencies, but quite a bit more
expensive. Toroids are very space efficient, especially
when you can use several layers of wire. Because they
generally lack a bobbin, mounting is more difficult. How-
ever, new designs for surface mount are available from
Coiltronics and Beckman Industrial Corp. which do not
increase the height significantly.
VREG is the desired output voltage (i.e., 5V, 3.3V). VOUT is
the measured output voltage. Thus VREG/VOUT = 1 in
regulation.
Note that as V decreases, the frequency decreases.
IN
When the input to output voltage differential drops
below 1.5V, the LTC1148 series reduces t
by in-
OFF
creasing the discharge current in C . This prevents
T
audible operation prior to dropout.
Once the frequency has been set by C , the inductor L
T
Power MOSFET and D1 Selection
must be chosen to provide no more than 25mV/R
SENSE
of peak-to-peak inductor ripple current. This results in
a minimum required inductor value of:
Two external power MOSFETs must be selected for use
with the LTC1148 series: a P-channel MOSFET for the
main switch, and an N-channel MOSFET for the synchro-
nous switch. The main selection criteria for the power
MOSFETs are the threshold voltage VGS(TH) and on resis-
5
L
= 5.1(10 )R
(C )V
SENSE T REG
MIN
As the inductor value is increased from the minimum
value, the ESR requirements for the output capacitor
are eased at the expense of efficiency. If too small an
inductorisused,theinductorcurrentwilldecreasepast
zero and change polarity. A consequence of this is that
the LTC1148 series may not enter Burst Modeoperation
and efficiency will be severely degraded at low currents.
tance RDS(ON)
.
The minimum input voltage determines whether standard
thresholdorlogic-levelthresholdMOSFETsmustbeused.
For VIN > 8V, standard threshold MOSFETs (VGS(TH) < 4V)
may be used. If VIN is expected to drop below 8V, logic-
Kool Mµis a registered trademark of Magnetics, Inc.
9
LTC1148
LTC1148-3.3/LTC1148-5
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level threshold MOSFETs (VGS(TH) < 2.5V) are strongly
recommended. The LTC1148/LTC1148HV series supply
voltage must always be less than the absolute maximum
CIN and COUT Selection
In continuous mode, the source of the P-channel MOSFET
is a square wave of duty cycle VOUT/VIN. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
RMS capacitor current is given by:
VGS ratings for the MOSFETs.
ThemaximumoutputcurrentIMAX determinestheRDS(ON)
requirement for the two MOSFETs. When the LTC1148
series is operating in continuous mode, the simplifying
assumption can be made that one of the two MOSFETs is
always conducting the average load current. The duty
cycles for the two MOSFETs are given by:
1/2
[V (V – V )]
OUT IN
OUT
C Required I
≈ I
MAX
IN
RMS
V
IN
This formula has a maximum at VIN = 2VOUT, where
RMS = IOUT/2. This simple worst-case condition is com-
I
V
V
OUT
monly used for design because even significant devia-
tions do not offer much relief. Note that capacitor
manufacturer’s ripple current ratings are often based on
only 2000 hours of life. This makes it advisable to further
derate the capacitor, or to choose a capacitor rated at a
higher temperature than required. Always consult the
manufacturer if there is any question. An additional 0.1µF
to 1µF ceramic capacitor is also required on VIN Pin 3 for
high frequency decoupling.
P-Ch Duty Cycle =
N-Ch Duty Cycle =
IN
(V – V
)
OUT
IN
V
IN
From the duty cycles the required RDS(ON) for each MOS-
FET can be derived:
V (P )
IN
P
P-Ch R
=
=
DS(ON)
DS(ON)
2
V
(I
)(1 + δ )
OUT MAX P
The selection of COUT is driven by the required effective
series resistance (ESR). The ESR of COUT must be less
than twice the value of RSENSE for proper operation of the
LTC1148 series:
V (P )
IN
N
N-Ch R
2
(V – V )(I
)(1 + δ )
N
IN
OUT MAX
where PP and PN are the allowable power dissipations and
dP and dN are the temperature dependencies of RDS(ON)
COUT Required ESR < 2RSENSE
.
PP and PN will be determined by efficiency and/or thermal
requirements (see Efficiency Considerations). (1 + d) is
generally given for a MOSFET in the form of a normalized
RDS(ON) vs temperature curve, but d = 0.007/°C can be
used as an approximation for low voltage MOSFETs.
Optimum efficiency is obtained by making the ESR equal
to RSENSE. As the ESR is increased up to 2RSENSE, the
efficiency degrades by less than 1%. If the ESR is greater
than 2RSENSE, the voltage ripple on the output capacitor
willprematurelytriggerBurstModeoperation, resultingin
disruption of continuous mode and an efficiency hit which
can be several percent.
The Schottky diode D1 shown in Figure 1 only conducts
during the dead-time between the conduction of the two
powerMOSFETs. D1’ssolepurposeinlifeistopreventthe
body diode of the N-channel MOSFET from turning on and
storing charge during the dead time, which could cost as
much as 1% in efficiency (although there are no other
harmful effects if D1 is omitted). Therefore, D1 should be
selected for a forward voltage of less than 0.7V when
Manufacturers such as Nichicon and United Chemicon
should be considered for high performance capacitors.
The OS-CON semiconductor dielectric capacitor available
fromSanyohasthelowestESR/sizeratioofanyaluminum
electrolytic at a somewhat higher price. Once the ESR
requirement for COUT has been met, the RMS current
rating generally far exceeds the IRIPPLE(P-P) requirement.
conducting IMAX
.
10
LTC1148
LTC1148-3.3/LTC1148-5
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In surface mount applications multiple capacitors may
have to be paralleled to meet the capacitance, ESR, or
RMS current handling requirements of the application.
Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount configurations. In the
case of tantalum, it is critical that the capacitors are surge
tested for use in switching power supplies. An excellent
choice is the AVX TPS series of surface mount tantalums,
available in case heights ranging from 2mm to 4mm. For
example, if 200µF/10V is called for in an application
requiring 3mm height, two AVX 100µF/10V (P/N TPSD
107K010) could be used. Consult the manufacturer for
other specific recommendations.
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, VOUT shifts by an
amountequalto ∆ILOAD •ESR,whereESRistheeffective
series resistance of COUT. ∆ILOAD also begins to charge
or discharge COUT until the regulator loop adapts to the
current change and returns VOUT to its steady state
value. During this recovery time VOUT can be monitored
for overshoot or ringing which would indicate a stability
problem. The Pin 6 external components shown in the
Figure 1 circuit will prove adequate compensation for
most applications.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately 25 • CLOAD.
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
Atlowsupplyvoltages, aminimumcapacitanceatC
OUT
is needed to prevent an abnormal low frequency oper-
ating mode (see Figure 4). When C is made too
OUT
small, the output ripple at low frequencies will be large
enough to trip the voltage comparator. This causes
BurstModeoperationtobeactivatedwhentheLTC1148
series would normally be in continuous operation. The
effect is most pronounced with low values of R
SENSE
andcanbeimprovedbyoperatingathigherfrequencies
withlowervaluesofL. Theoutputremainsinregulation
at all times.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
1000
L = 50µH
SENSE
R
= 0.02Ω
800
600
400
200
0
L = 25µH
SENSE
R
= 0.02Ω
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power. (For high efficiency circuits only small
errors are incurred by expressing losses as a percentage
of output power).
L = 50µH
= 0.05Ω
R
SENSE
0
1
2
3
4
5
(V – V ) VOLTAGE (V)
IN
OUT
Although all dissipative elements in the circuit produce
losses, threemainsourcesusuallyaccountformostofthe
losses in LTC1148 series circuits: 1) LTC1148 DC bias
current, 2) MOSFET gate charge current, and 3) I2R
losses.
LTC1148 • F04
Figure 4. Minimum Value of COUT
Checking Transient Response
1. The DC supply current is the current which flows into
VIN Pin 3 less the gate charge current. For VIN = 10V the
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
11
LTC1148
LTC1148-3.3/LTC1148-5
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100
95
90
85
80
LTC1148 DC supply current is 160µA for no load, and
increases proportionally with load up to a constant
1.6mA after the LTC1148 series has entered continu-
ous mode. Because the DC bias current is drawn from
VIN, the resulting loss increases with input voltage. For
VIN = 10V the DC bias losses are generally less than 1%
for load currents over 30mA. However, at very low load
currents the DC bias current accounts for nearly all of
the loss.
2
I R
GATE CHARGE
LTC1148 I
Q
2. MOSFETgatechargecurrentresultsfromswitchingthe
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from VIN to ground. The
resulting dQ/dt is a current out of VIN which is typically
much larger than the DC supply current. In continuous
mode, IGATECHG = f (QN + QP). The typical gate charge
for a 0.1Ω N-channel power MOSFET is 25nC, and for
a P-channel about twice that value. This results in
IGATECHG = 7.5mA in 100kHz continuous operation, for
a 2% to 3% typical mid-current loss with VIN = 10V.
0.01
0.03
0.1
0.3
1
3
OUTPUT CURRENT (A)
LTC1148 • F05
Figure 5. Efficiency Loss
The gate charge loss is responsible for the majority of
the efficiency lost in the mid-current region. If Burst
Mode operation was not employed at low currents, the
gatechargelossalonewouldcauseefficiencytodropto
unacceptable levels. With Burst Mode operation, the
DC supply current represents the lone (and unavoid-
able) loss component which continues to become a
higher percentage as output current is reduced. As
expected,theI2Rlossesdominateathighloadcurrents.
Note that the gate charge loss increases directly with
both input voltage and operating frequency. This is the
principal reason why the highest efficiency circuits
operate at moderate frequencies. Furthermore, it ar-
gues against using larger MOSFETs than necessary to
control I2R losses, since overkill can cost efficiency as
well as money!
Other losses including CIN and COUT ESR dissipative
losses, MOSFET switching losses, Schottky conduction
losses during dead time, and inductor core losses, gener-
ally account for less than 2% total additional loss.
3. I2R losses are easily predicted from the DC resistances
oftheMOSFET,inductor,andcurrentshunt.Incontinu-
ous mode the average output current flows through L
and RSENSE, but is “chopped” between the P-channel
and N-channel MOSFETs. If the two MOSFETs have
approximately the same RDS(ON), then the resistance of
one MOSFET can simply be summed with the resis-
tances of L and RSENSE to obtain I2R losses. For
example, if each RDS(ON) = 0.1Ω, RL = 0.15Ω, and
RSENSE = 0.05Ω, then the total resistance is 0.3Ω. This
results in losses ranging from 3% to 12% as the output
current increases from 0.5A to 2A. I2R losses cause the
efficiency to roll-off at high output currents.
Design Example
As a design example, assume VIN = 12V (nominal),
VOUT = 5V, IMAX = 2A, and f = 200kHz; RSENSE, CT and L
can immediately be calculated:
RSENSE = 100mV/2 = 0.05Ω
tOFF = (1/200kHz)[1 – (5/12)] = 2.92µs
CT = 2.92µs/[(1.3)(104)] = 220pF
LMIN = 5.1(
105)0.05Ω(220pF)5V = 28µH
Assume that the MOSFET dissipations are to be limited to
PN = PP = 250mW.
If TA = 50°C and the thermal resistance of each MOSFET
is 50°C/W, then the junction temperatures will be 63°C
Figure 5 shows how the efficiency losses in a typical
LTC1148 series regulator end up being apportioned.
12
LTC1148
LTC1148-3.3/LTC1148-5
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and δP = δN = 0.007(63 – 25) = 0.27. The required RDS(ON)
for each MOSFET can now be calculated:
To prevent stray pickup a 100pF capacitor is suggested
across R1 located close to the LTC1148.
For Figure 1 applications with VOUT below 2V, or when
12(0.25)
5(2) (1.27)
P-Ch R
=
=
= 0.12Ω
R
SENSE is moved to ground, the current sense comparator
DS(ON)
DS(ON)
2
inputsoperatenearground. Whenthecurrentcomparator
is operated at less than 2V common mode, the off time
increases approximately 40%, requiring the use of a
smaller timing capacitor CT.
12(0.25)
N-Ch R
= 0.085Ω
2
7(2) (1.27)
The P-channel requirement can be met by a Si9430DY,
while the N-channel requirement is exceeded by a
Si9410DY. Note that the most stringent requirement for
theN-channelMOSFETiswithVOUT =0(i.e., shortcircuit).
During a continuous short circuit, the worst-case
N-channel dissipation rises to:
Auxiliary Windings – Suppressing Burst Mode
Operation
The LTC1148 synchronous switch removes the normal
limitation that power must be drawn from the inductor
primary winding in order to extract power from auxil-
iary windings. With synchronous switching, auxiliary
outputs may be loaded without regard to the primary
outputload, providingthattheloopremainsincontinu-
ous mode operation.
PN = ISC(AVG)2(RDS(ON))(1 + δN)
With the 0.05Ω sense resistor ISC(AVG) = 2A will result,
increasingthe0.085ΩN-channeldissipationto450mWat
a die temperature of 73°C.
Burst Mode operation can be suppressed at low output
currents with a simple external network which cancels the
25mV minimum current comparator threshold. This tech-
nique is also useful for eliminating audible noise from
certain types of inductors in high current (IOUT > 5A)
applications when they are lightly loaded.
An external offset is put in series with the SENSE– pin to
subtract from the built-in 25mV offset. An example of this
technique is shown in Figure 6. Two 100Ω resistors are
inserted in series with the leads from the sense resistor.
CIN will require an RMS current rating of at least 1A at
temperature, and COUT will require an ESR of 0.05Ω for
optimum efficiency.
NowallowVIN todroptoitsminimumvalue. Atlowerinput
voltages the operating frequency will decrease and the
P-channel will be conducting most of the time, causing its
power dissipation to increase. At VIN(MIN) = 7V:
fMIN = (1/2.92µs)[1 – (5V/7V)] = 98kHz
2
5V(0.12Ω)(2A) (1.27)
R2
100Ω
P =
= 435mW
P
7V
+
SENSE (PIN 8)
R1
100Ω
This last step is necessary to assure that the power
dissipation and junction temperature of the P-channel are
not exceeded.
1000pF
R
SENSE
–
SENSE (PIN 7)
V
OUT
+
R3
C
OUT
LTC1148 Adjustable Applications
LTC1148 • F06
When an output voltage other than 3.3V or 5V is required,
the LTC1148 adjustable version is used with an external
resistive divider from VOUT to VFB Pin 9 (see Figure 9). The
regulated voltage is determined by:
Figure 6. Suppression of Burst Mode Operation
R2
R1
V
= 1.25 1 +
OUT
)
)
13
LTC1148
LTC1148-3.3/LTC1148-5
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With the addition of R3, a current is generated through R1
causing an offset of:
5
INTV
CC
FROM CROWBAR DETECT CIRCUIT
LTC1148
VN2222LL
(ACTIVE WHEN V
= V
IN
GATE
OFF WHEN V
= GROUND)
4
GATE
C
T
R1
LTC1148 • F07
V
= V
OUT
OFFSET
)
)
R1 + R3
Figure 7. Output Crowbar Interface
If VOFFSET > 25mV, the minimum threshold will be can-
celled and Burst Modeoperation is prevented from occur- Troubleshooting Hints
ring. SinceVOFFSET isconstant, themaximumloadcurrent
Since efficiency is critical to LTC1148 series applications,
it is very important to verify that the circuit is functioning
correctly in both continuous and Burst Mode operation.
The waveform to monitor is the voltage on the timing
capacitor Pin 4.
is also decreased by the same offset. Thus, to get back to
the same IMAX, the value of the sense resistor must be
lower:
75mV
R
≈
SENSE
In continuous mode (ILOAD > IBURST) the voltage on the CT
pin should be a sawtooth with a 0.9VP-P swing. This
voltage should never dip below 2V as shown in Figure 8a.
I
MAX
To prevent noise spikes from erroneously tripping the
current comparator, a 1000pF capacitor is needed across
Pins 7 and 8.
When load currents are low (ILOAD < IBURST) Burst Mode
operation should occur with the CT pin waveform periodi-
cally falling to ground as shown in Figure 8b.
Output Crowbar
An added feature to using an N-channel MOSFET as the
synchronous switch is the ability to crowbar the output
with the same MOSFET. Pulling the timing capacitor Pin
4 above 1.5V when the output voltage is greater than the
desired regulated value will turn “on” the N-channel
MOSFET.
3.3V
0V
(a) CONTINUOUS MODE OPERATION
3.3V
A fault condition which causes the output voltage to go
above a maximum allowable value can be detected by
external circuitry. Turning on the N-channel MOSFET
when this fault is detected will cause large currents to flow
and blow the system fuse.
0V
(b) Burst Mode OPERATION
LTC1148 • F08
Figure 8. CT Waveforms
If Pin 4 is observed falling to ground at high output
currents,itindicatespoordecouplingorimproperground-
ing. Refer to the Board Layout Checklist.
The N-channel MOSFET needs to be sized so it will safely
handle this overcurrent condition. The typical delay from
pulling the CT pin high and the N drive Pin 14 going high
is 250ns. Note: Under shutdown conditions, the N-chan-
nel is held OFF and pulling the CT pin high will not cause
the N-channel MOSFET to crowbar the output.
A simple N-channel FET can be used as an interface
between the overvoltage detect circuitry and the LTC1148
as shown in Figure 7.
14
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LTC1148-3.3/LTC1148-5
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3. Are the SENSE– and SENSE+ leads routed together
withminimumPCtracespacing?The1000pFcapacitor
between Pins 7 and 8 should be as close as possible to
the LTC1148.
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1148 series. These items are also illustrated graphi-
cally in the layout diagram of Figure 9. Check the following
in your layout:
4. Does the (+) plate of CIN connect to the source of the
P-channelMOSFETascloselyaspossible?Thiscapaci-
tor provides the AC current to the P-channel MOSFET.
1. Are the signal and power grounds segregated? The
LTC1148 signal ground Pin 11 must return to the (–)
5. Is the 1µF VIN decoupling capacitor connected closely
betweenPin3andpowergroundPin12?Thiscapacitor
carries the MOSFET driver peak currents.
plate of C . The power ground returns to the
OUT
source of the N-channel MOSFET, anode of the
Schottky diode, and (–) plate of C , which should
IN
6. IstheShutdownPin10activelypulledtogroundduring
normal operation? The Shutdown pin is high imped-
ance and must not be allowed to float.
have as short lead lengths as possible.
2. Does the LTC1148 SENSE– Pin 7 connect to a point
close to RSENSE and the (+) plate of COUT? In adjust-
able applications, the resistive divider R1, R2 must be
connected between the (+) plate of COUT and signal
ground.
+
BOLD LINES INDICATE HIGH CURRENT PATHS
C
IN
V
IN
P-CHANNEL
D1
N-CHANNEL
–
1
2
3
4
5
6
7
14
N-DRIVE
P-DRIVE
NC
NC 13
1µF
LTC1148
+
12
PGND
V
C
IN
L
11
10
9
SGND
SHDN
–
T
R1
R2
SHUTDOWN
INTV
CC
V
OUT
NC (V )
FB
I
TH
C
OUT
+
C
T
10nF
3300pF
1k
8
+
–
SENSE
1000pF
SENSE
R
SENSE
+
OUTPUT DIVIDER REQUIRED WITH
ADJUSTABLE VERSION ONLY
LTC1148 • F09
Figure 9. LTC1148 Layout Diagram (See Board Layout Checklist)
15
LTC1148
LTC1148-3.3/LTC1148-5
U
TYPICAL APPLICATIO S
V
V
IN
IN
4V TO 18V
5.2V TO 18V
+
+
C
C
IN
IN
1/2 Si4532
100µF
1/2 Si4532
100µF
D1
D1
25V
25V
MBRS140T3
MBRS140T3
1/2 Si4532
1/2 Si4532
1
2
3
4
5
6
7
14
13
12
11
10
9
1
2
3
4
5
6
7
14
13
12
11
10
9
P-DRIVE
NC
N-DRIVE
NC
P-DRIVE
NC
N-DRIVE
NC
1µF
1µF
*L
*L
+
+
50µH
100µH
LTC1148HV-5
LTC1148HV-3.3
V
C
PGND
V
IN
C
T
PGND
IN
T
SGND
SGND
C
C
T
T
390pF
300pF
INTV
SHUTDOWN
NC
SHUTDOWN
INTV
SHUTDOWN
NC
SHUTDOWN
CC
CC
C
C
OUT
OUT
I
TH
I
TH
220µF
220µF
10V
C
C
C
C
+
+
10V
OS-CON
8
8
3300pF
–
+
3300pF
–
+
AVX
SENSE
SENSE
SENSE
SENSE
R
R
C
1k
C
1k
R
**
R
**
SENSE
0.1Ω
SENSE
1000pF
1000pF
0.1Ω
V
V
OUT
3.3V/1A
OUT
5V/1A
*COILTRONICS CTX50-4 Kool Mµ CORE
LTC1148 • F11
*COILTRONICS CTX100-4 Kool Mµ CORE
LTC1148 • F10
**IRC LR2010-01-R100-G
**KRL SP-1/2-A1-0R100
Figure 10. 5V/1A High Efficiency Regulator
with Extended Input Voltage Range
Figure 11. High Efficiency 5V to 3.3V/1A Converter
with Extended Input Voltage Range
V
IN
8V TO 14V
+
C
IN
IRF7204
330µF
D1
20V
MBRS140T3
IRF7201
1
14
13
12
11
10
9
P-DRIVE
NC
N-DRIVE
1µF
2
3
4
5
6
7
*L
+
NC
PGND
SGND
50µH
LTC1148
V
C
IN
T
R1
10k
1%
INTV
SHUTDOWN
SHUTDOWN
100pF
CC
C
C
T
OUT
10nF
390pF
220µF
10V
I
TH
V
FB
+
C
R2
30k
1%
C
+
8
×2
OS-CON
3300pF
–
SENSE
SENSE
R
C
R
**
SENSE
220Ω
0.01µF
0.033Ω
V
OUT
5V/3A
LTC1148 • F12
R2
*COILTRONICS CTX50-2-MP
**KRL SL-1-C1-0R033J
V
=
1 +
1.25V
OUT
(
)
R1
VALUES SHOWN FOR V
= 5V
OUT
Figure 12. High Efficiency Adjustable 3A Regulator
16
LTC1148
LTC1148-3.3/LTC1148-5
U
TYPICAL APPLICATIO S
V
IN
3.5V TO 14V
+
C
IN
MMSF3P02HD
100µF
D1
20V
MBRS140T3
MMSF5N02HD
1
2
3
4
5
6
7
14
13
P-DRIVE
NC
N-DRIVE
NC
1µF
*L
+
25µH
LTC1148L-3.3
12
11
10
9
V
IN
C
T
PGND
SGND
C
T
270pF
INTV
SHUTDOWN
NC
SHUTDOWN
CC
C
OUT
220µF
10V
I
TH
C
C
+
8
×2
3300pF
–
+
SENSE
SENSE
AVX
R
C
1k
R
**
SENSE
0.05Ω
1000pF
V
OUT
3.3V/2A
*COILTRONICS CTX25-5 Kool Mµ CORE
LTC1148 • F13
**IRC LR2512-01-R050-G
Figure 13. 5V Input Voltage, 3.3V/2A Low Dropout, High Efficiency Regulator
V
IN
4V TO 9V
V
: ACTIVE
IN
0V: SHUTDOWN
TP0610L
+
C
IN
220µF
Si4431DY
D1
20V
MBRS140T3
Si4412DY
1
2
3
4
5
6
7
14
13
12
11
10
9
P-DRIVE
NC
N-DRIVE
1µF
*L
50µH
+
NC
PGND
LTC1148
V
IN
C
T
V
OUT
–5V/1.4A
SGND
1M
R1
25k
1%
200pF
INTV
SHUTDOWN
CC
C
C
T
OUT
220µF
10V
10nF
560pF
I
TH
V
FB
+
C
C
+
8
×2
6800pF
–
R2
75k
1%
SENSE
SENSE
OS-CON
R
C
1k
R
**
SENSE
0.05Ω
1000pF
LTC1148 • F14
*COILTRONICS CTX50-2-MP
**KRL SL-1-C1-0R050J
Figure 14. 4V to 9V Input Voltage to –5V/1A Regulator
17
LTC1148
LTC1148-3.3/LTC1148-5
U
TYPICAL APPLICATIO S
V
IN
5V
C
IN
+
100µF
20V
Si9803DY
D1
MBRS140T3
×2
Si9804DY
1
2
3
4
5
6
7
14
13
12
11
10
9
P-DRIVE
NC
N-DRIVE
NC
0.1µF
*L
10µH
LTC1148-3.3
V
IN
C
T
PGND
SGND
C
T
270pF
NPO
INTV
SHUTDOWN
NC
SHUTDOWN
CC
C
OUT
220µF
10V
I
TH
C
C
+
8
AVX
×2
3300pF
–
+
SENSE
SENSE
R
C
R
**
SENSE
0.02Ω
470Ω
1000pF
V
OUT
3.3V/4.5A
*COILTRONICS CTX10-5P
**KRL SP-1-C1-0R020
LTC1148 • F15
Figure 15. High Efficiency 5V to 3.3V/4.5A Converter
V
IN
4V TO 14V
+
C
IN
100µF
Si4435DY
20V
1
2
3
4
5
6
7
14
13
12
11
10
9
P-DRIVE
NC
N-DRIVE
NC
1µF
220µF*
+
L2
50µH
10V
+
OS-CON
LTC1148
L1
V
IN
C
T
PGND
50µH
V
OUT
5V/1A
SGND
C
T
D1
R2
75k
1%
390pF
MBRS140T3
INTV
SHUTDOWN
SHUTDOWN
Si4412DY
CC
1N4148
I
TH
V
V
FB
OUT
C
OUT
+
C
C
220µF
10V
8
3300pF
–
+
SENSE
SENSE
OS-CON
R
R1
25k
1%
C
1k
R
**
SENSE
0.082Ω
0.1µF
100pF
*LOW ESR REQUIRED
**KRL NP-1A-C1-0R082J
LTC1148 • F16
Figure 16. 4V to 14V Input Voltage to 5V/1A Regulator with Current Foldback
18
LTC1148
LTC1148-3.3/LTC1148-5
U
TYPICAL APPLICATIO S
V
IN
5.2V TO 14V
+
C
IN
100µF
NDS9435A
D1
20V
MBRS140T3
NDS9410A
1
2
3
4
5
6
7
14
13
12
11
10
9
P-DRIVE
NC
N-DRIVE
NC
1µF
*L
+
50µH
VN2222LL
0V: V
LTC1148
= 3.3V
= 5V
V
IN
C
T
PGND
OUT
OUT
5V: V
SGND
R1A
33k
1%
R1B
43k
1%
INTV
SHUTDOWN
SHUTDOWN
100pF
CC
C
T
390pF
C
OUT
10nF
220µF
10V
I
TH
V
FB
+
C
R2
56k
1%
C
+
8
×2
3300pF
–
SENSE
SENSE
OS-CON
R
C
1k
R
**
SENSE
1000pF
0.05Ω
V
OUT
3.3V/2A
OR 5V/2A
*COILTRONICS CTX50-2-MP
**KRL SL-1-C1-0R050R
LTC1148 • F17
Figure 17. Logic Selectable 5V/1A or 3.3V/1A High Efficiency Regulator
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
N Package
14-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
0.130 ± 0.005
(3.302 ± 0.127)
(1.143 – 1.651)
14
13
12
11
10
9
8
7
0.020
(0.508)
MIN
0.255 ± 0.015*
(6.477 ± 0.381)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.035
1
2
3
5
6
4
0.325
0.005
(0.125)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
–0.015
0.125
(3.175)
MIN
0.018 ± 0.003
N14 1197
+0.889
8.255
(0.457 ± 0.076)
(
)
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S Package
14-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.337 – 0.344*
(8.560 – 8.738)
0.010 – 0.020
(0.254 – 0.508)
14
13
12
11
10
9
8
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0° – 8° TYP
0.228 – 0.244
(5.791 – 6.197)
0.150 – 0.157**
(3.810 – 3.988)
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
0.016 – 0.050
0.406 – 1.270
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
S14 0695
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
4
5
6
7
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC1148
LTC1148-3.3/LTC1148-5
U
TYPICAL APPLICATION
V
IN
10V TO 18V
1N4148
C
IN
+
220Ω
2700µF
35V
100
90
80
70
60
2N3906
×2
V = 10V
IN
20k
220Ω
470nF
D1
2N2222
V
= 14V
IN
MUR110
N-CH
IRFZ44
1N5818
VN2222LL
1
2
3
4
5
6
7
14
N-CH
IRFZ44
P-DRIVE
NC
N-DRIVE
NC
1µF
13
12
11
10
9
*L
33µH
+
0.1
1
10
LTC1148HV-5
LOAD CURRENT (A)
V
IN
C
T
PGND
SGND
LTC1148 • F19
Figure 19. All N-Channel 5V/8A Efficiency
C
T
820pF
INTV
SHUTDOWN
NC
SHUTDOWN
CC
C
OUT
I
TH
For additional high efficiency application
circuits, seeApplicationNotes54, 58and66
2200µF
16V
×3
C
C
+
100Ω
8
3300pF
–
+
SENSE
SENSE
R
C
1000pF
R
**
SENSE
0.01Ω
510Ω
100Ω
V
OUT
5V/8A
LTC1148 • F18
22k
*COILTRONICS CTX33-10-KM
**DALE LVR-3-0.01
Figure 18. All N-Channel 5V/8A High Efficiency Regulator
(Burst Mode Operation Suppressed)
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1142
Dual High Efficiency Synchronous Step-Down Switching Regulator
Dual High Efficiency Step-Down Switching Regulator Controller
High Efficiency Step-Down Switching Regulator Controller
High Efficiency Synchronous Step-Down Switching Regulator
High Efficiency Synchronous Step-Down Switching Regulator
High Efficiency Step-Down and Inverting DC/DC Converter
1.2A, High Efficiency Step-Down DC/DC Converter
Dual LTC1148
LTC1143
Nonsynchronous Dual Output
Nonsynchronous Equivalent to LTC1148, 8-Pin
LTC1147
LTC1149
V
V
< 48V, Standard Threshold MOSFETs
< 40V, Logic Level MOSFETs
IN
IN
LTC1159
LTC1174
Nonsynchronous 8-Pin Internal Switch
Nonsynchronous Internal Switch
LTC1265
LTC1435A
LTC1538-AUX
High Efficiency Low Noise Synchronous Step-Down Switching Regulator
Synchronous N-Channel, Constant Frequency
Auxiliary Linear Regulator, 5V Standby in Shutdown
Dual High Efficiency, Low Noise, Synchronous Step-Down
Switching Regulator
114835fc LT/GP 1098 2K REV C • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1993
20 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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