LTC1159-3.3_15_技术文档

LTC1159

LTC1159-3.3/LTC1159-5

High Efficiency Synchronous

Step-Down Switching Regulators

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FEATURES

DESCRIPTIO

TheLTC^®1159seriesisafamilyofsynchronousstep-down

switching regulator controllers featuring automatic Burst

Mode^TMoperation to maintain high efficiencies at low

output currents. These devices drive external complemen-

tarypowerMOSFETsatswitchingfrequenciesupto250kHz

using a constant off-time current-mode architecture.

■

Operation from 4V to 40V Input Voltage

■

Ultrahigh Efficiency: Up to 95%

■

20µA Supply Current in Shutdown

■

High Efficiency Maintained Over Wide Current Range

Current Mode Operation for Excellent Line and Load

Transient Response

■

Very Low Dropout Operation: 100% Duty Cycle

Short-Circuit Protection

Synchronous FET Switching for High Efficiency

Adaptive Non-Overlap Gate Drives

Available in SSOP and SO Packages

A separate pin and on-board switch allow the MOSFET

driver power to be derived from the regulated output

voltageprovidingsignificantefficiencyimprovementwhen

operating at high input voltages. The constant off-time

current-mode architecture maintains constant ripple cur-

rent in the inductor and provides excellent line and load

transient response. The output current level is user pro-

grammable via an external current sense resistor.

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APPLICATIO S

■

Step-Down and Inverting Regulators

The LTC1159 automatically switches to power saving

Burst Mode operation when load current drops below

approximately 15% of maximum current. Standby current

is only 300µA while still regulating the output and shut-

down current is a low 20µA.

■

Notebook and Palmtop Computers

■

Portable Instruments

■

Battery-Operated Digital Devices

■

Industrial Power Distribution

■

Avionics Systems

Telecom Power Supplies

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode is a trademark of Linear Technology Corporation.

■

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TYPICAL APPLICATIO

V

IN

+

C

IN

1N4148

100µF

LTC1159-5 Efficiency

V

IN

100V

CAP

P-GATE

Si9435DY

100

90

80

70

60

0.15µF

FIGURE 1 CIRCUIT

V

0.1µF

V

= 10V

+

CC

IN

P-DRIVE

3.3µF

V

CC

EXTV

CC

D1

L*

33µH

R

SENSE

MBRS140T3

V

= 20V

0.05Ω

IN

LTC1159-5

1

2

4

V

OUT

5V/2A

3

+

SHDN1

SHDN2

SENSE

0V = NORMAL

>2V = SHUTDOWN

0.01µF

–

SENSE

I

TH

+

C

OUT

3300pF

1k

C

N-GATE

P-GND

Si9410DY

T

220µF

C

T

S-GND

300pF

*COILTRONICS CTX33-4-MP

0.02

0.2

LOAD CURRENT (A)

2

LTC1159 • F01

LTC1159 • TA01

Figure 1. High Efficiency Step-Down Regulator

1

LTC1159

LTC1159-3.3/LTC1159-5

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(Note 1)

ABSOLUTE AXI U RATI GS

Input Supply Voltage (Pin 2) ..................... –15V to 60V

Operating Temperature Range

V

_CCOutput Current (Pin 3) .................................. 50mA

LTC1159C .............................................. 0°C to 70°C

LTC1159I........................................... –40°C to 85°C

Extended Commercial

Continuous Pin Currents (Any Pin)...................... 50mA

Sense Voltages ......................................... –0.3V to 13V

Shutdown Voltages................................................... 7V

EXTV_CCInput Voltage ............................................. 15V

Junction Temperature (Note 2)............................ 125°C

Temperature Range ............................... –40°C to 85°C

Storage Temperature Range ................ – 65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

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PACKAGE RDER I FOR ATIO

ORDER PART

TOP VIEW

NUMBER

P-GATE

1

2

3

4

5

6

7

8

9

20 CAP

1

2

3

4

5

6

7

8

CAP

16

15

14

13

12

11

10

9

P-GATE

V

IN

19 SHDN2

SHDN2

V

IN

V

18 EXTV

CC

EXTV

CC

LTC1159CG

LTC1159CG-3.3

LTC1159CG-5

LTC1159CN

CC

V

CC

P-DRIVE

17 PGND

16 N-GATE

15 PGND

14 SGND

13 SHDN1

N-GATE

PGND

P-DRIVE

LTC1159CN-3.3

LTC1159CN-5

LTC1159CS

V

CC

V

SGND

CC

C

T

V

FB

(SHDN1)*

CC

I

TH

LTC1159CS-3.3

LTC1159CS-5

LTC1159IS

LTC1159IS-3.3

LTC1159IS-5

+

–

C

T

SENSE

I

12

V

FB

TH

–

N PACKAGE

S PACKAGE

16-LEAD PLASTIC SO

+

SENSE 10

11 SENSE

16-LEAD PDIP

*FIXED OUTPUT VERSIONS

G PACKAGE

20-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 80°C/ W (N)

T

_JMAX= 125°C, θ_JA= 110°C/ W (S)

T_JMAX= 125°C, θ_JA= 135°C/ W

Consult LTC Marketing for parts specified with wider operating temperature ranges.

The ● denotes specifications which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 12V, V_SHDN1= 0V (Note 3), unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

1.25

0.2

MAX

UNITS

V

FB

Feedback Voltage (LTC1159 Only)

Feedback Current (LTC1159 Only)

●

1.21

1.29

I

µA

FB

V

OUT

Regulated Output Voltage

LTC1159-3.3

V

LOAD

= 9V

IN

I

= 700mA

●

3.23

4.90

3.33

5.05

3.43

5.20

V

LTC1159-5

∆V

Output Voltage Line Regulation

V

IN

= 9V to 40V

–40

0

40

mV

OUT

Output Voltage Load Regulation

LTC1159-3.3

5mA < I

< 2A

●

40

60

65

100

mV

LOAD

LTC1159-5

Burst Mode Output Ripple

I

= 0A

50

mV

P-P

LOAD

I

V

Pin Current (Note 4)

Normal Mode

IN

V

= 12V, EXTV = 5V

200

300

µA

IN

CC

= 40V, EXTV = 5V

CC

Shutdown

V

IN

V

IN

= 12V, V

= 40V, V

= 2V

15

25

µA

SHDN2

EXTV Pin Current (Note 4)

EXTV = 5V, Sleep Mode

250

µA

EXTVCC

CC

2

LTC1159

LTC1159-3.3/LTC1159-5

The ● denotes specifications which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 12V, V_SHDN1= 0V (Note 3), unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

4.5

MAX

4.75

400

UNITS

V

Internal Regulator Voltage

V

= 12V to 40V, EXTV = 0V, I = 10mA

●

4.25

CC

IN

CC

V

– V

V

Dropout Voltage

= 4V, EXTV = Open, I = 10mA

300

250

mV

IN

CC

V

– V

EXTV Switch Drop

V

= 12V, EXTV = 5V, I

= 10mA

350

EXT

CC

IN

CC

SWITCH

– V

P-Gate to Source Voltage (Off)

V

= 12V

= 40V

–0.2

0

V

P-GATE

IN

+

–

V

–

Current Sense Threshold Voltage

LTC1159

SENSE

–

V

= 5V, V = 1.32V (Forced)

25

mV

SENSE

FB

= 5V, V = 1.15V (Forced)

●

130

150

170

FB

–

LTC1159-3.3

LTC1159-5

V

= 3.4V (Forced)

= 3.1V (Forced)

25

150

mV

SENSE

–

V

= 5.2V (Forced)

= 4.7V (Forced)

25

150

mV

SENSE

V

SHDN1 Threshold

SNDN1

LTC1159CG, LTC1159-3.3, LTC1159-5

0.5

0.8

1.4

12

2

V

SHDN2 Threshold

SHDN2

CT

I

Shutdown 2 Input Current

V

= 5V

20

µA

SHDN2

C Pin Discharge Current

T

V

in Regulation

= 0V

50

4

70

2

90

10

µA

OUT

t

Off-Time (Note 5)

C = 390pF, I

= 700mA, V = 10V

5

6

µs

OFF

T

LOAD

IN

t , t

r

Driver Output Transition Times

C = 3000pF (Pins P-Drive and N-Gate), V = 6V

100

200

ns

f

L

IN

–40°C ≤ T_A≤ 85°C (Note 6)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Feedback Voltage (LTC1159 Only)

1.2

1.25

1.3

V

FB

Regulated Output Voltage

LTC1159-3.3

V

LOAD

= 9V

IN

OUT

I

= 700mA

3.17

4.85

3.30

5.05

3.43

5.25

V

LTC1159-5

I

V

Pin Current (Note 4)

Normal

IN

V

= 12V, EXTV = 5V

200

300

µA

IN

CC

= 40V, EXTV = 5V

CC

Shutdown

V

= 12V, V

= 40V, V

= 2V

15

25

µA

IN

SHDN2

I

EXTV Pin Current (Note 4)

EXTV = 5V, Sleep Mode

250

4.5

µA

EXTVCC

CC

V

Internal Regulator Voltage

V

= 12V to 40V, EXTV = 0V, I = 10mA

V

CC

IN

CC

+

–

V

–

Current Sense Threshold Voltage

Low Threshold (Forced)

High Threshold (Forced)

25

mV

SENSE

125

0.8

3.5

150

175

2

V

SHDN2 Threshold

Off-Time (Note 5)

1.4

5

V

SHDN2

OFF

t

C = 390pF, I

= 700mA, V = 10V

6.5

µs

T

LOAD

IN

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 3: On LTC1159 versions which have a SHDN1 pin, it must be at

ground potential for testing.

Note 2: T is calculated from the ambient temperature T and power

Note 4: The LTC1159 V and EXTV current measurements exclude

J

A

IN

CC

dissipation P according to the following formulas:

MOSFET driver currents. When V power is derived from the output via

D

CC

LTC1159CG, LTC1159CG-3.3, LTC1159CG-5: T = T + (P • 135°C/W)

EXTV , the input current increases by (I

• Duty Cycle)/(Efficiency).

J

A

D

CC

GATECHG

LTC1159CN, LTC1159CN-3.3, LTC1159CN-5: T = T + (P • 80°C/W)

See Typical Performance Characteristics and Applications Information.

J

A

D

LTC1159CS, LTC1159CS-3.3, LTC1159CS-5: T = T + (P • 110°C/W)

J

A

D

Note 5: In applications where R

is placed at ground potential, the off-

SENSE

time increases approximately 40%.

3

LTC1159

LTC1159-3.3/LTC1159-5

ELECTRICAL CHARACTERISTICS

Note 6: The LTC1159C, LTC1159C-3.3, and LTC1159C-5 are not tested

and not quality assurance sampled at –40°C and 85°C. These

specifications are guaranteed by design and/or correlation. The LTC1159I,

LTC1159I-3.3 and LTC1159I-5 are guaranteed and tested over the –40°C

to 85°C operating temperature range.

Note 7: The logic-level power MOSFETs shown in Figure 1 are rated for

= 30V. For operation at V > 30V, use standard threshold

V

DS(MAX)

IN

MOSFETs with EXTV powered from a 12V supply. See Applications

CC

Information.

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TYPICAL PERFOR A CE CHARACTERISTICS

Line Regulation

Load Regulation

Efficiency vs Input Voltage

20

0

100

60

40

FIGURE 1 CIRCUIT

= 24V

I

= 1A

I

= 1A

LOAD

V

IN

95

20

–20

–40

NOTE 6

0

NOTE 6

90

–20

–40

–60

–80

85

80

–100

25 30

10 15 20

INPUT VOLTAGE (V)

0

0.5

1.0

1.5

2.0

2.5

0

5

10 15 20 25 30 35 40

INPUT VOLTAGE (V)

0

5

35 40

LOAD CURRENT (A)

LTC1159 • TPC01

LT1159 • TPC02

LTC1159 • TPC03

Operating Frequency

EXTV_CCPin Current

V_INPin Current

vs (V_IN– V_OUT

)

500

10

2.0

1.5

1.0

0.5

0

FIGURE 1 CIRCUIT

V

= 5V

OUT

T = 0°C

400

300

8

6

I

= 1A

LOAD

T = 25°C

T = 70°C

NORMAL

NOTE 6

200

100

0

4

2

0

I

= 100mA

LOAD

I

V

= 2V

= 0

SHDN2

LOAD

20

0

5

10 15

25 30 35 40

20

0

5

10 15

25 30 35 40

0

5

10

15

20

25

INPUT VOLTAGE (V)

(V – V ) VOLTAGE (V)

IN

OUT

LTC1159 • TPC05

LTC1159 • TPC04

LTC1159 • TPC06

4

LTC1159

LTC1159-3.3/LTC1159-5

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TYPICAL PERFOR A CE CHARACTERISTICS

EXTV_CCSwitch Drop

Current Sense Threshold Voltage

Off-Time vs V_OUT

600

500

80

70

60

50

40

30

20

10

0

160

140

120

100

80

MAXIMUM

THRESHOLD

400

300

60

200

100

0

40

MINIMUM

THRESHOLD

LTC1159-5

4

20

LTC1159-3.3

0

5

10

15

20

3

60

TEMPERATURE (°C)

80

0

1

2

5

0

20

40

100

SWITCH CURRENT (mA)

OUTPUT VOLTAGE (V)

LTC1159 • TPC07

LTC1159 • TPC08

LTC1159 • TPC09

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PI FU CTIO S

V_IN: Main Supply Input Pin.

SENSE⁺: The (+) Input for the Current Comparator. A built-

inoffsetbetweentheSENSE⁺andSENSE^–pins,inconjunc-

tion with R_SENSE, sets the current trip threshold.

SGND: Small-Signal Ground. Must be routed separately

from other grounds to the (–) terminal of C_OUT

.

N-Gate: High Current Drive for the Bottom N-Channel

MOSFET. The N-Gate pin swings from ground to V_CC.

PGND: Driver Power Grounds. Connect to source of N-

channel MOSFET and the (–) terminal of C_IN.

P-Gate: Level-Shifted Gate Drive Signal for the Top

P-Channel MOSFET. The voltage swing at the P-gate pin is

from V_INto V_IN– V_CC.

V_CC: Outputs of internal 4.5V linear regulator, EXTV_CC

switch, and supply inputs for driver and control circuits.

Thedriverandcontrolcircuitsarepoweredfromthehigher

of the 4.5V regulator or EXTV_CCvoltage. Must be closely

decoupled to power ground.

P-Drive: High Current Gate Drive for the Top P-Channel

MOSFET. The P-drive pin(s) swing(s) from V_CCto ground.

C_T: External capacitor C_Tfrom this pin to ground sets the

operating frequency. (The frequency is also dependent on

the ratio V_OUT/V_IN.)

CAP: Charge Compensation Pin. A capacitor to V_CCpro-

vides charge required by the P-gate level-shift capacitor

during supply transitions. The charge compensation ca-

pacitor must be larger than the gate drive capacitor.

I_TH: Gain Amplifier Decoupling Point. The current com-

parator threshold increases with the I_THpin voltage.

SHDN1:Thispinshutsdownthecontrolcircuitryonly(V_CC

is not affected). Taking SHDN1 pin high turns off the

control circuitry and holds both MOSFETs off. This pin

must be at ground potential for normal operation.

V_FB: For the LTC1159 adjustable version, the V_FBpin

receives the feedback voltage from an external resistive

divider used to set the output voltage.

SENSE^–: Connects to internal resistive divider which sets

theoutputvoltageinfixedoutputversions.TheSENSE^–pin

is also the (–) input of the current comparator.

SHDN2: Master Shutdown Pin. Taking SHDN2 high shuts

down V_CCand all control circuitry.

5

LTC1159

LTC1159-3.3/LTC1159-5

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FU CTIO AL DIAGRA

Internal divider broken at V_FBfor adjustable versions.

V

IN

V

P-GATE

CC

CAP

LOW DROPOUT

550k

SHDN2

4.5V REGULATOR

P-DRIVE

550k

V

CC

LOW DROP SWITCH

EXTV

CC

N-GATE

+

–

SENSE

PGND

–

V

+

R

–

+

Q

SLEEP

S

C

25mV TO 150mV

–

+

V

OS

V

TH1

T

13k

G

+

100k

+

S

V

LTC1159 • FD

–

TH2

FB

1.25V

REFERENCE

OFF-TIME

CONTROL

–

SENSE

SHDN1

SGND

I

TH

C

T

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OPERATIO

(Refer to Functional Diagram)

The LTC1159 uses a current mode, constant off-time

architecture to synchronously switch an external pair of

complementary power MOSFETs. Operating frequency is

set by an external capacitor at the C_Tpin.

level-shiftingtheP-drivesignalviaaninternal550kresistor

and external capacitor.

During the switch “ON” cycle in continuous mode, current

comparator C monitors the voltage between the SENSE⁺

and SENSE^–pins connected across an external shunt in

serieswiththeinductor.Whenthevoltageacrosstheshunt

reaches its threshold value, the P-gate output is switched

to V_IN, turning off the P-channel MOSFET. The timing

capacitor C_Tis now allowed to discharge at a rate deter-

mined by the off-time controller. The discharge current is

made proportional to the output voltage to model the

inductor current, which decays at a rate which is also

proportional to the output voltage. While the timing

capacitor is discharging, the N-gate output is high, turning

on the N-channel MOSFET.

The output voltage is sensed either by an internal voltage

divider connected to the SENSE^–pin (LTC1159-3.3 and

LTC1159-5) or an external divider returned to the V_FBpin

(LTC1159). A voltage comparator V, and a gain block G,

compare the divided output voltage with a reference volt-

age of 1.25V. To optimize efficiency, the LTC1159 auto-

matically switches between two modes of operation, burst

and continuous.

A low dropout 4.5V regulator provides the operating volt-

ageV_CCfortheMOSFETdriversandcontrolcircuitryduring

start-up. During normal operation, the LTC1159 family

powers the drivers and control from the output via the

EXTV_CCpin to improve efficiency. The N-GATE pin is

referenced to ground and drives the N-channel MOSFET

gate directly. The P-channel gate drive must be referenced

to the main supply input V_IN, which is accomplished by

WhenthevoltageonC_ThasdischargedpastV_TH1,compara-

torTtrips,settingtheflip-flop.ThiscausestheN-gateoutput

to go low (turning off the N-channel MOSFET) and the P-

gate output to also go low (turning the P-channel MOSFET

back on). The cycle then repeats. As the load current

6

LTC1159

LTC1159-3.3/LTC1159-5

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OPERATIO

increases,theoutputvoltagedecreasesslightly.Thiscauses

the output of the gain stage to increase the current com-

parator threshold, thus tracking the load current.

(Refer to Functional Diagram)

is turned off, dropping the supply current from several

milliamps (with the MOSFETs switching) to 300µA. When

the output capacitor has discharged by the amount of

hysteresis in comparator V, the P-channel MOSFET is

again turned on and this process repeats. To avoid the

operation of the current loop interfering with Burst Mode

operation, abuilt-inoffsetisincorporatedinthegainstage.

The sequence of events for Burst Mode operation is very

similar to continuous operation with the cycle interrupted

bythevoltagecomparator. Whentheoutputvoltageisator

above the desired regulated value, the P-channel MOSFET

is held off by comparator V and the timing capacitor con-

tinues to discharge below V_TH1. When the timing capacitor

discharges past V_TH2, voltage comparator S trips, causing

theinternalSLEEPlinetogolowandtheN-channelMOSFET

to turn off.

To prevent both the external MOSFETs from being turned

on at the same time, feedback is incorporated to sense the

stateofthedriveroutputpins. BeforetheN-gateoutputcan

gohigh, theP-driveoutputmustalsobehigh. Likewise, the

P-drive output is prevented from going low when the

N-gate output is high.

The circuit now enters sleep mode with both power

MOSFETs turned off. In sleep mode, much of the circuitry

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APPLICATIO S I FOR ATIO

The LTC1159 Compared to the LTC1148/LTC1149

Families

of 0.15V/R_SENSE. The current comparator threshold sets

thepeakoftheinductorripplecurrent, yieldingamaximum

output current I_MAXequal to the peak value less half the

peak-to-peak ripple current. For proper Burst Mode opera-

tion,I_RIPPLE(P-P)mustbelessthanorequaltotheminimum

current comparator threshold.

The LTC1159 family is closest in operation to the LTC1149

and shares much of the applications information. In addi-

tion to reduced quiescent and shutdown currents, the

LTC1159 adds an internal switch which allows the driver

and control sections to be powered from an external

source for higher efficiency. This change affects Power

MOSFET Selection, EXTV_CCPin Connection, Important

Information About LTC1159 Adjustable Applications, and

Efficiency Considerations found in this section.

Since efficiency generally increases with ripple current,

the maximum allowable ripple current is assumed, i.e.,

I_RIPPLE(P-P)= 0.025V/R_SENSE(see C_Tand L Selection for

Operating Frequency). Solving for R_SENSEand allowing

a margin for variations in the LTC1159 and external

component values yields:

The basic LTC1159 application circuit shown in Figure 1

is limited to a maximum input voltage of 30V due to

MOSFET breakdown. If the application does not require

greater than 18V operation, then the LTC1148 or

LTC1148HV should be used. For higher input voltages

wherequiescentandshutdowncurrentarenotcritical,the

LTC1149 may be a better choice since it is set up to drive

standard threshold MOSFETs.

100

MAX

R

=

mΩ

SENSE

I

A graph for selecting R_SENSEversus maximum output

current is given in Figure 2. The LTC1159 series works well

with values of R_SENSEfrom 0.02Ω to 0.2Ω.

The load current below which Burst Mode operation com-

mences, I_BURST, andthepeakshort-circuitcurrent, I_SC(PK)

,

R_SENSESelection for Output Current

both track I_MAX. Once R_SENSEhas been chosen, I_BURSTand

I_SC(PK)can be predicted from the following equations:

R_SENSEischosenbasedontherequiredoutputcurrent.The

LTC1159 current comparator has a threshold range that

extends from a minimum of 0.025V/R_SENSEto a maximum

7

LTC1159

LTC1159-3.3/LTC1159-5

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APPLICATIO S I FOR ATIO

1400

0.20

0.18

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0

V

= 5V

OUT

1200

1000

800

600

400

200

0

V

= 48V

IN

V

= 24V

IN

V

IN

= 12V

200

0

50

100

150

250

0

1

2

3

4

5

FREQUENCY (kHz)

MAXIMUM OUTPUT CURRENT (A)

LTC1159 • F03

LTC1159 • F02

Figure 2. R_SENSEvs Maximum Output Current

Figure 3. Timing Capacitor Selection

where t_OFF= 1.3 • 10⁴• C_T

Once the frequency has been set by C , the inductor L

15mV

SENSE

I

≈

BURST

R

T

mustbechosentoprovidenomorethan0.025V/R

SENSE

150mV

of peak-to-peak inductor ripple current. This results in a

minimum required inductor value of:

I

=

SC(PK)

R

SENSE

L_MIN= 5.1 • 10⁵• R_SENSE• C_T• V_REG

The LTC1159 automatically extends t_OFFduring a short

circuit to allow sufficient time for the inductor current to

decay between switch cycles. The resulting ripple current

causes the average short-circuit current I_SC(AVG)to be

Astheinductorvalueisincreasedfromtheminimumvalue,

the ESR requirements for the output capacitor are eased at

the expense of efficiency. If too small an inductor is used,

the LTC1159 may not enter Burst Mode operation and

efficiency will be severely degraded at low currents.

reduced to approximately I_MAX

.

L and C_TSelection for Operating Frequency

The LTC1159 uses a constant off-time architecture with

t_OFFdetermined by an external timing capacitor C_T. The

valueofC_Tiscalculatedfromthedesiredcontinuousmode

operating frequency, f:

Inductor Core Selection

Once the minimum value for L is known, the type of

inductor must be selected. High efficiency converters

generally cannot afford the core loss found in low cost

powdered iron cores, forcing the use of more expensive

ferrite, molypermalloyorKoolMµ^®cores. Actualcoreloss

is independent of core size for a fixed inductor value, but

–5

V

7.8 • 10

f

OUT

C =

1 –

T

)

IN

A graph for selecting C_Tversus frequency including the

effects of input voltage is given in Figure 3.

it is very dependent on the inductance selected. As induc

-

tance increases, core losses go down but copper (I²R)

losses will increase.

As the operating frequency is increased the gate charge

losses will be higher, reducing efficiency (see Efficiency

Considerations). The complete expression for operating

frequency is given by:

Ferritedesignshaveverylowcoreloss,sodesigngoalscan

concentrate on copper loss and preventing saturation.

Ferrite core material saturates “hard,” which means that

inductance collapses abruptly when the peak design cur-

rent is exceeded. This results in an abrupt increase in

V

1

OFF

OUT

f =

1 –

)

t

IN

Kool Mµ is a registered trademark of Magnetics, Inc.

8

LTC1159

LTC1159-3.3/LTC1159-5

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APPLICATIO S I FOR ATIO

U

inductor ripple current and consequent output voltage

ripple which can cause Burst Mode operation to be falsely

triggeredintheLTC1159. Donotallowthecoretosaturate!

The MOSFET dissipations at maximum output current are

given by:

V

OUT

2

P-Ch P =

(I

) (1 + ∂ ) R

+

D

MAX

P

DS(ON)

Molypermalloy (from Magnetics, Inc.) is a low loss core

material for toroids, but it is more expensive than ferrite.

A reasonable compromise from the same manufacturer is

Kool Mµ. Toroids are very space efficient, especially when

you can use several layers of wire. Because they generally

lack a bobbin, mounting is more difficult. However, new

surface mount designs available from Coiltronics do not

increase the height significantly.

IN

2

k(V ) (I

) (C ) (f)

IN

MAX

RSS

V – V

IN

OUT

2

N-Ch P =

(I

) (1 + ∂ ) R

D

MAX

N

DS(ON)

V

IN

where ∂ is the temperature dependency of R_DS(ON)and k

is a constant inversely related to the gate drive current.

Both MOSFETs have I²R losses while the P-channel

equation includes an additional term for transition losses,

which are highest at high input voltages. For V_IN< 20V the

high current efficiency generally improves with larger

MOSFETs,whileforV_IN>20Vthetransitionlossesrapidly

increase to the point that the use of a higher R_DS(ON)

device with lower C_RSSactually provides higher effi-

ciency. The N-channel MOSFET losses are the greatest at

high input voltage or during a short circuit when the

N-channel duty cycle is nearly 100%.

Power MOSFET Selection

Two external power MOSFETs must be selected for use

with the LTC1159: a P-channel MOSFET for the main

switch and an N-channel MOSFET for the synchronous

switch.

The peak-to-peak drive levels are set by the V_CCvoltage on

the LTC1159. This voltage is typically 4.5V during start-up

and 5V to 7V during normal operation (see EXTV_CCPin

Connection). Consequently, logic-level threshold

MOSFETs must be used in most LTC1159 family applica-

tions. The only exception is applications in which EXTV_CC

is powered from an external supply greater than 8V, in

whichstandardthresholdMOSFETs(V_GS(TH)<4V)maybe

used. PaycloseattentiontotheBV_DSSspecificationforthe

MOSFETs as well; many of the logic-level MOSFETs are

limited to 30V.

Theterm(1+∂)isgenerallygivenforaMOSFETintheform

of a normalized R_DS(ON)vs Temperature curve, but

∂ = 0.007/°C can be used as an approximation for low

voltage MOSFETs. C_RSSis usually specified in the MOSFET

electricalcharacteristics.Theconstantk=5canbeusedfor

the LTC1159 to estimate the relative contributions of the

two terms in the P-channel dissipation equation.

Selection criteria for the power MOSFETs include the “ON”

resistance R_DS(ON), reverse transfer capacitance C_RSS

input voltage and maximum output current. When the

LTC1159 is operating in continuous mode, the duty cycle

for the P-channel MOSFET is given by:

The Schottky diode D1 shown in Figure 1 only conducts

during the dead time between the conduction of the two

power MOSFETs. D1 prevents the body diode of the

N-channel MOSFET from turning on and storing charge

during the dead time, which could cost as much as 1% in

efficiency (although there are no other harmful effects if

D1 is omitted). Therefore, D1 should be selected for a

,

V

OUT

P-Ch Duty Cycle =

IN

forward voltage of less than 0.6V when conducting I_MAX

.

V – V

IN

OUT

N-Ch Duty Cycle =

V

IN

9

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LTC1159-3.3/LTC1159-5

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APPLICATIO S I FOR ATIO

if 200µF/10V is called for in an application requiring 3mm

height,twoAVX100µF/10V(P/NTPSD107K010)couldbe

used. Consult the manufacturer for other specific recom-

mendations.

C_INand C_OUTSelection

In continuous mode, the source current of the P-channel

MOSFET is a square wave of duty cycle V_OUT/V_IN.

To prevent large voltage transients, a low ESR input

capacitor sized for the maximum RMS current must be

used. The maximum RMS capacitor current is given by:

At low supply voltages, a minimum value of C_OUTis

suggestedtopreventanabnormallowfrequencyoperating

mode (see Figure 4). When C_OUTis too small, the output

ripple at low frequencies will be large enough to trip the

voltage comparator. This causes the Burst Mode operation

to be activated when the LTC1159 would normally be in

continuous operation. The effect is most pronounced with

low values of R_SENSEand can be improved by operating at

higher frequencies with lower values of L. The output

remains in regulation at all times.

1/2

I

[V (V – V )]

MAX OUT IN

OUT

C Required I

≈

IN

RMS

V

IN

This formula has a maximum at V_IN= 2V_OUT, where

I_RMS= I_MAX/2. This simple worst-case condition is com-

monlyusedfordesignbecauseevensignificantdeviations

donotoffermuchrelief.Notethatcapacitormanufacturer’s

ripple current ratings are often based on only 2000 hours

of life. This makes it advisable to further derate the

capacitor, or to choose a capacitor rated at a higher

temperature than required. Several capacitors may be

paralleled to meet size or height requirements in the

design. An additional 0.1µF ceramic capacitor may also be

required on V_INfor high frequency decoupling.

1000

L = 50µH

SENSE

R

= 0.02Ω

800

600

L = 25µH

SENSE

R

= 0.02Ω

400

200

0

L = 50µH

SENSE

The selection of C_OUTis driven by the required effective

series resistance (ESR). The ESR of C_OUTmust be less than

twice the value of R_SENSEfor proper operation of the

LTC1159:

R

= 0.05Ω

0

1

2

3

4

5

(V – V ) VOLTAGE (V)

IN

OUT

C_OUTRequired ESR < 2R_SENSE

LTC1159 • TPC04

OptimumefficiencyisobtainedbymakingtheESRequalto

R_SENSE. Manufacturers such as Nichicon, Chemicon, and

Sprague should be considered for high performance ca-

pacitors. The OS-CON semiconductor dielectric capacitor

available from Sanyo has the lowest ESR for its size at a

somewhat higher price. Once the ESR requirement for

C_OUThas been met, the RMS current rating generally far

exceeds the I_RIPPLE(P-P)requirement.

Figure 4. Minimum Suggested C_OUT

Load Transient Response

Switching regulators take several cycles to respond to a

step in DC (resistive) load current. When a load step

occurs, V_OUTshifts by an amount equal to ∆I_LOAD• ESR,

whereESRistheeffectiveseriesresistanceofC_OUT.∆I_LOAD

also begins to charge or discharge C_OUTuntil the regulator

loop adapts to the current change and returns V_OUTto its

steady-state value. During this recovery time V_OUTcan be

monitored for overshoot or ringing which would indicate a

stability problem. The I_THexternal components shown in

the Figure 1 circuit will provide adequate compensation for

most applications.

In surface mount applications, multiple capacitors may

havetobeparalleledtomeetthecapacitance, ESRorRMS

current handling requirements of the application. Alumi-

num electrolytic and dry tantalum capacitors are both

available in surface mount configurations. In the case of

tantalum, it is critical that the capacitors are surge tested

foruseinswitchingpowersupplies. Anexcellentchoiceis

the AVX TPS series of surface mount tantalums, available

in case heights ranging from 2mm to 4mm. For example,

A second, more severe transient is caused by switching in

loads with large (>1µF) supply bypass capacitors. The

10

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APPLICATIO S I FOR ATIO

U

MOSFET driver and control power to be derived from the

output during normal operation and from the internal

regulator when the output is out of regulation (start-up,

short circuit).

discharged bypass capacitors are effectively put in parallel

with C_OUT, causing a rapid drop in V_OUT. No regulator can

deliver enough current to prevent this problem if the load

switch resistance is low and it is driven quickly. The only

solution is to limit the rise time of the switch drive so that

SignificantefficiencygainscanberealizedbypoweringV_CC

from the output, since the V_INcurrent resulting from the

driver and control currents will be scaled by a factor of

(Duty Cycle)/(Efficiency). For 5V regulators this simply

means connecting the EXTV_CCpin directly to V_OUT. How-

ever, for 3.3V and other low voltage regulators, additional

circuitry is required to derive V_CCpower from the output.

the load rise time is limited to approximately 25 • C_LOAD

.

Thus a 10µF capacitor would require a 250µs rise time,

limiting the charging current to about 200mA.

Line Transient Response

The LTC1159 has better than 60dB line rejection and is

generally impervious to large positive or negative line

voltage transients. However, one rarely occurring condi-

tion can cause the output voltage to overshoot if the proper

precautions are not observed. This condition is a negative

V_INtransition of several volts followed within 100µs by a

positive transition of greater than 0.5V/µs slew rate.

The following list summarizes the four possible connec-

tions for EXTV_CC:

1. EXTV_CCLeft Open. This will cause V_CCto be powered

only from the internal 4.5V regulator resulting in reduced

MOSFET gate drive levels and an efficiency penalty of up to

10% at high input voltages.

The reason this condition rarely occurs is because it takes

tens of amps to slew the regulator input capacitor at this

rate! The solution is to add a diode between the cap and V_IN

pins of the LTC1159 as shown in several of the typical

application circuits. If you think your system could have

this problem, add the diode. Note that in surface mount

applications it can be combined with the P-gate diode by

using a low cost common cathode dual diode.

2. EXTV_CCConnected Directly to V_OUT. This is the normal

connection for a 5V regulator and provides the highest

efficiency.

3. EXTV_CCConnected to an Output-Derived Boost Net-

work. For 3.3V and other low voltage regulators, efficiency

gains can still be realized by connecting EXTV_CCto an

output-derived voltage which has been boosted to greater

than 4.5V. This can be done either with the inductive boost

winding shown in Figure 5a or the capacitive charge pump

shown in Figure 5b. The charge pump has the advantage of

simple magnetics and generally provides the highest effi-

ciency at the expense of a slightly higher parts count.

EXTV_CCPin Connection

The LTC1159 contains an internal PNP switch connected

between the EXTV_CCand V_CCpins. The switch closes and

supplies the V_CCpower whenever the EXTV_CCpin is higher

in voltage than the 4.5V internal regulator. This allows the

V

IN

V

IN

+

BAT85

C

IN

V

IN

C

IN

V

IN

P-GATE

P-CH

+

R

L

SENSE

L

1:1

P-GATE

P-CH

1µF

V

C

OUT

•

P-DRIVE

R

1

P-DRIVE

SENSE

2

LTC1159-3.3

N-GATE

P-GND

EXTV

BAT85

V

OUT

VN2222LL

•

3

4

LTC1159-3.3

N-GATE

P-GND

EXTV

+

N-CH

+

0.22µF

C

BAT85

OUT

BAT85

CC

LTC1159 • F05b

+

CC

1µF

LTC1159 • F05a

Figure 5a. Inductive Boost Circuit for EXTV_CC

Figure 5b. Capacitive Charge Pump for EXTV_CC

11

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APPLICATIO S I FOR ATIO

4. EXTV_CCConnected to an External Supply. If an external

supply is available in the 5V to 12V range, it may be used

to power EXTV_CCproviding it is compatible with the

MOSFETgatedriverequirements. Therearenorestrictions

on the EXTV_CCvoltage relative to V_IN. EXTV_CCmay be

higher than V_INproviding EXTV_CCdoes not exceed the 15V

absolute maximum rating.

In LTC1159N and LTC1159S applications with V_OUT>

5.5V, the V_CCpin may self-power through the SENSE pins

when SHDN2 is taken high, preventing shutdown. In these

applications, apull-downmustbeaddedtotheSENSE^–pin

as shown in Figure 6. This pull-down effectively takes the

place of the SHDN1 pin, ensuring complete shutdown.

Note: For versions in which both the SHDN1 and SHDN2

pins are available (LTC1159G and all fixed output ver-

sions),thetwopinsaresimplyconnectedtoeachotherand

driven together to guarantee complete shutdown.

When driving standard threshold MOSFETs, the exter-

nal supply must always be present during operation to

prevent MOSFET failure due to insufficient gate drive. The

LTC1149familyshouldalsobeconsideredforapplications

which require the use of standard threshold MOSFETs.

TheFigure6circuitcannotbeusedtoregulateaV_OUTwhich

is greater than the maximum voltage allowed on the

LTC1159 SENSE pins (13V). In applications with V_OUT

>

Important Information About LTC1159 Adjustable

Applications

13V, R_SENSEmust be moved to the ground side of the

output capacitor and load. This operates the current sense

comparator at 0V common mode, increasing the off-time

approximately 40% and requiring the use of a smaller

timing capacitor C_T.

When an output voltage other than 3.3V or 5V is required,

the LTC1159 adjustable version is used with an external

resistive divider from V_OUTto the V_FBpin (Figure 6). The

regulated voltage is determined by:

Inverting Regular Applications

R2

R1

V

= 1 +

1.25V

The LTC1159 can also be used to obtain negative output

voltages from positive inputs. In these inverting applica-

tions, the current sense resistor connects to ground while

the LTC1159 and N-channel MOSFET connections, which

would normally go to ground, instead ride on the negative

output. This allows the negative output voltage to be set by

OUT

)

The V_FBpin is extremely sensitive to pickup from the

inductor switching node. Care should be taken to isolate

the feedback network from the inductor, and the 100pF

capacitor should be connected between the V_FBand SGND

pins next to the package.

V

IN

+

100µF

50V

1N4148

V

IN

CAP

P-GATE

LTC1159

P-DRIVE

Si4401DY

Si4840DY

R

SENSE

0.039Ω

100µH

0.15µF

0.1µF

1

2

5M

V

OUT

V

I

CC

+

3

4

1µF

1N5819

N-GATE

PGND

CC

R2

TH

215k

+

150µF

16V

OS-CON

C

3300pF

T

EXTV

CC

R1

24.9k

C

T

390pF

V

FB

1k

100pF

SGND

100Ω

+

SENSE

0.01µF

0V = NORMAL

>3V = SHUTDOWN

–

SHDN2

SENSE

LTC1159 • F06

R2

V

= 1 +

1.25

OUT

VN2222LL

(

)

R1

VALUES SHOWN FOR V

= 12V/2.5A

OUT

Figure 6. High Efficiency Adjustable Regulator with 5.5V < V_OUT< 13V

12

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APPLICATIO S I FOR ATIO

U

the same process as in conventional applications, using

either the internal divider (LTC1159-3.3, LTC1159-5) or an

external divider with the adjustable version.

By powering EXTV_CCfrom an output-derived source, the

additional V_INcurrent resulting from the driver and control

currents will be scaled by a factor of (Duty Cycle)/(Effi-

ciency). For example in a 20V to 5V application, 10mA of

Figure 15 in the Typical Applications shows a synchronous

12V to –12V converter that can supply up to 1A with better

than 85% efficiency. By grounding the EXTV_CCpin in the

Figure 15 circuit, the entire 12V output voltage is placed

across the driver and control circuits since the LTC1159

ground pins are at –12V. During start-up or short-circuit

conditions, operating power is supplied by the internal

4.5V regulator. The shutdown signal is level-shifted to the

negative output rail by Q3, and Q4 ensures that Q1 and Q2

remain off during the entire shutdown sequence.

V_CCcurrent results in approximately 3mA of V_INcurrent.

Thisreducesthemid-currentlossfrom10%ormore(ifthe

driverwaspowereddirectlyfromV_IN)toonlyafewpercent.

3. I²R losses are easily predicted from the DC resistances

oftheMOSFET,inductorandcurrentshunt.Incontinuous

mode all of the output current flows through L and

R

_SENSE, but is “chopped” between the P-channel and

N-channel MOSFETs. If the two MOSFETs have approxi-

mately the same R_DS(ON), then the resistance of one

MOSFET can simply be summed with the resistances of L

and R_SENSEto obtain I²R losses. For example, if each

R_DS(ON)= 0.1Ω, R_L= 0.15Ω, and R_SENSE= 0.05Ω, then

the total resistance is 0.3Ω. This results in losses ranging

from 3% to 12% as the output current increases from

0.5A to 2A. I²R losses cause the efficiency to roll-off at

high output currents.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can be

expressed as:

4. Transition losses apply only to the P-channel MOSFET,

and only when operating at high input voltages (typically

20V or greater). Transition losses can be estimated from:

%Efficiency = 100 – (L1 + L2 + L3 + ...)

whereL1, L2, etc., aretheindividuallossesasapercentage

of input power.

Transition Loss ≈ 5(V_IN)²(I_MAX)(C_RSS)(f)

OtherlossesincludingC_INandC_OUTESRdissipativelosses,

Schottkyconductionlossesduringdeadtime,andinductor

core losses, generally account for less than 2% total

additional loss.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC1159 circuits: 1) LTC1159 V_INcurrent, 2)

LTC1159 V_CCcurrent, 3) I²R losses and 4) P-channel

transition losses.

Auxiliary Windings—Suppressing Burst Mode

Operation

1. LTC1159 V_INcurrent is the DC supply current given in

theelectricalcharacteristicswhichexcludesMOSFETdriver

and control currents. V_INcurrent results in a small (<1%)

loss which increases with V_IN.

The LTC1159 synchronous switch removes the normal

limitation that power must be drawn from the inductor

primarywindinginordertoextractpowerfromauxiliary

windings. With synchronous switching, auxiliary out-

putsmaybeloadedwithoutregardtotheprimaryoutput

load, providing that the loop remains in continuous

mode operation.

2. LTC1159 V_CCcurrent is the sum of the MOSFET driver

and control circuit currents. The MOSFET driver current

results from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from low

to high to low again, a packet of charge dQ moves from V_CC

to ground. The resulting dQ/dt is a current out of V_CCwhich

is typically much larger than the control circuit current. In

continuousmode, I_GATECHG≈f(Q_P+Q_N), whereQ_PandQ_N

are the gate charges of the two MOSFETs.

Burst Mode operation can be suppressed at low output

currents with a simple external network that cancels the

0.025Vminimumcurrentcomparatorthreshold.Thistech-

nique is also useful for eliminating audible noise from

13

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LTC1159-3.3/LTC1159-5

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APPLICATIO S I FOR ATIO

certain types of inductors in high current (I_OUT> 5A)

If V_OFFSET> 0.025V, the minimum threshold will be

cancelled and Burst Mode operation is prevented from

occurring. Since V_OFFSETis constant, the maximum load

current is also decreased by the same offset. Thus, to get

backtothesameI_MAX, thevalueofthesenseresistormust

be reduced:

applications when they are lightly loaded.

An external offset is put in series with the SENSE^–pin to

subtract from the built-in 0.025V offset. An example of this

technique is shown in Figure 7. Two 100Ω resistors are

inserted in series with the leads from the sense resistor.

With the addition of R3, a current is generated through R1

causing an offset of:

75

R

≈

mΩ

SENSE

I

MAX

R1

To prevent noise spikes from erroneously tripping the

current comparator, a 1000pF capacitor is needed across

the SENSE^–and SENSE⁺pins.

V

= V

OFFSET

OUT

)

R1 + R3

R

SENSE

L

Board Layout Checklist

1

2

3

4

LTC1159

+

R2

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1159. These items are also illustrated graphically in

the layout diagram of Figure 8. Check the following in your

layout:

C

OUT

100Ω

9

8

+

SENSE

R1

1000pF

R3

100Ω

–

SENSE

LTC1159 • F07

Figure 7. Suppressing Burst Mode Operation

+

BOLD LINES INDICATE HIGH CURRENT PATHS

P-CHANNEL

C

IN

1N4148

+

V

IN

0.15µF

D1

1µF

N-CHANNEL

+

–

1

2

3

4

5

6

7

8

16

P-GATE

CAP

SHDN2

EXTV

15

14

13

12

11

10

9

SHUTDOWN

V

IN

0.1 µF

CC

L

P-DRIVE

N-GATE

PGND

OUTPUT DIVIDER

REQUIRED WITH

ADJUSTABLE

5V EXTV

CC

CONNECTION

V

C

CC

T

VERSION ONLY

SGND

–

100pF

V

R1

R2

3

4

FB

I

TH

(SHDN1)

C

1

V

OUT

+

C

T

3300pF

–

+

R

SENSE

2

1k

1000pF

+

LTC1159 • F08

Figure 8. LTC1159 Layout Diagram (N and S Packages)

14

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1) Are the signal and power grounds segregated? The

LTC1159 signal ground must connect separately to the

(–) plate of C_OUT. The other ground pin(s) should return to

the source of the N-channel MOSFET, anode of the Schot-

tky diode and (–) plate of C_IN, which should have as short

lead lengths as possible.

2) Does the LTC1159 SENSE^–pin connect to a point close

to R_SENSEand the (+) plate of C_OUT? In adjustable applica-

tions, the resistive divider R1, R2 must be connected

between the (+) plate of C_OUTand signal ground.

7) Is the SHDN1 pin actively pulled to ground during

normal operation? SHDN1 is a high impedance pin and

must not be allowed to float.

Troubleshooting Hints

SinceefficiencyiscriticaltoLTC1159applicationsitisvery

important to verify that the circuit is functioning correctly

in both continuous and Burst Mode operation. The wave-

form to monitor is the voltage on the C_Tpin .

In continuous mode (I_LOAD> I_BURST) the voltage should be

asawtoothwitha0.9V_P-Pswing. Thisvoltageshouldnever

dip below 2V as shown in Figure 9a. When the load current

islow(I_LOAD<I_BURST), BurstModeoperationshouldoccur

with the C_Twaveform periodically falling to ground as

shown in Figure 9b.

3

) Are the SENSE^–and SENSE⁺leads routed together

with minimum PC trace spacing? The differential

decouplingcapacitorbetweenthetwoSENSEpinsshould

be as close as possible to the LTC1159. Up to 100Ω may

be placed in series with each sense lead to help decouple

the SENSE pins. However, when these resistors are used,

the capacitor should be no larger than 1000pF.

If the C_Tpin is observed falling to ground at high output

currents, it indicates poor decoupling or improper ground-

ing. Refer to the Board Layout Checklist.

4) Does the (+) plate of C_INconnect to the source of the

P-channel MOSFET as closely as possible? An additional

0.1µF ceramic capacitor between V_INand power ground

may be required in some applications.

3.3V

0V

5) Is the V_CCdecoupling capacitor connected closely be-

tween the V_CCpins of the LTC1159 and power ground?

This capacitor carries the MOSFET driver peak currents.

(a) CONTINUOUS MODE OPERATION

3.3V

0V

LTC1159 • F09

6) Inadjustableversions,thefeedbackpin isverysensitive

to pickup from the switch node. Care must be taken to

isolate V_FBfrom possible capacitive coupling of the induc-

tor switch signal.

(b) Burst Mode OPERATION

Figure 9. C_TPin 6 Waveforms

15

LTC1159

LTC1159-3.3/LTC1159-5

U

TYPICAL APPLICATIO S

V

IN

5V

8V TO 20V

+

47µF

25V × 2

OS-CON

1N4148

1µF

WIMA

1N4148

IRF7205

L*

15µH

R

**

2

SENSE

1

16

0.02Ω

P-GATE

CAP

1

3

V

OUT

0.15µF

2.5V/5A

2

3

4

5

6

7

8

15

14

13

12

11

10

9

4

SHUTDOWN

IRF7201

V

SHDN2

IN

0.1µF

EXTV

CC

+

330µF

CC

6.3V × 3

AVX

P-DRIVE

N-GATE

PGND

IRF7201

MBRS330

LTC1159

V

C

+

CC

T

3.3µF

SGND

10k

1%

10k

1%

100pF

1000pF

I

TH

V

FB

+

0.047µF

2k

–

SENSE

100Ω

10k

1000pF

LTC1159 • F10

*MAGNETICS 77120-A7 CORE, 16T 18GA. WIRE

**KRL SL-1-R020J

Figure 10. High Efficiency 8V to 20V Input 2.5/5A Output Regulator

V

IN

4V TO 20V

+

47µF

1N4148

0.1µF

25V

OS-CON

Si9435DY

L*

20µH

R

**

2

SENSE

0.04Ω

1

V

OUT

3.3V/2.5A

3

4

1

2

3

4

5

6

7

8

16

P-GATE

CAP

0.15µF

15

14

13

12

11

10

9

VN2222LL

BAT85

V

SHDN2

IN

0.1µF

1µF

BAT85

EXTV

CC

+

330µF

CC

0.22µF

BAT85

6.3V × 2

AVX

P-DRIVE

N-GATE

Si9410DY

MBRS130LT3

LTC1159-3.3

+

1µF

V

CC

PGND

SGND

+

C

T

270pF

I

TH

SHDN1

SHUTDOWN

3300pF

–

+

SENSE

1k

0.01µF

LTC1159 • F11

*COILTRONICS CTX20-4

**KRL SL-1/2-R040J

Figure 11. 5:1 Input Range (4V to 20V) High Efficiency 3.3V/2.5A Regulator

16

LTC1159

LTC1159-3.3/LTC1159-5

U

TYPICAL APPLICATIO S

V

IN

15V TO 40V

12V

0.33µF

0.1µF

+

1200µF

50V × 2

LXF

1µF

WIMA

MPSA06

MPSA56

1N4148

SMP40P06

HEAT SINK

1

2

3

4

5

6

7

8

16

L*

P-GATE

CAP

R

**

2

SENSE

22µH

0.01Ω

1

15

14

13

12

11

10

9

V

OUT

0.15µF

V

SHDN2

IN

5V/10A

3

4

1N4148

EXTV

CC

+

220µF

10V × 3

P-DRIVE

N-GATE

PGND

MTP75N05HD

MBR350

MPSA56

OS-CON

LTC1159-5

V

C

I

CC

T

SGND

SHDN1

SHUTDOWN

+

TH

10µF

750pF

100Ω

0.047µF

–

+

SENSE

470Ω

1000pF

LTC1159 • F12

*HURRICANE LAB HL-KK122T/BB

**DALE LVR-3-0.01

18k

Figure 12. High Current, High Efficiency 15V to 40V Input 5V/10A Output Regulator

V

IN

15V TO 40V

+

100µF

63V × 2

SXC

1µF

WIMA

1N4148

Si4401DY

5M

L*

50µH

R

**

2

SENSE

1

2

3

4

5

6

7

8

0.02Ω

16

15

14

13

12

11

10

9

1

3

V

OUT

P-GATE

CAP

12V/5A

4

0.15µF

V

SHDN2

IN

0.1µF

3.3µF

EXTV

CC

Si4840DY

+

P-DRIVE

N-GATE

PGND

MBR350

150µF

16V × 2

LTC1159

OS-CON

V

C

+

CC

T

SGND

10.5k

1%

90.9k

1%

100pF

390pF

I

V

TH

FB

+

3300pF

–

SENSE

100Ω

470Ω

1000pF

LTC1159 • F13

0V = NORMAL

>3V = SHUTDOWN

VN2222LL

*COILTRONICS CTX50-5-KM

**IRC LO-3-0.02 ±5%

Figure 13. High Efficiency 15V to 40V Input 12V/5A Output Regulator

17

LTC1159

LTC1159-3.3/LTC1159-5

U

TYPICAL APPLICATIO S

V

IN

5.5V TO 24V

47µF

25V × 2

OS-CON

1µF

WIMA

+

BAS16

Si9435DY

T*

5V

1

2

3

4

5

6

7

8

16

OUTPUT

•

P-GATE

CAP

0.33µF

15 0V = NORMAL

>2V = SHUTDOWN

14

V

SHDN2

IN

•

0.22µF

2.2µF

EXTV

CC

Si9410DY

13

+

220µF

10V × 2

AVX

Si9410DY

P-DRIVE

N-GATE

PGND

MBRS140T3

LTC1159

1µF

100k

BAS16

+

12

11

V

C

+

CC

T

SGND

24.9k

56pF

124k

1%

1000pF

2200pF

1k

0.01µF

10

1%

1k

I

V

TH

FB

+

220µF

10V × 4

9

102k

1%

–

+

SENSE

AVX

100Ω

3

4

1

2

BAS16

R

**

SENSE

1000pF

0.02Ω

100Ω

3.3V

OUTPUT

BAS16

LTC1159 • F14

+

*HURRICANE LAB HL-8700

**KRL SL-1-R020J

10µF

Figure 14. 17W Dual Output High Efficiency 5V and 3.3V Regulator

U

PACKAGE DESCRIPTIO

G Package

20-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

7.07 – 7.33*

(.278 – .289)

5.20 – 5.38**

(.205 – .212)

1.73 – 1.99

(.068 – .078)

20 19 18 17 16 15 14 13 12 11

0° – 8°

7.65 – 7.90

(.301 – .311)

.65

(.0256)

BSC

.13 – .22

.55 – .95

(.005 – .009)

(.022 – .037)

.05 – .21

(.002 – .008)

.25 – .38

(.010 – .015)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

G20 SSOP 0501

5

7

8

1

2

3

4

6

9 10

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED .152mm (.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

18

LTC1159

LTC1159-3.3/LTC1159-5

U

PACKAGE DESCRIPTIO

N Package

16-Lead PDIP (Narrow .300 Inch)

(Reference LTC DWG # 05-08-1510)

0.770*

(19.558)

MAX

14

12

10

9

8

15

13

11

16

0.255 ± 0.015*

(6.477 ± 0.381)

2

1

3

4

6

5

7

0.300 – 0.325

0.130 ± 0.005

0.045 – 0.065

(7.620 – 8.255)

(3.302 ± 0.127)

(1.143 – 1.651)

0.020

(0.508)

MIN

0.065

(1.651)

TYP

0.009 – 0.015

(0.229 – 0.381)

+0.035

–0.015

0.325

0.125

(3.175)

MIN

0.018 ± 0.003

(0.457 ± 0.076)

0.100

(2.54)

BSC

+0.889

8.255

(

)

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

N16 1098

S Package

16-Lead Plastic Small Outline (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1610)

0.386 – 0.394*

(9.804 – 10.008)

16

15

14

13

12

11

10

9

0.150 – 0.157**

(3.810 – 3.988)

0.228 – 0.244

(5.791 – 6.197)

5

7

8

1

2

3

4

6

0.010 – 0.020

(0.254 – 0.508)

× 45°

0.053 – 0.069

(1.346 – 1.752)

0.004 – 0.010

(0.101 – 0.254)

0.008 – 0.010

(0.203 – 0.254)

0° – 8° TYP

0.050

(1.270)

BSC

0.014 – 0.019

(0.355 – 0.483)

TYP

0.016 – 0.050

(0.406 – 1.270)

S16 1098

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

19

LTC1159

LTC1159-3.3/LTC1159-5

U

TYPICAL APPLICATIO

V

= 12V

IN

+

330

35V

NICHICON

µF

Q1

Si9435

1N4148

0.1µF

0.15µF

Q2

Si9410

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

P-GATE

CAP

MBRS140

V

IN

SHDN2

L*

100

µH

V

CC

EXTV

CC

0.1µF

LTC1159

P-DRIVE

3.3

N-GATE

PGND

1N5818

µF

V

C

I

CC

+

OUTPUT

–12V/1A

SGND

T

200pF

V

FB

10.5k

90.5k

5V OR 3.3V

150µF

16V × 2

OS-CON

TH

(SHDN1)

C

6800pF

1k

T

+

–

+

390pF

Q3

TP0610L

SENSE

Q4

2N7002

SHUTDOWN

1000pF

20k

100Ω

3

4

1

5.1V

1N5993

R

**

SENSE

510k

0.05Ω

2

1159 F15

*DALE TJ4-100-1

µ

**IRC LR2512-01-R050-J

Figure 15. High Efficiency 12V to –12V 1A Converter

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

≤ 36V, Minimum C , Current Mode

LTC1628

2-Phase, Dual Step-Down Controller

550kHz Dual, 2-Phase Step-Down Controller

Synchronous Step-Down Controller

550kHz Synchronous Step-Down Controller

V

IN

LTC1702

Minimum C , No Sense Resistor Required, V ≤ 7V

IN

LTC1735

3.5V ≤ V ≤ 36V, 0.8V ≤ V

≤ 6V, Synchronizable

IN

OUT

LTC1773

2.65V ≤ V ≤ 8.5V, 0.8V ≤ V

≤ V , Synchronizable to 750kHz, MS10

IN

OUT

IN

LTC1778

No R

^TMStep-Down Controller

No Sense Resistor Required, t

≤ 100ns, Current Mode, GN16

SENSE

ON(MIN)

LTC1876

Triple Output, 2-Phase Controller

Two, 2-Phase Step-Down Controllers and Step-Up DC/DC Converter in One IC

No R

is a trademark of Linear Technology Corporation.

SENSE

1159fa LT/TP 0801 2K REV A • PRINTED IN USA

LINEAR TECHNOLOGY CORPORATION 1994

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1159-3.3_15
厂家：	Linear
描述：	High Efficiency Synchronous Step-Down Switching Regulators
文件：	总20页 (文件大小：290K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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