LTC1198-1ACS8-PBF [Linear]
8-Bit, SO-8, 1Msps ADCs with Auto-Shutdown Options; 8位， SO - 8 ， 1MSPS ADC，具有自动关机选项
| 型号： | LTC1198-1ACS8-PBF |
| 厂家： | 
Linear |
| 描述： | 8-Bit, SO-8, 1Msps ADCs with Auto-Shutdown Options |
| 文件： | 总28页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1196/LTC1198
8-Bit, SO-8, 1Msps ADCs
with Auto-Shutdown Options
FEATURES
DESCRIPTION
The LTC®1196ꢀLTC1198 are 600ns, 8-bit AꢀD converters
with sampling rates up to 1MHz. They are offered in 8-pin
SO packages and operate on 3V to 6V supplies. Power
dissipation is only 10mW with a 3V supply or 50mW with
a 5V supply. The LTC1198 automatically powers down to a
typicalsupplycurrentof1nAwheneveritisnotperforming
conversions. These 8-bit switched-capacitor successive
approximation ADCs include sample-and-holds. The
LTC1196 has a differential analog input; the LTC1198 of-
fers a software selectable /-channel MUX.
n
High Sampling Rates: 1MHz (LTC1196)
750kHz (LTC1198)
n
Low Cost
n
Single Supply 3V and 5V Specifications
n
Low Power: 10mW at 3V Supply
50mW at 5V Supply
n
Auto-Shutdown: 1nA Typical (LTC1198)
n
1ꢀ/LSB Total Unadjusted Error over Temperature
n
3-Wire Serial IꢀO
n
1V to 5V Input Span Range (LTC1196)
n
Converts 1MHz Inputs to 7 Effective Bits
The 3-wire serial IꢀO, SO-8 packages, 3V operation and
extremely high sample rate-to-power ratio make these
ADCs an ideal choice for compact, high speed systems.
n
Differential Inputs (LTC1196)
n
/-Channel MUX (LTC1198)
n
SO-8 Plastic Package
These ADCs can be used in ratiometric applications or
with external references. The high impedance analog in-
puts and the ability to operate with reduced spans below
1V full scale (LTC1196) allow direct connection to signal
sources in many applications, eliminating the need for
gain stages.
APPLICATIONS
n
High Speed Data Acquisition
n
Disk Drives
n
Portable or Compact Instrumentation
n
Low Power or Battery-Operated Systems
The A grade devices are specified with total unadjusted
error of 1ꢀ/LSB maximum over temperature.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Single 5V Supply, 1Msps, 8-Bit Sampling ADC
Effective Bits and S/(N + D) vs Input Frequency
8
7
6
5
4
3
/
1
0
50
1μF
5V
V
= V = /.7V
CC
REF
44
f
f
= 383kHz (LTC1196)
= /87kHz (LTC1198)
SMPL
SMPL
V
= V = 5V
CC
REF
f
= 1MHz (LTC1196)
SMPL
1
/
3
4
8
7
6
5
f
= 750kHz (LTC1198)
CS
V
SMPL
CC
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP,
OR SHIFT REGISTERS
+IN
–IN
GND
CLK
ANALOG INPUT
0V TO 5V RANGE
LTC1196
D
OUT
V
REF
1196ꢀ98 TA01
T
= /5°C
A
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
1196ꢀ98 G/4
119698fa
1
LTC1196/LTC1198
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)
Supply Voltage (V ) to GND .................................... 7V
Operating Temperature Range
CC
Voltage
LTC1196-1AC, LTC1198-1AC, LTC1196-1BC,
LTC1198-1BC, LTC1196-/AC, LTC1198-/AC,
LTC1196-/BC, LTC1198-/BC ................. 0°C to 70°C
Storage Temperature Range.................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................ 300°C
Analog Reference ....................... –0.3V to V + 0.3V
CC
Digital Inputs ......................................... –0.3V to 7V
Digital Outputs ........................... –0.3V to V + 0.3V
CC
Power Dissipation.............................................. 500mW
PIN CONFIGURATION
TOP VIEW
TOP VIEW
LTC1196
LTC1198
CSꢀ
SHUTDOWN
CH0
1
/
3
4
8
7
6
5
V
1
/
3
4
8
7
6
5
V
(V
)
CS
+IN
CC
CC REF
CLK
CLK
D
D
V
CH1
GND
–IN
OUT
OUT
D
GND
REF
IN
S8 PACKAGE
8-LEAD PLASTIC SO
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 150°C, θ = 175°CꢀW
T
= 150°C, θ = 175°CꢀW
JMAX JA
JA
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
11961A
PACKAGE DESCRIPTION
8-Lead Plastic SO
8-Lead Plastic SO
8-Lead Plastic SO
8-Lead Plastic SO
8-Lead Plastic SO
8-Lead Plastic SO
8-Lead Plastic SO
8-Lead Plastic SO
TEMPERATURE RANGE
0°C to 70°C
LTC1196-1ACS8#PBF
LTC1196-1BCS8#PBF
LTC1196-/ACS8#PBF
LTC1196-/BCS8#PBF
LTC1198-1ACS8#PBF
LTC1198-1BCS8#PBF
LTC1198-/ACS8#PBF
LTC1198-/BCS8#PBF
LTC1196-1ACS8#TRPBF
LTC1196-1BCS8#TRPBF
LTC1196-/ACS8#TRPBF
LTC1196-/BCS8#TRPBF
LTC1198-1ACS8#TRPBF
LTC1198-1BCS8#TRPBF
LTC1198-/ACS8#TRPBF
LTC1198-/BCS8#TRPBF
11961B
0°C to 70°C
1196/A
0°C to 70°C
1196/B
0°C to 70°C
11981A
0°C to 70°C
11981B
0°C to 70°C
1198/A
0°C to 70°C
1198/B
0°C to 70°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http:ꢀꢀwww.linear.comꢀleadfreeꢀ
For more information on tape and reel specifications, go to: http:ꢀꢀwww.linear.comꢀtapeandreelꢀ
119698fa
2
LTC1196/LTC1198
The l denotes the specifications which apply over
RECOMMENDED OPERATING CONDITIONS
the full operating temperature range, otherwise specifications are at TA = 25°C.
LTC1196-1
LTC1198-1
TYP
LTC1196-2
LTC1198-2
TYP
SYMBOL PARAMETER
VCC Supply Voltage
= 5V Operation
CONDITIONS
MIN
MAX
MIN
MAX UNITS
/.7
6
/.7
6
V
V
CC
f
Clock Frequency
0.01
0.01
14.4
1/.0
0.01
0.01
1/.0
9.6
MHz
MHz
CLK
l
t
Total Cycle Time
LTC1196
LTC1198
1/
16
1/
16
CLK
CLK
CYC
t
t
t
Analog Input Sampling Time
/.5
10
/0
/.5
13
/6
CLK
ns
SMPL
Hold Time CS Low After Last CLK↑
hCS
ns
Setup Time CS↓ Before First CLK↑
(See Figures 1, /)
suCS
t
t
t
t
t
t
LTC1198
LTC1198
/0
/0
/6
/6
ns
ns
Hold Time D After CLK↑
hDI
IN
Setup Time D Stable Before CLK↑
suDI
IN
CLK High Time
f
f
= f
CLK(MAX)
= f
CLK(MAX)
40%
40%
/5
40%
40%
3/
1ꢀf
CLK
WHCLK
WLCLK
WHCS
WLCS
CLK
CLK
CLK Low Time
1ꢀf
CLK
CS High Time Between Data Transfer Cycles
CS Low Time During Data Transfer
ns
LTC1196
LTC1198
11
15
11
15
CLK
CLK
The l denotes the specifications
CONVERTER AND MULTIPLEXER CHARACTERISTICS
which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VREF = 5V, fCLK = fCLK(MAX)
as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1196-1
LTC1198-1
TYP
LTC1196-2
LTC1198-2
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX UNITS
l
l
l
l
l
No Missing Codes Resolution
Offset Error
8
8
Bits
1ꢀ/
1ꢀ/
1ꢀ/
1ꢀ/
1
1
1
1
LSB
LSB
LSB
LSB
Linearity Error
(Note 3)
Full-Scale Error
Total Unadjusted Error (Note 4)
LTC1196, V = 5.000V
REF
LTC1198, V = 5.000V
CC
Analog and REF Input Range
Analog Input Leakage Current
LTC1196
(Note 5)
–0.05V to V + 0.05V
V
CC
l
1
1
μA
The l denotes the specifications which
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
l
l
l
l
V
IH
V
IL
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 5./5V
= 4.75V
/.0
CC
CC
IN
0.8
/.5
V
I
I
= V
μA
μA
IH
IL
CC
= 0V
–/.5
IN
l
l
V
OH
V
CC
V
CC
= 4.75V, I = 10μA
= 4.75V, I = 360μA
4.5
/.4
4.74
4.71
V
V
O
O
119698fa
3
LTC1196/LTC1198
The l denotes the specifications which
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
= 4.75V, I = 1.6mA
MIN
TYP
MAX
0.4
3
UNITS
V
l
l
V
Low Level Output Voltage
Hi-Z Output Leakage
Output Source Current
Output Sink Current
Reference Current, LTC1196
V
CC
OL
O
I
I
I
I
CS = High
μA
OZ
V
V
= 0V
–/5
45
mA
mA
SOURCE
SINK
OUT
OUT
= V
CC
l
l
CS = V
SMPL
0.001
0.5
3
1
μA
mA
REF
CC
f
= f
SMPL(MAX)
l
l
l
I
CC
Supply Current
CS = V , LTC1198 (Shutdown)
0.001
7
11
3
15
/0
μA
mA
mA
CC
CS = V , LTC1196
CC
f
= f
, LTC1196ꢀLTC1198
SMPL(MAX)
SMPL
The l denotes the specifications which apply over the full operating temperature range,
DYNAMIC ACCURACY
otherwise specifications are at TA = 25°C. VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions,
unless otherwise noted.
LTC1196
TYP
LTC1198
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX UNITS
Sꢀ(N + D) Signal-to-Noise Plus Distortion
500kHzꢀ1MHz Input Signal
500kHzꢀ1MHz Input Signal
500kHzꢀ1MHz Input Signal
47ꢀ45
49ꢀ47
55ꢀ48
51
47ꢀ45
49ꢀ47
55ꢀ48
51
dB
dB
dB
dB
THD
IMD
Total Harmonic Distortion
Peak Harmonic or Spurious Noise
Intermodulation Distortion
f
IN1
f
IN/
= 499.37kHz
= 50/.446kHz
Full-Power Bandwidth
8
1
8
1
MHz
MHz
Full Linear Bandwidth [Sꢀ(N + D) > 44dB
The l denotes the specifications which apply over the full operating temperature range,
AC CHARACTERISTICS
otherwise specifications are at TA = 25°C. VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions,
unless otherwise noted.
LTC1196-1
LTC1198-1
TYP
LTC1196-2
LTC1198-2
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX UNITS
t
Conversion Time (See Figures 1, /)
600
710
710
900
ns
ns
CONV
l
f
Maximum Samping Frequency
LTC1196
LTC1196
LTC1198
LTC1198
1./0
1.00
0.90
0.75
1.00
0.80
0.75
0.60
MHz
MHz
MHz
MHz
SMPL(MAX)
l
l
t
C
= /0pF
55
64
73
68
78
94
ns
ns
Delay Time, CLK↑ to D
Delay Time CS↑ to D
Data Valid
dDO
LOAD
OUT
OUT
l
l
l
l
t
t
t
70
30
45
1/0
50
88
43
55
150
63
ns
ns
ns
Hi-Z
DIS
OUT
C
C
= /0pF
= /0pF
Delay Time, CLK↓ to D
Enabled
en
LOAD
Time Output Data Remains Valid After
CLK↑
30
30
hDO
LOAD
l
l
t
t
D
OUT
D
OUT
Fall Time
Rise
C
C
= /0pF
= /0pF
5
5
15
15
10
10
/0
/0
ns
ns
f
LOAD
r
LOAD
C
IN
Input Capacitance
Analog Input On Channel
Analog Input Off Channel
Digital Input
30
5
5
30
5
5
pF
pF
pF
119698fa
4
LTC1196/LTC1198
The l denotes the specifications which apply over
RECOMMENDED OPERATING CONDITIONS
the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V Operation.
LTC1196-1
LTC1198-1
LTC1196-2
LTC1198-2
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX UNITS
f
Clock Frequency
0.01
0.01
5.4
4.6
0.01
0.01
4
3
MHz
MHz
CLK
l
t
Total Cycle Time
LTC1196
LTC1198
1/
16
1/
16
CLK
CLK
CYC
t
t
t
Analog Input Sampling Time
/.5
/0
40
/.5
40
78
CLK
ns
SMPL
hCS
Hold Time CS Low After Last CLK↑
ns
Setup Time CS↓ Before First CLK↑
(See Figures 1, /)
suCS
t
t
t
t
t
LTC1198
LTC1198
40
40
78
78
ns
ns
Hold Time D After CLK↑
hDI
IN
Setup Time D Stable Before CLK↑
suDI
IN
CLK High Time
CLK Low Time
f
f
= f
= f
40%
40%
50
40%
40%
96
1ꢀf
CLK
WHCLK
WLCLK
WHCS
CLK
CLK
CLK(MAX)
CLK(MAX)
1ꢀf
CLK
CS High Time Between Data Transfer
Cycles
ns
t
CS Low Time During Data Transfer
LTC1196
LTC1198
11
15
11
15
CLK
CLK
WLCS
The l denotes the specifications
CONVERTER AND MULTIPLEXER CHARACTERISTICS
which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V, VREF = 2.5V,
fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1196-1
LTC1198-1
TYP
LTC1196-2
LTC1198-2
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX UNITS
l
l
l
l
l
No Missing Codes Resolution
Offset Error
8
8
Bits
1ꢀ/
1ꢀ/
1ꢀ/
1ꢀ/
1
1
1
1
LSB
LSB
LSB
LSB
Linearity Error
(Note 3)
Full-Scale Error
Total Unadjusted Error (Note 4)
LTC1196, V = /.5.000V
REF
LTC1198, V = /.700V
CC
Analog and REF Input Range
Analog Input Leakage Current
LTC1196
(Note 5)
–0.05V to V + 0.05V
V
CC
l
1
1
μA
The l denotes the specifications which apply
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
l
l
l
l
V
IH
V
IL
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 3.6V
= /.7V
1.9
CC
CC
IN
0.45
/.5
V
I
IH
I
IL
= V
μA
μA
CC
= 0V
–/.5
IN
l
l
V
V
CC
V
CC
= /.7V, I = 10μA
/.3
/.1
/.60
/.45
V
V
OH
O
= /.7V, I = 360μA
O
l
l
V
Low Level Output Voltage
Hi-Z Output Leakage
V
= /.7V, I = 400μA
0.3
3
V
OL
CC
O
I
OZ
CS = High
μA
119698fa
5
LTC1196/LTC1198
The l denotes the specifications which apply
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
–10
15
MAX
UNITS
mA
I
I
I
Output Source Current
Output Sink Current
Reference Current, LTC1196
V
V
= 0V
SOURCE
SINK
OUT
OUT
= V
mA
CC
l
l
CS = V
SMPL
0.001
0./5
3.0
0.5
μA
mA
REF
CC
f
= f
SMPL(MAX)
l
l
l
I
CC
Supply Current
CS = V = 3.3V, LTC1198 (Shutdown)
0.001
1.5
/.0
3.0
4.5
6.0
μA
mA
mA
CC
CS = V = 3.3V, LTC1196
CC
f
= f
, LTC1196ꢀLTC1198
SMPL(MAX)
SMPL
The l denotes the specifications which apply over the full operating temperature range,
DYNAMIC ACCURACY
otherwise specifications are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions,
unless otherwise noted.
LTC1196
TYP
LTC1198
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX UNITS
Sꢀ(N + D) Signal-to-Noise Plus Distortion
190kHzꢀ380kHz Input Signal
190kHzꢀ380kHz Input Signal
190kHzꢀ380kHz Input Signal
47ꢀ45
49ꢀ47
53ꢀ46
51
47ꢀ45
49ꢀ47
55ꢀ46
51
dB
dB
dB
dB
THD
IMD
Total Harmonic Distortion
Peak Harmonic or Spurious Noise
Intermodulation Distortion
f
IN1
f
IN/
= 189.37kHz
= 19/.446kHz
Full-Power Bandwidth
5
5
MHz
MHz
Full Linear Bandwidth [Sꢀ(N + D) > 44dB
0.5
0.5
The l denotes the specifications which apply over the full operating temperature range,
AC CHARACTERISTICS
otherwise specifications are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions,
unless otherwise noted.
LTC1196-1
LTC1198-1
TYP
LTC1196-2
LTC1198-2
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX UNITS
t
Conversion Time (See Figures 1, /)
1.58
1.85
/.13
/.84
μs
μs
CONV
l
f
Maximum Samping Frequency
LTC1196
LTC1196
LTC1198
LTC1198
450
383
337
/87
333
/50
/50
187
kHz
kHz
kHz
kHz
SMPL(MAX)
l
l
t
C
= /0pF
100
150
180
130
/00
/50
ns
ns
Delay Time, CLK↑ to D
Delay Time CS↑ to D
Data Valid
dDO
LOAD
OUT
OUT
l
l
l
l
t
t
t
110
80
//0
130
1/0
100
1/0
/50
/00
ns
ns
ns
Hi-Z
DIS
OUT
C
C
= /0pF
= /0pF
Delay Time, CLK↓ to D
Enabled
en
LOAD
Time Output Data Remains Valid After
CLK↑
45
90
45
hDO
LOAD
l
l
t
t
D
OUT
D
OUT
Fall Time
Rise
C
C
= /0pF
= /0pF
10
10
30
30
15
15
40
40
ns
ns
f
LOAD
r
LOAD
C
IN
Input Capacitance
Analog Input On Channel
Analog Input Off Channel
Digital Input
30
5
5
30
5
5
pF
pF
pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
119698fa
6
LTC1196/LTC1198
ELECTRICAL CHARACTERISTICS
Note 4: Total unadjusted error includes offset, full scale, linearity,
multiplexer and hold step errors.
Note 5: Channel leakage current is measured after the channel selection.
Note 2: All voltage values are with respect to GND.
Note 3: Integral nonlinearity is defined as deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Clock Rate
Supply Current vs Supply Voltage
Supply Current vs Sample Rate
9
8
7
6
5
4
3
/
1
0
10
1
14
1/
10
8
T
= /5°C
A
LT1196 V = 5V
CC
V
= 5V
CC
LT1196 V = /.7V
CC
“ACTIVE” MODE
CS = 0V
T
= /5°C
A
LT1198 V = 5V
CC
0.1
CS = 0V
V
LTC1196
LTC1198
= V
REF
CC
6
LT1198 V = /.7V
CC
4
V
CC
= /.7V
1/
0.01
“SHUTDOWN” MODE
CS = V
/
CC
LTC1198
0.00000/
T
= /5°C
A
0.001
0
4
6
8
14
5.5
6.0
/.5
3.0
3.5
4.0 4.5 5.0
SUPPLY VOLTAGE (V)
0
/
10
16
100
1k
10k
100k
1M
FREQUENCY (MHz)
SAMPLE RATE (Hz)
1196ꢀ98 G03
1196ꢀ98 G01
1196ꢀ98 G0/
Supply Current vs Temperature
Offset vs Reference Voltage
Offset vs Supply Voltage
10
9
8
7
6
5
4
3
/
1
0
0.5
0.4
1.6
1.4
1./
1.0
0.8
0.6
0.4
0./
0
T
= /5°C
= 5V
T
= /5°C
= V
CS = 0V
A
CC
A
REF
V
f
V
f
CC
= 1/MHz
= 3MHz
CLK
CLK
0.3
V
= 5V
CC
0./
0.1
0
–0.1
–0./
–0.3
–0.4
–0.5
V
CC
= /.7V
–55 –35 –15
5
/5 45 65 85 105 1/5
1.5
/.5 3.0 3.5
4.5
/.5
3.5 4.0 4.5
5.0 5.5 6.0
0.5 1.0
4.0
5.0
3.0
/.0
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
1196ꢀ98 G04
1196ꢀ98 G06
1196ꢀ98 G05
119698fa
7
LTC1196/LTC1198
TYPICAL PERFORMANCE CHARACTERISTICS
Linearity Error vs
Reference Voltage
Linearity Error vs Supply Voltage
Supply Current vs Sample Rate
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0./
0.1
0
0.5
0.4
0.5
0.4
T
= /5°C
= 5V
T
V
f
= /5°C
= V
T
V
f
= /5°C
= 5V
A
CC
A
REF
A
CC
V
f
CC
= 1/MHz
= 3MHz
= 1/MHz
CLK
CLK
CLK
0.3
0.3
0./
0./
0.1
0.1
0
0
–0.1
–0./
–0.3
–0.4
–0.5
–0.1
–0./
–0.3
–0.4
–0.5
1.5
/.5 3.0 3.5
4.5
4.5
SUPPLY VOLTAGE (V)
6.0
0.5 1.0
4.0
5.0
/.5
3.5 4.0
5.0
/.0
3.0
5.5
0
1.0
3.0 3.5 4.0 4.5 5.0
0.5
1.5 /.0 /.5
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
1196ꢀ98 G07
1196ꢀ98 G08
1196ꢀ98 G09
Maximum Clock Frequency vs
Supply Voltage
Maximum Clock Frequency vs
Source Resistance
Gain vs Supply Voltage
0.5
0.4
18
16
14
1/
10
8
19
17
15
13
11
9
T
A
CC
= /5°C
= V = 5V
REF
T
f
= /5°C
T
V
= /5°C
= V
A
A
REF
V
= 3MHz
CLK
REF
CC
V
= V
CC
0.3
0./
V
+IN
IN
0.1
–IN
0
–
R
SOURCE
–0.1
–0./
–0.3
–0.4
–0.5
6
4
7
/
0
5
/.5
3.5 4.0 4.5
5.0 5.5 6.0
1
10
1k
10k
100k
3.0
100
4.5
SUPPLY VOLTAGE (V)
5.5
6.0
/.5 3.0
3.5 4.0
5.0
SUPPLY VOLTAGE (V)
SOURCE RESISTANCE (Ω)
1196ꢀ98 G1/
1196ꢀ98 G10
1196ꢀ98 G11
Minimum Clock Rate for
0.1LSB* Error
ADC Noise vs Referenced and
Supply Voltage
Sample-and-Hold Acquisition
Time vs Source Resistance
100
90
80
70
60
50
40
30
/0
10
0
10000
1000
100
0.35
0.30
0./5
0./0
0.15
0.10
0.05
0
T
A
CC
= /5°C
= V = 5V
REF
V
V
= 5V
= 5V
T
V
= /5°C
= V
CC
REF
A
REF
V
CC
+
R
SOURCE
V
+IN
–IN
IN
–55 –35 –15
5
/5 45 65 85 105 1/5
1
10
100
1k
10k
4.5
SUPPLY VOLTAGE (V)
5.5
6.0
/.5 3.0
3.5 4.0
5.0
SOURCE RESISTANCE (Ω)
TEMPERATURE (°C)
1196ꢀ98 G15
1196ꢀ98 G13
1196ꢀ98 G14
*AS THE FREQUENCY IS DECREASED FROM 1/MHz, MINIMUM CLOCK FREQUENCY (ΔERROR ≤ 0.1LSB) REPRESENTS THE
FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 1/MHz VALUE IS FIRST DETECTED.
119698fa
8
LTC1196/LTC1198
TYPICAL PERFORMANCE CHARACTERISTICS
Digital Input Logic Threshold vs
Supply Voltage
DOUT Delay Time vs Supply
Voltage
DOUT Delay Time vs Temperature
160
140
1/0
100
80
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
V
REF
= V
CC
T
V
= /5°C
= V
T
= /5°C
A
REF
A
140
1/0
100
80
CC
V
CC
= /.7V
V
CC
= 5V
60
60
40
40
/0
/0
0
0
0
1/0
140
–60 –40 –/0
/0 40 60 80 100
4.5
SUPPLY VOLTAGE (V)
5.5
6.0
/.5 3.0
3.5 4.0
5.0
4.5
SUPPLY VOLTAGE (V)
5.5
6.0
/.5 3.0
3.5 4.0
5.0
TEMPERATURE (°C)
1196ꢀ98 G18
1196ꢀ98 G17
1196ꢀ98 G16
Input Channel Leakage Current
vs Temperature
Integral Nonlinearity vs
Code at 5V
Differential Nonlinearity vs
Code at 5V
0.5
0.5
1000
100
10
V
V
f
= 5V
= 5V
V
V
f
= 5V
= 5V
V
V
= 5V
= 5V
CC
REF
CC
REF
CC
REF
= 1/MHz
= 1/MHz
CLK
CLK
0
0
ON CHANNEL
1
OFF CHANNEL
0.1
0.01
–0.5
–0.5
0
0
3/ 64 96
1/8
160
19/ //4
/56
3/ 64 96
1/8
160 /56
19/ //4
0
1/0
140
–60 –40 –/0
/0 40 60 80 100
CODE
CODE
TEMPERATURE (°C)
1196ꢀ98 G/0
1196ꢀ98 G/1
1196ꢀ98 G19
Integral Nonlinearity vs
Code at 2.7V
Differential Nonlinearity vs
Code at 2.7V
Effective Bits and S/(N + D) vs
Input Frequency
0.5
0.5
8
7
6
5
4
3
/
1
0
50
44
V
V
f
= /.7V
= /.5V
V
V
f
= /.7V
= /.5V
CC
REF
CLK
CC
REF
CLK
V
= V = /.7V
CC
REF
f
f
= 383kHz (LTC1196)
= /87kHz (LTC1198)
SMPL
SMPL
= 3MHz
= 3MHz
V
= V = 5V
CC
REF
f
= 1MHz (LTC1196)
SMPL
f
= 750kHz (LTC1198)
SMPL
0
0
T
= /5°C
A
–0.5
–0.5
0
1/8
19/ //4
/56
0
3/ 64 96
1/8
160 /56
19/ //4
3/ 64 96
160
1k
10k
100k
1M
CODE
CODE
INPUT FREQUENCY (Hz)
1196ꢀ98 G/4
1196ꢀ98 G//
1196ꢀ98 G/3
119698fa
9
LTC1196/LTC1198
TYPICAL PERFORMANCE CHARACTERISTICS
FFT Output of 455kHz AM Signal
Digitized at 1Msps
4096 Point FFT Plot at 5V
4096 Point FFT Plot at 2.7V
0
–10
–/0
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–/0
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–/0
–30
–40
–50
–60
–70
–80
–90
–100
V
f
SMPL
= /.7V
V
f
SMPL
= 5V
V
f
SMPL
= 5V
CC
IN
CC
IN
CC
IN
= /9kHz
= 455kHz WITH /0kHz AM
= 1MHz
= /9kHz
f
= 340kHz
f
f
= 88/kHz
0
100
/00
300
400
500
0
50
100
FREQUENCY (kHz)
150
/00
0
100
/00
300
400
500
FREQUENCY (kHz)
FREQUENCY (kHz)
1196ꢀ98 G/5
1196ꢀ98 G/6
1196ꢀ98 G/7
Power Supply Feedthrough vs
Ripple Frequency
Power Supply Feedthrough vs
Ripple Frequency
S/(N + D) vs Reference Voltage
and Input Frequency
50
45
40
35
30
/5
0
–10
–/0
–30
–40
–50
–60
–70
0
–10
–/0
–30
–40
–50
–60
–70
T
= /5°C
CC RIPPLE
= 5MHz
T
= /5°C
CC RIPPLE
= 1/MHz
A
A
V
f
(V
= 10mV)
V
f
(V
= /0mV)
f
IN
= 500kHz
CLK
CLK
f
= /00kHz
IN
f
= 100kHz
IN
V
= 5V
CC
3./5
1./5 1.75 /./5 /.75
3.75 4./5 4.75 5./5
1k
10k
100k
1M
1k
10k
100k
1M
REFERENCE VOLTAGE (V)
RIPPLE FREQUENCY (Hz)
RIPPLE FREQUENCY (Hz)
1196ꢀ98 G/9
1196ꢀ98 G/8
1196ꢀ98 G30
Intermodulation Distortion at 2.7V
Intermodulation Distortion at 5V
S/(N + D) vs Input Level
50
40
30
/0
10
0
0
–10
–/0
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–/0
–30
–40
–50
–60
–70
–80
–90
–100
V
= 5V
V
= /.7V
V
= V = 5V
CC
CC
CC
REF
f1 = /00kHz
f/ = /10kHz
f1 = 100kHz
f/ = 110kHz
f
f
= 500kHz
IN
SMPL
= 1MHz
f
= 750kHz
f
= 4/0kHz
SMPL
SMPL
–/0
0
50
100
150
/00
/50
0
100
/00
FREQUENCY (kHz)
300
400
–40 –35 –30 –/5
–15 –10 –5
0
INPUT LEVEL (dB)
FREQUENCY (kHz)
1196ꢀ98 G33
1196ꢀ98 G31
1196ꢀ98 G3/
119698fa
10
LTC1196/LTC1198
TYPICAL PERFORMANCE CHARACTERISTICS
Output Amplitude vs
Input Frequency
Spurious-Free Dynamic Range
vs Frequency
100
80
60
40
/0
0
70
60
50
40
30
/0
10
0
V
CLK
= 5V
CC
f
= 1/MHz
V
= V = 5V
CC
REF
V
CLK
= 3V
CC
V
= V = /.7V
CC
REF
f
= 5MHz
T
= /5°C
A
1k
10k
100k
1M
10M
1k
10k
100k
FREQUENCY (Hz)
1M
10M
INPUT FREQUENCY (Hz)
1196ꢀ98 G34
1196ꢀ98 G35
PIN FUNCTIONS
LTC1196
LTC1198
CS (Pin 1): Chip Select Input. A logic low on this input
enables the LTC1196. A logic high on this input disables
the LTC1196.
CS/SHUTDOWN (Pin 1): Chip Select Input. A logic low
on this input enables the LTC1198. A logic high on this
input disables the LTC1198 and disconnects the power
to THE LTC1198.
+
IN (Pin 2): Analog Input. This input must be free of noise
with respect to GND.
CHO (Pin 2): Analog Input. This input must be free of
noise with respect to GND.
–
IN (Pin 3): Analog Input. This input must be free of noise
with respect to GND.
CH1(Pin3):AnalogInput. Thisinputmustbefreeofnoise
with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
V
(Pin 5): Reference Input. The reference input defines
REF
the span of the AꢀD converter and must be kept free of
D (Pin 5): Digital Data Input. The multiplexer address is
IN
noise with respect to GND.
shifted into this input.
D
(Pin 6): Digital Data Output. The AꢀD conversion
D
(Pin 6): Digital Data Output. The AꢀD conversion
OUT
OUT
result is shifted out of this output.
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the se-
rial data transfer.
CLK (Pin 7): Shift Clock. This clock synchronizes the se-
rial data transfer.
V (Pin8):PowerSupplyVoltage.Thispinprovidespower
V
(V )(Pin 8): Power Supply and Reference Voltage.
CC
CC REF
totheAꢀDconverter.Itmustbekeptfreeofnoiseandripple
This pin provides power and defines the span of the AꢀD
converter. It must be kept free of noise and ripple by by-
passing directly to the analog ground plane.
by bypassing directly to the analog ground plane.
119698fa
11
LTC1196/LTC1198
BLOCK DIAGRAM
CS
V (V ꢀV
CC CC REF
)
(CSꢀSHUTDOWN) CLK
BIAS AND
SHUTDOWN CIRCUIT
SERIAL PORT
D
OUT
+
IN (CH0)
C
SMPL
–
+
SAR
–
IN (CH1)
HIGH SPEED
COMPARATOR
CAPACITIVE DAC
1196ꢀ98 BD
PIN NAMES IN PARENTHESES
REFER TO THE LTC1198
GND
V (D )
REF IN
TEST CIRCUITS
On and Off Channel Leakage Current
Load Circuit for tdDO, tr and tf
5V
1.4V
I
ON
3k
A
ON CHANNEL
D
TEST POINT
OUT
I
OFF
A
100pF
1196ꢀ98 TC0/
OFF
CHANNEL
•
•
•
•
1196ꢀ98 TC01
POLARITY
Voltage Waveform for DOUT Rise and Fall Times, tr, tf
Voltage Waveform for DOUT Delay Time, tdDO, thDO
V
OH
V
IH
D
CLK
OUT
V
OL
t
dDO
t
hDO
t
r
t
f
1196ꢀ98 TC04
V
OH
D
OUT
V
OL
1196ꢀ98 TC03
119698fa
12
LTC1196/LTC1198
TEST CIRCUITS
Load Circuit for tdis and ten
Voltage Waveforms for tdis
TEST POINT
V
CS
IH
V
t
WAVEFORM /, t
CC dis en
3k
D
OUT
D
OUT
90%
WAVEFORM 1
(SEE NOTE 1)
t
dis
WAVEFORM 1
/0pF
t
dis
1196ꢀ98 TC05
D
OUT
WAVEFORM /
(SEE NOTE /)
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE /: WAVEFORM / IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
1196ꢀ98 TC06
Voltage Waveforms for ten
LTC1196
CS
CLK
/
3
1
4
B7
D
OUT
V
OL
1196ꢀ98 TC07
t
en
Voltage Waveforms for ten
LTC1198
CS
D
IN
START
CLK
5
1
/
3
4
6
7
B7
D
OUT
V
OL
1196ꢀ98 TC08
t
en
119698fa
13
LTC1196/LTC1198
APPLICATIONS INFORMATION
OVERVIEW
with respect to ground or the difference between the two.
It also automatically powers down when not performing
conversion, drawing only leakage current.
The LTC1196ꢀLTC1198 are 600ns sampling 8-bit AꢀD con-
verters packaged in tiny 8-pin SO packages and operating
on 3V to 6V supplies. The ADCs draw only 10mW from a
3V supply or 50mW from a 5V supply.
SERIAL INTERFACE
TheLTC1196ꢀLTC1198willinterfaceviathreeorfourwires
toASICs, PLDs, microprocessors, DSPs, orshiftregisters
(seeOperatingSequenceinFigures1and/).Torunattheir
fastest conversion rates (600ns), they must be clocked at
14.4MHz. HC logic families and any high speed ASIC or
PLD will easily interface to the ADCs at that speed (see
Data Transfer and Typical Application sections). Full speed
operation from a 3V supply can still be achieved with 3V
ASICs, PLDs or HC logic circuits.
Both the LTC1196 and the LTC1198 contain an 8-bit,
switched-capacitor ADC, a sample-and-hold, and a serial
port (see Block Diagram). The on-chip sample-and-holds
have full-accuracy input bandwidths of 1MHz. Although
theysharethesamebasicdesign,theLTC1196andLTC1198
differinsomerespects.TheLTC1196hasadifferentialinput
and has an external reference input pin. It can measure
signals floating on a DC common mode voltage and can
operate with reduced spans below 1V. The LTC1198 has a
/-channelinputmultiplexerandcanconverteitherchannel
t
(1/ CLKs)
CYC
CS
t
suCS
t
dDO
NULL
BITS
B5
(8.5 CLKs)
B4
B3
B1
B6
B/
B0*
B7
B0
NULL BITS
D
OUT
Hi-Z
Hi-Z
t
t
t
SMPL
SMPL
CYC
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
1196ꢀ98 F01
Figure 1. LTC1196 Operating Sequence
t
(16 CLKs)
CYC
CS
POWER
DOWN
t
suCS
CLK
ODDꢀ
SIGN
START
DUMMY
D
DON’T CARE
B4
IN
SGLꢀ
DIFF
DUMMY
t
dDO
Hi-Z
B7
B6
B5
B3
B/
B1
B0*
D
OUT
NULL BITS
HI-Z
t
(/.5 CLKs)
t
(8.5 CLKs)
SMPL
CONV
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
1196ꢀ98 F0/
Figure 2. LTC1198 Operating Sequence Example: Differential Inputs (CH1, CH0)
119698fa
14
LTC1196/LTC1198
APPLICATIONS INFORMATION
the end of the data exchange CS should be brought high.
This resets the LTC1198 in preparation for the next data
exchange.
Connection to a microprocessor or a DSP serial port is
quite simple (see Data Transfer section). It requires no
additional hardware, but the speed will be limited by the
clock rate of the microprocessor or the DSP which limits
the conversion time of the LTC1196ꢀLTC1198.
Input Data Word
The LTC1196 requires no D word. It is permanently con-
IN
Data Transfer
figured to have a single differential input. The conversion
result is output on the D
line in an MSB-first sequence,
Data transfer differs slightly between the LTC1196 and the
OUT
followed by zeros indefinitely if clocks are continuously
LTC1198. The LTC1196 interfaces over 3 lines: CS, CLK
applied with CS low.
and D . A falling CS initiates data transfer as shown
OUT
in the LTC1196 Operating Sequence. After CS falls, the
The LTC1198 clocks data into the D input on the ris-
IN
first CLK pulse enables D . After two null bits, the AꢀD
OUT
ing edge of the clock. The input data word is defined
as follows:
conversion result is output on the D
line. Bringing CS
OUT
high resets the LTC1196 for the next data exchange.
SGLꢀ
DIFF
ODDꢀ
SIGN
DUMMY DUMMY
START
The LTC1198 can transfer data with 3 or 4 wires. The ad-
MUX
ADDRESS
DUMMY
BITS
ditional input, D , is used to select the /-channel MUX
IN
119698 AI0/
configuration.
Start Bit
The data transfer between the LTC1198 and the digital
systemscanbebrokenintotwosections:InputDataWord
and AꢀD Conversion Result. First, each bit of the input data
word is captured on the rising CLK edge by the LTC1198.
The first “logical one” clocked into the D input after CS
IN
goes low is the start bit. The start bit initiates the data
transfer. The LTC1198 will ignore all leading zeros which
precede this logical one. After the start bit is received,
the remaining bits of the input word will be clocked in.
Second, each bit of the AꢀD conversion result on the D
OUT
lineisupdatedontherisingCLKedgebytheLTC1198.This
bit should be captured on the next rising CLK edge by the
digital systems (see AꢀD Conversion Result section).
Further inputs on the D pin are then ignored until the
next CS cycle.
IN
Data transfer is initiated by a falling chip select (CS) signal
as shown in the LTC1198 Operating Sequence. After CS
falls the LTC1198 looks for a start bit. After the start bit
Multiplexer (MUX) Address
The / bits of the input word following the START bit assign
the MUX configuration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following table.
In single-ended mode, all input channels are measured
with respect to GND.
is received, the 4-bit input word is shifted into the D
IN
input. The first two bits of the input word configure the
LTC1198. The last two bits of the input word allow the
ADC to acquire the input voltage by /.5 clocks before the
conversionstarts.Aftertheconversionstarts,twonullbits
and the conversion result are output on the D
line. At
OUT
LTC1198 Channel Selection
CS
MUX ADDRESS
SGL/DIFF ODD/SIGN
CHANNEL #
D
IN1
D
IN/
0
1
GND
1
1
0
0
0
1
0
1
+
–
–
D
D
OUT/
OUT1
SINGLE-ENDED
MUX MODE
+
–
+
SHIFT MUX
ADDRESS IN
+
–
DIFFERENTIAL
MUX MODE
1196ꢀ98 AI03
/ NULL BITS SHIFT AꢀD CONVERSION
RESULT OUT
1196ꢀ98 AI01
119698fa
15
LTC1196/LTC1198
APPLICATIONS INFORMATION
Dummy Bits
Unipolar Output Code
INPUT VOLTAGE
(V = 5.000V)
The last / bits of the input word following the MUX Ad-
dress are dummy bits. Either bit can be a “logical one” or
a “logical zero.” These / bits allow the ADC /.5 clocks to
acquire the input signal after the channel selection.
OUTPUT CODE
INPUT VOLTAGE
REF
4.9805V
1 1 1 1 1 1 1 1
V
V
– 1LSB
REF
REF
4.9609V
1 1 1 1 1 1 1 0
– /LSB
•
•
•
•
•
•
•
•
•
0.0195V
0V
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
1LSB
0V
A/D Conversion Result
1196ꢀ98 AI05
Both the LTC1196 and the LTC1198 have the AꢀD conver-
sion result appear on the D
line after two null bits (see
Operation with D and D
Tied Together
OUT
IN
OUT
Operating Sequence in Figures 1 and /). Data on the D
line is updated on the rising edge of the CLK line. The D
OUT
OUT
The LTC1198 can be operated with D and D
tied
IN
OUT
together. This eliminates one of the lines required to com-
municatetothedigitalsystems.Dataistransmittedinboth
directions on a single wire. The pin of the digital systems
connectedtothisdatalineshouldbeconfigurableaseither
an input or an output. The LTC1198 will take control of the
data line and drive it low on the 5th falling CLK edge after
the start bit is received (see Figure 4). Therefore the port
line of the digital systems must be switched to an input
before this happens to avoid a conflict.
data should also be captured on the rising CLK edge by the
digital systems. Data on the D line remains valid for a
OUT
minimum time of t
(30ns at 5V) to allow the capture
hDO
to occur (see Figure 3).
V
IH
CLK
t
dDO
t
hDO
V
OH
D
OUT
V
OL
REDUCING POWER CONSUMPTION
1196/98 TC03
The LTC1196ꢀLTC1198 can sample at up to a 1MHz rate,
drawingonly50mWfroma5Vsupply.Powerconsumption
can be reduced in two ways. Using a 3V supply lowers the
power consumption on both devices by a factor of five,
to 10mW. The LTC1198 can reduce power even further
because it shuts down whenever it is not converting.
Figure 5 shows the supply current versus sample rate for
the LTC1196 and LTC1198 on 3V and 5V. To achieve such
a low power consumption, especially for the LTC1198,
several things must be taken into consideration.
Figure 3. Voltage Waveform for DOUT Delay Time, tdDO and thDO
Unipolar Transfer Curve
The LTC1196ꢀLTC1198 are permanently configured for
unipolaronly. Theinputspanandcodeassignmentforthis
conversion type are shown in the following figures.
Unipolar Transfer Curve
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0
Shutdown (LTC1198)
•
•
•
Figure / shows the operating sequence of the LTC1198.
The converter draws power when the CS pin is low and
powersitselfdownwhenthatpinishigh. Forlowestpower
consumption in shutdown, the CS pin should be driven
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
V
IN
with CMOS levels (0V to V ) so that the CS input buffer
CC
of the converter will not draw current.
1196ꢀ98 AI04
119698fa
16
LTC1196/LTC1198
APPLICATIONS INFORMATION
DUMMY BITS LATCHED
BY LTC1198
CS
1
/
3
4
5
CLK
DATA (D ꢀD
)
START
SGLꢀDIFF
ODDꢀSIGN
DUMMY
IN OUT
THE DIGITAL SYSTEM CONTROLS DATA LINE
AND SENDS MUX ADDRESS TO LTC1198
LTC1198 CONTROLS DATA LINE AND SENDS
AꢀD RESULT BACK TO THE DIGITAL SYSTEM
THE DIGITAL SYSTEM MUST RELEASE
DATA LINE AFTER 5TH RISING CLK
AND BEFORE THE 5TH FALLING CLK
LTC1198 TAKES CONTROL OF
DATA LINE ON 5TH FALLING CLK
1196ꢀ98 F04
Figure 4. LTC1198 Operation with DIN and DOUT Tied Together
10
Minimize CS Low Time (LTC1198)
LT1198 V = 5V
CC
In systems that have significant time between conver-
sions, lowest power drain will occur with the minimum
CS low time. Bringing CS low, transfering data as quickly
as possible, then bringing it back high will result in the
lowest current drain. This minimizes the amount of time
the device draws power.
1
0.1
LT1196 V = /.87V
CC
LT1198 V = 5V
CC
LT1198 V = /.87V
CC
0.01
OPERATING ON OTHER THAN 5V SUPPLIES
0.001
100
1k
10k
100k
1M
The LTC1196ꢀLTC1198 operate from single /.7V to 6V
supplies. To operate the LTC1196ꢀLTC1198 on other than
5V supplies, a few things must be kept in mind.
SAMPLE RATE (Hz)
1196ꢀ98 F05
Figure 5. Supply Current vs Sample Rate for LTC1196/LTC1198
Operating on 5V and 2.7V Supplies
Input Logic Levels
When the CS pin is high (= supply voltage), the LTC1198
The input logic levels of CS, CLK and D are made to meet
is in shutdown mode and draws only leakage current.
IN
TTLon5Vsupply.Whenthesupplyvoltagevaries,theinput
logic levels also change (see typical curve of Digital Input
Logic Threshold vs Supply Voltage). For these two ADCs
to sample and convert correctly, the digital inputs have
to be in the logical low and high relative to the operating
supply voltage. If achieving micropower consumption is
desirable on the LTC1198, the digital inputs must go rail-
to-rail between supply voltage and ground (see Reducing
Power Consumption section).
The status of the D and CLK input has no effect on the
IN
supply current during this time. There is no need to stop
D
and CLK with CS = high; they can continue to run
IN
without drawing current.
119698fa
17
LTC1196/LTC1198
APPLICATIONS INFORMATION
Clock Frequency
supply is clean, the LTC1196ꢀLTC1198 can also operate
with smaller 0.1μF surface mount or ceramic bypass ca-
pacitors. Allanaloginputsshouldbereferenceddirectlyto
the single-point ground. Digital inputs and outputs should
be shielded from andꢀor routed away from the reference
and analog circuitry.
The maximum recommended clock frequency is 14.4MHz
at /5°C for the LTC1196ꢀLTC1198 running off a 5V supply.
Withthesupplyvoltagechanging, themaximumclockfre-
quency for the devices also changes (see the typical curve
of Maximum Clock Rate vs Supply Voltage). If the supply
is reduced, the clock rate must be reduced also. At 3V the
devices are specified with a 5.4MHz clock at /5°C.
SAMPLE-AND-HOLD
Both the LTC1196 and the LTC1198 provide a built-in
sample-and-hold (S&H) function to acquire the input
signal. The S&H acquires the input signal from “+” input
Mixed Supplies
Itispossibletohaveadigitalsystemrunningoffa5Vsupply
andcommunicatewiththeLTC1196ꢀLTC1198operatingon
during t
as shown in Figures 1 and /. The S&H of the
SMPL
a 3V supply. Achieving this reduces the outputs of D
LTC1198 can sample input signals in either single-ended
or differential mode (see Figure 7).
OUT
from the ADCs to toggle the equivalent input of the digital
system. The CS, CLK and D inputs of the ADCs will take
IN
5V signals from the digital system without causing any
problem(seetypicalcurveofDigitalInputLogicThreshold
vs Supply Voltage). With the LTC1196 operating on a 3V
Single-Ended Inputs
The sample-and-hold of the LTC1198 allows conversion
of rapidly varying signals. The input voltage is sampled
supply, the output of D
This signal easily meets TTL levels (see Figure 6).
only goes between 0V and 3V.
OUT
during the t
time as shown in Figure 7. The sampling
SMPL
interval begins as the bit preceding the first DUMMY bit is
shifted in and continues until the falling CLK edge after the
second DUMMY bit is received. On this falling edge, the
S&H goes into hold mode and the conversion begins.
3V
4.7μF
MPU
(e.g., 8051)
5V
Differential Inputs
V
CS
P1.4
P1.3
P1./
CC
CLK
DIFFERENTIAL INPUTS
+IN
–IN
GND
LTC1196
With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two volt-
ages. In this case, the voltage on the selected “+” input
is still sampled and held and therefore may be rapidly
time varying just as in single-ended mode. However, the
voltage on the selected “–” input must remain constant
and be free of noise and ripple throughout the conversion
time. Otherwise, the differencing operation may not be
performed accurately. The conversion time is 8.5 CLK
cycles. Therefore, a change in the “–” input voltage during
this interval can cause conversion errors. For a sinusoidal
voltage on the “–” input, this error would be:
COMMON MODE RANGE
0V TO 3V
D
OUT
V
3V
REF
1196ꢀ98 F06
Figure 6. Interfacing a 3V Powered LTC1196 to a 5V System
BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
The LTC1196ꢀLTC1198 are easy to use if some care is
taken. They should be used with an analog ground plane
and single-point grounding techniques. The GND pin
should be tied directly to the ground plane.
V
= V
• / • π • f(“–”) • 8.5ꢀfCLK
ERROR(MAX)
PEAK
TheV pinshouldbebypassedtothegroundplanewitha
wheref(“–”)isthefrequencyofthe“–”inputvoltage,V
PEAK
CC
1μF tantalum with leads as short as possible. If the power
is its peak amplitude and f is the frequency of the CLK.
CLK
119698fa
18
LTC1196/LTC1198
APPLICATIONS INFORMATION
SAMPLE
HOLD
“+” INPUT MUST
SETTLE DURING
THIS TIME
CS
t
t
CONV
SMPL
CLK
START
D
IN
SGLꢀDIFF
ODDꢀSIGN
DUMMY
DUMMY
DON’T CARE
B7
D
OUT
1ST BIT TEST “–” INPUT MUST
SETTLE DURING THIS TIME
“+” INPUT
“–” INPUT
1196ꢀ98 F07
Figure 7. LTC1198 “+” and “–” Input Settling Windows
V
isproportionaltof(“–”)andinverselyproportional
“+” Input Settling
ERROR
to f . For a 60Hz signal on the “–” input to generate a
CLK
The input capacitor of the LTC1196 is switched onto “+”
input at the end of the conversion and samples the input
signaluntiltheconversionbegins(seeFigure1). Theinput
capacitoroftheLTC1198isswitchedonto“+”inputduring
the sample phase (t
is /.5 CLK cycles before conversion starts. The voltage on
the “+” input must settle completely within t
LTC1196ꢀLTC1198. Minimizing R
input settling time. If a large “+” input source resistance
must be used, the sample time can be increased by allow-
ing more time between conversions for the LTC1196 or by
using a slower CLK frequency for the LTC1198.
1ꢀ4LSB error (5mV) with the converter running at CLK =
1/MHz, its peak value would have to be 18.7V.
ANALOG INPUTS
, see Figure 7). The sample phase
SMPL
Because of the capacitive redistribution AꢀD conversion
techniquesused,theanaloginputsoftheLTC1196ꢀLTC1198
have one capacitive switching input current spike per
conversion. These current spikes settle quickly and do
notcauseaproblem. However, ifsourceresistanceslarger
than 100Ω are used or if slow settling op amps drive the
inputs, care must be taken to insure that the transients
caused by the current spikes settle completely before the
conversion begins.
for the
SMPL
will improve the
+
SOURCE
119698fa
19
LTC1196/LTC1198
APPLICATIONS INFORMATION
“–” Input Settling
REFERENCE INPUT
At the end of the t
, the input capacitor switches to the
The voltage on the reference input of the LTC1196 defines
the voltage span of the AꢀD converter. The reference input
hastransientcapacitiveswitchingcurrentswhicharedueto
theswitched-capacitorconversiontechnique(seeFigure9).
During each bit test of the conversion (every CLK cycle), a
capacitive current spike will be generated on the reference
pin by the ADC. These high frequency current spikes will
settle quickly and do not cause a problem if the reference
input is bypassed with at least a 0.1μF capacitor.
SMPL
“–”inputandconversionstarts(seeFigures1and7).During
the conversion, the “+” input voltage is effectively “held”
by the sample-and-hold and will not affect the conversion
result.However,itiscriticalthatthe“–”inputvoltagesettle
completelyduringthefirstCLKcycleoftheconversiontime
and be free of noise. Minimizing R
settling time. If a large “–” input source resistance must
be used, the time allowed for settling can be extended by
using a slower CLK frequency.
–
will improve
SOURCE
The reference input can be driven with standard volt-
age references. Bypassing the reference with a 0.1μF
capacitor is recommended to keep the high frequency
impedance low as described above. Some references
require a small resistor in series with the bypass capaci-
tor for frequency stability. See the individual reference
data sheet for details.
Input Op Amps
When driving the analog inputs with an op amp it is im-
portant that the op amp settle within the allowed time (see
Figures 1 and 7). Again, the “+” and “–” input sampling
timescanbeextendedasdescribedabovetoaccommodate
slower op amps.
+
REF
LTC1196
To achieve the full sampling rate, the analog input should
be driven with a low impedance source (<100Ω) or a
high speed op amp (e.g., the LT1//3, LT1191 or LT1//6).
Higher impedance sources or slower op amps can easily
be accommodated by allowing more time for the analog
input to settle as described above.
5
EVERY CLK CYCLE
R
OUT
R
ON
5pF TO
30pF
V
REF
GND
4
1196/98 F09
Figure 9. Reference Input Equivalent Circuit
Source Resistance
Reduced Reference Operation
TheanaloginputsoftheLTC1196ꢀLTC1198looklikea/5pF
The minimum reference voltage of the LTC1198 is limited
capacitor (C ) in series with a 1/0Ω resistor (R ) as
IN
ON
to/.7VbecausetheV supplyandreferenceareinternally
CC
shown in Figure 8. C gets switched between the selected
IN
tied together. However, the LTC1196 can operate with
“+” and “–” inputs once during each conversion cycle.
Large external source resistors will slow the settling of the
inputs. It is important that the overall RC time constants
be short enough to allow the analog inputs to completely
reference voltages below 1V.
The effective resolution of the LTC1196 can be increased
by reducing the input span of the converter. The LTC1196
exhibits good linearity and gain over a wide range of ref-
erence voltages (see typical curves of Linearity and Full-
Scale Error vs Reference Voltage). However, care must be
settle within t
.
SMPL
“+”
+
INPUT
R
SOURCE
+
LTC1196
LTC1198
V
IN
taken when operating at low values of V because of the
lt
REF
SMPL
R
ON
1/0Ω
reduced LSB step size and the resulting higher accuracy
C
“–”
IN
requirementplacedontheconverter.Thefollowingfactors
–
/5pF
INPUT
R
SOURCE
t
n
SMPL
–
must be considered when operating at low V values.
V
IN
REF
1196ꢀ98 F08
1. Offset
/. Noise
Figure 8. Analog Input Equivalent Circuit
119698fa
20
LTC1196/LTC1198
APPLICATIONS INFORMATION
Offset with Reduced V
DYNAMIC PERFORMANCE
REF
The offset of the LTC1196 has a larger effect on the output
code when the ADC is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSB as the size of the
LSB is reduced. The typical curve of Unadjusted Offset
Error vs Reference Voltage shows how offset in LSBs is
The LTC1196ꢀLTC1198 have exceptionally high speed
sampling capability. Fast Fourier Transform (FFT) test
techniques are used to characterize the ADC’s frequency
response, distortion and noise at the rated throughput. By
applyingalowdistortionsinewaveandanalyzingthedigital
output using a FFT algorithm, the ADC’s spectral content
can be examined for frequencies outside the fundamental.
Figure 10 shows a typical LTC1196 FFT plot.
related to reference voltage for a typical value of V . For
OS
example, a V of /mV which is 0.1LSB with a 5V refer-
OS
ence becomes 0.5LSB with a 1V reference and /.5LSB
with a 0./V reference. If this offset is unacceptable, it
can be corrected digitally by the receiving system or by
offsetting the “–” input of the LTC1196.
0
V
= 5V
CC
–10
–/0
–30
–40
–50
–60
–70
–80
–90
–100
f
f
= /9kHz
IN
SMPL
= 88/kHz
Noise with Reduced V
REF
The total input referred noise of the LTC1196 can be
reduced to approximately /mV using a ground plane,
P-P
good bypassing, good layout techniques and minimizing
noise on the reference inputs. This noise is insignificant
with a 5V reference but will become a larger fraction of
an LSB as the size of the LSB is reduced.
0
100
/00
300
400
500
FREQUENCY (kHz)
1196ꢀ98 G/5
For operation with a 5V reference, the /mV noise is only
0.1LSB peak-to-peak. In this case, the LTC1196 noise
will contribute virtually no uncertainty to the output code.
However, for reduced references, the noise may become
a significant fraction of an LSB and cause undesirable jit-
ter in the output code. For example, with a 1V reference,
this same /mV noise is 0.5LSB peak-to-peak. This will
reduce the range of input voltages over which a stable
output code can be achieved by 1LSB. If the reference is
further reduced to /00mV, the /mV noise becomes equal
to /.5LSB and a stable code is difficult to achieve. In this
case averaging readings is necessary.
Figure 10. LTC1196 Non-Averaged, 4096 Point FFT Plot
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio [Sꢀ(N + D)] is
the ratio between the RMS amplitude of the fundamental
inputfrequencytotheRMSamplitudeofallotherfrequency
componentsattheADC’soutput.Theoutputisbandlimited
to frequencies above DC and below one half the sampling
frequency. Figure 10 shows a typical spectral content with
a 88/kHz sampling rate.
Effective Number of Bits
This noise data was taken in a very clean setup. Any setup
The Effective Number of Bits (ENOBs) is a measurement
of the resolution of an ADC and is directly related to
Sꢀ(N + D) by the equation:
induced noise (noise or ripple on V , V
or V ) will
CC REF
IN
add to the internal noise. The lower the reference voltage
to be used, the more critical it becomes to have a clean,
noise-free setup.
N = [Sꢀ(N + D) –1.76]ꢀ6.0/
119698fa
21
LTC1196/LTC1198
APPLICATIONS INFORMATION
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
where N is the effective number of bits of resolution and
Sꢀ(N + D) is expressed in dB. At the maximum sampling
rate of 1./MHz with a 5V supply the LTC1196 maintains
above7.5ENOBsat400kHzinputfrequency.Above500kHz
the ENOBs gradually decline, as shown in Figure 11, due
to increasing second harmonic distortion. The noise floor
remains low.
If two pure sine waves of frequencies f and f are applied
a
b
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at sum and difference
frequencies of mf nf , where m and n = 0, 1, /, 3, etc.
8
7
6
5
4
3
/
1
0
50
44
a
b
V
= V = /.7V
CC
REF
For example, the /nd order IMD terms include (f + f )
a
b
f
f
= 383kHz (LTC1196)
= /87kHz (LTC1198)
SMPL
SMPL
and (f – f ) while 3rd order IMD terms include (/f + f ),
a
b
a
b
V
= V = 5V
CC
REF
(/f – f ), (f + /f ) and (f – /f ). If the two input sine
a
b
a
b
a
b
f
= 1MHz (LTC1196)
SMPL
f
= 750kHz (LTC1198)
waves are equal in magnitudes, the value (in dB) of the
/nd order IMD products can be expressed by the follow-
ing formula:
SMPL
⎡
⎤
⎥
amplitude f
f
b
(
)
a
IMD f f = /0log
⎢
(
)
a
b
amplitude at fa
T
= /5°C
A
⎢
⎣
⎥
⎦
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
For input frequencies of 499kHz and 50/kHz, the IMD of
the LTC1196ꢀLTC1198 is 51dB with a 5V supply.
1196ꢀ98 G/4
Figure 11. Effective Bits and S/(N + D) vs Input Frequency
Peak Harmonic or Spurious Noise
Total Harmonic Distortion
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in dBs relative to the RMS value of a
full-scale input signal.
Total Harmonic Distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half of the sampling frequency. THD
is defined as:
Full-Power and Full-Linear Bandwidth
V// + V3/ + V4/ +...+ VN/
The full-power bandwidth is that input frequency at which
theamplitudeofthereconstructedfundamentalisreduced
by 3dB for a full-scale input.
THD = /0log
V1
where V is the RMS amplitude of the fundamental fre-
1
The full-linear bandwidth is the input frequency at which
the effective bits rating of the ADC falls to 7 bits. Beyond
this frequency, distortion of the sampled input signal
increases. The LTC1196ꢀLTC1198 have been designed to
optimize input bandwidth, allowing the ADCs to unders-
ampleinputsignalswithfrequenciesabovetheconverters’
Nyquist Frequency.
quencyandV throughV aretheamplitudesofthesecond
/
N
through the Nth harmonics. The typical THD specification
in the Dynamic Accuracy table includes the /nd through
5th harmonics. With a 100kHz input signal, the LTC1196ꢀ
LTC1198 have typical THD of 50dB and 49dB with V
5V and V = 3V, respectively.
=
CC
CC
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
119698fa
22
LTC1196/LTC1198
APPLICATIONS INFORMATION
3V VERSUS 5V PERFORMANCE COMPARISON
Table 1. 5V/3V Performance Comparison
LTC1196-1
5V
50mW
3V
10mW
Table 1 shows the performance comparison between 3V
and 5V supplies. The power dissipation drops by a factor
of five when the supply is reduced to 3V. The converter
slowsdownsomewhatbutstillgivesexcellentperformance
on a 3V rail. With a 3V supply, the LTC1196 converts in
1.6μs, samples at 450kHz, and provides a 500kHz linear-
input bandwidth.
P
DISS
Max f
1MHz
383kHz
1.6μs
SMPL
CONV
Min t
600ns
INL (Max)
0.5LSB
7.9 at 300kHz
1MHz
0.5LSB
Typical ENOBs
7.9 at 100kHz
500kHz
Linear Input Bandwidth (ENOBs > 7)
LTC1198-1
Dynamic accuracy is excellent on both 5V and 3V. The
ADCs typically provide 49.3dB of 7.9 ENOBs of dynamic
accuracy at both 3V and 5V. The noise floor is extremely
low,correspondingtoatransitionnoiseoflessthan0.1LSB.
DC accuracy includes 0.5LSB total unadjusted error at
5V. At 3V, linearity error is 0.5LSB while total unadjusted
error increases to 1LSB.
P
P
50mW
15μW
10mW
9μW
DISS
DISS
(Shutdown)
Max f
750kHz
600ns
/87kHz
1.6μs
SMPL
CONV
Min t
INL (Max)
0.5LSB
0.5LSB
Typical ENOBs
7.9 at 300kHz
1MHz
7.9 at 100kHz
500kHz
Linear Input Bandwidth (ENOBs > 7)
TYPICAL APPLICATIONS
PLD Interface Using the Altera EPM5064
goes high for one CLK cycle with every 1/ CLK cycles.
The inverted signal, EN, of the CS output makes the 8-bit
data available on the B0-B7 lines. Figures 13 and 14 show
the interconnection between the LTC1196 and EPM5064
and the timing diagram of the signals between these two
devices. The CLK frequency in this circuit can run up to
The Altera EPM5064 has been chosen to demonstrate the
interface between the LTC1196 and a PLD. The EPM5064
is programmed to be a 1/-bit counter and an equivalent
74HC595 8-bit shift register as shown in Figure 1/. The
circuit works as follows: bringing ENA high makes the CS
output high and the EN input low to reset the LTC1196 and
disable the shift register. Bringing ENA low, the CS output
f
of the LTC1196.
CLK(MAX)
V
CC
CLK
1μF
3, 14, /5, 36
8-BIT
SHIFT REGISTER
1
33
/3
34
35
ENA
EPM5064
CLK
DATA
B7
DATA
DATA
CLK
37
38
39
40
41
4/
44
1
8
7
6
5
CS
V
CC
CLK
EN
B0-B7
B0-B7
/
3
4
+
–
CLK
+IN
LTC1196
CLK
–IN
D
OUT
1/-BIT
CONVERTER
GND
V
REF
B0
ENA
CS
CS
ENA
RESERVE PINS OF EPM5064:
/, 4-8,15-/0, //, /4, /6-30
9-13, /1,
31, 3/, 43
1196ꢀ98 F13
1196ꢀ98 F1/
Figure 12. An Equivalent Circuit of the EPM5064
Figure 13. Interfacing the LTC1196 to the Altera EMP5064 PLD
119698fa
23
LTC1196/LTC1198
TYPICAL APPLICATIONS
DATA
CLK
CS
B7
B6
B5
B4
B3
B/
B1
B0
70 140 /10 /80 350 4/0 490
630
560
TIME (ns)
770 840 910 980 1050 11/0
700
1196ꢀ98 F14
Figure 14. The Timing Diagram
Interfacing the LTC1198 to the TMS320C25 DSP
LTC1198 in Figure 15 can be /.7V to 6V with f = 5MHz.
CLK
At/.7V, f =5MHzwillworkat/5°C. SeeRecommended
CLK
Figure 15 illustrates the interface between the LTC1198
8-bit data acquisition system and the TMS3/0C/5 digital
signal processor (DSP). The interface, which is optimized
forspeedoftransferandminimumprocessorsupervision,
can complete a conversion and shift the data in 4μs with
Operating Conditions for limits over temperature.
Hardware Description
The circuit works as follows: the LTC1198 clock line
controls the AꢀD conversion rate and the data shift rate.
f
= 5MHz. The cycle time, 4μs, of each conversion is
CLK
Data is transferred in a synchronous format over D and
limited by maximum clock frequency of the serial port of
IN
D
OUT
. The serial port of the TMS3/0C/5 is compatible
theTMS3/0C/5whichis5MHz. Thesupplyvoltageforthe
with that of the LTC1198. The data shift clock lines (CLKR,
CLKX) are inputs only. The data shift clock comes from
an external source. Inverting the shift clock is necessary
because the LTC1198 and the TMS3/0C/5 clock the input
data on opposite edges.
5MHz CLK
CLK
CH0
CH1
CLKX
CLKR
FSR
LTC1198
The schematic of Figure 15 is fed by an external clock
source. The signal is fed into the CLK pin of the LTC1198
directly. The signal is inverted with a 74HC04 and then
applied to the data shift clock lines (CLKR, CLKX). The
framing pulse of the TMS3/0C/5 is fed directly to the CS
CS
TMS3/0C/5
FSX
DX
D
IN
DR
D
OUT
1196ꢀ98 F15
of the LTC1198. DX and DR are tied directly to D and
IN
Figure 15. Interfacing the LTC1198 to the TMS320C25 DSP
D
respectively.
OUT
119698fa
24
LTC1196/LTC1198
TYPICAL APPLICATIONS
The timing diagram of Figure 16 was obtained from the
circuit of Figure 15. The CLK was 5MHz for the timing
diagram and the TMS3/0C/5 clock rate was 40MHz.
Figure 17 shows the timing diagram with the LTC1198
running off a /.7V supply and 5MHz CLK.
Software Description
The software configures and controls the serial port of
the TMS3/0C/5.
The code first sets up the interrupt and reset vectors. On
reset the TMS3/0C/5 starts executing code at the label
INIT. Upon completion of a 16-bit data transfer, an inter-
rupt is generated and the DSP will begin executing code
at the label RINT.
CS
CLK
In the beginning, the code initializes registers in the
TMS3/0C/5 that will be used in the transfer routine. The
interruptsaretemporarilydisabled.Thedatamemorypage
pointerregisterissettozero. Theauxiliaryregisterpointer
is loaded with one and auxiliary register one is loaded with
the value /00 hexadecimal. This is the data memory loca-
tion where the data from the LTC1198 will be stored. The
interrupt mask register (IMR) is configured to recognize
the RINT interrupt, which is generated after receiving the
last of 16 bits on the serial port. This interrupt is still dis-
abled at this time. The transmit framing synchronization
pin (FSX) is configured to be an output. The F0 bit of the
status register ST1, is initialized to zero which sets up the
serial port to operate in the 16-bit mode.
D
IN
D
OUT
1196ꢀ98 F16
NULL
BITS
MSB
(B7)
LSB
(B0)
HORIZONTAL: 1500nsꢀDIV
Figure 16. Scope Trace the LTC1198 Running Off
5V Supply in the Circuit of Figure 15
CS
Next, the code in TXRX routine starts to transmit and
receive data. The DIN word is loaded into the ACC and
shifted left eight times so that it appears as in Figure 18.
CLK
ThisD wordconfigurestheLTC1198forCH0withrespect
IN
D
IN
to CH1. The D word is then put in the transmit register
IN
and the RINT interrupt is enabled. The NOP is repeated
3 times to mask out the interrupts and minimize the cycle
time of the conversion to be /0 clock cycles. All clocking
and CS functions are performed by the hardware.
D
OUT
1196ꢀ98 F17
NULL
BITS
MSB
(B7)
LSB
(B0)
B15
0
B8
0
1
0
SꢀD
0
0
1
0
HORIZONTAL: 500nsꢀDIV
START
OꢀS DUMMY DUMMY
L1196ꢀ98 F18
Figure 17. Scope Trace the LTC1198 Running Off
1.7V Supply in the Circuit of Figure 15
Figure 18. DIN Word in ACC of TMS20C25 for the
Circuit in Figure 15
119698fa
25
LTC1196/LTC1198
TYPICAL APPLICATIONS
MSB
LSB
0
Once RINT is generated the code begins execution at
X
X
X
X
X
X
X
X
7
6
5
4
3
/
1
> /00
the label RINT. This code stores the D
word from the
OUT
L1196ꢀ98 F19
LTC1198 in the ACC and then stores it in location /00
hex. The data appears in location /00 hex right-justified
as shown in Figure 19. The code is set up to continually
loop, so at this point the code jumps to label TXRX and
repeats from here.
D
FROM LTC1198 STORED IN TMS3/0C/5 RAM
OUT
Figure 19. Memory Map for the Circuit in Figure 15
LABEL
MNEMONIC
COMMENTS
AORG
B
0
INIT
ON RESET CODE EXECUTION STARTS AT 0
BRANCH TO INITIALIZATION ROUTINE
AORG
B
>/6
RINT
ADDRESS TO RINT INTERRUPT VECTOR
BRANCH TO RINT SERVICE ROUTINE
AORG
DINT
>3/
MAIN PROGRAM STARTS HERE
INIT
DISABLE INTERRUPTS
LDPK
LARP
LRLK
LACK
SACL
STXM
FORT
>0
>1
SET DATA MEMORY PAGE POINTER TO 0
SET AUXILIARY REGISTER POINTER TO 1
SET AUXILIARY REGISTER 1 TO >/00
LOAD IMR CONFIG WORD INTO ACC
STORE IMR CONFIG WORD INTO IMR
CONFIGURE FSX AS AN OUTPUT
SET SERIAL PORT TO 16-BIT MODE
AR1, >/00
>10
>4
0
TXRX
RINT
LACK
SFSM
RPTK
SFL
>44
LOAD LTC1198 D WORD INTO ACC
IN
FSX PULSES GENERATED ON XSR LOAD
REPEAT NEXT INSTRUCTION 8 TIMES
7
SHIFTS D WORD TO RIGHT POSITION
IN
SACL
EINT
>1
PUT D WORD IN TRANSMIT REGISTER
IN
ENABLE INTERRUPT (DISABLE ON RINT)
RPTK
NOP
/
MINIMIZE THE CONVERSION CYCLE TIME
TO BE /0 CLOCK CYCLES
ZALS
SACL
B
>0
*, 0
TXRX
STORE LTC1198 D
WORD IN ACC
OUT
STORE ACC IN LOCATION >/00
BRANCH TO TRANSMIT RECEIVE ROUTINE
END
Figure 20. TMS320C25 Code for the Circuit in Figure 15
119698fa
26
LTC1196/LTC1198
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
.045 .005
NOTE 3
.050 BSC
7
5
8
6
.245
MIN
.160 .005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 .005
TYP
1
3
4
2
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
SO8 0303
119698fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC1196/LTC1198
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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LTC140/
1/-Bit, /./Msps Serial ADC
1/-ꢀ14-Bit, /.8Msps Serial ADCs
1/-ꢀ14-Bit, /.8Msps Serial ADCs
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LTC1403ꢀLTC1403A
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1/-ꢀ14-Bit, 3Msps Simultaneous Sampling ADCs 3V, /-Channel Differential, Unipolar Inputs, 14mW, MSOP Package
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5V, Selectable Spans, 80dB SINAD
LTC141/
5V Supply, /.5V Span, 7/dB SINAD
5V Supply, /.5V Span, 78dB SINAD
5V, Selectable Spans, 7/dB SINAD
LCT1414
LTC14/0
LTC1604
5V Supply, /.5V Span, 90dB SINAD
5V Supply, /.5V Span, 90dB SINAD
5V, Configurable BipolarꢀUnipolar Inputs
5V Supply, 1 and / Channel, 4.3mW, MSOP Package
3.3V Supply, 0V to /.5V Span, MSOP Package
3.3V Supply, 1./5V Span, MSOP Package
LTC1608
LTC1609
LTC1864ꢀLTC1865
LTC/355-1/ꢀ LTC/355-14
LTC/356-1/ꢀLTC/356-14
DACs
LTC1666ꢀLTC1667ꢀLTC1668 1/-ꢀ14-ꢀ16-Bit, 50Msps DACs
87dB SFDR, /0ns Settling Time
LTC159/
16-Bit, Serial SoftSpan™ I
DAC
1LSB INLꢀDNL, Software Selectable Spans
OUT
References
LT1790-/.5
LT1461-/.5
LT1460-/.5
Micropower Series Reference in SOT-/3
Precision Voltage Reference
0.05% Initial Accuracy, 10ppm Drift
0.04% Initial Accuracy, 3ppm Drift
0.1% Initial Accuracy, 10ppm Drift
Micropower Series Voltage Reference
SoftSpan is a trademark of Linear Technology Corporation.
119698fa
LT 0108 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 1993
(408) 43/-1900 FAX: (408) 434-0507 www.linear.com
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