LTC1199LCS8 [Linear]
10-Bit, 500ksps ADCs in MSOP with Auto Shutdown; 10位， 500KSPS的ADC ，采用MSOP与自动关机
| 型号： | LTC1199LCS8 |
| 厂家： | 
Linear |
| 描述： | 10-Bit, 500ksps ADCs in MSOP with Auto Shutdown |
| 文件： | 总28页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1197/LTC1197L
LTC1199/LTC1199L
10-Bit, 500ksps ADCs in
MSOP with Auto Shutdown
U
DESCRIPTIO
EATURE
S
F
The LTC®1197/LTC1197L/LTC1199/LTC1199L are
10-bit A/D converters with sampling rates up to 500kHz.
They have 2.7V (L) and 5V versions and are offered in
8-pin MSOP and SO packages. Power dissipation is typi-
cally only 2.2mW at 2.7V (25mW at 5V) during full speed
operation. The automatic power down reduces supply
current linearly as sample rate is reduced. These 10-bit,
switched-capacitor, successive approximation ADCs in-
clude a sample-and-hold. The LTC1197/LTC1197L have a
differential analog input with an adjustable reference pin.
The LTC1199/LTC1199L offer a software-selectable
2-channel MUX.
■
■
■
■
8-Pin MSOP and SO Packages
10-Bit Resolution at 500ksps
Single Supply: 5V or 3V
Low Power at Full Speed:
25mW Typ at 5V
2.2mW Typ at 2.7V
Auto Shutdown Reduces Power Linearly
at Lower Sample Rates
10-Bit Upgrade to 8-Bit LTC1196/LTC1198
SPI and MICROWIRETM Compatible Serial I/O
Low Cost
■
■
■
■
O U
The 3-wire serial I/O, MSOP and SO-8 packages, 2.7V
operation and extremely high sample rate-to-power ratio
make these ADCs ideal choices for compact, low power
high speed systems.
PPLICATI
A
S
■
■
■
High Speed Data Acquisition
Portable or Compact Instrumentation
Low Power or Battery-Operated Instrumentation
These circuits can be used in ratiometric applications or
with external references. The high impedance analog
inputs and the ability to operate with reduced spans below
1V full scale (LTC1197/LTC1197L) allow direct connec-
tion to signal sources in many applications, eliminating
the need for gain stages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
U
O
TYPICAL APPLICATI
Supply Current vs Sampling Frequency
Single 2.7V Supply, 250ksps, 10-Bit Sampling ADC
10000
1µF
1000
2.7V
V
= 5V
CC
= 7.2MHz
f
CLK
100
10
1
LTC1197L
1
2
3
4
8
7
6
CS
V
CC
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
V
f
= 2.7V
= 3.5MHz
+IN
–IN
GND
CLK
CC
CLK
ANALOG INPUT
0V TO 2.7V RANGE
D
OUT
5
V
REF
1197/99 TA01
0.1
0.01
0.1
1
10
100
1000
SAMPLING FREQUENCY (kHz)
1197/99 G03
1
LTC1197/LTC1197L
LTC1199/LTC1199L
W W W
U
ABSOLUTE AXI U RATI GS
(Notes 1, 2)
Operating Temperature Range
Supply Voltage (VCC) ............................................... 12V
Voltage
LTC1197C/LTC1197LC
LTC1199C/LTC1199LC........................... 0°C to 70°C
LTC1197I/LTC1197LI
LTC1199I/LTC1199LI ........................ –45°C to 85°C
Lead Temperature (Soldering, 10 sec)................. 300°C
Analog Input ..................... GND – 0.3V to VCC + 0.3V
Digital Input ................................ GND – 0.3V to 12V
Digital Output .................... GND – 0.3V to VCC + 0.3V
Power Dissipation.............................................. 500mW
Storage Temperature Range ................. –65°C to 150°C
W
U
/O
PACKAGE RDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
TOP VIEW
NUMBER
TOP VIEW
1
2
3
4
8
7
6
5
CS
+IN
V
CC
LTC1197LCMS8
LTC1197CS8
LTC1197IS8
LTC1197LCS8
LTC1197LIS8
CS
+IN
–IN
1
2
3
4
8 V
CC
CLK
7 CLK
6 D
OUT
REF
–IN
D
OUT
5 V
GND
GND
V
REF
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 210°C/W
S8 PACKAGE
8-LEAD PLASTIC SO
MS8 PART MARKING
LTBL
S8 PART MARKING
TJMAX = 150°C, θJA = 175°C/W
1197
1197L
1197I 1197LI
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
1
2
3
4
8
7
6
5
CS
CH0
CH1
GND
V
CC
LTC1199LCMS8
LTC1199CS8
LTC1199IS8
LTC1199LCS8
LTC1199LIS8
CS
CH0
CH1
GND
1
2
3
4
8 V
CC
CLK
7 CLK
6 D
OUT
IN
D
D
OUT
IN
5 D
MS8 PACKAGE
8-LEAD PLASTIC MSOP
S8 PACKAGE
8-LEAD PLASTIC SO
MS8 PART MARKING
LTCM
S8 PART MARKING
TJMAX = 150°C, θJA = 210°C/W
T
JMAX = 150°C, θJA = 175°C/W
1199
1199I
1199L
1199LI
Consult factory for Military grade parts.
W W U
U
U
U
RECO E DED OPERATI G CO DITIO S
LTC1197
TYP
LTC1199
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
V
Supply Voltage
= 5V Operation
4
9
4
6
V
CC
V
CC
f
t
t
t
Clock Frequency
●
0.05
14
7.2
0.05
16
7.2
MHz
CLK
CLK
ns
CLK
CYC
SMPL
hCS
Total Cycle Time
Analog Input Sampling Time
Hold Time CS Low After Last CLK↑
1.5
13
1.5
13
2
LTC1197/LTC1197L
LTC1199/LTC1199L
W W U
U
U
U
RECO E DED OPERATI G CO DITIO S
LTC1197
TYP
LTC1199
SYMBOL PARAMETER
= 5V Operation
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
V
CC
t
Setup Time CS↓ Before First CLK↑
(See Figures 1, 2)
26
26
ns
suCS
t
t
t
t
t
t
Hold Time D After CLK↑
LTC1199
LTC1199
26
26
ns
ns
hDI
IN
Setup Time D Stable Before CLK↑
suDI
IN
CLK High Time
f
f
= f
= f
40%
40%
32
40%
40%
32
1/f
1/f
WHCLK
WLCLK
WHCS
WLCS
CLK
CLK
CLK(MAX)
CLK(MAX)
CLK
CLK Low Time
CLK
CS High Time Between Data Transfer Cycles
CS Low Time During Data Transfer
ns
13
15
CLK
LTC1197L
TYP
LTC1199L
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
V
Supply Voltage
= 2.7V Operation
2.7
4
2.7
4
V
CC
V
CC
f
t
t
t
t
Clock Frequency
●
0.01
14
3.5
0.01
16
3.5
MHz
CLK
CLK
ns
CLK
CYC
SMPL
hCS
suCS
Total Cycle Time
Analog Input Sampling Time
Hold Time CS Low After Last CLK↑
1.5
40
1.5
40
Setup Time CS↓ Before First CLK↑
(See Figures 1, 2)
78
78
ns
t
t
t
t
t
t
Hold Time D After CLK↑
LTC1199L
LTC1199L
78
78
ns
ns
hDI
IN
Setup Time D Stable Before CLK↑
suDI
IN
CLK High Time
f
f
= f
= f
40%
40%
96
40%
40%
96
1/f
1/f
WHCLK
WLCLK
WHCS
WLCS
CLK
CLK
CLK(MAX)
CLK(MAX)
CLK
CLK Low Time
CLK
CS High Time Between Data Transfer Cycles
CS Low Time During Data Transfer
ns
13
15
CLK
U
U W
CONVERTER AND MULTIPLEXER CHARACTERISTICS
VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1197
TYP
LTC1199
TYP
PARAMETER
CONDITIONS
MIN
MAX
±2
MIN
MAX
±2
UNITS
LSB
LSB
LSB
Bits
V
Offset Error
●
●
●
●
Linearity Error
(Note 3)
±1
±1
Gain Error
±4
±4
No Missing Codes Resolution
Analog Input Range
Reference Input Range
10
10
–0.05V to V + 0.05V
CC
LTC1197, V ≤ 6V
0.2
0.2
V
+ 0.05V
6
V
V
CC
CC
LTC1197, V > 6V
CC
Analog Input Leakage Current
(Note 4)
●
±1
±1
µA
3
LTC1197/LTC1197L
LTC1199/LTC1199L
U
U W
CONVERTER AND MULTIPLEXER CHARACTERISTICS
VCC = 2.7V, VREF = 2.5V (LTC1197L), fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1197L
TYP
LTC1199L
TYP
PARAMETER
CONDITIONS
MIN
MAX
±2
MIN
MAX
±2
UNITS
LSB
LSB
LSB
Bits
V
Offset Error
●
●
●
●
Linearity Error
(Note 3)
±1
±1
Gain Error
±4
±4
No Missing Codes Resolution
Analog Input Range
Reference Input Range
Analog Input Leakage Current
10
10
–0.05V to V + 0.05V
CC
LTC1197L
(Note 4)
0.2
V
CC
+ 0.05V
V
●
±1
±1
µA
U W
DYNAMIC ACCURACY
VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1197
TYP
LTC1199
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
S/(N + D) Signal-to-Noise Plus
Distortion Ratio
100kHz Input Signal
60
60
dB
THD
IMD
Total Harmonic Distortion
First 5 Harmonics
100kHz Input Signal
–64
–68
–64
–68
dB
dB
Peak Harmonic or Spurious Noise
Intermodulation Distortion
100kHz Input Signal
f
= 97.046kHz, f = 102.905kHz
IN2
2nd Order Terms
3rd Order Terms
IN1
–65
–70
–65
–70
dB
dB
VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1197L
TYP
LTC1199L
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
S/(N + D) Signal-to-Noise Plus
Distortion Ratio
50kHz Input Signal
58
58
dB
THD
IMD
Total Harmonic Distortion
First 5 Harmonics
50kHz Input Signal
–60
–63
–60
–63
dB
dB
Peak Harmonic or Spurious Noise
Intermodulation Distortion
50kHz Input Signal
f
= 48.5kHz, f = 51.5kHz
IN2
2nd Order Terms
3rd Order Terms
IN1
–60
–65
–60
–65
dB
dB
4
LTC1197/LTC1197L
LTC1199/LTC1199L
U
DIGITAL ANDDCELECTRICALCHARACTERISTICS
VCC = 5V, VREF = 5V, unless otherwise noted.
LTC1197
LTC1199
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
V
V
IH
V
IL
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 5.25V
= 4.75V
●
●
●
●
2.4
2.4
CC
CC
IN
0.8
2.5
0.8
2.5
V
I
I
= V
µA
µA
IH
IL
CC
= 0V
–2.5
–2.5
IN
V
OH
V
CC
V
CC
= 4.75V, I = 10µA
= 4.75V, I = 360µA
●
●
4.5
2.4
4.74
4.72
4.5
2.4
4.74
4.72
V
V
O
O
V
Low Level Output Voltage
Hi-Z Output Leakage
V
= 4.75V, I = 1.6mA
●
●
0.4
0.4
V
µA
OL
CC
O
I
I
I
I
CS = High
±3
±3
OZ
Output Source Current
Output Sink Current
V
OUT
V
OUT
= 0V
–25
45
–25
45
mA
mA
SOURCE
SINK
= V
CC
Reference Current (LTC1197)
CS = V
●
●
0.001
0.5
3
1
µA
mA
REF
CC
f
= f
SMPL(MAX)
SMPL
I
Supply Current
CS = V
SMPL
●
●
0.001
4.5
3
8
0.001
5
3
8.5
µA
mA
CC
CC
f
= f
SMPL(MAX)
P
D
Power Dissipation
f
= f
SMPL(MAX)
22.5
25
mW
SMPL
VCC = 2.7V, VREF = 2.5V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS
LTC1197L
TYP
LTC1199L
TYP
MIN
MAX
MIN
MAX
UNITS
V
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 3.6V
= 2.7V
●
●
●
●
1.9
1.9
IH
IL
CC
CC
IN
0.45
2.5
0.45
2.5
V
I
I
= V
µA
IH
IL
CC
= 0V
–2.5
–2.5
µA
IN
V
V
V
= 2.7V, I = 10µA
●
●
2.3
2.1
2.60
2.45
2.3
2.1
2.60
2.45
V
V
OH
CC
CC
O
= 2.7V, I = 360µA
O
V
Low Level Output Voltage
Hi-Z Output Leakage
V
= 2.7V, I = 400µA
●
●
0.3
0.3
V
µA
OL
CC
O
I
I
I
I
CS = High
±3
±3
OZ
Output Source Current
Output Sink Current
V
V
= 0V
–6.5
11
–6.5
11
mA
mA
SOURCE
SINK
OUT
OUT
= V
CC
Reference Current (LTC1197L)
CS = V
●
●
0.001
0.250
3.0
0.5
µA
mA
REF
CC
f
= f
SMPL
SMPL(MAX)
I
Supply Current
CS = V
SMPL
●
●
0.001
0.8
3
2
0.001
0.8
3
2
µA
mA
CC
CC
f
= f
SMPL(MAX)
P
Power Dissipation
f
= f
2.2
2.2
mW
D
SMPL
SMPL(MAX)
5
LTC1197/LTC1197L
LTC1199/LTC1199L
AC CHARACTERISTICS
VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1197
TYP
LTC1199
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
µs
t
f
t
Conversion Time (See Figures 1, 2)
Maximum Sampling Frequency
●
●
1.4
1.4
CONV
500
450
kHz
SMPL(MAX)
dDO
Delay Time, CLK↑ to D
Data Valid
C
= 20pF
68
78
100
68
78
100
ns
ns
OUT
LOAD
●
●
●
●
t
t
t
Delay Time, CS↑ to D
Hi-Z
75
40
55
150
68
75
40
55
150
68
ns
ns
ns
dis
en
OUT
Delay Time, CLK↓ to D
Enabled
C
C
= 20pF
= 20pF
OUT
LOAD
LOAD
Time Output Data Remains
Valid After CLK↑
25
25
hDO
t
t
D
D
Rise Time
Fall Time
C
C
= 20pF
= 20pF
●
●
10
10
20
20
10
10
20
20
ns
ns
r
f
OUT
OUT
LOAD
LOAD
C
IN
Input Capacitance
Analog Input On Channel
Analog Input Off Channel
Digital Input
20
5
5
20
5
5
pF
pF
pF
VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1197L
TYP
LTC1199L
TYP
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
µs
t
f
t
Conversion Time (See Figures 1, 2)
Maximum Sampling Frequency
●
●
2.9
2.9
CONV
250
210
kHz
SMPL(MAX)
dDO
Delay Time, CLK↑ to D
Data Valid
C
= 20pF
130
180
250
130
180
250
ns
ns
OUT
LOAD
●
●
●
●
t
t
t
Delay Time, CS↑ to D
Hi-Z
120
100
120
250
200
120
100
120
250
200
ns
ns
ns
dis
en
OUT
Delay Time, CLK↓ to D
Enabled
C
C
= 20pF
= 20pF
OUT
LOAD
LOAD
Time Output Data Remains
Valid After CLK↑
45
45
hDO
t
t
D
D
Rise Time
Fall Time
C
C
= 20pF
= 20pF
●
●
15
15
40
40
15
15
40
40
ns
ns
r
f
OUT
OUT
LOAD
LOAD
C
Input Capacitance
Analog Input On Channel
Analog Input Off Channel
Digital Input
20
5
5
20
5
5
pF
pF
pF
IN
The
●
denotes specifications which apply over the full operating
Note 3: Integral nonlinearity is defined as deviation of a code from a
temperature range.
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 4: Channel leakage current is measured after the channel selection.
Note 2: All voltage values are with respect to GND.
6
LTC1197/LTC1197L
LTC1199/LTC1199L
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current
vs Sampling Frequency
Supply Current vs Clock Rate*
Supply Current vs Supply Voltage
20
18
16
14
10000
16
14
12
10
8
80
70
60
50
40
30
20
10
0
f
= 3.5MHz
CLK
= 25°C
T
A
V
= 9V
CC
1000
100
10
V
= 5V
CC
f
= 7.2MHz
CLK
ACTIVE
MODE
12
10
8
6
4
2
0
6
V
CLK
= 2.7V
= 3.5MHz
CC
f
4
V
= 5V
CC
1
SHUTDOWN
MODE
2
V
= 2.7V
CC
0.1
0
10
100
1000
10000
3
0.01
0.1
1
10
100
1000
0
1
2
4
5
6
7
8
9
FREQUENCY (kHz)
SAMPLING FREQUENCY (kHz)
SUPPLY VOLTAGE (V)
1197/99 G01
1197/99 G03
1197/99 G02
INL Plot
DNL Plot
LTC1197 4096 Point FFT
0
–10
–20
–30
1.0
0.5
1.0
0.5
0
f
f
= 500kHz
V
f
A
= V
= 5V
V
f
A
= V
= 5V
SMPL
= 97.045898kHz
CC
CLK
REF
= 7.2MHz
CC
CLK
REF
= 7.2MHz
IN
T
= 25°C
T
= 25°C
–40
–50
–60
–70
–80
–90
–100
0
–0.5
–0.5
–1.0
–1.0
0
128 256 384 512 640 768 896 1024
CODE
0
128 256 384 512 640 768 896 1024
CODE
0
50
100
150
200
250
FREQUENCY (kHz)
1197/99 G04
1197/99 G26
1197/99 G06
ENOBs vs Frequency
THD vs Frequency
Intermodulation Distortion Plot
10
9
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
f
f
f
= 500kHz
T
A
= 25°C
SMPL
IN1
IN2
= 97.045898kHz
V
SMPL
= 2.7V
= 102.905273kHz
CC
8
f
= 250kHz
V
= 5V
7
CC
f
= 500kHz
SMPL
6
5
V
SMPL
= 2.7V
CC
4
3
2
1
0
f
= 250kHz
–80
–90
V
SMPL
= 5V
CC
f
= 500kHz
–100
–80
1
10
100
1000
10
100
FREQUENCY (kHz)
1000
0
50
100
150
200
250
FREQUENCY (kHz)
FREQUENCY (kHz)
1197/99 G07
1197/99 G08
1197/99 G09
*Part is continuously sampling, spending only a minimum amount of time in shutdown.
7
LTC1197/LTC1197L
LTC1199/LTC1199L
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC1197L Change in Linearity
vs Supply Voltage
LTC1197L Change in Gain Error
vs Supply Voltage
LTC1197L Change in Offset
vs Supply Voltage
2.0
1.5
1.0
0.5
1.0
0.8
1.0
0.8
V
f
= 2.5V
= 3.5MHz
V
f
= 2.5V
= 3.5MHz
V
f
= 2.5V
REF
= 3.5MHz
REF
REF
CLK
CLK
CLK
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.5
–1.0
–1.5
–2.0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
1197/99 G12
1197/99 G10
1197/99 G11
LTC1197 Change in Linearity
vs Supply Voltage
LTC1197 Change in Offset
vs Supply Voltage
LTC1197 Change in Gain Error
vs Supply Voltage
1.0
0.8
2.0
1.5
2.0
1.5
V
f
= 4V
V
f
= 4V
V
f
= 4V
REF
REF
REF
= 7MHz
= 7MHz
= 7MHz
CLK
CLK
CLK
T
= 25°C
T
= 25°C
T
= 25°C
A
A
A
0.6
1.0
1.0
0.4
0.5
0.5
0.2
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
1197/99 G13
1197/99 G15
1197/99 G14
LTC1197 Linearity Error
vs Reference Voltage
LTC1197 Gain Error
vs Reference Voltage
LTC1197 Offset Error
vs Reference Voltage
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
V
f
A
= 5V
V
f
= 5V
V
CLK
= 5V
CC
CC
CLK
CC
= 7.2MHz
= 7.2MHz
f
= 7.2MHz
CLK
T
= 25°C
T
= 25°C
T
= 25°C
A
A
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
1197/99 F16
1197/99 G17
1197/99 F18
8
LTC1197/LTC1197L
LTC1199/LTC1199L
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Linearity vs Temperature
Offset vs Temperature
Gain Error vs Temperature
0.5
0.4
0.3
0.2
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
0
V
V
f
= 5V
= 5V
V
V
f
= 5V
= 5V
CC
REF
CLK
V
V
f
= 5V
= 5V
CC
REF
CLK
CC
REF
CLK
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
= 7.2MHz
= 7.2MHz
= 7.2MHz
–55 –30 –5
20
45
70
95 120
–55 –30 –5
20
45
70
95 120
–55 –30 –5
20
45
70
95 120
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1197/99 G19
1197/99 G20
1197/99 G21
Minimum Clock Frequency for
0.1LSB Error* vs Temperature
Digital Input Threshold
vs Supply Voltage
Input Channel Leakage Current
vs Temperature
100
10
5
4
3
2
1
0
1000
100
10
V
V
= 5V
T
A
= 25°C
V
V
= 5V
REF
= 5V
REF
CC
= 5V
CC
ON CHANNEL
1
OFF CHANNEL
0.1
1
0.01
0.001
0.1
0
25
50
75
100
125
–55 –35 –15
5
25 45 65 85 105 125
0
2
6
8
10
4
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
1197/99 G24
1197/99 G22
1197/99 G23
Maximum Clock Frequency†
vs Source Resistance
Acquisition Time
vs Source Resistance
Maximum Clock Frequency
vs Supply Voltage
11
10
9
10000
1000
100
100
10
1
V
T
= V
= 5V
REF
V
T
= 2.5V
CC
A
V
T
= V = 5V
CC
REF
= 25°C
REF
A
= 25°C
= 25°C
A
8
+
7
R
SOURCE
V
+INPUT
COM
IN
6
5
4
V
+INPUT
–INPUT
IN
3
2
–
R
SOURCE
1
0
0.1
0
1
2
3
4
5
6
7
8
9
10
100
1000
SOURCE RESISTANCE (Ω)
10000
100
1000
SOURCE RESISTANCE (Ω)
10000
SUPPLY VOLTAGE (V)
1197/99 G27
1197/99 G25
1197/99 G26
*As the CLK frequency is decreased from 2MHz, minimum CLK frequency (∆error ≤ 0.1LSB)
represents the frequency at which a 0.1LSB shift in any code translation from its 2MHz value
is first detected.
† Maximum CLK frequency represents the clock frequency at which a 0.1LSB shift in the error
at any code transition from its 3.5MHz value is first detected.
9
LTC1197/LTC1197L
LTC1199/LTC1199L
U
U
U
PI FU CTIO S
DIN (Pin 5): LTC1199/LTC1199L Digital Data Input. The
CS (Pin 1): Chip Select Input. A logic low on this input
enables the LTC1197/LTC1197L/LTC1199/LTC1199L.
Power shutdown is activated when CS is brought high.
A/D configuration word is shifted into this input.
DOUT (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
+IN, CH0 (Pin 2): Analog Input. This input must be free of
noise with respect to GND.
CLK(Pin7):ShiftClock. Thisclocksynchronizestheserial
data transfer.
–IN, CH1 (Pin 3): Analog Input. This input must be free of
noise with respect to GND.
V
CC (Pin 8): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane. For LTC1199/LTC1199L, VREF is
tied internally to this pin.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
VREF (Pin 5): LTC1197/LTC1197L Reference Input. The
reference input defines the span of the A/D converter and
must be kept free of noise with respect to GND.
W
BLOCK DIAGRA
V
CS (D ) CLK
IN
CC
BIAS AND
SHUTDOWN CIRCUIT
SERIAL PORT
D
OUT
+IN (CH0)
–IN (CH1)
C
SMPL
–
+
SAR
MICROPOWER
COMPARATOR
CAPACITIVE DAC
GND
PIN NAMES IN PARENTHESES
REFER TO THE LTC1199/LTC1199L
V
REF
10
LTC1197/LTC1197L
LTC1199/LTC1199L
TEST CIRCUITS
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
Load Circuit for tdDO, tr, tf, tdis and ten
TEST POINT
3k
V
OH
D
OUT
V
OL
V
t
WAVEFORM 2, t
CC dis
en
D
OUT
t
r
t
f
1197/99 TC04
t
WAVEFORM 1
dis
20pF
1197/99 TC01
Voltage Waveforms for DOUT Delay Time, tdDO
Voltage Waveforms for tdis
V
IH
V
IH
CLK
CS
t
dDO
t
D
hDO
OUT
90%
10%
WAVEFORM 1
(SEE NOTE 1)
V
V
OH
OL
D
OUT
t
dis
D
OUT
1197/99 TC02
WAVEFORM 2
(SEE NOTE 2)
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
1197/99 TC05
LTC1197/LTC1197L ten Voltage Waveforms
LTC1199/LTC1199L ten Voltage Waveforms
CS
CS
D
IN
CLK
1
2
3
4
START
CLK
D
1
2
3
4
5
6
OUT
1197/99 TC03
t
en
D
OUT
t
en
1197/99 TC06
11
LTC1197/LTC1197L
LTC1199/LTC1199L
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PPLICATI
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A
OVERVIEW
SERIAL INTERFACE
The LTC1197/LTC1197L/LTC1199/LTC1199L are 10-bit
switched-capacitorA/Dconverters. ThesesamplingADCs
typically draw 5mA of supply current when sampling up to
500kHz (800µA at 2.7V sampling up to 250kHz). Supply
current drops linearly as the sample rate is reduced (see
Supply Current vs Sample Rate in the Typical Perfor-
mance Characteristics). The ADCs automatically power
down when not performing a conversion, drawing only
leakage current. They are packaged in 8-pin MSOP and SO
packages. The LTC1197L/LTC1199L operate on a single
supplyrangingfrom2.7Vto4V. TheLTC1197operateson
a single supply ranging from 4V to 9V while the LTC1199
operates from 4V to 6V.
TheLTC1199/LTC1199Lcommunicatewithmicroproces-
sors and other external circuitry via a synchronous, half
duplex, 4-wire serial interface while the LTC1197/
LTC1197Lusea3-wireinterface(seeOperatingSequence
in Figures 1 and 2). These interfaces are compatible with
bothSPIandMICROWIREprotocolswithoutrequiringany
additional glue logic (see MICROPROCESSOR INTER-
FACES: Motorola SPI).
DATA TRANSFER
TheCLKsynchronizesthedatatransferwitheachbitbeing
transmitted and captured on the rising CLK edge in both
transmitting and receiving systems. The LTC1199/
LTC1199L first receives input data and then transmits
back the A/D conversion result (half duplex). Because of
the half-duplex operation, DIN and DOUT may be tied
together allowing transmission over just three wires: CS,
CLK and DATA (DIN/DOUT).
These ADCs contain a 10-bit, switched-capacitor ADC, a
sample-and-hold and a serial port (see Block Diagram).
Although they share the same basic design, the LTC1197/
LTC1197L and LTC1199/LTC1199L differ in some re-
spects. The LTC1197/LTC1197L have a differential input
and have an external reference input pin. They can mea-
sure signals floating on a DC common mode voltage and
can operate with reduced spans down to 200mV. Reduc-
ing the span allows it to achieve 200µV resolution. The
LTC1199/LTC1199L have a 2-channel input multiplexer
with the reference connected to the supply (VCC) pin. They
can convert the input voltage of either channel with re-
spect to ground or the difference between the voltages of
the two channels.
Datatransferisinitiatedbyafallingchipselect(CS)signal.
AfterCSfallstheLTC1199/LTC1199Llookforastartbiton
the DIN input. After the start bit is received, the 3-bit input
word is shifted into the DIN input which configures the
LTC1199/LTC1199L and starts the conversion. After two
null bits, the result of the conversion is output on the DOUT
line in MSB-first format. At the end of the data exchange
CS should be brought high. This resets the LTC1199/
LTC1199L in preparation for the next data exchange.
Bringing CS high after the conversion also minimizes
supply current if CLK is left running.
t
(14 CLKs )*
CYC
CS
t
suCS
1
2
3
4
5
6
7
8
9
10
11
12
CLK
OUT
13
14
1
t
dDO
HI-Z
t
Hi-Z
NULL
BITS
B9
B8
B7
B6
B5
B4
B3
B1
B0*
B2
D
t
CONV
(10.5 CLKs)
POWER
DOWN
SMPL
(1.5 CLKs)
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT ZEROS INDEFINITELY
1197/99 F01
Figure 1. LTC1197/LTC1197L Operating Sequence
12
LTC1197/LTC1197L
LTC1199/LTC1199L
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PPLICATI
A
S I FOR ATIO
t
(16 CLKs)*
CYC
CS
t
suCS
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
ODD/
SIGN
START
D
DON’T CARE
IN
SGL/
DIFF
DUMMY
t
dDO
t
en
HI-Z
Hi-Z
NULL
BITS
D
OUT
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0*
t
CONV
t
SMPL
POWER
DOWN
(10.5 CLKs)
(1.5 CLKs)
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT ZEROS INDEFINITELY
1197/99 F02
Figure 2. LTC1199/LTC1199L Operating Sequence
The LTC1197/LTC1197L do not require a configuration
input word and have no DIN pin. A falling CS initiates data
transfer as shown in the LTC1197/LTC1197L operating
sequence. After CS falls, the second CLK pulse enables
DOUT. Aftertwonullbits, theA/Dconversionresultisoutput
on the DOUT line in MSB-first format. Bringing CS high
resets the LTC1197/LTC1197L for the next data exchange
and minimizes the supply current if CLK is continuously
running.
transfer and all leading zeros that precede this logical one
will be ignored. After the start bit is received the remaining
bits of the input word will be clocked in. Further inputs on
the DIN pin are then ignored until the next CS cycle.
Multiplexer (MUX) Address
The bits of the input word following the start bit assign the
MUX configuration for the requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+” and
“–” signs in the selected row of the following table. In
single-ended mode, all input channels are measured with
respect to GND. Only the + inputs have sample-and-holds.
Signals applied at the – inputs must not change more than
the required accuracy during the conversion.
INPUT DATA WORD (LTC1199/LTC1199L ONLY)
The LTC1199 4-bit data word is clocked into the DIN input
on the rising edge of the clock after CS goes low and the
start bit has been recognized. Further inputs on the DIN pin
are then ignored until the next CS cycle. The input word is
defined as follows:
Multiplexer Channel Selection
SGL/
DIFF
ODD/
SIGN
START
DUMMY
MUX ADDRESS
SGL/DIFF ODD/SIGN
CHANNEL #
0
1
GND
–
1197/99 AI01
MUX
ADDRESS
1
1
0
0
0
1
0
1
+
+
–
+
–
+
–
Start Bit
1197/99 AI02
The first “logical one” clocked into the DIN input after CS
goes low is the start bit. The start bit initiates the data
13
LTC1197/LTC1197L
LTC1199/LTC1199L
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A
Unipolar Transfer Curve
Dummy Bit
The dummy bit is a placeholder that extends the acquisi-
tion time of the ADC. This bit can be either high or low and
does not affect the conversion of the ADC.
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 0
•
•
•
Operation with DIN and DOUT Tied Together
The LTC1199/LTC1199L can be operated with DIN and
DOUT tied together. This eliminates one of the lines
required to communicate to the microprocessor (MPU).
Data is transmitted in both directions on a single wire. The
processor pin connected to this data line should be
configurableaseitheraninputoranoutput.TheLTC1199/
LTC1199L will take control of the data line and drive it low
on the 4th falling CLK edge after the start bit is received
(see Figure 3). Therefore the processor port line must be
switched to an input before this happens to avoid a
conflict.
0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0
V
IN
1197/99 AI03
Unipolar Output Code
INPUT VOLTAGE
(V = 5.000V)
OUTPUT CODE
INPUT VOLTAGE
REF
4.99512V
1 1 1 1 1 1 1 1 1 1
V
V
– 1LSB
REF
REF
4.99023V
1 1 1 1 1 1 1 1 1 0
– 2LSB
•
•
•
•
•
•
4.88mV
0V
0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0
1LSB
0V
In the Typical Applications section, there is an example of
interfacing the LTC1199/LTC1199L with DIN and DOUT
tied together to the Intel 8051 MPU.
1197/99 AI04
ACHIEVING MICROPOWER PERFORMANCE
Unipolar Transfer Curve
With typical operating currents of 5mA (LTC1197/
LTC1199) at 5V and 0.8mA (LTC1197L/LTC1199L) at
2.7V it is possible for these ADCs to achieve true
micropower performance by taking advantage of the
automatic shutdown between conversions. In systems
TheLTC1197/LTC1197L/LTC1199/LTC1199Lareperma-
nently configured for unipolar only. The input span and
codeassignmentforthisconversiontypeareshowninthe
following figures for a 5V reference.
CS
1
2
3
4
CLK
DATA (D /D
)
START
SGL/DIFF
ODD/SIGN
DUMMY
NULL BITS
B9
B8
IN OUT
MPU CONTROLS DATA LINE AND SENDS
MUX ADDRESS TO LTC1199/LTC1199L
LTC1199/LTC1199L CONTROL DATA LINE
AND SEND A/D RESULT BACK TO MPU
PROCESSOR MUST RELEASE
DATA LINE AFTER 4TH RISING CLK
AND BEFORE THE 4TH FALLING CLK
LTC1199/LTC1199L TAKE CONTROL OF
DATA LINE ON 4TH FALLING CLK
1197/99 F03
Figure 3. LTC1199/LTC1199L Operation with DIN and DOUT Tied Together
14
LTC1197/LTC1197L
LTC1199/LTC1199L
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A
Lower Supply Voltage
that convert continuously, the LTC1197/LTC1197L/
LTC1199/LTC1199Lwilldrawtheirnormaloperatingpower
continuously. Several things must be taken into account
to achieve micropower operation.
For lower supply voltages, LTC offers the LTC1197L/
LTC1199L. These pin compatible devices offer specified
performance to 2.7V supplies.
Shutdown
OPERATING ON OTHER THAN 5V SUPPLIES
Figures 1 and 2 show the operating sequence of the
LTC1197/LTC1197L/LTC1199/LTC1199L. The converter
draws power when the CS pin is low and powers itself
down when that pin is high. If the CS pin is not taken all the
way to ground when it is low and not taken to VCC when it
ishigh, theinputbuffersoftheconverterwilldrawcurrent.
This current may be tens of microamps. It is worthwhile to
bring the CS pin all the way to ground when it is low and
all the way to VCC when it is high to obtain the lowest
supply current.
The LTC1197 operates from 4V to 9V supplies and the
LTC1199operatesfrom4Vto6Vsupplies.TheLTC1197L/
LTC1199L operate from 2.7V to 4V supplies. To use these
parts at other than 5V supplies a few things must be kept
in mind.
Bypassing
At higher supply voltages, bypass capacitors on VCC and
VREF if applicable, need to be increased beyond what is
necessary for 5V. For a 9V supply a 10µF tantalum in
parallel with a 0.1µF ceramic is recommended.
When the CS pin is high (= supply voltage), the converter
is in shutdown mode and draws only leakage current. The
status of the DIN and CLK inputs have no effect on supply
current during this time. There is no need to stop DIN and
CLK with CS = high, except the MPU may benefit.
Input Logic Levels
The input logic levels of CS, CLK and DIN are made to meet
TTL threshold levels on a 5V supply. When the supply
voltage varies, the input logic levels also change. For the
ADC to sample and convert correctly, the digital inputs
have to meet logic low and high levels relative to the
operating supply voltage (see typical curve of Digital Input
Logic Threshold vs Supply Voltage). If achieving mi-
cropower consumption is desirable, the digital inputs
mustgorail-to-railbetweenVCC andground(seeACHIEV-
ING MICROPOWER PERFORMANCE section).
Minimize CS Low Time
In systems that have significant time between conver-
sions, lowest power drain will occur with the minimum CS
low time. Bringing CS low, transferring data as quickly as
possible, and then returning CS high will result in the
lowest possible current drain. This minimizes the amount
of time the device draws power. Even though the device
drawsmorepowerathighclockrates,thenetpowerisless
because the device is on for a shorter time.
Clock Frequency
The maximum recommended clock frequency is 7.2MHz
for the LTC1197/LTC1199 running off a 5V supply and
3.5MHz for the LTC1197L/LTC1199L running off a 2.7V
supply. With the supply voltage changing, the maximum
clock frequency for the devices also changes (see the
typical curve of Maximum Clock Rate vs Supply Voltage).
If the maximum clock frequency is used, care must be
taken to ensure that the device converts correctly.
DOUT Loading
Capacitive loading on the digital output can increase
power consumption. A 100pF capacitor on the DOUT pin
can add 200µA to the supply current at a 7.2MHz clock
frequency. The extra 200µA goes into charging and dis-
chargingtheloadcapacitor.Thesamegoesfordigitallines
drivenatahighfrequencybyanylogic.TheC•V•fcurrents
must be evaluated and the troublesome ones minimized.
15
LTC1197/LTC1197L
LTC1199/LTC1199L
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A
Mixed Supplies
SAMPLE-AND-HOLD
It is possible to have a microprocessor running off a 5V
supply and communicate with the ADC operating on 3V or
9V supplies. The requirement to achieve this is that the
outputs of CS, CLK and DIN from the MPU have to be able
to trip the equivalent inputs of the ADC and the output of
the ADC must be able to toggle the equivalent input of the
MPU (see typical curve of Digital Input Logic Threshold vs
Supply Voltage). With the LTC1197 operating on a 9V
supply,theoutputofDOUT maygobetween0Vand9V.The
9V output may damage the MPU running off a 5V supply.
The way to solve this problem is to have a resistor divider
on DOUT (Figure 4) and connect the center point to the
MPUinput.Itshouldbenotedthattogetfullshutdown,the
CSinputoftheADCmustbedriventotheVCC voltage. This
would require adding a level shift circuit to the CS signal
in Figure 4.
The LTC1197/LTC1197L/LTC1199/LTC1199L provide a
built-in sample-and-hold (S/H) function to acquire sig-
nals. The S/H of the LTC1197/LTC1197L acquires input
signals for the “+” input relative to the “–” input during the
t
SMPL time(seeFigure1).HowevertheS/HoftheLTC1199/
LTC1199L can sample input signals from the “+” input
relativetogroundandfromthe“–”inputrelativetoground
in addition to acquiring signals from the “+” input relative
to the “–” input (see Figure 5) during tSMPL
.
Single-Ended Inputs
The sample-and-hold of the LTC1199/LTC1199L allows
conversion of rapidly varying signals. The input voltage is
sampled during the tSMPL time as shown in Figure 5. The
sampling interval begins as the ODD/SGN bit is shifted in
and continues until the falling CLK edge after the dummy
bit is received. On this falling edge, the S/H goes into hold
mode and the conversion begins.
9V
OPTIONAL
LEVEL SHIFT
Differential Inputs
4.7µF
9V
With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two volt-
ages. In this case, the voltage on the selected “+” input is
still sampled and held and therefore may be rapidly time
varying just as in single-ended mode. However, the volt-
age onthe selected “–”inputmust remain constant andbe
free of noise and ripple throughout the conversion time.
Otherwise, the differencing operation may not be per-
formedaccurately.Theconversiontimeis10.5CLKcycles.
Therefore, a change in the “–” input voltage during this
interval can cause conversion errors. For a sinusoidal
voltage on the “–” input this error would be:
MPU
5V
(e.g. 8051)
CS
V
P1.4
CC
DIFFERENTIAL INPUTS
+IN
–IN
GND
CLK
P1.3
P1.2
4.7k
6V
COMMON MODE RANGE
0V TO 6V
D
OUT
V
REF
4.7k
LTC1197
1197/99 F04
Figure 4. Interfacing a 9V-Powered LTC1197 to a 5V System
BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
VERROR (MAX) = VPEAK • 2 • π • f(“–”) • 10.5/fCLK
Where f(“–”) is the frequency of the “–” input voltage,
VPEAK is its peak amplitude and fCLK is the frequency of the
CLK. In most cases VERROR will not be significant. For a
60Hz signal on the “–” input to generate a 1/4LSB error
(1.22mV) with the converter running at CLK = 7.2MHz, its
peak value would have to be 2.22V.
The LTC1197/LTC1197L/LTC1199/LTC1199L should be
usedwithananaloggroundplaneandsinglepointground-
ing techniques. The GND pin should be tied directly to the
ground plane. The VCC pin should be bypassed to the
ground plane using a 1µF tantalum capacitor with leads as
short as possible. All analog inputs should be referenced
directly to the single point ground. Digital inputs and
outputs should be shielded from and/or routed away from
the reference and analog circuitry.
16
LTC1197/LTC1197L
LTC1199/LTC1199L
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PPLICATI
A
S
I FOR ATIO
SAMPLE
HOLD
“+” INPUT MUST
SETTLE DURING
THIS TIME
CS
t
t
CONV
SMPL
CLK
D
START
SGL/DIFF
ODD/SGN
DUMMY
DON‘T CARE
IN
D
OUT
1ST BIT TEST “–” INPUT MUST
SETTLE DURING THIS TIME
“+” INPUT
“–” INPUT
1197/99 F05
Figure 5. LTC1199/LTC1199L “+” and “–” Input Settling Windows
“+”
ANALOG INPUTS
+
INPUT
R
SOURCE
+
–
LTC1197/LTC1197L
LTC1199/LTC1199L
= 200Ω
V
IN
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1197/
LTC1197L/LTC1199/LTC1199Lhavecapacitiveswitching
input current spikes. These current spikes settle quickly
and do not cause a problem if source resistances are less
than 200Ω or high speed op amps are used (e.g., the
LT®1224, LT1191, LT1226 or LT1215). However, if large
source resistances are used or if slow settling op amps
drive the inputs, take care to ensure that the transients
caused by the current spikes settle completely before the
conversion begins.
C1
R
ON
“–”
INPUT
C
IN
= 20pF
–
R
SOURCE
V
IN
C2
1197/99 F06
Figure 6. Analog Equivalent Circuit
input must settle completely within tSMPL for the ADC to
perform an accurate conversion. Minimizing RSOURCE
+
and C1 will improve the input settling time (see Figure 6).
If a large “+” input source resistance must be used, the
sample time can be increased by using a slower CLK
frequency.
“+” Input Settling
TheinputcapacitoroftheLTC1197/LTC1197Lisswitched
onto the “+” input in the falling edge of CS and the sample
time continues until the second falling CLK edge (see
Figure 1). However, the input capacitor of the LTC1199/
LTC1199L is switched onto “+” input after ODD/SGN is
clocked into the ADC and remains there until the fourth
fallingCLKedge(seeFigure5).Thesampletimeis1.5CLK
cycles before conversion starts. The voltage on the “+”
“–” Input Settling
At the end of tSMPL, the input capacitor switches to the
“–” input and conversion starts (see Figures 1 and 5).
During the conversion the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
17
LTC1197/LTC1197L
LTC1199/LTC1199L
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PPLICATI
S I FOR ATIO
A
across the resistor. The magnitude of the DC current is
approximately IDC = 20pF(VIN/tCYC) and is roughly pro-
portional to VIN. When running at the minimum cycle time
of 2µs, the input current equals 50µA at VIN = 5V. In this
case a filter resistor of 10Ω will cause 0.1LSB of full-scale
error. If a larger filter resistor must be used, errors can be
eliminated by increasing the cycle time.
conversion result. However, it is critical that the “–” input
voltage settles completely during the first CLK cycle of the
–
conversiontimeandbefreeofnoise.MinimizingRSOURCE
and C2 will improve settling time (see Figure 6). If a large
“–”inputsourceresistancemustbeused,thetimeallowed
for settling can be extended by using a slower CLK
frequency.
Input Leakage Current
Input Op Amps
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum
inputleakagespecificationof1µA(at85°C)flowingthrough
a source resistance of 1k will cause a voltage drop of 1mV
or 0.2LSB. This error will be much reduced at lower
temperatures because leakage drops rapidly (see typical
curve of Input Channel Leakage Current vs Temperature).
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(seeFigure5). Again, the“+”and“–”inputsamplingtimes
can be extended as described above to accommodate
slower op amps. Highspeed opampssuchas theLT1224,
LT1191,LT1226orLT1215canbemadetosettlewelleven
with the minimum settling window of 200ns which occurs
at the maximum clock rate of 7.2MHz.
REFERENCE INPUTS
Source Resistance
The voltage on the reference input of the LTC1197/
LTC1197L defines the voltage span of the A/D converter.
The reference input transient capacitive switching cur-
rents are due to the switched-capacitor conversion tech-
nique used in these ADCs (see Figure 8). During each bit
test of the conversion (every CLK cycle), a capacitive
current spike will be generated on the reference pin by the
ADC. These current spikes settle quickly and do not cause
a problem.
The analog inputs of the LTC1197/LTC1197L/LTC1199/
LTC1199L look like a 20pF capacitor (CIN) in series with a
200Ω resistor (RON) as shown in Figure 6. CIN gets
switched between the selected “+” and “–” inputs once
duringeachconversioncycle.Largeexternalsourceresis-
tors and capacitors will slow the settling of the inputs. It is
important that the overall RC time constants be short
enough to allow the analog inputs to completely settle
within the allowed time.
Reduced Reference Operation
RC Input Filtering
The minimum reference voltage of the LTC1199 is 4V and
the minimum reference voltage of the LTC1199L is 2.7V
because the VCC supply and reference are internally tied
together. However, the LTC1197/LTC1197L can operate
with reference voltages below 1V.
It is possible to filter the inputs with an RC network as
shown in Figure 7. For large values of CF (e.g., 1µF), the
capacitive input switching currents are averaged into a net
DC current. Therefore, a filter should be chosen with a
small resistor and large capacitor to prevent DC drops
REF
5
I
DC
LTC1197
R
FILTER
V
“
“
+”
EVERY CLK CYCLE
IN
R
R
OUT
ON
LTC1199
C
F
V
5pF TO 25pF
REF
GND
4
–”
1197/99 F07
1197/99 F08
Figure 7. RC Input Filtering
Figure 8. Reference Input Equivalent Circuit
18
LTC1197/LTC1197L
LTC1199/LTC1199L
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PPLICATI
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LTC1197L noise will contribute virtually no uncertainty
to the output code. However, for reduced references, the
noise may become a significant fraction of an LSB and
cause undesirable jitter in the output code. For example,
with a 1V reference, this same 200µV noise is 0.2LSB
peak-to-peak. This will reduce the range of input volt-
ages over which a stable output code can be achieved. If
the reference is further reduced to 200mV, the 200µV of
noise becomes equal to 1LSB and a stable code may be
difficult to achieve. In this case averaging readings may
be necessary.
The effective resolution of the LTC1197/LTC1197L can be
increased by reducing the input span of the converter. The
LTC1197/LTC1197L exhibits good linearity and gain over
a wide range of reference voltages (see typical curves of
LinearityandFull-ScaleErrorvsReferenceVoltage). How-
ever, care must be taken when operating at low values of
VREF because of the reduced LSB step size and the
resulting higher accuracy requirement placed on the con-
verter. The following factors must be considered when
operating at low VREF values.
1. Offset
2. Noise
This noise data was taken in a very clean setup. Any setup-
induced noise (noise or ripple on VCC, VREF or VIN) will add
to the internal noise. The lower the reference voltage to be
used, the more critical it becomes to have a clean, noise-
free setup.
3. Conversion speed (CLK frequency)
Offset with Reduced VREF
TheoffsetoftheLTC1197/LTC1197Lhasalargereffecton
the output code when the ADC is operated with reduced
reference voltage. The offset (which is typically a fixed
voltage) becomes a larger fraction of an LSB as the size of
the LSB is reduced. The typical curve of LTC1197 Offset
Error vs Reference Voltage shows how offset in LSBs is
related to reference voltage for a typical value of VOS. For
example,aVOS of1mVwhichis0.2LSBwitha5Vreference
becomes 1LSB with a 1V reference and 5LSBs with a 0.2V
reference. If this offset is unacceptable, it can be corrected
digitally by the receiving system or by offsetting the “–”
input of the LTC1197/LTC1197L.
Conversion Speed with Reduced VREF
With reduced reference voltages the LSB step size is
reduced and the LTC1197/LTC1197L internal comparator
overdrive is reduced. Therefore, it may be necessary to
reduce the maximum CLK frequency when low values of
VREF are used.
Input Divider
It is OK to use an input divider on the reference input of the
LTC1197/LTC1197L as long as the reference input can be
made to settle within the bit time at which the clock is
running. When using a larger value resistor divider on the
reference input the “–” input should be matched with an
equivalent resistance.
Noise with Reduced VREF
The total input referred noise of the LTC1197/LTC1197L
can be reduced to approximately 200µV peak-to-peak
using a ground plane, good bypassing, good layout tech-
niques and minimizing noise on the reference inputs. This
noise is insignificant with a 5V reference but will become
alargerfractionofanLSBasthesizeoftheLSBisreduced.
Bypassing Reference Input with Divider
Bypassing the reference input with a divider is also pos-
sible. However, care must be taken to make sure that the
DC voltage on the reference input will not drop too much
below the intended reference voltage.
For operation with a 5V reference, the 200µV noise is
only 0.04LSB peak-to-peak. In this case, the LTC1197/
19
LTC1197/LTC1197L
LTC1199/LTC1199L
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S I FOR ATIO
A
Signal-to-Noise Ratio
Effective Number of Bits
T
he signal-to-noise ratio (SNR) is the ratio between the
The effective number of bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
RMS amplitude of the fundamental input frequency to
the RMS amplitude of all other frequency components at
the A/D output. This includes distortion as well as noise
products and for this reason it is sometimes referred to
as signal-to-noise + distortion [S/(N + D)]. The output is
band limited to frequencies from DC to one half the
sampling frequency. Figure 9 shows spectral content
from DC to 250kHz which is 1/2 the 500kHz sampling
rate.
ENOB = [S/(N + D) –1.76]/6.02
where S/(N + D) is expressed in dB. At the maximum
sampling rate of 500kHz the LTC1197 maintains 9.5
ENOBs or better to 200kHz. Above 200kHz the ENOBs
graduallydecline, asshowninFigure10, duetoincreasing
second harmonic distortion. The noise floor remains
approximately 100dB.
0
–10
–20
–30
f
f
= 500kHz
SMPL
= 97.045898kHz
IN
–40
–50
–60
–70
–80
–90
–100
0
50
100
150
200
250
FREQUENCY (kHz)
1197/99 G06
Figure 9. This Clean FFT of a 97kHz Input Shows Remarkable
Performance for an ADC Sampling at the 500kHz Rate
10
9
V
SMPL
= 2.7V
CC
8
7
f
= 250kHz
V
= 5V
CC
f
= 500kHz
SMPL
6
5
4
3
2
1
0
1
10
100
1000
FREQUENCY (kHz)
1197/99 G07
Figure 10. Dynamic Accuracy is Maintained
Up to an Input Frequency of 200kHz for the
LTC1197 and 50kHz for the LTC1197L
20
LTC1197/LTC1197L
LTC1199/LTC1199L
U
O
TYPICAL APPLICATI S
MICROPROCESSOR INTERFACES
Motorola SPI (MC68HC05C4, MC68HC11)
The MC68HC05C4 has been chosen as an example of an
MPU with a dedicated serial port. This MPU transfers data
MSB-first and in 8-bit increments. With two 8-bit trans-
fers, the A/D result is read into the MPU. The first 8-bit
transfersendstheDIN wordtotheLTC1199andclocksthe
two ADC MSBs (B9 and B8) into the MPU. The second 8-
bit transfer clocks the next 8 bits, B7 through B0, of the
ADC into the MPU.
The LTC1197/LTC1197L/LTC1199/LTC1199L can inter-
face directly (without external hardware to most popular
microprocessor (MPU) synchronous serial formats (see
Table 1). If an MPU without a dedicated serial port is used,
then three or four of the MPU’s parallel port lines can be
programmed to form the serial link. Included here is one
serial interface example and one example showing a
parallel port programmed to form the serial interface.
ANDing the first MPU received byte with 03Hex clears the
six MSBs. Notice how the position of the start bit in the DIN
word is used to position the A/D result so that it is right-
justified in two memory locations.
Table 1. Microprocessor with Hardware Serial Interfaces
Compatible with the LTC1197/LTC1197L/LTC1199/LTC1199L
PART NUMBER
Motorola
TYPE OF INTERFACE
MC6805S2,S3
MC68HC11
MC68HC05
SPI
SPI
SPI
RCA
CDP68HC05
Hitachi
SPI
HD6301
HD6303
HD6305
HD63701
HD63705
HD64180
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
CSI/O
National Semiconductor
COP400 Family
COP800 Family
NSC8050U
MICROWIRETM
MICROWIRE/PLUSTM
MICROWIRE/PLUS
MICROWIRE/PLUS
HPC16000 Family
Texas Instruments
TMS7000 Family
TMS320 Family
Serial Port
Serial Port
Microchip Technology
PIC16C60 Family
PIC16C70 Family
SPI, SCI Synchronous
SPI, SCI Synchronous
MICROWIRE and MICROWIRE/PLUS are trademarks of
National Semiconductor Corp.
21
LTC1197/LTC1197L
LTC1199/LTC1199L
U
O
TYPICAL APPLICATI S
Data Exchange Between LTC1199 and MC68HC05C4
START
BIT
BYTE 1
BYTE 2 (DUMMY)
MPU TRANSMIT
WORD
SGL/ ODD/
DIFF SIGN
1
X
X
X
X
X
X
X
X
X
X
X
X
DUMMY
X = DON‘T CARE
CS
START
DUMMY
SGL/
DIFF
ODD/
SIGN
D
IN
DON‘T CARE
CLK
D
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
OUT
MPU RECEIVED
WORD
B7
B6
B5
B4
B3
B2
B1
B0
?
?
?
?
0
0
B9
B8
1ST TRANSFER
2ND TRANSFER
1197/99 TA03
Hardware and Software Interface to Motorola MC68HC05C4
LABEL
MNEMONIC
COMMENTS
Bit 0 Port C goes low (CS goes low)
Load LTC1199 D word into ACC
START
BCLRn
LDA
STA
IN
C0
CS
Load LTC1199 D word into SPI from ACC
IN
Transfer begins
SCK
MC68HC05C4
MISO
CLK
ANALOG
INPUTS
TST
BPL
Test status of SPIF
Loop to previous instruction if not done
with transfer
LTC1199
D
IN
D
MOSI
LDA
Load contents of SPI data register
OUT
into ACC (D
MSBs)
OUT
1197/99 TA04
STA
AND
STA
TST
BPL
Start next SPI cycle
Clear 6 MSBs of the first D
Store in memory location A (MSBs)
Test status of SPIF
Loop to previous instruction if not done
with transfer
word
OUT
DOUT from LTC1199 Stored in MC68HC05C4
BSETn
LDA
Set B0 of Port C (CS goes high)
Load contents of SPI data register into
MSB
LOCATION A
0
0
0
0
0
0
B9
B8
BYTE 1
BYTE 2
ACC. (D
LSBs)
OUT
LSB
STA
Store in memory location A + 1 (LSBs)
LOCATION A + 1
B7
B6
B5
B4
B3
B2
B1
B0
1197/99 TA05
22
LTC1197/LTC1197L
LTC1199/LTC1199L
U
O
TYPICAL APPLICATI S
Interfacing to the Parallel Port of the
Intel 8051 Family
LABEL
MNEMONIC
OPERAND
COMMENTS
word for LTC1199
Make sure CS is high
CS goes low
MOV
SETB
CLR
MOV
RLC
CLR
MOV
SETB
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ
MOV
MOV
SETB
CLR
A, #FFH
P1.4
P1.4
R4, #04
A
P1.3
P1.2, C
P1.3
R4, LOOP 1
P1, #04
P1.3
R4, #0AH
C, P1.2
A
D
IN
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1199 and parallel port micro-
processors. Normally the CS, CLK and DIN signals would
be generated on three port lines and the DOUT signal read
on a fourth port line. This works very well. However, we
will demonstrate here an interface with the DIN and DOUT
of the LTC1199 tied together as described in the
SERIAL INTERFACE section. This saves one wire.
Load counter
LOOP 1
Rotate D bit into Carry
IN
CLK goes low
Output D bit into Carry
IN
CLK goes high
Next bit
Bit 2 becomes an input
CLK goes low
Load counter
Read data bit into Carry
Rotate data bit into ACC
CLK goes high
CLK goes low
Next bit
LOOP
The 8051 first sends the start bit and MUX address to the
LTC1199 over the data line connected to P1.2. Then P1.2
is reconfigured as an input (by writing to it a one) and
the 8051 reads back the 8-bit A/D result over the same
data line.
P1.3
P1.3
R4, LOOP
R2, A
C, P1.2
P1.3
Store MSBs in R2
Read data bit into Carry
CLK goes high
P1.3
CLK goes low
CLR
RLC
A
A
Clear ACC
Rotate data bit from Carry to
ACC
CS
CLK
P1.4
P1.3
P1.2
ANALOG
INPUTS
MOV
RRC
RRC
MOV
SETB
C, P1.2
A
Read data bit into Carry
Rotate right into ACC
Rotate right into ACC
Store LSBs in R3
CS goes high
LTC1199
8051
D
OUT
D
IN
A
MUX ADDRESS
A/D RESULT
R3, A
P1.4
1197/99 TA06
DOUT from LTC1199 Stored in 8051 RAM
MSB
R2 B9
B8
B7
0
B6
0
B5
0
B4
0
B3
0
B2
LSB
B0
R3 B1
0
1197/99 TA07
CS
1
2
3
4
CLK
)
SGL/
DIFF
ODD/
SIGN
DATA (D /D
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
START
DUMMY
IN OUT
1197/99 TA08
8051 P1.2 OUTPUTS DATA
TO LTC1199
LTC1199 SENDS A/D RESULT
BACK TO 8051 P1.2
8051 P1.2 RECONFIGURED
AS AN INPUT AFTER THE 4TH RISING
CLK AND BEFORE THE 4TH FALLING CLK
LTC1199 TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK
23
LTC1197/LTC1197L
LTC1199/LTC1199L
U
O
TYPICAL APPLICATI S
A “Quick Look” Circuit for the LTC1197
oscilloscope that is set up to trigger on the falling edge
of CS (Figure 12). Note that after the LSB is clocked out,
the LTC1197 clocks out zeros until CS goes high. Also
note that with the resistor divider on DOUT the output
goes midway between VCC and ground when in the high
impedance mode.
Users can get a quick look at the function and timing of
theLTC1197byusingthefollowingsimplecircuit(Figure
11). VREF is tied to VCC. VIN is applied to the+IN input and
the –IN input is tied to the ground. CS is driven at 1/16
theclockratebythe74HC161andDOUT outputsthedata.
The output data from the DOUT pin can be viewed on an
5V
1µF
+
10k
CLR
CLK
A
V
5V
CC
RC
CS
V
CC
QA
QB
QC
QD
T
V
+IN
–IN
GND
CLK
B
C
IN
74HC161
LTC1197
D
D
P
GND
OUT
V
REF
LOAD
10k
CLK IN 7.2MHz MAX
D
CLK CS
OUT
TO OSCILLOSCOPE
1197/99 F11
Figure 11. “Quick Look” Circuit for the LTC1197
CS
CLK
DOUT
HIGH
IMPEDANCE
2 NULL MSB
BITS (B9)
LSB
FILL
(B0) ZEROES
VERTICAL: 5V/DIV
HORIZONTAL: 10µs/DIV
Figure 12. Scope Photo of the LTC1197 “Quick Look” Circuit
Waveforms Showing A/D Output 1001001001 (249HEX
)
24
LTC1197/LTC1197L
LTC1199/LTC1199L
U
O
TYPICAL APPLICATI S
Resistive Touchscreen Interface
interface. RC combinations R1C1, R2C2 and R3C3 form
lowpass filters that attenuate noise from possible sources
such as the processor clock, switching power supplies
and bus signals. The 74HC14 inverter is used to detect
screen contact both during a conversion sequence and to
trigger its start. Using the single channel LTC1197, 5-wire
resistive touchscreens are as easily accommodated.
Figure 13 shows the LTC1199 in a 4-wire resistive touch-
screen application. Transistor pairs Q1-Q3, Q2-Q4 apply
5V and ground to the X axis and Y axis, respectively. The
LTC1199, with its 2-channel multiplexer, digitizes the
voltage generated by each axis and transmits the conver-
sion results to the system’s processor through a serial
5V
R7
100k
R6
4.7k
Q2
2N2907
C5
1000pF
R3
10Ω
R7
100k
+
–
C6
Y
X
Q1
2N2907
+
1000pF
C3
10µF
R8
R9
100k
4.7k
R6
4.7k
C4
Q3
2N2222A
1000pF
LTC1199
V
1
2
3
4
8
7
6
5
C1
R1
CS
CC
1µF
100Ω
CLK
CH0
CH1
GND
D
OUT
R10
4.7k
C7
1000pF
C2
1µF
R2
R12
100k
D
Q4
2N2222A
–
+
IN
100Ω
Y
X
R11
100k
74HC14
TOUCH SENSE
CHIP SELECT
SERIAL CLK
DATA IN
DATA OUT
1197/99 F13
Figure 13. The LTC1199 Digitizes Resistive Touchscreen X and Y Axis Voltages. The ADC’s Auto Shutdown Feature
Helps Maximize Battery Life in Portable Touchscreen Equipment
25
LTC1197/LTC1197L
LTC1199/LTC1199L
U
O
TYPICAL APPLICATI S
Battery Current Monitor
by the LTC1152. The LTC1197L digitizes the amplifier
output and sends it to the microprocessor in serial
format. After each sample the LTC1197L automatically
powers down. The LT1004 provides the full-scale refer-
ence for the ADC. The circuit’s 45µA supply current is
dominated by the reference and the op amp. The circuit
can be located near the battery and data transmitted
serially to the microprocessor.
The LTC1197L/LTC1199L are ideal for 3V systems. Fig-
ure 14 shows a 2.7V to 4V battery current monitor that
draws only 45µA at 3V from the battery it monitors,
sampling at a 1Hz rate. To minimize supply current, the
microprocessor uses the LTC1152 SHDN pin to turn on
the op amp prior to making a measurement and then turn
it off after the measurement has been made. The battery
current is sensed with the 0.005Ω resistor and amplified
500pF
+
2.7V
TO 4V
1µF
240k
56k
TO µP
L
O
A
D
LTC1197L
2k
–
1
2
3
4
8
7
6
5
CS
V
CC
0.005Ω
2A FULL
SCALE
SHDN
LTC1152
100Ω
1µF
+IN
–IN
GND
CLK
+
D
OUT
V
REF
LT1004-1.2
0.1µF
Figure 14. This 0A to 2A Battery Current Monitor Draws Only 45µA from a 3V Battery
26
LTC1197/LTC1197L
LTC1199/LTC1199L
U
Dimensions in inches (millimeters), unless otherwise noted.
PACKAGE DESCRIPTIO
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.10)
8
7
6
5
0.118 ± 0.004**
(3.00 ± 0.10)
0.192 ± 0.004
(4.88 ± 0.10)
1
0.040 ± 0.006
2
3
4
0.006 ± 0.004
(0.15 ± 0.10)
(1.02 ± 0.15)
0.007
(0.18)
0° – 6° TYP
SEATING
PLANE
0.021 ± 0.004
(0.53 ± 0.01)
0.012
(0.30)
0.025
(0.65)
TYP
*
DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
MSOP08 0596
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
3
4
2
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
SO8 0996
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC1197/LTC1197L
LTC1199/LTC1199L
RELATED PARTS
PART NUMBER
SAMPLE RATE
POWER DISSIPATION
DESCRIPTION
8-Bit, Pin Compatible Serial Output ADCs
LTC1096/LTC1096L
LTC1098/LTC1098L
LTC1196
33kHz/15kHz
33kHz/15kHz
1MHz/383kHz
750kHz/287kHz
0.5mW*
0.6mW*
20mW
1-Channel, Unipolar Operation with Reference Input, 5V/3V
2-Channel, Unipolar Operation, 5V/3V
1-Channel, Unipolar Operation with Reference Input, 5V/3V
2-Channel, Unipolar Operation, 5V/3V
LTC1198
20mW*
10-Bit Serial I/O ADCs
LTC1090
25kHz
30kHz
35kHz
25kHz
25kHz
15kHz
5mW
7.5mW
5mW
8-Channel, Bipolar or Unipolar Operation, 5V
2-Channel, Unipolar Operation, 5V
LTC1091
LTC1092
2-Channel, Unipolar Operation with Reference Input, 5V
6-Channel, Bipolar or Unipolar Operation, 5V
8-Channel, Bipolar or Unipolar Operation, 5V
8-Channel, Bipolar or Unipolar Operation, 3V
LTC1093
5mW
LTC1094
5mW
LTC1283
0.5mW
12-Bit Serial I/O ADCs
LTC1285/LTC1288
LTC1286/LTC1298
LTC1287
7.5kHz/6.6kHz
12.5kHz/11.1kHz
30kHz
0.4mW/0.6mW*
1.3mW/1.7mW*
3mW
1-Channel with Reference (LTC1285), 2-Channel (LTC1288), 3V
1-Channel with Reference (LTC1286), 2-Channel (LTC1298), 5V
1-Channel, Unipolar Operation, 3V
LTC1289
33kHz
3mW
8-Channel, Bipolar or Unipolar Operation, 3V
8-Channel, Bipolar or Unipolar Operation, 5V
2-Channel, Unipolar Operation, 5V
LTC1290
50kHz
30mW
LTC1291
54kHz
30mW
LTC1292
60kHz
30mW
1-Channel, Unipolar Operation, 5V
LTC1293
46kHz
30mW
6-Channel, Bipolar or Unipolar Operation, 5V
8-Channel, Bipolar or Unipolar Operation, 5V
8-Channel, Bipolar or Unipolar Operation, 5V
1-Channel, Unipolar Operation, 5V
LTC1294
46kHz
30mW
LTC1296
46kHz
30mW
LTC1297
50kHz
30mW
LTC1400
400kHz
75mW**
1.6mW/0.5mW*
1.6mW/0.5mW*
1-Channel, Bipolar or Unipolar Operation, Internal Reference, 5V
4-Channel, Unipolar Operation, 5V/3V
LTC1594/LTC1594L
LTC1598/LTC1598L
PART NUMBER
Low Power References
LT1004
20kHz/12.5kHz
20kHz/12.5kHz
DESCRIPTION
8-Channel, Unipolar Operation, 5V/3V
COMMENTS
Micropower Voltage Reference
Precision Bandgap Reference
Precision Low Noise Reference
0.3% Max, 20ppm/°C Typ, 10µA Max
LT1019
0.05% Max, 5ppm/°C Max
LT1236
0.05% Max, 5ppm/°C Max, SO Package
0.075% Max, 10ppm/°C Max, 130µA Max, SO Package
0.05% Max, 25ppm/°C Max, 7µA Max, MSOP Package
LT1460-2.5
LT1634
Micropower Precision Series Reference
Micropower Precision Reference
*These devices have auto shutdown which reduces power dissipation
linearly as sample rate is reduced from f
**Has nap and sleep shutdown modes.
.
SMPL(MAX)
11979f LT/TP 0897 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1997
Linear Technology Corporation
●
1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900
28
●
●
FAX: (408) 434-0507 TELEX: 499-3977 www.linear-tech.com
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