LTC1272-3CCN#TR_技术文档

LTC1272

12-Bit, 3µs, 250kHz

Sampling A/D Converter

U

FEATURES

DESCRIPTIO

■

The LTC1272 is a 3µs, 12-bit, successive approximation

sampling A/D converter. It has the same pinout as the

industry standard AD7572 and offers faster conversion

time, on-chip sample-and-hold, and single supply opera-

tion.ItusesLTBiCMOS^TMswitched-capacitortechnologyto

combine a high speed 12-bit ADC with a fast, accurate

sample-and-hold and a precision reference.

AD7572 Pinout

■

12-Bit Resolution

■

3µs and 8µs Conversion Times

■

On-Chip Sample-and-Hold

■

Up to 250kHz Sample Rates

■

5V Single Supply Operation

■

No Negative Supply Required

■

On-Chip 25ppm/°C Reference

The LTC1272 operates with a single 5V supply but can also

accept the 5V/–15V supplies required by the AD7572 (Pin

23, the negative supply pin of the AD7572, is not connected

ontheLTC1272). TheLTC1272hasthesame0Vto5Vinput

range as the AD7572 but, to achieve single supply opera-

tion, it provides a 2.42V reference output instead of the

–5.25V of the AD7572. It plugs in for the AD7572 if the

reference capacitor polarity is reversed and a 1µs sample-

and-hold acquisition time is allowed between conversions.

■

75mW (Typ) Power Consumption

■

24-Pin Narrow DIP and SOL Packages

■

ESD Protected on All Pins

U

APPLICATIO S

■

High Speed Data Acquisition

■

Digital Signal Processing (DSP)

■

Multiplexed Data Acquisition Systems

Single Supply Systems

■

The output data can be read as a 12-bit word or as two

8-bit bytes. This allows easy interface to both 8-bit and

higher processors. The LTC1272 can be used with a

crystal or an external clock and comes in speed grades of

3ms and 8ms.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

LTBiCMOS is a trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

U

TYPICAL APPLICATIO

Single 5V Supply, 3µs, 12-Bit Sampling ADC

1024 Point FFT, f = 250kHz, f = 10kHz

S

IN

5V

LTC1272

0

–20

ANALOG INPUT

A

V

DD

IN

(0V TO 5V)

2.42V

REF

OUTPUT

+

S

NC

BUSY

CS

V

= 72.1

REF

10µ F

µP

0.1µF

+

(N+D)

0.1µF

10µF

AGND

D11 (MSB)

D10

–40

–60

CONTROL

LINES

RD

–80

D9

HBEN

CLK OUT

CLK IN

D0/8

D8

–100

–120

–140

D7

D6

8 OR 12-BIT

PARALLEL

BUS

D5

D1/9

0

20

40

60

80

100

120

D4

D2/10

D3/11

FREQUENCY (kHz)

DGND

LTC1272 • TA02

LTC1272 • TA01

1272fb

1

LTC1272

W W W

U

ABSOLUTE AXI U RATI GS

(Notes 1 and 2)

Supply Voltage (V_DD)................................................. 6V

Analog Input Voltage (Note 3) ...................–0.3V to 15V

Digital Input Voltage ..................................–0.3V to 12V

Digital Output Voltage.................... –0.3V to V_DD+ 0.3V

Power Dissipation.............................................. 500mW

Operating Temperature Range

LTC1272-XAC, CC ................................. 0°C to 70°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

W U

/O

PACKAGE RDER I FOR ATIO

TOP VIEW

ORDER PART NUMBER

A

1

2

3

4

5

6

7

8

9

24 V

DD

A

1

2

3

4

5

6

7

8

9

24 V

DD

IN

CONVERSION

23 NC

V

23 NC

V

REF

TIME = 8µs

TIME = 3µs

AGND

22 BUSY

21 CS

AGND

22 BUSY

21 CS

(MSB) D11

LTC1272-8ACN

LTC1272-8CCN

(MSB) D11

LTC1272-3ACN

LTC1272-3CCN

D10

D9

D8

D7

D6

20 RD

D10

D9

D8

D7

D6

20 RD

19 HBEN

18 CLK OUT

17 CLK IN

16 D0/8

15 D1/9

14 D2/10

13 D3/11

19 HBEN

18 CLK OUT

17 CLK IN

16 D0/8

15 D1/9

14 D2/10

13 D3/11

SW PACKAGE ONLY

LTC1272-8ACSW

LTC1272-8CCSW

LTC1272-3ACSW

LTC1272-3CCSW

D5 10

D4 11

D5 10

D4 11

DGND 12

SW PACKAGE

24-LEAD PLASTIC SO WIDE

N PACKAGE

24-LEAD PDIP

T_JMAX= 110°C, θ_JA= 100°C/W

T_JMAX= 110°C, θ_JA= 130°C/W

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

U

CO VERTER

CHARACTERISTICS

The

●

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. With Internal Reference (Note 4)

A

LTC1272-XA

LTC1272-XC

TYP

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNITS

Bits

Resolution (No Missing Codes)

Integral Linearity Error

Differential Linearity Error

Offset Error

●

12

(Note 5)

±1/2

±1

LSB

±3

±4

±6

LSB

●

Gain Error

±10

±25

±15

±45

LSB

Full-Scale Tempco

I

(Reference) = 0

±5

±10

ppm/°C

OUT

1272fb

2

LTC1272

U U

U

The

●

denotes the specifications which apply over the full

I TER AL REFERE CE CHARACTERISTICS

operating temperature range, otherwise specifications are at T = 25°C. (Note 4)

A

LTC1272-XA

LTC1272-XC

TYP

PARAMETER

CONDITIONS

MIN

TYP

2.420

5

MAX

2.440

25

MIN

MAX

2.440

45

UNITS

V

Output Voltage (Note 6)

Output Tempco

I

= 0

2.400

2.420

10

REF

OUT

●

ppm/°C

LSB/V

LSB/mA

Line Regulation

4.75V ≤ V ≤ 5.25V, I

= 0

OUT

0.01

2

0.01

2

DD

Load Regulation (Sourcing Current) 0 ≤ ⎢I

⎢≤ 1mA

OUT

U

The

●

denotes the specifications which

DIGITAL AND DC ELECTRICAL CHARACTERISTICS

apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4)

A

LTC1272-XA/C

TYP

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNITS

V

High Level Input Voltage CS, RD, HBEN, CLK IN

Low Level Input Voltage CS, RD, HBEN, CLK IN

Input Current CS, RD, HBEN

V

= 5.25V

= 4.75V

= 0V to V

= 4.75V

●

2.4

IH

IL

DD

IN

0.8

± 10

± 20

V

I

µA

V

IN

DD

Input Current CLK IN

IN

V

High Level Output Voltage All Logic Outputs

I = –10µA

OUT

4.7

4.0

OH

OL

DD

I

= –200µA

●

V

OUT

Low Level Output Voltage All Logic Outputs

High-Z Output Leakage D11-D0/8

High-Z Output Capacitance (Note 7)

Output Source Current

V

= 4.75V, I

= 1.6mA

0.4

± 10

15

V

DD

OUT

I

= 0V to V

µA

pF

OZ

OUT

DD

C

OZ

I

V

= 0V

–10

10

mA

mW

SOURCE

SINK

DD

OUT

Output Sink Current

= V

DD

Positive Supply Current

CS = RD = V , A = 5V

●

15

30

DD IN

P

Power Dissipation

75

D

W

U

(Note 4) f

= 250kHz (LTC1272-3), 166kHz (LTC1272-5), 111kHz (LTC1272-8)

LTC1272-XA/C

SAMPLE

DY

A IC

ACCURACY

SYMBOL

PARAMETER

Signal-to-Noise Plus Distortion Ratio

CONDITIONS

MIN

TYP

MAX

UNITS

dB

S/(N + D)

THD

10kHz Input Signal

72

Total Harmonic Distortion (Up to 5th Harmonic)

Peak Harmonic or Spurious Noise

–82

dB

U

The

●

denotes the specifications which apply over the full operating temperature range, otherwise

LTC1272-XA/B/C

A ALOG I PUT

specifications are at T = 25°C. (Note 4)

A

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Input Voltage Range

Input Current

4.75V ≤ V ≤ 5.25V

●

0

5

V

IN

DD

I

3.5

mA

pF

IN

C

Input Capacitance

50

IN

t

Sample-and-Hold Acquisition Time

●

0.45

1

µs

ACQ

1272fb

3

LTC1272

U W

The

●

denotes the specifications which apply over the full operating temperature

LTC1272-XA/C

TI I G CHARACTERISTICS

range, otherwise specifications are at T = 25°C. (Note 8)

A

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

t

CS to RD Setup Time

RD to BUSY Delay

●

0

ns

1

2

C = 50pF

COM Grade

80

50

70

190

230

ns

L

t

Data Access Time After RD

↓

C = 20pF

90

110

ns

3

L

COM Grade

C = 100pF

125

150

ns

L

COM Grade

t

RD Pulse Width

t

ns

4

3

COM Grade

●

t

CS to RD Hold Time

0

ns

5

6

Data Setup Time After BUSY

40

30

70

90

ns

COM Grade

●

t

Bus Relinquish Time

20

75

85

ns

7

●

t

HBEN to RD Setup Time

HBEN to RD Hold Time

0

ns

µs

ns

8

9

Delay Between RD Operations

Delay Between Conversions

Aperture Delay of Sample and Hold

CLK to BUSY Delay

200

1

10

11

12

13

Jitter <50ps

COM Grade

25

80

170

220

ns

●

t

Conversion Time

12

13

CLK

CONV

CYCLES

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground with DGND and

AGND wired together, unless otherwise noted.

Note 3: When the analog input voltage is taken below ground it will be

clamped by an internal diode. This product can handle, with no external

diode, input currents of greater than 60mA below ground without latch-up.

Note 5: Linearity error is specified between the actual end points of the

A/D transfer curve.

Note 6: The LTC1272 has the same 0V to 5V input range as the AD7572

but, to achieve single supply operation, it provides a 2.42V reference

output instead of the –5.25V of the AD7572. This requires that the polarity

of the reference bypass capacitor be reversed when plugging an LTC1272

into an AD7572 socket.

Note 7: Guaranteed by design, not subject to test.

Note 8: V = 5V. Timing specifications are sample tested at 25°C to

DD

Note 4:

V

DD

= 5V, f

= 4MHz for LTC1272-3, and 1.6MHz for

ensure compliance. All input control signals are specified with t = t = 5ns

CLK

r

f

LTC1272-8, t = t = 5ns unless otherwise specified. For best analog

(10% to 90% of 5V) and timed from a voltage level of 1.6V. See Figures 13

through 17.

r

f

performance, the LTC1272 clock should be synchronized to the RD and

CS control inputs with at least 40ns separating convert start from the

nearest clock edge.

1272fb

4

LTC1272

U

O

U

PI

FU CTI

S

HBEN (Pin 19): High Byte Enable Input. This pin is used to

multiplex the internal 12-bit conversion result into the

lowerbitoutputs(D7toD0/8). Seetablebelow. HBENalso

disables conversion starts when HIGH.

A_IN(Pin 1): Analog Input, 0V to 5V Unipolar Input.

V_REF(Pin2):2.42VReferenceOutput.Whenplugginginto

anAD7572socket, reversethereferencebypasscapacitor

polarity and short the 10Ω series resistor.

RD (Pin 20): Read Input. This active low signal starts a

conversion when CS and HBEN are low. RD also enables

the output drivers when CS is low.

AGND (Pin 3): Analog Ground.

D11 to D4 (Pins 4-11): Three-State Data Outputs.

DGND (Pin 12): Digital Ground.

CS(Pin21):TheChipSelectInputmustbelowfortheADC

to recognize RD and HBEN inputs.

D3/11 to D0/8 (Pins 13-16): Three-State Data Outputs.

BUSY (Pin 22): The BUSY Output is low when a conver-

sion is in progress.

CLK IN (Pin 17): Clock Input. An external TTL/CMOS

compatibleclockmaybeappliedtothispinoracrystalcan

be connected between CLK IN and CLK OUT.

NC (Pin 23): Not Connected Internally. The LTC1272 does

not require negative supply. This pin can accommodate

the –15V required by the AD7572 without problems.

CLKOUT(Pin18):ClockOutput.AninvertedCLKINsignal

appears at this pin.

V

_DD(Pin 24): Positive Supply, 5V.

Data Bus Output, CS and RD = LOW

Pin 4

D11

Pin 5

D10

Pin 6

D9

Pin 7

D8

Pin 8

D7

Pin 9

Pin 10

D5

Pin 11

D4

Pin 13

D3/11

DB3

Pin 14

D2/10

DB2

Pin 15

D1/9

DB1

Pin 16

D0/8

DB0

MNEMONIC*

HBEN = LOW

HBEN = HIGH

D6

DB11

DB10

DB9

DB8

DB7

LOW

DB6

LOW

DB5

LOW

DB4

LOW

DB11

DB10

DB9

DB8

*D11...D0/8 are the ADC data output pins.

DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Integral Nonlinearity

1.0

V

CLK

= 5V

= 4MHz

DD

f

0.5

0

–0.5

–1.0

0

512 1024 1536 2048 2560 3072 3584 4096

CODE

LTC1272 • TPC01

1272fb

5

LTC1272

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Differential Nonlinearity

1.0

V

CLK

= 5V

= 4MHz

DD

f

0.5

0

–0.5

–1.0

0

512 1024 1536 2048 2560 3072 3584 4096

CODE

LTC1272 • TPC02

V

Supply Current vs

Minimum Clock Frequency vs

Temperature

Maximum Clock Frequency vs

Temperature

DD

Temperature

30

25

8

7

600

V

CLK

= 5V

= 4MHz

V

= 5V

DD

f

500

20

15

6

5

400

300

10

5

4

3

2

200

100

0

–55 –25

0

25

50

75

100 125

–55 –25

0

25

50

75

100 125

–55 –25

0

25

50

75

100 125

TEMPERATURE (°C)

LT1272 • TPC03

LT1272 • TPC05

LT1272 • TPC04

V

REF

vs I

(mA)

LTC1272 ENOBs* vs Frequency

LOAD

2.435

2.430

12

11

10

9

2.425

2.420

8

7

6

5

4

3

2

1

0

2.415

2.410

2.405

f

= 250kHz

DD

S

V

= 5V

–5 –4

–3

–2

–1

(mA)

0

1

2

0

20

40

60

80

100 120

I

f

(kHz)

L

IN

LT1272 • TPC06

LT1272 • TPC07

S/(N + D) – 1.76dB

6.02

*EFFECTIVE NUMBER OF BITS, ENOBs =

1272fb

6

LTC1272

O U

W U

PPLICATI

A

S I FOR ATIO

A

IN

Conversion Details

SAMPLE

Conversion start is controlled by the CS, RD and HBEN

inputs. At the start of conversion the successive approxi-

mation register (SAR) is reset and the three-state data

outputs are enabled. Once a conversion cycle has begun

it cannot be restarted.

300Ω

SI

C

SAMPLE

HOLD

–

+

2.7k

COMPARATOR

C

V

DAC

During conversion, the internal 12-bit capacitive DAC

output is sequenced by the SAR from the most significant

bit (MSB) to the least significant bit (LSB). Referring to

Figure 1, the A_INinput connects to the sample-and-hold

capacitor through a 300Ω/2.7kΩ divider. The voltage

divider allows the LTC1272 to convert 0V to 5V input

signals while operating from a 4.5V supply. The conver-

sion has two phases: the sample phase and the convert

phase. During the sample phase, the comparator offset is

nulled by the feedback switch and the analog input is

stored as a charge on the sample-and-hold capacitor,

C_SAMPLE. This phase lasts from the end of the previous

conversion until the next conversion is started. A mini-

mum delay between conversions (t₁₀) of 1µs allows

enoughtimefortheanaloginputtobeacquired.Duringthe

convert phase, the comparator feedback switch opens,

putting the comparator into the compare mode. The

sample-and-hold capacitor is switched to ground inject-

ingtheanaloginputchargeontothecomparatorsumming

junction. This input charge is successively compared to

binary weighted charges supplied by the capacitive DAC.

Bit decisions are made by the comparator (zero crossing

detector) which checks the addition of each successive

weighted bit from the DAC output. The MSB decision is

made 50ns (typically) after the second falling edge of CLK

IN following a conversion start. Similarly, the succeeding

bit decisions are made approximately 50ns after a CLK IN

edge until the conversion is finished. At the end of a

conversion,theDACoutputbalancestheA_INoutputcharge.

The SAR contents (12-bit data word) which represent the

A_INinput signal are loaded into a 12-bit latch.

S

A

R

12-BIT

LATCH

LTC1272 • TA07

Figure 1. A Input

IN

nonlinearity and differential nonlinearity. These specs are

useful for characterizing an ADC’s DC or low frequency

signal performance.

These specs alone are not adequate to fully specify the

LTC1272 because of its high speed sampling ability. FFT

(Fast Fourrier Transform) test techniques are used to

characterize the LTC1272’s frequency response, distor-

tion and noise at the rated throughput.

By applying a low distortion sine wave and analyzing the

digital output using a FFT algorithm, the LTC1272’s spec-

tral content can be examined for frequencies outside the

fundamental. Figure 2 shows a typical LTC1272 FFT plot.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

0

20

40

60

80

100

120

Sample-and-Hold and Dynamic Performance

FREQUENCY (kHz)

LTC1272 • TA23

Traditionally A/D converters have been characterized by

such specs as offset and full-scale errors, integral

Figure 2. LTC1272 Non-Averaged, 1024 Point FFT Plot.

f = 250kHz, f = 10kHz

S

IN

1272fb

7

LTC1272

PPLICATI

O U

W

U

A

S I FOR ATIO

1.0

0.5

Signal-to-Noise Ratio

The Signal-to-Noise Ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency to the

RMS amplitude of all other frequency components at the

A/D output. This includes distortion as well as noise

products and for this reason it is sometimes referred to as

Signal-to-Noise + Distortion [S/(N + D)]. The output is

band limited to frequencies from DC to one half the

samplingfrequency.Figure2showsspectralcontentfrom

DC to 125kHz which is 1/2 the 250kHz sampling rate.

0

–0.5

–1.0

0

1

2

3

4

CODE (THOUSANDS)

LTC1272 • TA24

Effective Number of Bits

Figure 4. LTC1272 Dynamic DNL. f

= 4MHz,

CLK

CC

The effective number of bits (ENOBs) is a measurement of

the resolution of an A/D and is directly related to the

S/(N + D) by the equation:

f = 250kHz, f = 122.25342kHz, V = 5V

S

IN

Total Harmonic Distortion

N = [S/(N + D) –1.76]/6.02,

Total Harmonic Distortion (THD) is the ratio of the RMS

sumofallharmonicsoftheinputsignaltothefundamental

itself. The harmonics are limited to the frequency band

between DC and one half the sampling frequency. THD is

where N is the effective number of bits of resolution and

S/(N + D) is expressed in dB. At the maximum sampling

rate of 250kHz the LTC1272 maintains 11.5 ENOBs or

better to 20kHz. Above 20kHz the ENOBs gradually de-

cline, as shown in Figure 3, due to increasing second

harmonic distortion. The noise floor remains approxi-

mately 90dB. The dynamic differential nonlinearity re-

mains good out to 120kHz as shown in Figure 4.

2

expressed as: 20 LOG [√V₂+ V₃+ ... +V_N/ V₁] where

V₁istheRMSamplitudeofthefundamentalfrequencyand

V₂through V_Nare the amplitudes of the second through

Nth harmonics.

Clock and Control Synchronization

12

11

For best analog performance, the LTC1272 clock should

besynchronizedtotheCSandRDcontrolinputsasshown

inFigure5,withatleast40nsseparatingconvertstartfrom

the nearest CLK IN edge. This ensures that transitions at

CLK IN and CLK OUT do not couple to the analog input and

get sampled by the sample-and-hold. The magnitude of

this feedthrough is only a few millivolts, but if CLK and

convert start (CS and RD) are asynchronous, frequency

components caused by mixing the clock and convert

signals may increase the apparent input noise.

10

9

8

7

6

5

4

3

2

f

= 250kHz

DD

S

1

0

V

= 5V

0

20

40

60

80

100 120

When the clock and convert signals are synchronized,

small endpoint errors (offset and full-scale) are the most

that can be generated by clock feedthrough. Even these

errors (which can be trimmed out) can be eliminated by

ensuringthatthestartofaconversion(CSandRD’sfalling

edge) does not occur within 40ns of a clock edge, as in

1272fb

f

(kHz)

IN

LT1272 • TPC07

Figure 3. LTC1272 Effective Number of Bits (ENOBs) vs Input

Frequency. f = 250kHz

S

8

LTC1272

O U

W

U

PPLICATI

A

S I FOR ATIO

CS & RD

t

2

t

CONV

BUSY

t

≥40ns*

13

CLK IN

t

14

DB11

(MSB)

DB10

DB1

DB0

(LSB)

UNCERTAIN CONVERSION TIME FOR 30ns < t < 180ns

14

LTC1272 • TA06

*

THE LTC1272 IS ALSO COMPATIBLE WITH THE AD7572 SYNCHRONIZATION MODES.

Figure 5. RD and CLK IN for Synchronous Operation

CLK OUT

Figure 5. Nevertheless, even without observing this guide-

line,theLTC1272isstillcompatiblewithAD7572synchro-

nization modes, with no increase in linearity error. This

means that either the falling or rising edge of CLK IN may

be near RD’s falling edge.

LTC1272

C1

C2

18

17

CLOCK

CLK IN

1M

NOTES:

LTC1272-3 – 4MHz CRYSTAL/CERAMIC RESONATOR

LTC1272-8 – 1.6MHz CRYSTAL/CERAMIC RESONATOR

Driving the Analog Input

LTC1272 • TA09

The analog input of the LTC1272 is much easier to drive

than that of the AD7572. The input current is not modu-

lated by the DAC as in the AD7572. It has only one small

current spike from charging the sample-and-hold capaci-

tor at the end of the conversion. During the conversion the

analog input draws only DC current. The only requirement

is that the amplifier driving the analog input must settle

after the small current spike before the next conversion is

started. Any op amp that settles in 1µs to small current

transients will allow maximum speed operation. If slower

op amps are used, more settling time can be provided by

increasing the time between conversions. Suitable de-

vices capable of driving the LTC1272 A_INinput include the

LT1006 and LT1007 op amps.

Figure 6. LTC1272 Internal Clock Circuit

connected to CLK IN. For an external clock the duty cycle

is not critical. An inverted CLK IN signal will appear at the

CLK OUT pin as shown in the operating waveforms of

Figure 7. Capacitance on the CLK OUT pin should be

minimized for best analog performance.

Internal Reference

The LTC1272 has an on-chip, temperature compensated,

curvature corrected, bandgap reference, which is factory

trimmed to 2.42V ±1%. It is internally connected to the

DAC and is also available at pin 2 to provide up to 1mA

current to an external load.

Internal Clock Oscillator

Figure 6 shows the LTC1272 internal clock circuit. A

crystal or ceramic resonator may be connected between

CLK IN (Pin 17) and CLK OUT (Pin 18) to provide a clock

oscillator for ADC timing. Alternatively the crystal/resona-

tor may be omitted and an external clock source may be

For minimum code transition noise the reference output

should be decoupled with a capacitor to filter wideband

noise from the reference (10µF tantalum in parallel with a

0.1µF ceramic). A simplified schematic of the reference

with its recommended decoupling is shown in Figure 8.

1272fb

9

LTC1272

O U

W

U

PPLICATI

A

S I FOR ATIO

CS & RD

BUSY

50ns TYP

CLK IN

CLK OUT

DB11

(MSB)

DB10

DB1

DB0

(LSB)

LTC1272 • TA08

Figure 7. Operating Waveforms Using an External Clock Source for CLK IN

FULL-SCALE

TRANSITION

11...111

11...110

11...101

5V

LTC1272

+

–

CURVATURE

CORRECTED

BANDGAP

TO DAC

REFERENCE

FS = 5V

1LSB =

FS

––––

4096

00...011

00...010

AGND

V

REF

3

2

00...001

00...000

0.1µF

10µF

0

1

LSB

2

3

LSBs

FS

FS – 1LSB

LSBs

A

, INPUT VOLTAGE (IN TERMS OF LSBs)

IN

LTC1272 • TA10

LT1272 • TA11

Figure 8. LTC1272 Internal 2.42V Reference

Figure 9. LTC1272 Ideal Input/Output Transfer Characteristic

Unipolar Operation

error must be adjusted before full-scale error. Figure 10

shows the extra components required for full-scale error

adjustment. Zero offset is achieved by adjusting the offset

of the op amp driving A_IN(i.e., A1 in Figure 10). For zero

offset error apply 0.61mV (i.e., 1/2LBS) at V_INand adjust

the op amp offset voltage until the ADC output code

flickers between 0000 0000 0000 and 0000 0000 0001.

Figure9showstheidealinput/outputcharacteristicforthe

0V to 5V input range of the LTC1272. The code transitions

occur midway between successive integer LSB values

(i.e., 1/2LSB, 3/2LSBs, 5/2LSBs . . . FS – 3/2LSBs). The

output code is natural binary with 1 LSB = FS/4096 =

(5/4096)V = 1.22mV.

For zero full-scale error apply an analog input of 4.99817V

(i.e., FS–3/2LSBsorlastcodetransition)atV_INandadjust

R1 until the ADC output code flickers between 1111 1111

1110 and 1111 1111 1111.

Unipolar Offset and Full-Scale Error Adjustment

Inapplicationswhereabsoluteaccuracyisimportant, then

offset and full-scale error can be adjusted to zero. Offset

1272fb

10

LTC1272

O U

W U

PPLICATI

A

S I FOR ATIO

0V TO 5V

ANALOG

INPUT

the foil width for these tracks should be as wide as

possible.

V

IN

R3

+

15Ω

A1

LT1007

A

1

3

IN

–

Noise: Input signal leads to A_INand signal return leads

from AGND (pin 3) should be kept as short as possible to

minimize input noise coupling. In applications where this

is not possible, a shielded cable between source and ADC

is recommended. Also, since any potential difference in

groundsbetweenthesignalsourceandADCappearsasan

error voltage in series with the input signal, attention

should be paid to reducing the ground circuit impedances

as much as possible.

LTC1272

AGND

R1

200Ω

R2

20k

*ADDITIONAL PINS OMITTED FOR CLARITY

LTC1272 • TA12

Figure 10. Unipolar 0V to 5V Operation with Gain Error Adjust

Application Hints

In applications where the LTC1272 data outputs and

control signals are connected to a continuously active

microprocessor bus, it is possible to get LSB errors in

conversion results. These errors are due to feedthrough

fromthemicroprocessortothesuccessiveapproximation

comparator. The problem can be eliminated by forcing the

microprocessor into a Wait state during conversion (see

Slow Memory Mode interfacing), or by using three-state

buffers to isolate the LTC1272 data bus.

Wire wrap boards are not recommended for high resolu-

tion or high speed A/D converters. To obtain the best

performance from the LTC1272 a printed circuit board is

required. Layout for the printed circuit board should

ensurethatdigitalandanalogsignallinesareseparatedas

much as possible. In particular, care should be taken not

to run any digital track alongside an analog signal track or

underneath the LTC1272. The analog input should be

screened by AGND.

Timing and Control

A single point analog ground separate from the logic

system ground should be established with an analog

groundplaneatpin3(AGND)orascloseaspossibletothe

LTC1272, as shown in Figure 11. Pin 12 (LTC1272 DGND)

and all other analog grounds should be connected to this

single analog ground point. No other digital grounds

should be connected to this analog ground point. Low

impedance analog and digital power supply common

returnsareessentialtolownoiseoperationoftheADCand

Conversion start and data read operations are controlled

by three LTC1272 digital inputs; HBEN, CS and RD. Figure

12 shows the logic structure associated with these inputs.

The three signals are internally gated so that a logic “0” is

required on all three inputs to initiate a conversion. Once

initiated it cannot be restarted until conversion is com-

plete. Converter status is indicated by the BUSY output,

and this is low while conversion is in progress.

1

LTC1272

DIGITAL

SYSTEM

A

IN

AGND

3

V

+

DGND

REF

DD

ANALOG

INPUT

CIRCUITRY

2

24

C4

12

–

C3

C2

C1

GROUND CONNECTION

TO DIGITAL CIRCUITRY

LTC1272 • TA13

ANALOG GROUND PLANE

Figure 11. Power Supply Grounding Practice

1272fb

11

LTC1272

PPLICATI

O U

W U

A

S I FOR ATIO

Therearetwomodesofoperationasoutlinedbythetiming

diagrams of Figures 13 to 17. Slow Memory Mode is

designed for microprocessors which can be driven into a

Wait state, a Read operation brings CS and RD low which

initiates a conversion and data is read when conversion is

complete.

The second is the ROM Mode which does not require

microprocessor Wait states. A Read operation brings CS

and RD low which initiates a conversion and reads the

previous conversion result.

5V

LTC1272

D

Q

CONVERSION START

(RISING EDGE TRIGGER)

HBEN 19

CS 21

FLIP

FLOP

RD 20

CLEAR

BUSY

ACTIVE HIGH

ENABLE THREE-STATE OUTPUTS

D11....D0/8 = DB11....DB0

ACTIVE HIGH

ENABLE THREE-STATE OUTPUTS

D11....D8 = DB11....DB8

D7....D4 = LOW

D3/11....D0/8 = DB11....DB8

D11....D0/8 ARE THE ADC DATA OUTPUT PINS

DB11....DB0 ARE THE 12-BIT CONVERSION RESULTS

LTC1272 • TA14

Figure 12. Internal Logic for Control Inputs CS, RD and HBEN

CS & RD

t

2

t

CONV

BUSY

t

≥40ns*

13

CLK IN

t

14

DB11

(MSB)

DB10

DB1

DB0

(LSB)

UNCERTAIN CONVERSION TIME FOR 30ns < t < 180ns

14

*

THE LTC1272 IS ALSO COMPATIBLE WITH THE AD7572 SYNCHRONIZATION MODES.

LTC1272 • TA15

SEE “DIGITAL INTERFACE” TEXT.

Figure 13. RD and CLK IN for Synchronous Operation

Table 1. Data Bus Output, CS and RD = Low

PIN 4

D11

PIN 5

D10

PIN 6

D9

PIN 7

D8

PIN 8

D7

PIN 9

D6

PIN 10

D5

PIN 11

D4

PIN 13

PIN 14

D2/10

DB2

PIN 15

D1/9

DB1

PIN 16

D0/8

DB0

Data Outputs*

HBEN = Low

HBEN = High

D3/11

DB3

DB11

DB10

DB9

DB8

DB7

Low

DB6

Low

DB5

Low

DB4

Low

DB11

DB10

DB9

DB8

Note: *D11 . . . D0/8 are the ADC data output pins

DB11 . . . DB0 are the 12-bit conversion results, DB11 is the MSB

1272fb

12

LTC1272

O U

W

U

PPLICATI

A

S

I FOR ATIO

CS

t

1

5

RD

t

10

t

11

2

t

CONV

BUSY

t

7

3

6

OLD DATA

DB11-DB0

NEW DATA

DB11-DB0

DATA

t

12

HOLD

TRACK

LTC1272 • TA16

Figure 14. Slow Memory Mode, Parallel Read Timing Diagram

Table 2. Slow Memory Mode, Parallel Read Data Bus Status

Data Outputs

D11

D10

D9

D8

D7

D6

D5

D4

D3/11

D2/10

D1/9

D0/8

Read

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Data Format

Slow Memory Mode, Two Byte Read

The output data format can be either a complete parallel

load for 16-bit microprocessors or a two byte load for

8-bit microprocessors. Data is always right justified (i.e.,

LSB is the most right-hand bit in a 16-bit word). For a two

byte read, only data outputs D7. . . D0/8 are used. Byte

selectionisgovernedbytheHBENinputwhichcontrolsan

internal digital multiplexer. This multiplexes the 12 bits of

conversion data onto the lower D7. . . D0/8 outputs

(4MSBs or 8LSBs) where it can be read in two read cycles.

The 4MSBs always appear on D11 . . . D8 whenever the

three-state output drives are turned on.

For a two byte read, only 8 data outputs D7 . . . D0/8 are

used. Conversion start procedure and data output status

for the first read operation is identical to Slow Memory

Mode, Parallel Read. See Figure 15 timing diagram and

Table 3 data bus status. At the end of conversion the low

data byte (DB7 . . . DB0) is read from the ADC. A second

Read operation with HBEN high, places the high byte on

dataoutputsD3/11... D0/8anddisablesconversionstart.

Note the 4MSBs appear on data outputs D11 . . . D8 during

the two Read operations above.

ROM Mode, Parallel Read (HBEN = Low)

Slow Memory Mode, Parallel Read (HBEN = Low)

The ROM Mode avoids placing a microprocessor into a

Wait state. A conversion is started with a Read operation

and the 12 bits of data from the previous conversion is

available on data outputs D11 . . . D0/8 (see Figure 16 and

Table 4). This data may be disregarded if not required. A

secondReadoperationreadsthenewdata(DB11... DB0)

and starts another conversion. A delay at least as long as

theLTC1272conversiontimeplusthe1µsminimumdelay

between conversions must be allowed between Read

Figure 14 and Table 2 show the timing diagram and data

bus status for Slow Memory Mode, Parallel Read. CS and

RD going low triggers a conversion and the LTC1272

acknowledgesbytakingBUSYlow.Datafromtheprevious

conversionappearsonthethree-statedataoutputs. BUSY

returns high at the end of conversion when the output

latches have been updated and the conversion result is

placed on data outputs D11 . . . D0/8.

operations.

1272fb

13

LTC1272

O U

W

U

PPLICATI

A

S I FOR ATIO

HBEN

t

9

8

9

8

CS

RD

t

5

1

5

1

4

t

10

t

11

2

CONV

BUSY

DATA

t

7

3

6

7

3

OLD DATA

DB7-DB0

NEW DATA

DB7-DB0

NEW DATA

DB11-DB8

t

12

HOLD

TRACK

LTC1272 • TA17

Figure 15. Slow Memory Mode, Two Byte Read Timing Diagram

Table 3. Slow Memory Mode, Two Byte Read Data Bus Status

Data Outputs

First Read

D7

D6

D5

D4

D3/11

DB3

D2/10

DB2

D1/9

D0/8

DB0

DB8

DB7

Low

DB6

Low

DB5

Low

DB4

Low

DB1

DB9

Second Read

DB11

DB10

CS

t

5

1

4

5

1

4

RD

t

11

t

CONV

2

CONV

2

BUSY

t

7

3

7

3

OLD DATA

DB11-DB0

NEW DATA

DB11-DB0

DATA

t

12

HOLD

TRACK

LTC1272 • TA18

Figure 16. ROM Mode, Parallel Read Timing Diagram

Table 4. ROM Mode, Parallel Read Data Bus Status

Data Outputs

D11

DB11

D10

DB10

D9

D8

D7

D6

D5

D4

D3/11

D2/10

D1/9

DB1

D0/8

First Read (Old Data)

Second Read

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB0

1272fb

14

LTC1272

O U

W U

PPLICATI

A

S I FOR ATIO

HBEN

t

9

8

9

8

9

8

CS

RD

t

5

1

4

5

1

4

5

1

4

t

10

t

2

CONV

11

BUSY

DATA

t

7

3

7

3

7

3

OLD DATA

DB7-DB0

NEW DATA

DB11-DB8

NEW DATA

DB7-DB0

t

12

HOLD

TRACK

LTC1272 • TA19

Figure 17. ROM Mode, Two Byte Read Timing Diagram

Table 5. ROM Mode, Two Byte Read Data Bus Status

Data Outputs

First Read

D7

D6

D5

D4

D3/11

DB3

D2/10

DB2

D1/9

DB1

DB9

DB1

D0/8

DB0

DB8

DB0

DB7

Low

DB7

DB6

Low

DB6

DB5

Low

DB5

DB4

Low

DB4

Second Read

Third Read

DB11

DB3

DB10

DB2

ROM Mode, Two Byte READ

Microprocessor Interfacing

As previously mentioned for a two byte read, only data

outputs D7 . . . D0/8 are used. Conversion is started in the

normal way with a Read operation and the data output

status is the same as the ROM Mode, Parallel Read. See

Figure17timingdiagramandTable5databusstatus. Two

more Read operations are required to access the new

conversion result. A delay equal to the LTC1272 conver-

sion time must be allowed between conversion start and

the second data Read operation. The second Read opera-

tion, withHBENhigh, disablesconversionstartandplaces

the high byte (4 MSBs) on data outputs D3/11 . . . DO18.

A third read operation accesses the low data byte (DB7

. . . DB0) and starts another conversion. The 4 MSB’s

appear on data outputs D11 . . . D8 during all three read

operations above.

The LTC1272 is designed to interface with microproces-

sors as a memory mapped device. The CS and RD control

inputs are common to all peripheral memory interfacing.

The HBEN input serves as a data byte select for 8-bit

processors and is normally connected to the micropro-

cessor address bus.

MC68000 Microprocessor

Figure 18 shows a typical interface for the MC68000. The

LTC1272 is operating in the Slow Memory Mode. Assum-

ing the LTC1272 is located at address C000, then the

following single 16-bit Move instruction both starts a

conversion and reads the conversion result:

Move.W $C000,D0

1272fb

15

LTC1272

O U

W U

PPLICATI

A

S I FOR ATIO

is accomplished with the single 16-bit Load instruction

below.

A23

A1

ADDRESS BUS

For the 8085A

For the Z80

LHLD (B000)

LDHL, (B000)

ADDRESS

AS

EN

DECODE

LTC1272

MC68000

CS

DTACK

This is a two byte read instruction which loads the ADC

data (address B000) into the HL register pair. During the

first read operation, BUSY forces the microprocessor to

Wait for the LTC1272 conversion. No Wait states are

inserted during the second read operation when the mi-

croprocessor is reading the high data byte.

BUSY

R/W

RD

D11

D0

D11

DATA BUS

D0/8

HBEN

ADDITIONAL PINS OMITTED FOR CLARITY

LTC1272 • TA20

Figure 18. LTC1272 MC68000 Interface

TMS32010 Microcomputer

At the beginning of the instruction cycle when the ADC

address is selected, BUSY and CS assert DTACK, so that

the MC68000 is forced into a Wait state. At the end of

conversion BUSY returns high and the conversion result

is placed in the D0 register of the microprocessor.

Figure 20 shows an LTC1272 TMS32010 interface. The

LTC1272 is operating in the ROM Mode. The interface is

designed for a maximum TMS32010 clock frequency of

18MHz but will typically work over the full TMS32010

clock frequency range.

8085A, Z80 Microprocessor

The LTC1272 is mapped at a port address. The following

I/O instruction starts a conversion and reads the previous

conversion result into data memory.

Figure 19 shows a LTC1272 interface for the Z80 and

8085A. The LTC1272 is operating in the Slow Memory

Mode and a two byte read is required. Not shown in the

figure is the 8-bit latch required to demultiplex the 8085A

common address/data bus. A0 is used to assert HBEN, so

that an even address (HBEN = LOW) to the LTC1272 will

start a conversion and read the low data byte. An odd

address (HBEN = HIGH) will read the high data byte. This

IN A,PA

(PA = PORT ADDRESS)

When conversion is complete, a second I/O instruction

reads the up-to-date data into memory and starts another

conversion. A delay at least as long as the ADC conversion

time must be allowed between I/O instructions.

PA2

A15

A0

PORT ADDRESS BUS

PA0

ADDRESS BUS

ADDRESS

A0

ADDRESS

DEN

TMS32010

EN

MREQ

EN

DECODE

HBEN

LTC1272

Z80

8085A

CS

RD

CS

BUSY

LTC1272

WAIT

RD

D11

D0

D11

D7

D0

D7

DATA BUS

D0/8

HBEN

LINEAR CIRCUITRY OMITTED FOR CLARITY

LTC1272 • TA21

LTC1272 • TA22

Figure 19. LTC1272 8085A/Z80 Interface

Figure 20. LTC1272 TMS32010 Interface

1272fb

16

LTC1272

O U

W

U

PPLICATI

A

S I FOR ATIO

Compatibility with the AD7572

minimum time between conversions must be provided to

allow the sample-and-hold to reacquire the analog input.

Figure 22 shows that if the clock is synchronous with CS

and RD, it is only necessary to short out the 10Ω series

resistor and reverse the polarity of the 10µF bypass

capacitor on the V_REFpin. The –15V supply is not required

and can be removed, or, because there is no internal

connection to pin 23, it can remain unmodified. The clock

can be considered synchronous with CS and RD in cases

wheretheLTC1272CLKINsignalisderivedfromthesame

clock as the microprocessor reading the LTC1272.

Figure 21 shows the simple, single 5V configuration

recommended for new designs with the LTC1272. If an

AD7572 replacement or upgrade is desired, the LTC1272

can be plugged into an AD7572 socket with minor modi-

fications. It can be used as a replacement or to upgrade

with sample-and-hold, single supply operation and re-

duced power consumption.

The LTC1272, while consuming less power overall than

the AD7572, draws more current from the 5V supply (it

draws no power from the –15V supply). Also, a 1µs

5V

LTC1272

ANALOG INPUT

(0V TO 5V)

A

V

DD

IN

2.42V

REF

OUTPUT

+

NC

BUSY

CS

V

REF

10µ F

µP

0.1µF*

+

10µF

0.1µF

AGND

D11 (MSB)

D10

CONTROL

LINES

RD

D9

HBEN

CLK OUT

CLK IN

D0/8

D8

D7

D6

8 OR 12-BIT

PARALLEL

BUS

D5

D1/9

D4

D2/10

D3/11

*

DGND

LTC1272 • TA03

* FOR GROUNDING AND BYPASSING HINTS

SEE FIGURE 11 AND APPLICATION HINTS

SECTION

Figure 21. Single 5V Supply, 3µs, 12-Bit Sampling ADC

1272fb

17

LTC1272

PPLICATI

O U

W

U

A

S

I FOR ATIO

LTC1272

ANALOG INPUT

(0V TO 5V)

5V

A

V

DD

IN

+

2.42V*

REF

OUTPUT

10Ω*

✝

10µ F

–15V

NC

0.1µF

V

REF

+

0.1µF

10µ F

10µF

0.1µF

AGND

D11 (MSB)

D10

BUSY

CS

+

µP

†

RD

CONTROL

LINES

D9

HBEN

CLK OUT

CLK IN**

D0/8

D8

D7

D6

µP

DATA

BUS

* THE LTC1272 HAS THE SAME 0V TO 5V INPUT RANGE BUT PROVIDES A 2.42V

REFERENCE OUTPUT AS OPPOSED TO THE –5.25V OF THE AD7572. FOR PROPER

OPERATION, REVERSE THE REFERENCE CAPACITOR POLARITY AND SHORT OUT THE

10Ω RESISTOR.

D5

D1/9

D4

D2/10

D3/11

** THE ADC CLOCK SHOULD BE SYNCHRONIZED TO THE CONVERSION START

SIGNALS (CS, RD) OR 1-2 LSBs OF OUTPUT CODE NOISE MAY OCCUR. DERIVING

THE ADC CLOCK FROM THE µP CLOCK IS ADEQUATE.

DGND

✝

THE LTC1272 CAN ACCOMMODATE THE –15V SUPPLY OF THE AD7572 BUT DOES

NOT REQUIRE IT. PIN 23 OF THE LTC1272 IS NOT INTERNALLY CONNECTED.

LTC1272 • TA04

Figure 22. Plugging the LTC1272 into an AD7572 Socket

Case 1: Clock Synchronous with CS and RD

If the clock signal for the AD7572 is derived from a over the first: because the RD is delayed by the flip-flop,

separate crystal or other signal which is not synchronous the actual conversion start and the enabling of the

with the microprocessor clock, then the signals need to be LTC1272’s BUSY and data outputs can take up to one CLK

synchronized for the LTC1272 to achieve best analog IN cycle to respond to a RD↓ convert command from the

performance (see Clock and Control Synchronization). processor. The sampling of the analog input no longer

The best way to synchronize these signals is to drive the occurs at the processor’s falling RD edge but may be

CLK IN pin of the LTC1272 with a derivative of the delayed as much as one CLK IN cycle. Although the

processor clock, as mentioned above and shown in Figure LTC1272 will still exhibit excellent DC performance, the

22. Another way, shown in Figure 23, is to use a flip-flop flip-flop will introduce jitter into the sampling which may

to synchronize the RD to the LTC1272 with the CLK IN reduce the usefulness of this method for AC systems.

signal. This method will work but has two disavantages

1272fb

18

LTC1272

O U

W

U

PPLICATI

A

S I FOR ATIO

5V

+

–15V

10µ F

0.1µF

LTC1272

10µ F

0.1µF

+

ANALOG INPUT

(0V TO 5V)

A

V

DD

IN

2.42V*

REF

10Ω*

✝

†

NC

V

REF

+

OUTPUT

10µF

0.1µF

AGND

D11 (MSB)

D10

BUSY

CS

RD

µP

74HC04

CONTROL

S

D9

HBEN

CLK OUT

CLK IN

D0/8

LINES

1/2

74HC74

RD

D**

Q

D8

D7

CLK

D6

µP

DATA

BUS

D5

D1/9

D4

D2/10

D3/11

DGND

EXTERNAL

ASYNCHRONOUS OR

CLOCK

* THE LTC1272 HAS THE SAME 0V TO 5V INPUT RANGE BUT PROVIDES A 2.42V

REFERENCE OUTPUT AS OPPOSED TO THE –5.25V OF THE AD7572. FOR PROPER

OPERATION, REVERSE THE REFERENCE CAPACITOR POLARITY AND SHORT OUT THE

10Ω RESISTOR.

** THE D FLIP-FLOP SYNCHRONIZES THE CONVERSION START SIGNAL (RD ) TO THE

ADC CLK

SIGNAL TO PREVENT OUTPUT CODE NOISE WHICH OCCURS WITH

OUT

AN ASYNCHRONOUS CLOCK.

✝

THE LTC1272 CAN ACCOMMODATE THE –15V SUPPLY OF THE AD7572 BUT DOES

NOT REQUIRE IT. PIN 23 OF THE LTC1272 IS NOT INTERNALLY CONNECTED.

LTC1272 • TA05

Figure 23. Plugging the LTC1272 into an AD7572 Socket

Case 2: Clock Not Synchronous with CS and RD

1272fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

19

LTC1272

U

PACKAGE DESCRIPTIO

N Package

24-Lead PDIP (Narrow .300 Inch)

(Reference LTC DWG # 05-08-1510)

1.280*

(32.512)

MAX

24

23

22

21

20

19

18

17

16

15

10

14

11

13

12

.255 .015*

(6.477 0.381)

3

4

5

6

7

8

9

1

2

.300 – .325

(7.620 – 8.255)

.045 – .065

(1.143 – 1.651)

.130 .005

(3.302 0.127)

.020

(0.508)

MIN

.065

(1.651)

TYP

.008 – .015

(0.203 – 0.381)

+.035

N24 0405

.120

(3.048)

MIN

.018 .003

(0.457 0.076)

.100

(2.54)

BSC

.325

–.015

+0.889

8.255

(

)

–0.381

NOTE:

INCHES

1. DIMENSIONS ARE

MILLIMETERS

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

SW Package

24-Lead Plastic Small Outline (Wide .300 Inch)

(Reference LTC DWG # 05-08-1620)

.050 BSC .045 ±.005

.030 ±.005

TYP

.598 – .614

(15.190 – 15.600)

NOTE 4

N

24 23 22 21 20 19 18

16 15 14 13

17

N

.325 ±.005

.420

MIN

.394 – .419

(10.007 – 10.643)

NOTE 3

1

2

3

N/2

RECOMMENDED SOLDER PAD LAYOUT

.291 – .299

(7.391 – 7.595)

NOTE 4

2

3

5

7

8

9

10

1

4

6

11 12

.037 – .045

.093 – .104

.010 – .029

(0.940 – 1.143)

× 45°

(2.362 – 2.642)

(0.254 – 0.737)

.005

(0.127)

RAD MIN

0° – 8° TYP

.050

(1.270)

BSC

.004 – .012

.009 – .013

(0.102 – 0.305)

NOTE 3

(0.229 – 0.330)

.014 – .019

.016 – .050

(0.356 – 0.482)

TYP

(0.406 – 1.270)

NOTE:

1. DIMENSIONS IN

INCHES

(MILLIMETERS)

S24 (WIDE) 0502

2. DRAWING NOT TO SCALE

3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.

THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

1272fb

LT 0107 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1272-3CCN#TR
厂家：	Linear
描述：	IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP24, 0.300 INCH, PLASTIC, DIP-24, Analog to Digital Converter 转换器模数转换器光电二极管信息通信管理
文件：	总20页 (文件大小：233K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1272-3CCN#TR [Linear]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E