LTC1343IGW#TRPBF [Linear]
LTC1343 - Software-Selectable Multiprotocol Transceiver; Package: SSOP; Pins: 44; Temperature Range: -40°C to 85°C;
| 型号： | LTC1343IGW#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC1343 - Software-Selectable Multiprotocol Transceiver; Package: SSOP; Pins: 44; Temperature Range: -40°C to 85°C |
| 文件： | 总28页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1343
Software-Selectable
Multiprotocol Transceiver
U
FEATURES
DESCRIPTIO
The LTC®1343 is a 4-driver/4-receiver multiprotocol trans-
ceiver that operates from a single 5V supply. Two LTC1343s
form the core of a complete software-selectable DTE or DCE
interface port that supports the RS232, RS449, EIA-530,
EIA-530-A, V.35, V.36 or X.21 protocols. Cable termination
maybeimplementedusingtheLTC1344software-selectable
cable termination chip or by using existing discrete designs.
■
Software-Selectable Transceiver Supports:
RS232, RS449, EIA-530, EIA-530-A, V.35, V.36,
X.21
■
NET1 and NET2 Compliant
■
Software-Selectable Cable Termination Using
the LTC1344
■
4-Driver/4-Receiver Configuration Provides a
Complete 2-Chip DTE or DCE Port
The LTC1343 runs from a single 5V supply using an internal
charge pump that requires only five space saving surface mount
capacitors. The mode pins are latched internally to allow sharing
of the select lines between multiple interface ports.
■
Operates from Single 5V Supply
■
Internal Echoed Clock and Loop-Back Logic
U
APPLICATIO S
Software-selectableechoedclockandloop-backmodeshelp
eliminate the need for external glue logic between the serial
controller and line transceiver. The part features a flow-
througharchitecturetosimplifyEMIshieldingandisavailable
in the 44-lead SSOP surface mount package.
■
Data Networking
■
CSU and DSU
■
Data Routers
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATIO
DTE Multiprotocol Serial Interface with DB-25 Connector
CTS
DSR
DCD
DTR
RTS
RL
TM
RXD
RXC
TXC
SCTE
TXD
D2
LL
LTC1343
D4
LTC1343
D4
D1
D2
D3
D1
D3
R3
R2
R1
R4
R3
R2
R1
R4
LTC1344
13
5
22
6
10
8
23 20 19
4
21
1
7
25 16
3
9
17 12 15
11 24 14
2
18
DB-25 CONNECTOR
1343 TA01
1
LTC1343
W W
U W
U
W U
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
TOP VIEW
Supply Voltage ....................................................... 6.5V
Input Voltage
Transmitters ........................... –0.3V to (VCC + 0.3V)
Receivers............................................... –18V to 18V
Logic Pins .............................. –0.3V to (VCC + 0.3V)
Output Voltage
Transmitters ................. (VEE – 0.3V) to (VDD + 0.3V)
Receivers................................ –0.3V to (VCC + 0.3V)
Logic Pins .............................. –0.3V to (VCC + 0.3V)
VEE........................................................ –10V to 0.3V
VDD ....................................................... –0.3V to 10V
Short-Circuit Duration
Transmitter Output ..................................... Indefinite
Receiver Output.......................................... Indefinite
VEE.................................................................. 30 sec
Operating Temperature Range
ORDER PART
NUMBER
+
V
1
2
3
4
5
6
7
8
9
44 C2
43 C2
DD
+
–
C1
CHARGE PUMP
PWRV
CC
42 V
EE
–
C1
41 PGND
40 GND
39 D1 A
38 D2 A
37 D2 B
36 D3 A
35 D3 B
34 D4 A
33 D4 B
32 R1 A
31 R1 B
30 R2 A
29 R2 B
28 R3 A
27 R3 B
26 R4 A
25 423 SET
24 EC
LTC1343CGW
LTC1343IGW
D1
D2
D3
D1
D2
V
CC
D4
D3
D4EN 10
INVERT 11
R1EN 12
R1O 13
D4
R1
R2O 14
15
16
17
18
19
20
21
22
R3O
R4O
R2
R3
R4
M0
M1
M2
CTRL/CLK
DCE/DTE
LATCH
LTC1343C .............................................. 0°C to 70°C
LTC1343I........................................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
23 LB
GW PACKAGE
44-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 65°C/ W
Consult factory for Military grade parts.
The ● denotes specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V (Notes 2, 3)
SYMBOL PARAMETER
Supplies
CONDITIONS
MIN
TYP
MAX
UNITS
I
V
Supply Current (DCE Mode,
CC
V.10 Mode, No Load
12
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
CC
All Digital Pins = GND or V
)
V.10 Mode, Full Load
●
●
●
150
200
160
CC
RS530, RS530-A, X.21 Modes, No Load
RS530, RS530-A, X.21 Modes, Full Load
V.35 Mode, No Load
80
160
20
V.35 Mode, Full Load
115
20
V.28 Mode, No Load
V.28 Mode, Full Load
●
●
30
90
1
No-Cable Mode
0.05
P
Internal Power Dissipation (DCE Mode,
All Digital Pins = GND or V
V.10 Mode, Full Load
400
680
500
150
mW
mW
mW
mW
D
)
CC
RS530, RS530-A, X.21 Modes, Full Load
V.35 Mode, Full Load
V.28 Mode, Full Load
+
–
V
V
Positive Charge Pump Output Voltage
Negative Charge Pump Output Voltage
Any Mode, No Load
●
●
8.5
8.0
9.1
7.0
V
V
V.28 Mode, with Load
V.28 Mode, Full Load
V.35 Mode, Full Load
●
–7.8
–8.4
–6.7
V
●
●
–5.8
–5.5
V
V
–40°C ≤ T ≤ 85°C
A
V.10, RS530, RS530A, X.21 Modes, Full Load
●
●
–5.0
–4.8
–6.1
V
V
–40°C ≤ T ≤ 85°C
A
2
LTC1343
The ● denotes specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
Supply Rise Time
No-Cable Mode or Power-Up to Turn On
2
ms
r
Logic Inputs and Outputs
V
V
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
●
●
●
●
●
2
V
V
IH
IL
0.8
I
±10
µA
V
IN
V
V
Output High Voltage
I = –4mA
3
4.5
0.3
OH
OL
O
Output Low Voltage
I = 4mA
O
0.8
V
I
Output Short-Circuit Current
0V ≤ V ≤ V , 0°C ≤ T ≤ 70°C
●
●
–60
–70
60
70
mA
mA
OSR
O
CC
A
0V ≤ V ≤ V , –40°C ≤ T ≤ 85°C
O
CC
A
I
Three-State Output Current
Differential Output Voltage
M0 = M1 = M2 = V , 0V ≤ V ≤ V
CC
±1
µA
OZR
CC
O
V.11 Driver
V
Open Circuit, R = 1.95k
●
●
±6
V
V
OD
L
R = 50Ω (Figure 1),
±2
L
OD
V
at 50Ω > 1/2 V at R = 1.95k
OD L
∆V
OD
Change in Magnitude of Differential
Output Voltage
R = 50Ω (Figure 1)
L
●
0.2
V
V
Common Mode Output Voltage
R = 50Ω (Figure 1)
●
●
3.0
0.2
V
V
OC
L
∆V
Change in Magnitude of Common Mode R = 50Ω (Figure 1)
Output Voltage
OC
L
I
I
Short-Circuit Current
–0.25V ≤ V ≤ 0.25V, Power Off or
±150
±100
25
mA
µA
ns
SS
OZ
O
No-Cable Mode or Driver Disabled
Output Leakage Current
–0.25V ≤ V ≤ 0.25V, Power Off or
●
●
±0.01
O
No-Cable Mode or Driver Disabled
t , t
Rise or Fall Time
Input to Output
(Figures 2, 6)
4
13
r
f
t
(Figures 2, 6), 0°C ≤ T ≤ 70°C
●
●
25
25
55
55
80
90
ns
ns
PLH
A
(Figures 2, 6), –40°C ≤ T ≤ 85°C
A
t
Input to Output
(Figures 2, 6), 0°C ≤ T ≤ 70°C
●
●
25
25
55
55
80
90
ns
ns
PHL
A
(Figures 2, 6), –40°C ≤ T ≤ 85°C
A
∆t
Input to Output Difference,
t
– t
PHL
(Figures 2, 6), 0°C ≤ T ≤ 70°C
●
●
0
0
3
3
17
25
ns
ns
PLH
A
(Figures 2, 6), –40°C ≤ T ≤ 85°C
A
t
Output to Output Skew
(Figures 2, 6)
3
ns
SKEW
V.11 Receiver
V
Input Threshold Voltage
–7V ≤ V ≤ 7V, 0°C ≤ T ≤ 70°C
●
●
–0.2
–0.3
0.2
0.3
V
V
TH
CM
A
–7V ≤ V ≤ 7V, –40°C ≤ T ≤ 85°C
CM
A
∆V
TH
Input Hysteresis
–7V ≤ V ≤ 7V, 0°C ≤ T ≤ 70°C
●
●
15
40
60
mV
mV
CM
A
–7V ≤ V ≤ 7V, –40°C ≤ T ≤ 85°C
CM
A
I
Input Current (A, B)
Input Impedance
Rise or Fall Time
Input to Output
–10V ≤ V
≤ 10V
≤ 10V
●
●
±0.50
mA
kΩ
ns
IN
A, B
A, B
R
–10V ≤ V
20
32
15
IN
t , t
(Figures 2, 7)
(Figures 2, 7), CTRL = GND, 0°C ≤ T ≤ 70°C
r
f
t
●
●
35
25
80
400
115
130
ns
ns
PLH
A
CTRL = V , 0°C ≤ T ≤ 70°C
CC
A
(Figures 2, 7), CTRL = GND, –40°C ≤ T ≤ 85°C
80
400
ns
ns
A
CTRL = V , –40°C ≤ T ≤ 85°C
CC
A
3
LTC1343
The ● denotes specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
(Figures 2, 7), CTRL = GND, 0°C ≤ T ≤ 70°C
MIN
TYP
MAX
UNITS
t
Input to Output
●
●
35
80
400
115
ns
ns
PHL
A
CTRL = V , 0°C ≤ T ≤ 70°C
CC
A
(Figures 2, 7), CTRL = GND, –40°C ≤ T ≤ 85°C
25
80
400
130
ns
ns
A
CTRL = V , –40°C ≤ T ≤ 85°C
CC
A
∆t
Input to Output Difference,
Differential Output Voltage
t
– t
(Figures 2, 7), 0°C ≤ T ≤ 70°C
●
●
0
0
5
5
17
25
ns
ns
PLH
PHL
A
(Figures 2, 7), –40°C ≤ T ≤ 85°C
A
V.35 Driver
V
Open Circuit
6.0
±0.66
V
V
OD
With Load, –4.0V ≤ V = 4.0V (Figure 3)
●
●
●
●
±0.44
–12.6
9.4
±0.55
–11
11
CM
I
I
I
Transmitter Output High Current
Transmitter Output Low Current
V
V
= 0V
= 0V
–9.4
12.6
mA
mA
µA
OH
A, B
A, B
OL
OZ
Transmitter Output Leakage Current
Rise or Fall Time
–0.25V ≤ V
≤ 0.25V
±0.01
5
±100
A, B
t , t
r
(Figures 3, 6)
(Figures 3, 6), 0°C ≤ T ≤ 70°C
ns
f
t
Input to Output
●
●
25
25
45
45
75
90
ns
ns
PLH
A
(Figures 3, 6), –40°C ≤ T ≤ 85°C
A
t
Input to Output
(Figures 3, 6), 0°C ≤ T ≤ 70°C
●
●
25
25
45
45
75
90
ns
ns
PHL
A
(Figures 3, 6), –40°C ≤ T ≤ 85°C
A
∆t
Input to Output Difference,
Output to Output Skew
t
– t
PHL
(Figures 3, 6), 0°C ≤ T ≤ 70°C
●
●
0
0
5
5
17
25
ns
ns
PLH
A
(Figures 3, 6), –40°C ≤ T ≤ 85°C
A
t
(Figures 3, 6)
4
ns
SKEW
V.35 Receiver
V
Differential Receiver Input
Threshold Voltage
–2V ≤ (V + V )/2 ≤ 2V (Figure 3)
●
–0.2
20
0.2
V
TH
A
B
∆V
Receiver Input Hysteresis
–2V ≤ (V + V )/2 ≤ 2V (Figure 3)
●
●
●
11
40
mV
mA
kΩ
ns
TH
A
B
I
Receiver Input Current (A, B)
Receiver Input Impedance
Rise or Fall Time
–10V ≤ V
≤ 10V
±0.50
IN
A, B
A, B
R
–10V ≤ V
≤ 10V
32
15
IN
t , t
r
(Figures 3, 7)
(Figures 3, 7), 0°C ≤ T ≤ 70°C
f
t
Input to Output
●
●
80
80
115
130
ns
ns
PLH
A
(Figures 3, 7), –40°C ≤ T ≤ 85°C
A
t
Input to Output
(Figures 3, 7), 0°C ≤ T ≤ 70°C
●
●
100
100
115
130
ns
ns
PHL
A
(Figures 3, 7), –40°C ≤ T ≤ 85°C
A
∆t
Input to Output Difference,
t
– t
PHL
(Figures 3, 7), 0°C ≤ T ≤ 70°C
●
●
4
4
17
25
ns
ns
PLH
A
(Figures 3, 7), –40°C ≤ T ≤ 85°C
A
V.10 Driver
V
Output Voltage
Open Circuit, R = 3.9k
L
±4.0
±3.6
±6.0
V
V
O
L
R = 450Ω (Figure 4)
V at 450Ω > 0.9 V at R = 3.9k
O
O
L
Driver 1 Only
I
I
Short-Circuit Current
V = GND; EIA-530, X.21, EIA-530-A Modes
±150
±100
mA
SS
OZ
O
Output Leakage Current
–0.25V ≤ V ≤ 0.25V, Power Off or
●
±0.1
µA
O
No-Cable Mode or Driver Disabled
t , t
Rise or Fall Time
Input to Output
Input to Output
(Figures 4, 8), R = 450Ω, C = 100pF
r
f
PLH
PHL
L
L
R
= 100k
4
8
8
µs
µs
µs
423SET
t
t
(Figures 4, 8), R = 450Ω, C = 100pF
L
L
R
= 100k
423SET
(Figures 4, 8), R = 450Ω, C = 100pF
L
L
R
= 100k
423SET
4
LTC1343
The ● denotes specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V.10 Receiver
V
Receiver Input Threshold Voltage
0°C ≤ T ≤ 70°C
●
●
–0.2
–0.3
0.2
0.3
V
V
TH
A
–7V ≤ V ≤ 7V, –40°C ≤ T ≤ 85°C
CM
A
∆V
Receiver Input Hysteresis
Receiver Input Current
Receiver Input Impedance
Rise or Fall Time
●
●
●
11
50
mV
mA
kΩ
ns
TH
I
–10V ≤ V ≤ 10V
±0.50
IN
A
R
–10V ≤ V ≤ 10V
20
30
15
IN
A
t , t
(Figures 5, 9)
(Figures 5, 9)
(Figures 5, 9)
r
f
PLH
PHL
t
t
Input to Output
350
350
ns
Input to Output
ns
V.28 Driver
V
Output Voltage
Open Circuit
L
±10
V
V
O
R = 3k (Figure 4)
●
●
●
±5
7.6
I
I
Short-Circuit Current
V = GND
O
±150
±100
mA
SS
OZ
Output Leakage Current
–0.25V ≤ V ≤ 0.25V, Power Off or
±0.01
µA
O
No-Cable Mode or Driver Disabled
SR
Slew Rate
(Figures 4, 8), R = 3k, C = 2500pF
●
●
●
4.0
30.0
2.5
V/µs
µs
L
L
t
t
Input to Output
Input to Output
(Figures 4, 8), R = 3k, C = 2500pF
1.6
1.6
PLH
PHL
L
L
(Figures 4, 8), R = 3k, C = 2500pF
2.5
µs
L
L
V.28 Receiver
V
V
Input Low Threshold Voltage
Input High Threshold Voltage
Receiver Input Hysteresis
Receiver Input Impedance
Rise or Fall Time
●
●
●
●
1.4
1.4
0.4
5
0.8
V
V
THL
TLH
2.0
0.1
3
∆V
1.0
7
V
TH
R
–15V ≤ V ≤ 15V
kΩ
ns
IN
A
t , t
r
(Figures 5, 9)
15
f
t
Input to Output
(Figures 5, 9), CTRL = 0V
CTRL = V
110
330
ns
ns
PLH
●
●
800
800
CC
t
Input to Output
(Figures 5, 9), CTRL = 0V
CTRL = V
170
480
ns
ns
PHL
CC
Note 1: Absolute Maximum Ratings are those beyond which the safety of a
device may be impaired.
Note 3: All typicals are given for V = 5V, C1 = C2 = C
= C
= 1µF,
VDD
CC
VCC
C
= 3.3µF tantalum capacitors and T = 25°C.
VEE A
Note 2: All currents into device pins are positive; all currents out of device
are negative. All voltages are referenced to device ground unless otherwise
specified.
U
U
U
PIN FUNCTIONS
C1– (Pin 4): Capacitor C1 Negative Terminal.
D1 (Pin 5): TTL Level Driver 1 Input.
D2 (Pin 6): TTL Level Driver 2 Input.
VDD (Pin 1): Generated Positive Supply Voltage for
RS232. Connect a 1µF capacitor to ground.
C1+ (Pin 2): Capacitor C1 Positive Terminal. Connect a
1µF capacitor between C1+ and C1–.
D3 (Pin 7): TTL Level Driver 3 Input. Becomes a CMOS
level output when the chip is in the echoed clock mode
(EC = 0V).
PWRVCC (Pin 3): Positive Supply for the Charge Pump.
4.75V ≤ PWRVCC ≤ 5.25V. Tie to VCC (Pin 8) and bypass
with a 1µF capacitor to ground.
5
LTC1343
U
U
U
PIN FUNCTIONS
V
V
CC (Pin 8): Positive Supply for the Transceivers. 4.75V ≤
CC ≤ 5.25V. Tie to PWRVCC (Pin 3).
respective input buffers. The data latch allows the logic
lines to be shared between multiple I/O ports.
D4 (Pin 9): TTL Level Driver 4 Input.
LB (Pin 23): TTL Level Loop-Back Select Input. When low
the chip enters the loop-back configuration and is config-
ured for normal operation when LB is high. The data on LB
is latched when LATCH is high.
D4EN (Pin 10): TTL Level Enable Input for Driver 4. When
high, driver 4 outputs are enabled. When low, driver 4
outputs are forced into a high impedance state. D4EN is
not affected by the LATCH pin.
EC (Pin 24): TTL Level Echoed Clock Select Input. When
low the part enters the echoed clock configuration and is
configured for normal operation when EC is high. The data
on EC is latched when LATCH is high.
INVERT (Pin 11): TTL Level Signal Invert Input. When
high, an extra inverter will be added to the driver 4 and
receiver 1 signal path. The data stream will change polar-
ity, i.e., a 1 becomes 0 and a 0 becomes a 1. When the pin
is low the data flows through with no polarity change.
INVERT is not affected by the LATCH pin.
423 SET (Pin 25): Analog Input Pin for the RS423 Driver
Output Rise and Fall Time Set Resistor. Connect the
resistor from the pin to ground.
R1EN (Pin 12): Logic Level Enable Input for Receiver 1.
When low, receiver 1 output is enabled. When high,
receiver 1 output is forced into a high impedance state.
R4 A (Pin 26): Receiver 4 Inverting Input.
R3 B (Pin 27): Receiver 3 Noninverting Input.
R3 A (Pin 28): Receiver 3 Inverting Input.
R2 B (Pin 29): Receiver 2 Noninverting Input.
R2 A (Pin 30): Receiver 2 Inverting Input.
R1 B (Pin 31): Receiver 1 Noninverting Input.
R1 A (Pin 32): Receiver 1 Inverting Input.
D4 B (Pin 33): Driver 4 Noninverting Output.
D4 A (Pin 34): Driver 4 Inverting Output.
D3 B (Pin 35): Driver 3 Noninverting Output.
D3 A (Pin 36): Driver 3 Inverting Output.
D2 B (Pin 37): Driver 2 Noninverting Output.
D2 A (Pin 38): Driver 2 Inverting Output.
D1 A (Pin 39): Driver 1 Inverting Output.
GND (Pin 40): Signal Ground. Connect to PGND (Pin 41).
R1O (Pin 13): CMOS Level Receiver 1 Output.
R2O (Pin 14): CMOS Level Receiver 2 Output.
R3O (Pin 15): CMOS Level Receiver 3 Output.
R4O (Pin 16): CMOS Level Receiver 4 Output.
M0 (Pin 17): TTL Level Mode Select Input 0. The data on
M0 is latched when LATCH is high.
M1 (Pin 18): TTL Level Mode Select Input 1. The data on
M1 is latched when LATCH is high.
M2 (Pin 19): TTL Level Mode Select Input 2. The data on
M2 is latched when LATCH is high.
CTRL/CLK (Pin 20): TTL Level Mode Select Input. When
the pin is low the chip will be configured for clock and data
signals.Whenthepinishighthechipwillbeconfiguredfor
control signals. The data on CTRL/CLK is latched when
LATCH is high.
PGND (Pin 41): Charge Pump Power Ground. Connect to
the GND (Pin 40).
DCE/DTE (Pin 21): TTL Level Mode Select Input. When
high, the DCE mode is selected. When low the DTE mode
is selected. The data on DCE/DTE is latched when LATCH
is high.
VEE (Pin42):GeneratedNegativeSupplyVoltage.Connect
a 3.3µF capacitor to ground.
C2– (Pin 43): Capacitor C2 Negative Terminal. Connect a
LATCH(Pin22):TTLLevelLogicSignalLatchInput.When
low the input buffers on M0, M1, M2, CTRL/CLK, DCE/
DTE, LB and EC are transparent. When LATCH is pulled
high the data on the logic pins is latched into their
1µF capacitor between C2+ and C2–.
C2+ (Pin 44): Capacitor C2 Positive Terminal. Connect a
1µF capacitor between C2+ and C2–.
6
LTC1343
TEST CIRCUITS
A
R
C
L
L
B
A
50Ω
100pF
B
A
R
R
L
100Ω
C
L
100pF
V
OD
15pF
R
V
OC
L
50Ω
1343 F01
1343 F02
B
Figure 1. RS422 Driver Test Circuit
Figure 2. RS422 Driver/Receiver AC Test Circuit
50Ω
125Ω
50Ω
V
CM
B
B
D
125Ω
R
V
OD
A
A
15pF
50Ω
50Ω
1343 F03
Figure 3. V.35 Driver/Receiver Test Circuit
D
A
D
A
A
R
R
L
C
L
15pF
1343 F04
1343 F04
Figure 4. V.10/V.28 Driver Test Circuit
Figure 5. V.10/V.28 Receiver Test Circuit
W
U
ODE SELECTIO
LTC1343 MODE NAME
V.10, RS423
M2
0
M1
0
M0
0
CTRL/CLK
D1
D2
D3
D4
R1
R2
R3
R4
X
0
1
X
X
0
1
X
X
X
V.10
V.10
V.10
V.10
V.10
V.28
V.28
V.10
V.28
Z
V.10
V.11
V.11
V.11
V.11
V.35
V.28
V.11
V.28
Z
V.10
V.11
V.10
V.11
V.11
V.35
V.28
V.11
V.28
Z
V.10
V.11
V.11
V.11
V.11
V.35
V.28
V.11
V.28
Z
V.10
V.11
V.11
V.11
V.11
V.35
V.28
V.11
V.28
Z
V.10
V.11
V.10
V.11
V.11
V.35
V.28
V.11
V.28
Z
V.10
V.11
V.11
V.11
V.11
V.35
V.28
V.11
V.28
Z
V.10
V.10
V.10
V.10
V.10
V.28
V.28
V.10
V.28
Z
EIA-530-A Clock and Data
EIA-530-A Control
Reserved
0
0
1
0
0
1
0
1
0
X.21
0
1
1
V.35 Clock and Data
V.35 Control
1
0
0
1
0
0
EIA-530, RS449, V.36
V.28, RS232
1
0
1
1
1
0
No Cable
1
1
1
7
LTC1343
U
W
W
SWITCHI G TI E WAVEFOR S
5V
f = 1MHz : t ≤ 10ns : t ≤ 10ns
r
f
1.5V
1.5V
D
0V
t
t
PHL
PLH
B – A
V
O
90%
90%
10%
V
= V(A) – V(B)
DIFF
50%
50%
10%
–V
1/2 V
O
O
t
t
f
r
A
V
O
B
t
t
1343 F06
SKEW
SKEW
Figure 6. V.11, V.35 Driver Propagation Delays
V
B – A
OD2
f = 1MHz : t ≤ 10ns : t ≤ 10ns
INPUT
r
f
0V
t
0V
–V
OD2
t
PLH
PHL
V
R
OH
OUTPUT
1.5V
1.5V
V
OL
1343 F07
Figure 7. V.11, V.35 Receiver Propagation Delays
3V
0V
D
A
1.5V
t
1.5V
PHL
3V
t
PLH
V
O
3V
1343 F08
0V
0V
–3V
–3V
–V
O
t
t
r
f
Figure 8. V.10, V.28 Driver Propagation Delays
V
IH
1.7V
A
1.3V
V
IL
t
PHL
t
PLH
V
OH
2.4V
R
1343 F09
0.8V
V
OL
Figure 9. V.10, V.28 Receiver Propagation Delays
8
LTC1343
U
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APPLICATIONS INFORMATION
Overview
software-selectable cable termination chip or by using
existing discrete designs.
The LTC1343 is a 4-driver/4-receiver multiprotocol trans-
ceiverthatoperatesfromasingle5Vsupply.TwoLTC1343s
form the core of a complete software-selectable DTE or
DCE interface port that supports the RS232, RS449,
EIA-530, EIA-530-A, V.35, V.36 or X.21 protocols. Cable
termination may be implemented using the LTC1344
A complete DCE-to-DTE interface operating in EIA-530
modeisshowninFigure10.ThefirstLTC1343ofeachport
is used to generate the clock and data signals along with
LL (Local Loop-back) and TM (Test Mode). The second
LTC1343isusedtogeneratethecontrolsignalsalongwith
DTE
DCE
LTC1343
D1
LTC1344
LTC1344
LTC1343
R4
SERIAL
SERIAL
CONTROLLER
CONTROLLER
LL
LL
LL
103Ω
103Ω
R3
R2
R1
D4
D2
D3
D4
R1
TXD
TXD
TXD
SCTE
SCTE
SCTE
TXC
RXC
103Ω
103Ω
103Ω
TXC
RXC
TXC
RXC
R2
D3
RXD
TM
RXD
TM
RXD
TM
R3
R4
D2
D1
LTC1343
D1
LTC1343
R4
RL
RL
RL
RTS
RTS
D2
D3
D4
R1
RTS
DTR
R3
R2
R1
D4
DTR
DTR
DCD
DSR
DCD
DSR
DCD
DSR
R2
D3
CTS
RI
R3
R4
D2
D1
CTS
RI
CTS
RI
1343 F10
Figure 10. Complete Multiprotocol Interface in EIA-530 Mode
9
LTC1343
U
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APPLICATIONS INFORMATION
will configure the port for DCE mode when high, and DTE
when low.
RL (Remote Loop-back) and RI (Ring Indicate). The
LTC1344 cable termination chip is used only for the clock
and data signals because they must support V.35 cable
termination. The control signals do not need any external
resistors.
Theinterfaceprotocolmaybeselectedsimplybyplugging
the appropriate interface cable into the connector. The
mode pins are routed to the connector and are left uncon-
nected (1) or wired to ground (0) in the cable as shown in
Figure 11.
Mode Selection
The interface protocol is selected using the mode select
pins M0, M1, M2 and CTRL/CLK (see the Mode Selection
table). The CTRL/CLK pin should be pulled high if the
LTC1343 is being used to generate control signals and
pulled low if used to generate clock and data signals.
The pull-up resistors R1 through R4 will ensure a binary
1whenapinisleftunconnectedandthatthetwoLTC1343s
and the LTC1344 enter the no-cable mode when the cable
is removed. In the no-cable mode the LTC1343 supply
current drops to less than 200µA and all LTC1343 driver
outputs and LTC1344 resistive terminations are forced
into a high impedance state. Note that the data latch pin,
LATCH, is shorted to ground for all chips.
For example, if the port is configured as a V.35 interface,
the mode selection pins should be M2 =1, M1=0, M0 = 0.
For the control signals, CTRL/CLK = 1 and the drivers and
receiverswilloperateinRS232(V.28)electricalmode. For
the clock and data signals, CTRL/CLK = 0 and the drivers
and receivers will operate in V.35 electrical mode, except
for the single-ended driver and receiver which will operate
in the RS232 (V.28) electrical mode. The DCE/DTE pin
The interface protocol may also be selected by the serial
controller or host microprocessor as shown in Figure 12.
The mode selection pins M0, M1, M2 and DCE/DTE can be
shared between multiple interface ports, while each port
21
LATCH
LTC1344
DCE/
DTE M2 M1 M0 (DATA)
22 23 24
1
CONNECTOR
(DATA)
M0
R1, 10k
R2, 10k
R3, 10k
R4, 10k
LTC1343
V
V
V
V
CC
CC
CC
17
18
19
21
20
22
M1
CTRL/CLK
M2
LATCH
NC
CC
DCE/DTE
NC
CABLE
LTC1343
21
19
18
17
DCE/DTE
M2
20
22
CTRL/CLK
LATCH
M1
V
CC
M0
1343 F11
(DATA)
Figure 11: Single Port DCE/V.35 Mode Selection in the Cable
10
LTC1343
U
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APPLICATIONS INFORMATION
remain off even though the signal voltage is beyond the
supply voltage for the FET drivers or the power is off.
PORT #1
M0
M1
Using the LTC1344 along with the LTC1343 solves the
cable termination switching problem. Via software con-
trol, the LTC1344 provides termination for the V.10
(RS423), V.11 (RS422), V.28 (RS232) and V.35 electrical
protocols.
M2
DCE/DTE
LATCH
PORT #2
M0
V.10 (RS423) Interface
M1
A typical V.10 unbalanced interface is shown in Figure 13.
A V.10 single-ended generator output A with ground C is
M2
DCE/DTE
connected to a differential receiver with inputs A
nected to A, and input B connected to the signal return
ground C. The receiver’s ground C is separate from the
' con-
'
'
LATCH
CONTROLLER
signal return. Usually, no cable termination is required for
V.10 interfaces, but the receiver inputs must be compliant
with the impedance curve shown in Figure 14.
PORT #3
M0
M0
M1
M1
M2
M2
BALANCED
INTERCONNECTING
DCE/DTE
DCE/DTE
LATCH 1
LATCH 2
LATCH 3
CABLE
LOAD
GENERATOR
CABLE
TERMINATION
RECEIVER
LATCH
A
C
A'
1343 F12
Figure 12: Mode Selection by the Controller
B
'
'
has a unique data latch signal which acts as a write enable.
When the LATCH pin is low the buffers on the M0, M1, M2,
CTRL/CLK, DCE/DTE, LB and EC pins are transparent.
When the LATCH pin is pulled high the buffers latch the
data and changes on the input pins will no longer affect
the chip.
1343 F13
C
Figure 13. Typical V.10 Interface
I
Z
3.25mA
The mode selection may also be accomplished by using
jumpers to connect the mode pins to ground or VCC.
Cable Termination
–10V
–3V
V
Z
Traditional implementations have included switching re-
sistors with expensive relays, or requiring the user to
change termination modules every time the interface
standard has changed. Custom cables have been used
with the termination in the cable head, or separate termi-
nations are built on the board and a custom cable routes
the signals to the appropriate termination. Switching the
terminations with FETs is difficult because the FETs must
3V
10V
1343 F14
–3.25mA
Figure 14. V.10 Receiver Input Impedance
11
LTC1343
U
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APPLICATIONS INFORMATION
ceiver inputs must also be compliant with the impedance
curve shown in Figure 14.
The V.10 receiver configuration in the LTC1343 and
LTC1344 is shown in Figure 15. In V.10 mode switches S1
and S2 inside the LTC1344 and S3 inside the LTC1343 are
turned off. Switch S4 inside the LTC1343 shorts the
noninverting receiver input to ground so the B input at the
connector can be left floating. The cable termination is
then the 30k input impedance to ground of the LTC1343
V.10 receiver.
In V.11 mode, all switches are off except S1 inside the
LTC1344 which connects a 103Ω differential termination
impedance to the cable as shown in Figure 17.
V.28 (RS232) Interface
A typical V.28 unbalanced interface is shown in Figure 18.
A. V.28 single-ended generator output A with ground C is
V.11 (RS422) Interface
connected to a single-ended receiver with inputs A
nected to A, ground C
ground C.
'
con-
A typical V.11 balanced interface is shown in Figure 16. A
V.11 differential generator with outputs A and B with
ground C is connected to a differential receiver with
' connected via the signal return
In V.28 mode all switches are off except S3 inside the
LTC1343 which connects a 6k (R8) impedance to ground
in parallel with 20k (R5) plus 10k (R6) for a combined
impedance of 5k as shown in Figure 19. The noninverting
input is disconnected inside the LTC1343 receiver and
connected to a TTL level reference voltage for a 1.4V
receiver trip point.
groundC',inputsA'connectedtoA,B'connectedtoB.The
V.11 interface has a differential termination at the receiver
end that has a minimum value of 100Ω. The termination
resistor is optional in the V.11 specification, but for the
highspeedclockanddatalines,theterminationisrequired
to prevent reflections from corrupting the data. The re-
A'
A'
A
A
LTC1343
LTC1343
LTC1344
R5
20k
LTC1344
R5
20k
R1
R1
R8
6k
R8
6k
51.5Ω
51.5Ω
R6
10k
R6
10k
RECEIVER
RECEIVER
S1
S2
S1
S2
S3
S3
R3
124Ω
R3
124Ω
R7
10k
R7
10k
R2
51.5Ω
R2
51.5Ω
R4
20k
R4
20k
B
B
B'
C'
B'
C'
S4
S4
1343 F17
GND
1343 F15
GND
Figure 17. V.11 Receiver Configuration
Figure 15. V.10 Receiver Configuration
BALANCED
BALANCED
INTERCONNECTING
INTERCONNECTING
CABLE
LOAD
GENERATOR
CABLE
LOAD
GENERATOR
CABLE
TERMINATION
CABLE
TERMINATION
RECEIVER
RECEIVER
A
A'
A
A'
100Ω
MIN
B
C
B'
C'
1343 F18
C
C'
1343 F16
Figure 18. Typical V.28 Interface
Figure 16. Typical V.11 Interface
12
LTC1343
U
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APPLICATIONS INFORMATION
A
'
A
'
A
A
LTC1343
LTC1343
LTC1344
R5
20k
LTC1344
R5
20k
R1
R1
R8
6k
R8
6k
51.5Ω
51.5Ω
R6
10k
R6
10k
RECEIVER
RECEIVER
S3
S1
S2
S1
S2
S3
R3
124Ω
R3
124Ω
R7
10k
R7
10k
R2
51.5Ω
R2
51.5Ω
R4
20k
R4
20k
B
B
B'
B'
S4
S4
C'
1343 F19
GND
C'
1343 F21
GND
Figure 19. V.28 Receiver Configuration
Figure 21. V.35 Receiver Configuration
V.35 Interface
The generator differential impedance must be 50Ω to
150Ω and the impedance between shorted terminals (A
and B) and ground C must be 150Ω ±15Ω. For the
generatortermination,switchesS1andS2arebothonand
the top side of the center resistor is brought out to a pin so
it can be bypassed with an external capacitor to reduce
common mode noise as shown in Figure 22.
A typical V.35 balanced interface is shown in Figure 20. A
V.35 differential generator with outputs A and B with
ground C is connected to a differential receiver with
groundC',inputsA'connectedtoA,B'connectedtoB.The
V.35 interface requires a T or delta network termination at
the receiver end and the generator end. The receiver
differentialimpedancemeasuredattheconnectormustbe
100Ω ±10Ω, and the impedance between shorted termi-
Any mismatch in the driver rise and fall times or skew in
the driver propagation delays will force current through
the center termination resistor to ground, causing a high
frequency common mode spike on the A and B terminals.
ThecommonmodespikecancauseEMIproblemsthatare
reduced by capacitor C1 which shunts much of the com-
mon mode energy to ground rather than down the cable.
nals (A' and B) and ground C' must be 150Ω ±15Ω.
InV.35mode,bothswitchesS1andS2insidetheLTC1344
are on, connecting the T network impedance as shown in
Figure 21. Both switches in the LTC1343 are off. The 30k
input impedance of the receiver is placed in parallel with
the T network termination, but does not affect the overall
input impedance significantly.
A
LTC1344
51.5Ω
BALANCED
INTERCONNECTING
S1
ON
CABLE
GENERATOR
LOAD
V.35 DRIVER
S2
ON
124Ω
CABLE
TERMINATION
RECEIVER
51.5Ω
A'
A
B
50Ω
50Ω
C1
100pF
125Ω
125Ω
C
1343 F22
50Ω
50Ω
B
'
B
C
Figure 22. V.35 Driver Using the LTC1344
C'
1343 F20
Figure 20. Typical V.35 Interface
13
LTC1343
U
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APPLICATIONS INFORMATION
Echoed Clock Mode
Loop-Back
The LTC1343 contains the logic to generate the echoed
clock when using a serial controller with only two clock
pins. Figure 23 shows the chip in both the DTE and DCE
echoed clock in EIA-530 mode. The control signals are not
shown. The echoed clock configuration is selected by
pulling the EC pin low. On the DTE side the transmit clock
TXC receiver output is connected to the echoed clock,
SCTE, driver input. The TXC pin on the serial controller is
configuredasaninput. OntheDCEside, thetransmitclock
from the serial controller is used to generate both TXC and
RXC. A phase inverter is placed in the TXC signal path on
both the DTE and DCE side to help correct phase problems
with long cables. If the Invert pin is high, the phase of the
data is inverted.
The LTC1343 contains logic for placing the interface into
a loop-back configuration for testing. Both DTE and DCE
loop-back configurations are supported. Figure 24 shows
a complete DTE interface in the loop-back configuration
with the EC pin pulled high. The loop-back configuration is
selected by pulling the LB pin low. Both the line side and
logic side signals are looped back. The DCE loop-back
configuration is shown in Figure 25.
If the echoed clock mode is selected by pulling EC low, D3
becomesanoutputandisconnectedtoreceiver2’soutput
R3inDTEmodeasshowninFigure26.Intheechoedclock
DCE loop-back mode, driver 4 is connected to driver 3’s
input D3 as shown in Figure 27.
DTE
DCE
LTC1344
SERIAL
LTC1343
LTC1344
LTC1343
SERIAL
CONTROLLER
LL
CONTROLLER
LL
R4
R3
R2
R1
D1
D2
D3
D4
LL
TXD
TXC
RXD
RXC
103Ω
103Ω
TXD
SCTE
INVERT
INVERT
TXC
D4
R1
103Ω
TXC
RXC
D3
D2
R2
R3
R4
103Ω
103Ω
RXC
RXD
TM
RXD
TM
TXD
TM
D1
1343 F23
1
0
1
0
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
0
1
1
0
0
Figure 23. EIA-530 Echoed Clock Configuration
14
LTC1343
U
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APPLICATIONS INFORMATION
SERIAL
LTC1343
LTC1344
LTC1344
LTC1343
SERIAL
CONTROLLER
LL
CONTROLLER
LL
LL
D1
D2
R4
R3
LL
103Ω
103Ω
TXD
TXD
TXD
TXD
SCTE
SCTE
D3
D4
SCTE
R2
R1
SCTE
103Ω
TXC
RXC
TXC
RXC
TXC
RXC
R1
D4
TXC
RXC
D3
R2
103Ω
103Ω
RXD
TM
RXD
TM
RXD
TM
D2
D1
RXD
TM
R3
R4
1
0
1
0
0
0
1
0
1
0
1
0
0
1
0
1 1
0
1
0
1
0
1
0
1
0
LTC1343
LTC1343
RL
RL
D1
RL
R4
RL
RTS
DTR
RTS
DTR
R3
D2
D3
D4
RTS
RTS
DTR
DTR
R2
R1
DCD
DSR
DCD
DSR
R1
DCD
DSR
DCD
DSR
D4
R2
D3
CTS
RI
D2
D1
CTS
RI
R3
R4
CTS
RI
CTS
RI
1343 F24
1343 F25
1
0
1
1
1
0
1
0
1
0
1
1
0
0
1
0
Figure 24. Normal DTE Loop-Back
Figure 25. Normal DCE Loop-Back
15
LTC1343
APPLICATIONS INFORMATION
U
W U U
SERIAL
LTC1343
LTC1344
LTC1344
LTC1343
SERIAL
CONTROLLER
CONTROLLER
LL
LL
D1
D2
R4
R3
LL
LL
103Ω
103Ω
RXD
RXC
TXD
TXC
TXD
TXD
D3
D4
TXCE
SCTE
R2
R1
103Ω
TXC
RXC
TXC
RXC
R1
D4
D3
TXC
R2
103Ω
103Ω
RXC
TXD
TM
RXD
TM
RXD
TM
D2
D1
RXD
TM
R3
R4
1
0
1
0
0
0
0
0
1
0
1
0
0
1
0
1 1
0
1
0
1
0
1
0
0
0
LTC1343
LTC1343
RL
RL
D1
RL
R4
RL
R3
D2
D3
D4
RTS
RTS
DTR
RTS
RTS
DTR
DTR
DTR
R2
R1
DCD
DSR
DCD
DSR
R1
DCD
DSR
DCD
DSR
D4
R2
D3
CTS
RI
D2
D1
CTS
RI
R3
R4
CTS
RI
CTS
RI
1343 F27
1
0
1
1
1
0
1
0
1
0
1
1
0
0
1
0
1343 F26
Figure 26. Echoed Clock, DTE Loop-Back
Figure 27. Echoed Clock, DCE Loop-Back
16
LTC1343
U
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APPLICATIONS INFORMATION
5V
No-Cable Mode
1
2
3
4
8
44
+
–
V
C2
C2
DD
+
+
+
C3
C2
The no-cable mode (M0 = M1 = M2 = 1) is intended for the
case when the cable is disconnected from the connector.
The charge pump, bias circuitry, drivers and receivers are
turned off, the driver outputs are forced into a high
impedancestate, andthesupplycurrentdropstolessthan
200µA. It can also be used to share I/O lines with other
drivers and receivers without loading down the signals.
1µF
+
43
42
41
40
1µF
C1
C1
1µF
LTC1343
CC
PWRV
V
EE
C5
+
C4
1µF
+
3.3µF
–
C1
PGND
GND
V
CC
1343 F28
Charge Pump
Figure 28. Charge Pump
The LTC1343 uses an internal capacitive charge pump to
generate VDD and VEE as shown in Figure 28. A voltage
doubler generates about 8V on VDD and a voltage inverter
generates about –7.5V for VEE. Four 1µF surface mounted
tantalum or ceramic capacitors are required for C1, C2, C3
and C4. The VEE capacitor C5 should be a minimum of
3.3µF. All capacitors are 16V.
100
10
1
Receiver Fail-Safe and Glitch Filter
All LTC1343 receivers feature fail-safe operation in all
modesexceptno-cablemode. Ifthereceiverinputsareleft
floating or shorted together by a termination resistor, the
receiver output will always be forced to a logic high.
External pull-up resistors are required on receiver outputs
if fail-safe operation in the no-cable mode is desired.
0.1
1k
10k
100k
1M
5M
RESISTANCE (Ω)
1343 F29
When the chip is configured for control signals by pulling
the CTRL/CLK pin high, a glitch filter is connected to all
receiver inputs. The filter will reject any glitches at the
receiver inputs less than 300ns.
Figure 29. V.10 Driver Rise and Fall Time vs Resistor Value
V.10 Driver Rise and Fall Times
The rise and fall times of the V.10 drivers is programmed
by placing a 1/8W, 5% resistor between the 423 SET (Pin
25) and ground. The graph of Driver Rise and Fall Times
vs Resistor Value is shown in Figure 29.
LTC1343
39
26
5
21
16
20
24
D1
DCE/DTE
R4
Enabling the Single-Ended Driver and Receiver
V
CC
CTRL/CLK
EC
When the LTC1343 is being used to generate the control
signals(CTRL/CLK=high)andtheECpinispulledlow, the
DCE/DTE pin becomes an enable for driver 1 and receiver
4sotheirinputsandoutputscanbetiedtogetherasshown
in Figure 30.
1343 F30
Figure 30. Single-Ended Driver and Receiver Enable
17
LTC1343
U
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APPLICATIONS INFORMATION
The EC pin has no affect on the configuration when CTRL/
CLK is high except to allow the DCE/DTE pin to become an
enable. When DCE/DTE is low, the driver 1 output is
enabled. The receiver 4 output goes into three-state and
the input presents a 30kΩ load to ground.
drivers and receivers into a high impedance state. In the
DCE mode, the middle two LTC1343s are enabled and the
topandbottomLTC1343sdisabled.Withthisscheme,any
connector pin can be configured for sending or receiving
signals. Note that only one LTC1344 is required.
WhenDCE/DTEishigh,thedriver1outputgoesintothree-
state and the receiver 4 output is enabled. The receiver 4
input presents a 30kΩ load to ground in all modes except
when configured for RS232 operation when the input
impedance is 5kΩ to ground.
Multiprotocol Interface with Ring-Indicate and a
DB-25 Connector
If the RI signal in RS232 mode is implemented, driver 4
and receiver 1 in the control chip can be tied to connector
Pin 22 in order to implement the RI signal in RS232 mode
andDSRBsignalfortheothermodes.Figure35showsthe
DTE configuration and Figure 36 the DCE configuration. In
DCE mode, the DCE/DTE pin should be driven with a logic
signal from the controller that goes low only when the
interface is in the RS232 mode. Since the receiver 4 input
impedance is greater than 30kΩ in all modes except
RS232, it can be enabled at all other times and not load
down the line. When driver 1 is disabled, it remains in a
high impedance state and does not load the line.
DTE vs DCE Operation
TheDCE/DTEpindoesnotallowagivenLTC1343pintobe
reconfigured as a driver or receiver. The DCE/DTE pin only
selects the loop-back topology and acts as an enable for
the single-ended driver and receiver for control signals.
However, theLTC1343canbeconfiguredforeitherDTEor
DCE operation in one of three ways: a dedicated DTE or
DCE port with a connector of appropriate gender, a port
with one connector that can be configured for DTE or DCE
operation by rerouting the signals to the LTC1343 using a
dedicated DTE cable or dedicated DCE cable, or a port with
one connector and one cable using four LTC1343s.
Cable-Selectable Multiprotocol Interface
A cable-selectable multiprotocol DTE/DCE interface is
shown in Figure 37. The control signals LL, RL and TM are
not implemented. The select lines M0, M1 and DCE/DTE
are brought out to the connector. The mode is selected
through the cable by wiring M0 (connector Pin 18), M1
(connector Pin 21) and DCE/DTE (connector Pin 25) to
ground (connector Pin 7) or letting them float. If M0, M1
or DCE/DTE are floating, pull-up resistors R3, R4 and R5
will pull the signals to VCC. The select bit M1 is hard wired
to VCC. When the cable is pulled out, the interface will go
into the no-cable mode.
A dedicated DTE port using a DB-25 male connector is
showninFigure31.Theinterfacemodeisselectedbylogic
outputs from the controller or from jumpers to either VCC
or GND on the mode select pins. A dedicated DCE port
using a DB-25 female connector is shown in Figure 32.
A port with one DB-25 connector that can be configured
for either DTE or DCE operation is shown in Figure 33. The
configuration requires separate cables for proper signal
routing in DTE or DCE operation. For example, in DTE
mode, the TXD signal is routed to connector Pins 2 and 14
via driver 2 in the LTC1343. In DCE mode, driver 2 now
routes the RXD signal to Pins 2 and 14.
Multiprotocol Interface with a µDB-26 Connector
The controller-selectable multiprotocol DTE/DCE inter-
face with a standard µDB-26 connector is shown in Figure
38. The RL, LL and TM signals are implemented and RI is
mapped to Pin 26 on the connector. A cable-selectable
versionisshowninFigure39. TheTMandRLsignalshave
been dropped, but LL is still implemented.
AcombinationDTE/DCEportthatdoesn’trequireseparate
DCE/DTE cables is shown in Figure 34. In DTE mode, the
top and bottom LTC1343s are enabled and the middle two
are placed in the no-cable mode, which forces all of the
18
LTC1343
U
W U U
APPLICATIONS INFORMATION
C6
C7
C8
100pF 100pF 100pF
13
12
3
8
11
LTC1344
V
CC
5V
14
2
21
V
V
LATCH
LATCH
CC
1
2
44
+
+
C2
C3
1µF
43
42
1µF
+
C1
1µF
4
3
8
CHARGE
PUMP
EE
C4
+
DB-25 MALE
CONNECTOR
3.3µF
DCE/
DTE M2 M1 M0
41
+
C5
1µF
LTC1343
D1
5
4
6
7
10 16 15 18 17 19 20 22 23 24
9 1
5
39
18
LL A (141)
LL
TXD
38
37
36
35
34
33
2
14
24
11
TXD A (103)
TXD B
SCTE A (113)
SCTE B
6
7
9
D2
D3
D4
SCTE
10
12
13
15
12
17
9
3
16
32
31
30
29
28
27
TXC A (114)
TXC B
RXC A (115)
RXC B
RXD A (104)
RXD B
TXC
RXC
RXD
TM
R1
R2
R3
R4
14
15
16
20
22
11
25
25
26
21
TM A (142)
DCE
CTRL
19
18
17
LATCH
INVERT
423 SET
M2
M1
M0
R1
100k
40
23
GND
LB
24
44
V
7
1
EC
CC
SGND (102)
1
2
+
+
SHIELD (101)
C10
C11
43
42
1µF
1µF
+
C9
1µF
4
3
8
CHARGE
PUMP
C13
+
3.3µF
V
CC
41
+
C12
1µF
LTC1343
D1
5
21
39
RL
RL A (140)
4
19
20
23
38
37
36
RTS A (105)
RTS B
DTR A (108)
DTR B
6
7
9
D2
D3
D4
RTS
DTR
35
34
33
10
12
13
32
31
30
29
8
10
6
DCD A (109)
DCD B
DSR A (107)
DSR B
CTS A (106)
CTS B
DCD
DSR
CTS
R1
R2
R3
R4
14
22
28
27
5
13
15
16
26
21
19
18
17
24
20
22
11
25
DCE
M2
M1
M0
V
CC
CTRL
1343 F31
LATCH
INVERT
423 SET
LATCH
R2
100k
EC
40
23
GND
LB
LB
M2
M1
M0
Figure 31: Controller-Selectable Multiprotocol DTE Port with DB-25 Connector
19
LTC1343
APPLICATIONS INFORMATION
U
W U U
C6
C7
C8
100pF 100pF 100pF
13
12
3
8
11
LTC1344
V
CC
5V
14
21
V
V
LATCH
LATCH
CC
1
2
44
+
1µF
+
C2
C3
43
42
1µF
+
C1
1µF
2
4
3
8
CHARGE
PUMP
EE
C4
DB-25 FEMALE
CONNECTOR
3.3µF
+
DCE/
DTE M2 M1 M0
41
+
C5
1µF
LTC1343
D1
5
4
6
7
9
10 16 15 18 17 19 20 22 23 24 1
5
39
25
TM A (142)
TM
RXD
RXC
TXC
38
37
36
35
34
33
3
16
17
9
15
12
RXD A (104)
RXD B
RXC A (115)
RXC B
TXC A (114)
TXC B
6
7
9
D2
D3
D4
10
12
13
V
CC
V
CC
32
31
30
29
28
27
R1
R2
R3
R4
24
11
2
SCTE A (113)
SCTE B
TXD A (103)
TXD B
14
15
SCTE
TXD
LL
14
16
20
22
11
25
18
26
21
19
18
17
LL A (141)
DCE
V
CC
CTRL
M2
M1
M0
LATCH
INVERT
423 SET
R1
100k
40
23
GND
LB
24
44
EC
V
CC
7
1
SGND (102)
1
2
+
SHIELD (101)
+
C10
C11
1µF
43
42
1µF
+
C9
1µF
4
3
8
CHARGE
PUMP
C13
+
3.3µF
V
CC
41
+
C12
1µF
LTC1343
D1
5
39
5
13
6
22
8
38
37
36
CTS A (106)
CTS B
DSR A (107)
DSR B
DCD A (109)
DCD B
6
7
9
D2
D3
D4
CTS
DSR
35
34
33
10
DCD
10
12
13
V
CC
32
31
30
29
R1
R2
R3
R4
20
23
DTR A (108)
DTR B
14
15
DTR
CTS
RL
28
27
4
19
RTS A (105)
RTS B
16
20
22
11
25
26
21
19
18
17
21
RL A (140)
DCE
M2
M1
M0
V
CC
V
CC
CTRL
LATCH
LATCH
INVERT
423 SET
1343 F32
R2
100k
40
23
GND
LB
24
LB
EC
M2
M1
M0
Figure 32: Controller-Selectable Multiprotocol DCE Port with DB-25 Connector
20
LTC1343
U
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APPLICATIONS INFORMATION
C6
C7
C8
100pF 100pF 100pF
13
12
3
8
11
LTC1344
V
CC
5V
14
2
21
V
V
LATCH
LATCH
CC
1
2
44
+
+
C2
C3
43
42
1µF
1µF
+
C1
1µF
4
3
8
CHARGE
PUMP
EE
C4
+
DB-25 CONNECTOR
3.3µF
DCE/
DTE M2 M1 M0
41
+
C5
1µF
LTC1343
D1
5
4
6
7
9
10 16 15 18 17 19 20 22 23 24 1
DTE
LL A
DCE
TM A
5
39
18
DTE_LL/DCE_TM
DTE_TXD/DCE_RXD
DTE_SCTE/DEC_RXC
38
37
36
35
34
33
2
14
24
11
TXD A
TXD B
SCTE A
SCTE B
RXD A
RXD B
RXC A
RXC B
6
7
9
D2
D3
D4
10
12
13
32
31
30
29
28
27
15
12
17
9
3
16
TXC A
TXC B
RXC A
RXC B
RXD A
RXD B
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
DTE_TM/DCE_LL
R1
R2
R3
R4
14
15
16
20
22
11
25
25
26
21
19
18
17
TM A
LL A
DCE
CTRL
M2
M1
M0
LATCH
INVERT
423 SET
R1
100k
40
23
GND
LB
24
44
V
7
1
EC
CC
SGND
1
2
+
+
SHIELD
C10
C11
43
42
1µF
1µF
+
C9
1µF
4
3
8
CHARGE
PUMP
C13
+
3.3µF
V
41
CC
+
C12
1µF
LTC1343
D1
5
21
39
DTE_RL/DCE_RL
RL A
RL A
4
19
20
23
38
37
36
RTS A
RTS B
DTR A
DTR B
CTS A
CTS B
DSR A
DSR B
6
7
9
D2
D3
D4
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
35
34
33
10
12
13
32
31
30
29
8
10
6
DCD A
DCD B
DSR A
DSR B
DCD A
DCD B
DTR A
DTR B
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
DTE_CTS/DCE_RTS
R1
R2
R3
R4
14
15
22
28
27
5
13
CTS A
CTS B
RTS A
RTS B
16
20
22
11
25
26
21
19
18
17
DCE
M2
M1
M0
V
CC
CTRL
1343 F33
LATCH
INVERT
423 SET
LATCH
R2
100k
40
23
GND
LB
24
LB
EC
DCE/DTE
M2
M1
M0
Figure 33. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
21
LTC1343
U
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APPLICATIONS INFORMATION
C6
C7
C8
LTC1343
100pF 100pF 100pF
5
6
39
D1
D2
D3
D4
38
37
36
35
34
13
12
3
8
11
7
21
9
DCE
DCE
DCE
DCE
33
10
12
LTC1344
32
31
30
29
13
14
15
16
R1
R2
R3
R4
DCE/
DTE
28
27
5
4
6
7
9
10 16 15 18 17 19 20 22
26
DCE/DTE
DB-25 CONNECTOR
TM A (142)
LTC1343
D1
25
5
6
39
TM
RXD
RXC
TXC
3
16
17
9
15
12
38
37
36
35
34
33
RXD A (104)
RXD B
RXC A (115)
RXC B
TXC A (114)
TXC B
D2
D3
D4
7
21
9
10
12
13
V
32
31
30
29
CC
R1
R2
R3
R4
24
11
2
SCTE A (113)
SCTE B
TXD A (103)
TXD B
14
15
16
SCTE
TXD
LL
28
27
14
18
26
LL A (141)
7
SGND (102)
LTC1343
D1
5
6
39
38
37
36
35
34
33
5
13
6
22
8
10
CTS A (106)
CTS B
DSR A (107)
DSR B
DCD A (109)
DCD B
D2
D3
D4
CTS
DSR
DCD
7
21
9
V
CC
10
12
13
1
32
31
30
29
SHIELD (101)
R1
R2
R3
R4
20
23
4
DTR A (108)
DTR B
RTS A (105)
RTS B
14
15
16
DTR
RTS
RL
28
27
19
26
21
RL A (140)
LTC1343
D1
1343 F34
5
6
39
38
37
36
35
34
33
D2
D3
D4
7
21
9
10
12
13
32
31
30
29
R1
R2
R3
R4
14
15
16
28
27
26
Figure 34. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25
22
LTC1343
U
W U U
APPLICATIONS INFORMATION
C6
C7
C8
100pF 100pF 100pF
13
12
3
8
11
LTC1344
V
CC
5V
14
2
21
V
V
LATCH
LATCH
CC
1
2
44
+
1µF
+
C2
C3
1µF
43
42
+
C1
1µF
4
3
8
CHARGE
PUMP
EE
C4
+
DB-25 MALE
CONNECTOR
3.3µF
DCE/
DTE M2 M1 M0
41
+
C5
1µF
LTC1343
D1
5
4
6
7
9
10 16 15 18 17 19 20 22 23 24
1
5
39
18
LL A (141)
LL
TXD
38
37
36
35
34
33
2
14
24
11
TXD A (103)
TXD B
SCTE A (113)
SCTE B
6
7
9
D2
D3
D4
SCTE
10
12
13
15
12
17
9
3
16
32
31
30
29
28
27
TXC A (114)
TXC B
RXC A (115)
RXC B
RXD A (104)
RXD B
TXC
RXC
RXD
TM
R1
R2
R3
R4
14
15
16
20
22
11
25
25
26
21
TM A (142)
DCE
CTRL
19
18
17
LATCH
INVERT
423 SET
M2
M1
M0
R1
100k
40
23
GND
LB
24
44
EC
V
7
1
CC
SGND (102)
1
2
+
SHIELD (101)
+
C10
C11
43
42
1µF
1µF
+
C9
1µF
4
3
8
CHARGE
PUMP
C13
+
3.3µF
V
CC
41
+
C12
1µF
LTC1343
D1
5
21
39
RL
RL A (140)
4
19
20
23
38
37
36
RTS A (105)
RTS B
DTR A (108)
DTR B
6
7
9
D2
D3
D4
RTS
DTR
35
34
33
10
12
13
32
31
30
29
8
10
6
DCD A (109)
DCD B
DSR A (107)
DSR B/RI A (125)
CTS A (106)
CTS B
DCD
DSR
CTS
RI
R1
R2
R3
R4
14
22
28
27
5
13
15
16
26
21
20
22
11
25
V
DCE
CTRL
CC
1343 F35
LATCH
INVERT
423 SET
LATCH
19
18
17
M2
M1
M0
R2
100k
40
23
GND
LB
24
V
LB
EC
CC
M2
M1
M0
Figure 35. Controller-Selectable Multiprotocol DTE Port with RI and DB-25 Connector
23
LTC1343
APPLICATIONS INFORMATION
U
W U U
C6
C7
C8
100pF 100pF 100pF
13
12
3
8
11
LTC1344
V
CC
5V
14
21
V
V
LATCH
LATCH
CC
1
2
44
+
1µF
+
C2
C3
43
42
1µF
+
C1
1µF
2
4
3
8
CHARGE
PUMP
EE
C4
DB-25 FEMA;E
CONNECTOR
+
3.3µF
DCE/
DTE M2 M1 M0
41
+
C5
1µF
LTC1343
D1
5
4
6
7
9
10 16 15 18 17 19 20 22 23 24 1
5
39
25
TM A (142)
TM
RXD
RXC
TXC
38
37
36
35
34
33
3
16
17
9
15
12
RXD A (104)
RXD B
RXC A (115)
RXC B
TXC A (114)
TXC B
6
7
9
D2
D3
D4
10
12
13
V
CC
V
CC
32
31
30
29
28
27
R1
R2
R3
R4
24
11
2
SCTE A (113)
SCTE B
TXD A (103)
TXD B
14
15
SCTE
TXD
LL
14
16
20
22
11
25
18
26
21
19
18
17
LL A (141)
DCE
V
CC
CTRL
M2
M1
M0
LATCH
INVERT
423 SET
R1
100k
40
23
GND
LB
24
44
EC
V
CC
7
1
SGND (102)
1
2
+
+
SHIELD (101)
C10
C11
1µF
43
42
1µF
+
C9
1µF
4
3
8
CHARGE
PUMP
C13
+
3.3µF
V
CC
41
+
C12
1µF
LTC1343
D1
5
39
RI
5
13
6
22
8
38
37
36
CTS A (106)
CTS B
DSR A (107)
DSR B/RI A (125)
DCD A (109)
DCD B
6
7
9
D2
D3
D4
CTS
DSR
35
34
33
10
DCD
10
12
13
V
CC
32
31
30
29
R1
R2
R3
R4
20
23
DTR A (108)
DTR B
14
15
DTR
CTX
RL
28
27
4
19
RTS A (105)
RTS B
16
20
22
11
25
26
21
19
18
17
21
RL A (140)
DCE
M2
M1
M0
V
CC
RIEN = RS232
CTRL
LATCH
LATCH
INVERT
423 SET
1343 F36
R2
100k
40
23
GND
LB
24
LB
EC
M2
M1
M0
Figure 36. Controller-Selectable Multiprotocol DCE Port with RI and DB-25 Connector
24
LTC1343
U
W U U
APPLICATIONS INFORMATION
C6
C7
C8
100pF 100pF 100pF
13
12
3
8
11
LTC1344
V
CC
5V
14
2
21
V
LATCH
CC
1
2
44
+
1µF
+
C2
C3
43
42
1µF
+
C1
1µF
4
3
8
CHARGE
PUMP
V
EE
C4
+
DB-25 CONNECTOR
3.3µF
DCE/
DTE M2 M1 M0
41
+
C5
1µF
LTC1343
D1
5
4
6
7
9
10 16 15 18 17 19 20 22 23 24 1
5
39
V
DTE
DCE
CC
38
37
36
35
34
33
2
14
24
11
TXD A
TXD B
SCTE A
SCTE B
RXD A
RXD B
RXC A
RXC B
6
7
9
D2
D3
D4
DTE_TXD/DCE_RXD
DTE_SCTE/DEC_RXC
10
12
13
32
31
30
29
28
27
15
12
17
9
3
16
TXC A
TXC B
RXC A
RXC B
RXD A
RXD B
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
R1
R2
R3
R4
14
15
16
20
22
11
25
26
21
19
18
17
DCE
CTRL
7
1
SGND
V
M2
M1
M0
LATCH
INVERT
423 SET
CC
SHIELD
R1
100k
40
23
GND
LB
24
44
EC
V
CC
V
V
V
CC
1
2
CC
CC
+
+
C10
C11
43
42
R3
10k
R4
10k
R5
1µF
+
1µF
C9
10k
4
3
8
25
CHARGE
1µF
C13
+ 3.3µF
DCE/DTE
M1
PUMP
21
18
V
41
CC
+
C12
1µF
M0
LTC1343
D1
5
39
4
19
20
23
38
37
36
RTS A
RTS B
DTR A
DTR B
CTS A
CTS B
DSR A
DSR B
6
7
9
D2
D3
D4
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
35
34
33
10
12
13
32
31
30
29
8
10
6
DCD A
DCD B
DSR A
DSR B
DCD A
DCD B
DTR A
DTR B
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
DTE_CTS/ DCE_RTS
R1
R2
R3
R4
14
15
22
28
27
5
13
CTS A
CTS B
RTS A
RTS B
16
20
22
11
25
26
21
19
18
17
DCE
M2
M1
M0
V
CTRL
CC
1343 F37
V
LATCH
INVERT
423 SET
CC
R2
100k
CABLE WIRING FOR MODE SELECTION
CABLE WIRING FOR DTE/DCE
SELECTION
40
23
GND
LB
MODE
V.35
EIA-530, RS449,
V.36, X.21
RS232
PIN 18
PIN 7
NC
PIN 21
PIN 7
PIN 7
24
MODE
DTE
DCE
PIN 25
PIN 7
NC
LB
EC
PIN 7
NC
Figure 37. Cable-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
25
LTC1343
APPLICATIONS INFORMATION
U
W U U
C6
C7
C8
100pF 100pF 100pF
13
12
3
8
11
LTC1344
V
CC
5V
14
2
21
V
V
LATCH
LATCH
CC
1
2
44
+
1µF
+
C2
C3
43
42
+
1µF
C1
1µF
4
3
8
CHARGE
PUMP
EE
C4
+
µDB-26 CONNECTOR
3.3µF
DCE/
DTE M2 M1 M0
41
+
C5
1µF
LTC1343
D1
5
4
6
7
9
10 16 15 18 17 19 20 22 23 24 1
DTE
LL A
DCE
TM A
5
39
18
DTE_LL/DCE_TM
DTE_TXD/DCE_RXD
DTE_SCTE/DEC_RXC
38
37
36
35
34
33
2
14
24
11
TXD A
TXD B
SCTE A
SCTE B
RXD A
RXD B
RXC A
RXC B
6
7
9
D2
D3
D4
10
12
13
32
31
30
29
28
27
15
12
17
9
3
16
TXC A
TXC B
RXC A
RXC B
RXD A
RXD B
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
DTE_TM/DCE_LL
R1
R2
R3
R4
14
15
16
20
22
11
25
25
26
21
19
18
17
TM A
LL A
DCE
CTRL
M2
M1
M0
LATCH
INVERT
423 SET
R1
100k
40
23
GND
LB
24
44
V
7
1
EC
CC
SGND
1
2
+
+
SHIELD
C10
C11
1µF
43
42
1µF
+
C9
1µF
4
3
8
CHARGE
PUMP
C13
+
3.3µF
V
41
CC
+
C12
1µF
LTC1343
D1
5
21
39
DTE_RL/DCE_RI
RL A
RI A
4
19
20
23
38
37
36
RTS A
RTS B
DTR A
DTR B
CTS A
CTS B
DSR A
DSR B
6
7
9
D2
D3
D4
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
35
34
33
10
12
13
32
31
30
29
8
10
6
DCD A
DCD B
DSR A
DSR B
CTS A
CTS B
DCD A
DCD B
DTR A
DTR B
RTS A
RTS B
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
R1
R2
R3
R4
14
15
22
28
27
5
13
DTE_CTS/DCE_RTS
DTE_RI/DCE_RL
16
20
22
11
25
26
21
19
18
17
26
RI A
RL A
DCE
M2
M1
M0
V
CC
CTRL
LATCH
INVERT
423 SET
LATCH
1343 F38
R2
100k
40
23
GND
LB
24
EC
V
CC
LB
DCE/DTE
M2
M1
M0
Figure 38. Controller-Selectable Multiprotocol DTE/DCE Port with DB-26 Connector
26
LTC1343
U
W U U
APPLICATIONS INFORMATION
C6
C7
C8
100pF 100pF 100pF
13
12
3
8
11
LTC1344
V
CC
5V
14
2
21
V
V
LATCH
CC
1
2
44
+
1µF
+
C2
C3
43
42
1µF
+
C1
1µF
4
3
8
CHARGE
PUMP
EE
C4
+
µDB-26 CONNECTOR
3.3µF
DCE/
DTE M2 M1 M0
41
+
C5
1µF
LTC1343
D1
5
4
6
7
9
10 16 15 18 17 19 20 22 23 24 1
5
39
V
CC
DTE
DCE
38
37
36
35
34
33
2
14
24
11
TXD A
TXD B
SCTE A
SCTE B
RXD A
RXD B
RXC A
RXC B
6
7
9
D2
D3
D4
DTE_TXD/DCE_RXD
DTE_SCTE/DEC_RXC
10
12
13
32
31
30
29
28
27
15
12
17
9
3
16
TXC A
TXC B
RXC A
RXC B
RXD A
RXD B
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
R1
R2
R3
R4
14
15
16
20
22
11
25
26
21
19
18
17
DCE
CTRL
7
1
SGND
V
CC
M2
M1
M0
LATCH
INVERT
423 SET
SHIELD
R1
100k
40
23
GND
LB
24
44
EC
V
CC
V
V
V
CC
1
2
CC
CC
+
+
C10
C11
1µF
43
42
R3
10k
R4
10k
R5
1µF
+
C9
1µF
10k
4
3
8
25
CHARGE
DCE/DTE
M1
C13
+ 3.3µF
PUMP
21
18
V
CC
41
+
C12
1µF
M0
LTC1343
D1
5
39
DTE_LL/DCE_LL
4
19
20
23
38
37
36
RTS A
RTS B
DTR A
DTR B
CTS A
CTS B
DSR A
DSR B
6
7
9
D2
D3
D4
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
35
34
33
10
12
13
32
31
30
29
8
10
6
DCD A
DCD B
DSR A
DSR B
DCD A
DCD B
DTR A
DTR B
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
DTE_CTS/DCE_RTS
R1
R2
R3
R4
14
15
22
28
27
5
13
CTS A
CTS B
RTS A
RTS B
26
16
20
22
11
25
26
21
19
18
17
LL B
LL B
DCE
M2
M1
M0
V
CC
CTRL
V
CC
LATCH
INVERT
423 SET
1343 F39
R2
100k
CABLE WIRING FOR MODE SELECTION
CABLE WIRING FOR DTE/DCE
SELECTION
40
23
GND
LB
MODE
V.35
EIA-530, RS449,
V.36, X.21
RS232
PIN 18
PIN 7
NC
PIN 21
PIN 7
PIN 7
24
MODE
DTE
DCE
PIN 25
PIN 7
NC
LB
EC
PIN 7
NC
Figure 39. Cable-Selectable Multiprotocol DTE Port with DB-26 Connector
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC1343
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
GW Package
44-Lead Plastic SSOP (Wide 0.300)
(LTC DWG # 05-08-1642)
17.805 – 18.059*
(0.701 – 0.711)
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
10.160 – 10.414
(0.400 – 0.410)
7.417 – 7.595**
(0.292 – 0.299)
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
2.286 – 2.387
(0.090 – 0.094)
2.463 – 2.641
(0.097 – 0.104)
0.254 – 0.406
(0.010 – 0.016)
× 45°
0° – 8° TYP
0.127 – 0.292
(0.005 – 0.0115)
0.800
(0.0315)
BSC
0.610 – 1.016
(0.024 – 0.040)
0.231 – 0.3175
(0.0091 – 0.0125)
0.304 – 0.431
(0.012 – 0.017)
NOTE: DIMENSIONS ARE IN MILLIMETERS
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
*
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
G44 SSOP 1098
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1321
Dual RS232/RS485 Transceiver
2 RS232 Driver/Receiver Pairs or 2 RS485 Driver/Receiver Pairs
2 RS232 Driver/Receiver or 4 RS232 Driver/Receiver Pairs
Perfect for Terminating the LTC1343
LTC1334
Single 5V RS232/RS485 Multiprotocol Transceiver
LTC1344/LTC1344A Software-Selectable Cable Terminator
LTC1345
LTC1346A
LTC1543
LTC1544
LTC1545
Single Supply V.35 Transceiver
3 Driver/3 Receiver for Data and Clock Signals
Dual Supply V.35 Transceiver
3 Driver/3 Receiver for Data and Clock Signals
Software-Selectable Multiprotocol Transceiver
Software-Selectable Multiprotocol Transceiver
Software-Selectable Multiprotocol Transceiver
3 Driver/3 Receiver for Data and Clock Signals
4 Driver/4 Receiver for Control Signals Including LL
5 Driver/5 Receiver for Control Signals Including LL, RL, TM
1343fa LT/TP 0899 2K REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1996
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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