LTC1344AC [Linear]
Software-Selectable Cable Terminator; 软件可选的电缆端接
| 型号： | LTC1344AC |
| 厂家： | 
Linear |
| 描述： | Software-Selectable Cable Terminator |
| 文件： | 总12页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1344A
So ftwa re -Se le c ta b le
Ca b le Te rm ina to r
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DESCRIPTION
FEATURES
The LTC®1344A features six software-selectable
multiprotocol cable terminators. Each terminator can be
configured as an RS422 (V.11) 100Ω minimum differen-
tial load, V.35 T-network load or an open circuit for use
with RS232 (V.28) or RS423 (V.10) transceivers that
provide their own termination. When combined with the
LTC1543 and LTC1544, the LTC1344A forms a complete
software-selectable multiprotocol serial port. A data bus
latch feature allows sharing of the select lines between
multiple interface ports.
■
Software-Selectable Cable Termination for:
RS232 (V.28)
RS423 (V.10)
RS422 (V.11)
RS485
RS449
EIA530
EIA530-A
V.35
V.36
X.21
The LTC1344A is similar to the LTC1344 except for a
difference in the Mode Selection table.
■
Outputs Won’t Load the Line with Power Off
U
The LTC1344A is available in a 24-lead SSOP.
APPLICATIONS
■
Data Networking
CSU and DSU
Data Routers
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATION
DTE or DCE Multiprotocol Serial Interface with DB-25 Connector
LL
CTS
DSR
DCD
DTR
RTS
TXC SCTE TXD
RXD
RXC
Daisy-Chained Control Outputs
LTC1543
LTC1544
D2
D1
D3
D4
D2
D1
D3
R3
R2
R1
R4
R3
R2
R1
LTC1344A
18
13
5
10
8
22
6
23 20 19
4
1
7
16
3
9
17
12 15 11 24 14
2
DB-25 CONNECTOR
1344A TA01
1
LTC1344A
W
U
W W
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/O
PACKAGE RDER I FOR ATIO
ABSOLUTE MAXIMUM RATINGS
(Note 1)
TOP VIEW
Positive Supply Voltage (V )................................... 7V
Negative Supply Voltage (V ) ........................... –13.2V
ORDER PART
NUMBER
CC
1
2
M1
24
23
22
21
20
19
18
17
16
15
14
13
M0
EE
M2
V
EE
Input Voltage
LTC1344ACG
LTC1344AIG
3
DCE/DTE
LATCH
R6B
R1C
R1B
R1A
R2A
R2B
R2C
R3A
R3B
R3C
GND
(Logic Inputs) .................... (V – 0.3V) to (V + 0.3V)
EE
CC
4
Input Voltage (Load Inputs).................................. ±18V
Power Dissipation.............................................. 600mW
Operating Temperature Range
LTC1344AC ............................................ 0°C to 70°C
LTC1344AI ......................................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
5
6
R6A
R5A
R5B
7
8
9
R4A
R4B
10
11
12
V
CC
GND
G PACKAGE
24-LEAD PLASTIC SSOP
JMAX = 150°C, θJA = 100°C/W
T
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VCC = 5V ±5%, VEE = –5V ±5%, TA = TMIN to TMAX (Notes 2, 3) unless otherwise noted.
SYMBOL PARAMETER
Supplies
CONDITIONS
MIN
TYP
MAX
UNITS
I
CC
Supply Current
All Digital Pins = GND or V
●
0.4
1.0
mA
CC
Terminator Pins
R
V.35
Differential Mode Impedance
Common Mode Impedance
All Loads (Figure 1), –2V ≤ V ≤ 2V (Commercial)
●
●
90
135
104
153
110
165
Ω
Ω
CM
All Loads (Figure 2), –2V ≤ V ≤ 2V (Commercial)
CM
All Loads (Figure 1), –2V ≤ V ≤ 2V (Industrial)
●
●
90
130
104
153
115
170
Ω
Ω
CM
All Loads (Figure 2), –2V ≤ V ≤ 2V (Industrial)
CM
R
Differential Mode Impedance
All Loads (Figure 1), V = 0V (Commercial)
●
●
●
100
100
104
104
110
115
±50
Ω
Ω
V.11
CM
All Loads (Figure 1), –7V ≤ V ≤ 7V (Commercial)
CM
All Loads (Figure 1), V = 0V (Industrial)
95
100
104
104
Ω
Ω
CM
All Loads (Figure 1), –7V ≤ V ≤ 7V (Industrial)
CM
I
High Impedance Leakage Current
All Loads, –7V ≤ V ≤ 7V
±1
µA
LEAK
CM
Logic Inputs
V
Input High Voltage
Input Low Voltage
Input Current
All Logic Input Pins
All Logic Input Pins
All Logic Input Pins
●
●
●
2
V
V
IH
V
IL
0.8
I
IN
±10
µA
The
●
denotes specifications which apply over the full operating
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are reference to ground unless otherwise
specified.
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 3: All typicals are given at V = 5V, V = –5V, T = 25°C.
CC EE A
2
LTC1344A
W
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TYPICAL PERFORMANCE CHARACTERISTICS
V.11 or V.35 Differential Mode
Impedance vs Supply Voltage
(V )
CC
V.11 or V.35 Differential Mode
V.11 or V.35 Differential Mode
Impedance vs Common Mode
Impedance vs Temperature
Voltage
105
104
103
120
115
T = 25°C
A
T = 25°C
A
108
106
104
102
100
V
= –7V
= –2V
CM
V
CM
110
105
100
V
CM
= 0V
V
= 7V
CM
–40 –20
0
20
40
60
80 100
4.6
4.8
5.0
5.2
5.4
–8 –6 –4 –2
0
2
4
6
8
V
CC
VOLTAGE (V)
TEMPERATURE (°C)
COMMON MODE VOLTAGE (V)
1344 G03
1344 G01
1344 G02
V.11 or V.35 Differential Mode
Impedance vs Negative Supply
V.35 Common Mode Impedance
vs Temperature
V.35 Common Mode Impedance
vs Common Mode Voltage
Voltage (V )
EE
105
104
103
165
160
158
156
154
152
150
T
A
= 25°C
T
= 25°C
A
V
= –2V
CM
155
150
145
V
CM
= 0V
V
= 2V
CM
–5.4
–5.2
V
–5.0
–4.8
–4.6
–40
–20
0
20
40
60
80 100
–2
–1
0
1
2
VOLTAGE (V)
TEMPERATURE (°C)
COMMON MODE VOLTAGE (V)
EE
1344 G04
1344 G05
1344 G06
V.35 Common Mode Inpedance
V.35 Common Mode Impedance
vs Negative Supply Voltage (V )
Supply Current vs Temperature
vs Supply Voltage (V )
EE
CC
500
420
340
260
180
154
153
152
151
150
153
152
151
T
= 25°C
T
= 25°C
A
A
4.6
4.8
5.0
5.2
5.4
–20
0
40
60
80 100
–5.4
–5.2
V
–5.0
–4.8
–4.6
–40
20
V
VOLTAGE (V)
VOLTAGE (V)
TEMPERATURE (°C)
CC
EE
1344 G07
1344 G08
1344 G09
3
LTC1344A
U
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PIN FUNCTIONS
M0 (Pin 1): TTL Level Mode Select Input. The data on M0
is latched when LATCH is high.
R4B (Pin 15): Load 4 Node B.
R4A (Pin 16): Load 4 Node A.
R5B (Pin 17): Load 5 Node B.
R5A (Pin 18): Load 5 Node A.
R6A (Pin 19): Load 6 Node A.
R6B (Pin 20): Load 6 Node B.
V (Pin 2): Negative Supply Voltage Input. Can connect
EE
directly to the LTC1543 V pin. Connect a 1µF capacitor
EE
to ground.
R1C (Pin 3): Load 1 Center Tap.
R1B (Pin 4): Load 1 Node B.
LATCH(Pin21):TTLLevelLogicSignalLatchInput.When
LATCH is low the input buffers on M0, M1, M2 and DCE/
DTE are transparent. When LATCH is high the logic pins
are latched into their respective input buffers. The data
latch allows the select lines to be shared between multiple
I/O ports.
R1A (Pin 5): Load 1 Node A.
R2A (Pin 6): Load 2 Node A.
R2B (Pin 7): Load 2 Node B.
R2C (Pin 8): Load 2 Center Tap.
R3A (Pin 9): Load 3 Node A.
DCE/DTE (Pin 22): TTL Level Mode Select Input. DCE
mode is selected when high and DTE mode when low. The
data on DCE/DTE is latched when LATCH is high.
R2B (Pin 10): Load 2 Node B.
R3C (Pin 11): Load 3 Center Tap.
GND (Pin 12): Ground Connection for Load 1 to Load 3.
GND (Pin 13): Ground Connection for Load 4 to Load 6.
M2 (Pin 23): TTL Level Mode Select Input 1. The data on
M2 is latched when LATCH is high.
M1 (Pin 24): TTL Level Mode Select Input 2. The data on
M1 is latched when LATCH is high.
V (Pin 14): Positive Supply Input. 4.75V ≤ V ≤ 5.25V.
CC
CC
TEST CIRCUITS
C
C
LTC1344A
A
LTC1344A
R1
51.5Ω
R1
51.5Ω
S1
ON
S2
OFF
S1
ON
R3
124Ω
S2
ON
R3
124Ω
Ω
A, B
R2
51.5Ω
R2
51.5Ω
Ω
B
V
±7V OR ±2V
±2V
V
1344 F01
1344 F02
Figure 1. Differential V.11 or V.35 Impedance Measurement
Figure 2. V.35 Common Mode Impedance Measurement
4
LTC1344A
W
U
ODE SELECTIO
LTC1344A
MODE NAME
DCE/DTE
M2
M1
M0
R1
R2
R3
R4
R5
R6
V.10/RS423
RS530A
X
0
0
0
Z
Z
Z
Z
Z
Z
0
1
0
0
0
0
1
1
Z
Z
Z
Z
Z
Z
V.11
Z
V.11
V.11
V.11
V.11
RS530
X.21
0
1
0
0
1
1
0
0
Z
Z
Z
Z
Z
Z
V.11
Z
V.11
V.11
V.11
V.11
0
1
0
0
1
1
1
1
Z
Z
Z
Z
Z
Z
V.11
Z
V.11
V.11
V.11
V.11
V.35
0
1
1
1
0
0
0
0
V.35
V.35
V.35
V.35
Z
V.35
V.35
Z
V.35
V.35
V.35
V.35
RS449/V.36
0
1
1
1
0
0
1
1
Z
Z
Z
Z
Z
Z
V.11
Z
V.11
V.11
V.11
V.11
V.28/RS232
No Cable
X
X
1
1
1
1
0
1
Z
Z
Z
Z
Z
Z
V.11
V.11
V.11
V.11
V.11
V.11
X = don’t care, 0 = logic low, 1 = logic high
C
C
C
A
A
A
LTC1344A
LTC1344A
LTC1344A
R1
51.5Ω
R1
51.5Ω
R1
51.5Ω
S1
ON
S2
OFF
S1
ON
S1
OFF
S2
OFF
R3
124Ω
S2
ON
R3
124Ω
R3
124Ω
R2
51.5Ω
R2
51.5Ω
R2
51.5Ω
B
B
B
V.11 Mode
V.35 Mode
Figure 3. LTC1344A Modes
High-Z Mode
1344 F03
5
LTC1344A
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APPLICATIONS INFORMATION
BALANCED
INTERCONNECTING
CABLE
Multiprotocol Cable Termination
GENERATOR
LOAD
One of the most difficult problems facing the designer of
a multiprotocol serial interface is how to allow the trans-
mitters and receivers for different electrical standards to
share connector pins. In some cases the transmitters and
receivers for each interface standard can be simply tied
together and the appropriate circuitry enabled. But the
biggest problem still remains: how to switch the various
cable termination required by the different standards.
CABLE
TERMINATION RECEIVER
A
C
A'
C'
1344 F04
Figure 4. Typical V.10 Interface
A
Traditional implementations have included switching re-
sistors with expensive relays or requiring the user to
change termination modules every time the interface
standard has changed. Custom cables have been used
with the termination in the cable head. Another method
uses separateterminationbuiltontheboard,andacustom
cable which routes the signals to the appropriate termina-
tion. Switching the termination using FETs is difficult
because the FETs must remain off even though the signal
voltage is beyond the supply voltage for the FET drivers or
the power is off.
V.10
RECEIVER
LTC1344A
51.5Ω
S1
OFF
S2
OFF
Z
Z
124Ω
51.5Ω
B
C
I
Z
3.25mA
–10V
–3V
Z
V
Z
3V
10V
The LTC1344A solves the cable termination switching
problem via software control. The LTC1344A provides
termination for the V.10 (RS423), V.11 (RS422), V.28
(RS232) and V.35 electrical protocols.
–3.25mA
1344 F05
Figure 5. V.10 Interface Using the LTC1344A
V.10 (RS423) Termination
V.11 (RS422) Termination
A typical V.10 unbalanced interface is shown in Figure 4.
A V.10 single-ended generator output A with ground C is
A typical V.11 balanced interface is shown in Figure 6. A
V.11 differential generator with outputs A and B with
ground C is connected to a differential receiver with
connected to a differential receiver with input A
' con-
nected to A and input C connected to the signal return
'
groundC',inputs A' connectedtoA,B' connectedtoB.The
groundC.Usuallynocableterminationis requiredforV.10
interfaces but the receiver inputs must be compliant with
the impedance curve shown in Figure 5.
V.11 interface requires a differential termination at the
receiver end that has a minimum value of 100Ω. The
receiver inputs must also be compliant with the imped-
ance curve shown in Figure 7.
In V.10 mode, both switches S1 and S2 are turned off so
the only cable termination is the input impedance of the
V.10 receiver.
In V.11 mode, switch S1 is turned on and S2 is turned off
so the cable is terminated with a 103Ω impedance.
6
LTC1344A
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APPLICATIONS INFORMATION
BALANCED
BALANCED
INTERCONNECTING
CABLE
INTERCONNECTING
GENERATOR
CABLE
LOAD
CABLE
GENERATOR
LOAD
CABLE
TERMINATION RECEIVER
TERMINATION RECEIVER
A
A'
100Ω
MIN
A
C
A'
C'
B
C
B'
1344 F08
1344 F06
C'
Figure 8. Typical V.28 Interface
Figure 6. Typical V.11 Interface
A
A
V.11
RECEIVER
V.28
RECEIVER
LTC1344A
LTC1344A
51.5Ω
51.5Ω
S1
ON
S2
OFF
S1
OFF
S2
OFF
Z
Z
124Ω
124Ω
5k
51.5Ω
51.5Ω
B
C
B
C
1344 F09
I
Z
Figure 9. V.28 Interface Using the LTC1344A
3.25mA
–10V
–3V
Z
V
Z
3V
10V
V.35 Termination
–3.25mA
1344 F07
A typical V.35 balanced interface is shown in Figure 10. A
V.35 differential generator with outputs A and B with
ground C is connected to a differential receiver with
Figure 7. V.11 Interface Using the LTC1344A
groundC',inputs A' connectedtoA,B' connectedtoB.The
V.28 (RS232) Termination
V.35 interface requires a T-network termination at the
receiver end and the generator end. In V.35 mode both
switches S1 and S2 in the LTC1344A are turned on as
shown in Figure 11.
A typical V.28 unbalanced interface is shown in Figure 8.
A V.28 single-ended generator output A with ground C is
connected to a single-ended receiver with input A
' con-
nected to A, ground C connected via the signal return
'
The differential impedance measured at the connector
ground to C. The V.28 standard requires a 5k terminating
resistor to ground which is included in almost all compli-
ant receivers as shown in Figure 9. Because the termina-
tion is included in the receiver, both switches S1 and S2 in
the LTC1344A are turned off.
must be 100Ω ±10Ω and the impedance between shorted
terminals A' and B' to ground C' must be 150Ω ±15Ω. The
input impedance of the V.35 receiver is connected in
parallel with the T-network inside the LTC1344A, which
could cause the overall impedance to fail the specification
7
LTC1344A
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APPLICATIONS INFORMATION
A
BALANCED
INTERCONNECTING
GENERATOR
CABLE
LOAD
CABLE
LTC1344A
51.5Ω
V.35
DRIVER
TERMINATION RECEIVER
S1
ON
S2
ON
124Ω
A
A'
50Ω
50Ω
51.5Ω
125Ω
125Ω
B
50Ω
50Ω
C1
100pF
B
C
B'
C
1344 F12
1344 F10
C'
Figure 12. V.35 Driver Using the LTC1344A
Figure 10. Typical V.35 Interface
A
The generator differential impedance must be 50Ω to
150Ω and the impedance between shorted terminals A
and B to ground C must be 150Ω ±15Ω. For the generator
termination, switches S1 and S2 are both on and the top
side of the center resistor is brought out to a pin so it can
bebypassedwithanexternalcapacitortoreducecommon
mode noise as shown in Figure 12.
V.35
RECEIVER
LTC1344A
51.5Ω
S1
ON
Z
Z
S2
ON
124Ω
51.5Ω
B
C
Any mismatch in the driver rise and fall times or skew in
the driver propagation delays will force current through
the center termination resistor to ground causing a high
frequency common mode spike on the A and B terminals.
ThecommonmodespikecancauseEMIproblems thatare
reduced by capacitor C1 which shunts much of the com-
mon mode energy to ground rather than down the cable.
I
Z
1mA
–7V
–3V
Z
V
Z
3V
12V
–0.8mA
1344 F11
Figure 11. V.35 Receiver Using the LTC1344A
The LATCH Pin
The LATCH pin (21) allows the select lines (M0, M1, M2
and DCE/DTE) to be shared with multiple LTC1344As,
each with its own LATCH signal. When the LATCH pin is
heldlowtheselectlineinputbuffers aretransparent.When
the LATCH pin is pulled high, the select line input buffers
latch the state of the Select pins so that changes on the
select lines are ignored until LATCH is pulled low again. If
the latch feature is not used, the LATCH pin should be tied
to ground.
if the receiver input impedance is on the low side. All of
Linear Technology’s V.35 receivers meet the RS485 input
impedance specification as shown in Figure 11, which
insures compliance with the V.35 specification when used
with the LTC1344A.
8
LTC1344A
U
TYPICAL APPLICATIONS N
Controller Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
C6
C7
C8
100pF 100pF 100pF
3
8
11 12 13
LTC1344A
LATCH
V
CC
5V
21
14
2
V
CC
1
2
C13
1µF
44
C2
1µF
C3
43
42
1µF
C1
1µF
CHARGE
PUMP
V
EE
4
3
C4
+
3.3µF
41
5
4
6
7
9
10
16 15 18 17 19 20 22 23 24 1
C5
1µF
C12
1µF
8
5
LTC1343
D1
DTE
DCE
18
2
39
DTE_LL/DCE_TM
DTE_TXD/DCE_RXD
DTE_SCTE/DCE_RXC
LL A
TM A
38
37
36
35
34
33
TXD A
TXD B
SCTE A
SCTE B
RXD A
RXD B
RXC A
RXC B
6
7
D2
D3
D4
14
24
11
9
10
12
13
15
12
32
31
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
TXC A
TXC B
RXC A
RXC B
RXD A
RXD B
R1
R2
R3
R4
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
DTE_TM/DCE_LL
30
29
17
9
14
15
28
27
3
16
26
25
7
16
TM A
SG
LL A
20
22
11
25
21
19
18
17
CTRL
DCE
M2
M1
M0
LATCH
INVERT
423SET
1
SHIELD
R1
100k
V
CC
24
40
GND
EC
LB
23
DB-25
CONNECTOR
LB
V
CC
C9, 1µF
28
27
1
2
V
V
CC
EE
C11
V
DD
GND
1µF
C10
1µF
26
4
RTS A
RTS B
DTR A
DTR B
CTS A
3
4
D1
D2
D3
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
25
24
23
19
20
23
CTS B
DSR A
DSR B
5
LTC1544
R1
22
21
20
19
8
10
6
6
7
8
DCD A
DCD B
DSR A
DCD A
DCD B
DTR A
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
DTE_CTS/DCE_RTS
DTE_RL/DCE_RL
R2
R3
22
DSR B
CTS A
CTS B
DTR B
RTS A
RTS B
5
18
17
13
10
9
16
21
R4
D4
RL A
RL A
15
11
12
13
14
INVERT
M0
NC
M1
M2
DCE/DTE
DCE/DTE
M2
1344A TA04
M1
M0
9
LTC1344A
TYPICAL APPLICATIONS N
U
Cable Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
C6
C7
C8
100pF 100pF 100pF
3
8
11 12 13
LTC1344A
V
CC
5V
14
2
21
LATCH
V
CC
C13
1µF
3
1
28
C2
1µF
C3
1µF
27
26
C1
1µF
CHARGE
PUMP
V
EE
2
4
C4
+
3.3µF
25
5
4
6
7
9
10
16 15 18 17 19 20 22 23 24 1
C12
1µF
C5
1µF
DTE
DCE
LTC1543
D1
V
CC
2
24
TXD A
TXD B
RXD A
RXD B
5
6
DTE_TXD/DCE_RXD
DTE_SCTE/DCE_RXC
23
22
14
24
SCTE A RXC A
SCTE B RXC B
D2
11
21
7
8
D3
R1
20
19
18
17
16
15
15
12
TXC A
TXC B
RXC A
RXC B
RXD A
RXD B
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
17
9
9
R2
R3
3
10
11
12
13
14
16
7
M0
M1
M2
SG
NC
1
SHIELD
DCE/DTE
DB-25
CONNECTOR
V
CC
25
21
18
C9, 1µF
28
27
DCE/DTE
1
2
V
V
CC
EE
M1
M0
C11
1µF
V
DD
GND
C10
1µF
26
4
RTS A
RTS B
DTR A
DTR B
CTS A
CTS B
DSR A
DSR B
3
4
5
D1
D2
D3
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
25
24
23
19
20
23
LTC1544
22
21
20
19
8
10
6
6
7
8
DCD A
DCD B
DSR A
DCD A
DCD B
DTR A
R1
R2
R3
R4
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
DTE_CTS/DCE_RTS
22
DSR B
CTS A
CTS B
DTR B
RTS A
RTS B
5
18
17
13
10
9
16
CABLE WIRING FOR MODE SELECTION
CABLE WIRING FOR
DTE/DCE SELECTION
MODE
V.35
PIN 18
PIN 7
NC
PIN 21
PIN 7
PIN 7
NC
D4
MODE
DTE
PIN 25
11
12
13
14
PIN 7
NC
RS449, V.36
RS232
M0
M1
M2
DCE
PIN 7
NC
15
NC
INVERT
DCE/DTE
1344A TA05
10
LTC1344A
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
G Package
24-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.318 – 0.328*
(8.07 – 8.33)
24 23 22 21 20 19 18 17 16 15 14
13
0.301 – 0.311
(7.65 – 7.90)
5
7
8
1
2
3
4
6
9 10 11 12
0.205 – 0.212**
(5.20 – 5.38)
0.068 – 0.078
(1.73 – 1.99)
0° – 8°
0.0256
(0.65)
BSC
0.005 – 0.009
(0.13 – 0.22)
0.022 – 0.037
(0.55 – 0.95)
0.002 – 0.008
(0.05 – 0.21)
0.010 – 0.015
(0.25 – 0.38)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
G24 SSOP 0595
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofits circuits as describedhereinwillnotinfringeonexistingpatentrights.
11
LTC1344A
U
TYPICAL APPLICATIO
Figure 13 shows a typical application for the LTC1344A DCE/DTE are shared by both chips. Each driver output and
using the LTC1543 mixed mode transceiver chip to gener-
ate the clock and data signals for a serial interface. The
receiver input is connected to one of the LTC1344A
termination ports. Each electrical protocol can then be
chosen using the digital select lines.
LTC1344A V supply is generated from the LTC1543
EE
charge pump and the select lines M0, M1, M2 and
100pF
100pF
100pF
3
11 12
13
8
1
M0
M0
24
23
M1
M2
M1
M2
LTC1344A
22
21
DCE/DTE
DCE/DTE
LATCH
V
CC
V
EE
9
18
19
5
4
6
7
10
16 15
17
20
14
2
C1
1µF
C2
3.3µF
4
26
LTC1543
M0
11
12
13
14
M1
M2
DCE/DTE
DTE
TXD
DCE
RXD
24
+
+
5
6
7
23
22
–
–
TXD
RXD
+
–
+
SCTE
RXC
21
–
SCTE
RXC
20
+
+
TXC
TXC
8
9
19
18
–
–
TXC
TXC
+
+
RXC
SCTE
17
16
–
–
RXC
SCTE
TXD
+
+
RXD
10
15
–
–
RXD
TXD
1344 F13
Figure 13. Typical Application Using the LTC1344A
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
2 RS485 Dr/Rx or 4 RS232 Dr/Rx Pairs
LTC1334
Single Supply RS232/RS485 Transceiver
Multiprotocol Serial Transceiver
Single Supply V.35 Transceiver
Dual Supply V.35 Transceiver
LTC1343
Software Selectable Mulitprotocol Interface
3 Dr/3 Rx for Data and CLK Signals
3 Dr/3 Rx for Data and CLK Signals
LTC1345
LTC1346A
LTC1543
Multiprotocol Serial Transceiver
Multiprotocol Serial Transceiver
Software-Selectable Transceiver for Data and CLK Signals
Software-Selectable Transceiver for Control Signals
LTC1544
1344af, sn1344a LT/TP 0898 4K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
12
●
●
LINEAR TECHNOLOGY CORPORATION 1998
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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