LTC1403CMSE-1#TRPBF_技术文档

LTC1403-1/LTC1403A-1

Serial 12-Bit/14-Bit, 2.8Msps

Sampling ADCs with Shutdown

FEATURES

DESCRIPTION

The LTC^®1403-1/LTC1403A-1 are 12-bit/14-bit, 2.8Msps

serial ADCs with differential inputs. The devices draw only

4.7mA from a single 3V supply and come in a tiny 10-lead

n

2.8Msps Conversion Rate

n

Low Power Dissipation: 14mW

n

3V Single Supply Operation

n

MSE package. A Sleep shutdown feature lowers power

consumption to 10µW. The combination of speed, low

powerandtinypackagemakestheLTC1403-1/LTC1403A-1

suitable for high speed, portable applications.

2.5V Internal Bandgap Reference Can Be Overdriven

n

3-Wire Serial Interface

n

Sleep (10µW) Shutdown Mode

n

Nap (3mW) Shutdown Mode

n

80dB Common Mode Rejection

The80dBcommonmoderejectionallowsuserstoeliminate

ground loops and common mode noise by measuring

signals differentially from the source.

n

1.25V Bipolar Input Range

n

Tiny 10-Lead MSE Package

The devices convert –1.25V to 1.25V bipolar inputs

+

differentially. The absolute voltage swing for A

IN

and

IN

APPLICATIONS

–

A

extends from ground to the supply voltage.

n

Communications

Theserialinterfacesendsouttheconversionresultsduring

the16clockcyclesfollowingCONV forcompatibilitywith

standard serial interfaces. If two additional clock cycles

for acquisition time are allowed after the data stream in

between conversions, the full sampling rate of 2.8Msps

can be achieved with a 50.4MHz clock.

n

Data Acquisition Systems

↑

n

Uninterrupted Power Supplies

n

Multiphase Motor Control

n

Multiplexed Data Acquisition

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners.

BLOCK DIAGRAM

THD, 2nd and 3rd vs Input

10µF 3V

Frequency for Differential Input

Signals

–44

7

V

LTC1403A-1

DD

–50

–56

–62

+

–

THREE-

STATE

SERIAL

OUTPUT

PORT

A

IN

1

2

+

14-BIT ADC

SDO

S & H

8

–68

–74

IN

–

THD 3rd

2nd

14

–80

–86

V

REF

3

4

10

9

CONV

SCK

2.5V

REFERENCE

TIMING

LOGIC

–92

10µF

GND

5

–98

–104

14031 TA01a

0.1

1

10

100

6

11

EXPOSED PAD

FREQUENCY (MHz)

14031 TA01b

14031fd

1

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Notes 1, 2)

Supply Voltage (V ) .................................................4V

DD

Analog Input Voltage

TOP VIEW

+

–

(Note 3) ...................................–0.3V to (V + 0.3V)

A

1

2

3

4

5

10 CONV

IN

DD

9

8

7

6

SCK

SDO

DD

GND

Digital Input Voltage .................. – 0.3V to (V + 0.3V)

V

11

DD

REF

GND

V

Digital Output Voltage ..................–0.3V to (V + 0.3V)

Power Dissipation...............................................100mW

MSE PACKAGE

10-LEAD PLASTIC MSOP

Operation Temperature Range

T

JMAX

= 125°C, θ = 40°C/ W

JA

LTC1403C-1/LTC1403AC-1....................... 0°C to 70°C

LTC1403I-1/LTC1403AI-1 .....................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)...................300°C

EXPOSED PAD (PIN 11) IS GND MUST BE SOLDERED TO PCB

http://www.linear.com/product/LTC1403-1#orderinfo

ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING

LTBGP

PACKAGE DESCRIPTION

10-Lead Plastic MSOP

TEMPERATURE RANGE

LTC1403CMSE-1#PBF

LTC1403IMSE-1#PBF

LTC1403ACMSE-1#PBF

LTC1403AIMSE-1#PBF

LTC1403CMSE-1#TRPBF

LTC1403IMSE-1#TRPBF

LTC1403ACMSE-1#TRPBF

LTC1403AIMSE-1#TRPBF

0°C to 70°C

LTBGQ

–40°C to 85°C

0°C to 70°C

LTBGR

LTBGS

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

The l denotes the specifications which apply over the full operating

CONVERTER CHARACTERISTICS

temperature range, otherwise specifications are at T_A= 25°C. With internal reference. V_DD= 3V

LTC1403-1

TYP

LTC1403A-1

PARAMETER

CONDITIONS

MIN

12

MAX

MIN

14

TYP

MAX

UNITS

Bits

l

Resolution (No Missing Codes)

Integral Linearity Error

Offset Error

(Notes 4, 5, 18)

(Notes 4, 18)

(Note 4, 18)

–2

0.25

1

2

–4

0.5

2

4

LSB

–10

–30

10

30

–20

–60

20

60

LSB

Gain Error

5

10

LSB

Gain Tempco

Internal Reference (Note 4)

External Reference

15

1

15

1

ppm/°C

ANALOG INPUT^Thel denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 25°C. V_DD= 3V

SYMBOL PARAMETER

CONDITIONS

2.7V ≤ V ≤ 3.3V

MIN

TYP

MAX

UNITS

l

V

Analog Differential Input Range (Notes 3, 8, 9)

–1.25 to 1.25

V

IN

DD

Analog Common Mode + Differential

Input Range (Note 10)

0 to V

CM

DD

l

I

Analog Input Leakage Current

Analog Input Capacitance

1

µA

pF

IN

C

13

IN

14031fd

2

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

ANALOG INPUT^Thel denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 25°C. V_DD= 3V

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

ns

l

t

Sample-and-Hold Acquisition Time

(Note 6)

39

ACQ

AP

Sample-and-Hold Aperture Delay Time

Sample-and-Hold Aperture Delay Time Jitter

Analog Input Common Mode Rejection Ratio

1

ns

0.3

ps

JITTER

CMRR

f

IN

f

IN

= 1MHz, V = 0V to 3V

= 100MHz, V = 0V to 3V

–60

–15

dB

IN

DYNAMIC ACCURACY

V_CM= 1.5V at A_INand A_IN

The l denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. V_DD= 3V. Single-ended A_IN⁺signal drive with A_IN^–= 1.5V DC. Differential signal drive with

+

–

LTC1403-1

TYP

LTC1403A-1

Symbol

PARAMETER

CONDITIONS

MIN

MAX

MIN

TYP

MAX

UNITS

SINAD

Signal-to-Noise Plus

Distortion Ratio

100kHz Input Signal (Note 19)

1.4MHz Input Signal (Note 19)

70.5

72

73.5

76.3

dB

l

68

70

100kHz Input Signal, External V = 3.3V,

REF

V

≥ 3.3V (Note 19)

DD

750kHz Input Signal, External V = 3.3V,

72

76.3

dB

REF

V

≥ 3.3V (Note 19)

DD

THD

SFDR

IMD

Total Harmonic

Distortion

100kHz First 5 Harmonics (Note 19)

1.4MHz First 5 Harmonics (Note 19)

–87

–83

–90

–86

dB

l

–76

–78

Spurious Free

Dynamic Range

100kHz Input Signal (Note 19)

1.4MHz Input Signal (Note 19)

–87

–83

–90

–86

dB

Intermodulation

Distortion

0.625V 1.4MHz Summed with 0.625V

–82

dB

P-P

+

–

1.56MHz into A and Inverted into A

IN

Code-to-Code

Transition Noise

V

REF

= 2.5V (Note 18)

0.25

1

LSB

RMS

Full Power Bandwidth

Full Linear Bandwidth

V

= 2.5V , SDO = 11585LSB (Note 15)

50

5

50

5

MHz

IN

P-P

S/(N + D) ≥ 68dB

INTERNAL REFERENCE CHARACTERISTICS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. V_DD= 3V

PARAMETER

CONDITIONS

I = 0

OUT

MIN

TYP

2.5

15

MAX

UNITS

V

REF

V

REF

V

REF

V

REF

V

REF

Output Voltage

Output Tempco

Line Regulation

Output Resistance

Settling Time

ppm/°C

µV/V

Ω

V

DD

= 2.7V to 3.6V, V = 2.5V

600

0.2

2

REF

Load Current = 0.5mA

ms

14031fd

3

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

DIGITAL INPUTS AND DIGITAL OUTPUTS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. V_DD= 3V

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

V

= 3.3V

= 2.7V

2.4

V

IH

IL

DD

IN

0.6

10

I

= 0V to V

µA

pF

V

IN

DD

C

V

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

(Note 20)

5

IN

l

V

= 3V, I = –200µA

OUT

2.5

2.9

OH

OL

DD

V

= 2.7V, I

= 160µA

= 1.6mA

0.05

0.10

V

DD

OUT

l

0.4

10

I

Hi-Z Output Leakage D

V

= 0V to V

DD

µA

pF

OZ

OUT

C

Hi-Z Output Capacitance D

1

OZ

OUT

I

Output Short-Circuit Source Current

Output Short-Circuit Sink Current

V

= 0V, V = 3V

20

15

mA

SOURCE

SINK

OUT

DD

I

= V = 3V

DD

The l denotes the specifications which apply over the full operating temperature

POWER REQUIREMENTS

range, otherwise specifications are at T_A= 25°C. (Note 17)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

DD

Supply Voltage

2.7

3.6

V

l

I

DD

Positive Supply Voltage

Active Mode

4.7

1.1

2

7

mA

µA

Nap Mode

1.5

15

10

Sleep Mode (LTC1403-1)

Sleep Mode (LTC1403A-1)

2

µA

P

Power Dissipation

Active Mode with SCK in Fixed State (Hi or Lo)

12

mW

D

TIMING CHARACTERISTICS

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. V_DD= 3V

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

f

Maximum Sampling Frequency per Channel

(Conversion Rate)

2.8

MHz

SAMPLE(MAX)

l

t

Minimum Sampling Period (Conversion + Acquisition Period)

Clock Period

357

ns

THROUGHPUT

(Note 16)

19.8

17

2

10000

ns

SCK

Conversion Time

(Note 6)

18

SCLK cycles

CONV

Minimum Positive or Negative SCLK Pulse Width

CONV to SCK Setup Time

(Note 6)

ns

ms

1

(Notes 6, 10)

(Note 6)

3

2

Nearest SCK Edge Before CONV

Minimum Positive or Negative CONV Pulse Width

SCK to Sample Mode

0

3

(Note 6)

4

(Note 6)

4

5

CONV to Hold Mode

(Notes 6, 11)

(Notes 6, 7, 13)

(Notes 6, 12)

(Notes 6, 14)

1.2

45

6

↑

16th SCK to CONV Interval (Affects Acquisition Period)

Minimum Delay from SCK to Valid Data

SCK to Hi-Z at SDO

7

8

6

8

9

Previous SDO Bit Remains Valid After SCK

2

10

12

V

REF

Settling Time After Sleep-to-Wake Transition

2

14031fd

4

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns)

because the 2.2ns delay through the sample-and-hold is subtracted from

the CONV to Hold mode delay.

Note 12: The rising edge of SCK is guaranteed to catch the data coming

Note 2: All voltage values are with respect to GND.

out into a storage latch.

Note 3: When these pins are taken below GND or above V , they will be

clamped by internal diodes. This product can handle input currents greater

Note 13: The time period for acquiring the input signal is started by the

16th rising clock and it is ended by the rising edge of convert.

DD

than 100mA below GND or greater than V without latchup.

DD

Note 14: The internal reference settles in 2ms after it wakes up from Sleep

Note 4: Offset and full-scale specifications are measured for a single-

mode with one or more cycles at SCK and a 10µF capacitive load.

Note 15: The full power bandwidth is the frequency where the output code

+

–

ended A input with A grounded and using the internal 2.5V reference.

IN

Note 5: Integral linearity is tested with an external 2.55V reference and is

defined as the deviation of a code from the straight line passing through

the actual endpoints of a transfer curve. The deviation is measured from

the center of quantization band.

Note 6: Guaranteed by design, not subject to test.

Note 7: Recommended operating conditions.

swing drops to 3dB with a 2.5V input sine wave.

Note 16: Maximum clock period guarantees analog performance during

conversion. Output data can be read without an arbitrarily long clock.

P-P

Note 17: V = 3V, f

= 2.8Msps.

SAMPLE

DD

Note 18: The LTC1403A-1 is measured and specified with 14-bit

Resolution (1LSB = 152µV) and the LTC1403-1 is measured and specified

with 12-bit Resolution (1LSB = 610µV).

Note 19: Full-scale sinewaves are fed into the noninverting input while the

inverting input is kept at 1.5V DC.

Note 8: The analog input range is defined for the voltage difference

+

–

between A and A . Performance is specified with A = 1.5V DC while

IN

+

IN

driving A

.

IN

+

–

Note 9: The absolute voltage at A and A must be within this range.

IN

Note 20: The sampling capacitor at each input accounts for 4.1pF of the

Note 10: If less than 3ns is allowed, the output data will appear one

clock cycle later. It is best for CONV to rise half a clock before SCK, when

running the clock at rated speed.

input capacitance.

14031fd

5

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, V}_DD= 3V. Single ended A_IN⁺signal drive

with A_IN^–= 1.5V DC, differential signals drive both inputs with V_CM= 1.5V DC (LTC1403A-1)

ENOBs and SINAD

vs Input Frequency

THD, 2nd and 3rd vs Input

Frequency

SFDR vs Input Frequency

12.0

11.5

11.0

10.5

10.0

9.5

74

71

68

65

62

59

56

53

50

–44

–50

–56

–62

104

98

92

86

80

74

68

62

56

50

44

–68

–74

THD

3rd

–80

–86

2nd

9.0

–92

8.5

–98

–104

8.0

0.1

1

10

100

0.1

1

10

100

0.1

1

10

100

FREQUENCY (MHz)

14031 G02

14031 G01

14031 G03

ENOBs and SINAD vs Input

Frequency for Differential Input

Signals

THD, 2nd and 3rd vs Input

Frequency for Differential Input

Signals

SNR vs Input Frequency

–44

–50

–56

–62

74

71

68

65

62

59

56

53

50

12.0

11.5

11.0

10.5

10.0

9.5

74

71

68

65

62

59

56

53

50

–68

–74

THD 3rd

2nd

–80

–86

9.0

–92

8.5

–98

–104

8.0

0.1

1

10

100

0.1

1

10

100

0.1

1

10

100

FREQUENCY (MHz)

14031 G19

14031 G04

14031 G18

SFDR vs Input Frequency for

Differential Input Signals

98kHz Sine Wave 4096 Point

FFT Plot

1.3MHz Sine Wave 4096 Point

FFT Plot

104

98

92

86

80

74

68

62

56

50

44

0

–10

–20

0

–10

–20

–30

–40

–50

–30

–40

–50

–60

–70

–80

–90

–60

–70

–80

–90

–100

–110

–120

–100

–110

–120

0.1

1

10

100

0

350

700k

1.05M

1.4M

0

350k

700k

1.05M

1.4M

FREQUENCY (MHz)

FREQUENCY (Hz)

14031 G20

14031 G05

14031 G06

14031fd

6

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

T_A= 25°C, V_DD= 3V. Single ended A_IN⁺signal drive

TYPICAL PERFORMANCE CHARACTERISTICS

with A_IN^–= 1.5V DC, differential signals drive both inputs with V_CM= 1.5V DC (LTC1403A-1)

1.4MHz Input Summed with

1.56MHz Input IMD 4096 Point FFT

Plot for Differential Input Signals

1.3MHz Sine Wave 4096 Point

FFT Plot for Differential Input

Signals

10.7MHz Sine Wave 4096 Point

FFT Plot for Differential Input

Signals

0

–10

0

–10

–20

0

–10

–20

–30

–40

–50

–30

–40

–50

–40

–50

–60

–70

–60

–70

–80

–90

–100

–110

–120

–100

–110

–100

–110

–120

0

200k 400k 600k 800k 1M 1.2M 1.4M

0

350

700k

1.05M

1.4M

0

350

700k

1.05M

1.4M

FREQUENCY (Hz)

14031 G07

14031 G21

14031 G22

Differential Linearity

vs Output Code

Integral Linearity

vs Output Code

Integral Linearity vs Output Code

for Differential Input Signals

4

3

1.0

0.8

4

3

0.6

2

0.4

1

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1

–2

–3

–4

–1

–2

–3

–4

0

8192

12288

0

8192

12288

0

8192

12288

4096

16384

4096

16384

4096

16384

OUTPUT CODE

14071 G23

14031 G08

14071 G09

Differential and Integral Linearity

vs Conversion Rate

SINAD vs Conversion Rate

78

77

76

75

74

73

72

71

70

69

68

8

7

18 CLOCKS PER CONVERSION

6

5

4

MAX INL

3

2

MAX DNL

MIN DNL

1

0

–1

–2

–3

–4

EXTERNAL V

INTERNAL V

= 3.3V f ~ f /3

IN S

REF

= 3.3V f ~ f /40

IN

S

MIN INL

= 2.5V f ~ f /3

IN S

= 2.5V f ~ f /40

IN

S

2

2.25 2.5 2.75

3

3.25 3.5 3.75

4

2

2.25 2.5 2.75

3

3.25 3.5 3.75

4

CONVERSION RATE (Msps)

14031 G11

14031 G10

14031fd

7

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, V}_DD= 3V (LTC1403-1 and LTC1403A-1)

2.5V_P-PPower Bandwidth

CMRR vs Frequency

PSRR vs Frequency

–25

–30

–35

–40

–45

–50

–55

–60

–65

–70

12

6

0

–20

0

–40

–6

–12

–18

–60

–80

–24

–30

–36

–100

–120

1

10

100

1k

10k 100k

1M

10M

100M

1G

100

10k

100k 1M

10M 100M

1k

FREQUENCY (Hz)

14031 G14

14031 G12

14031 G13

Reference Voltage vs Load

Current

V_DDSupply Current vs

Conversion Rate

Reference Voltage vs V_DD

2.4902

2.4900

2.4898

2.4896

2.4894

2.4892

2.4890

2.4902

2.4900

2.4898

2.4896

2.4894

2.4892

2.4890

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

LOAD CURRENT (mA)

2.6

2.8

3.0

3.2

(V)

3.4

3.6

0

0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0

CONVERSION RATE (Msps)

V

DD

14031 G15

14031 G16

14031 G17

14031fd

8

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

PIN FUNCTIONS

IN

+

A

(Pin 1): Noninverting Analog Input. A operates

solid analog ground plane with a 10µF ceramic capacitor

(or 10µF tantalum in parallel with 0.1µF ceramic). Keep in

mindthatinternalanalogcurrentsanddigitaloutputsignal

currents flow through this pin. Care should be taken to

place the 0.1µF bypass capacitor as close to Pins 6 and

7 as possible.

IN

–

fully differentially with respect to A with a –1.25V to

IN

–

1.25V differential swing with respect to A and a 0V to

IN

V

DD

common mode swing.

–

A

(Pin 2): Inverting Analog Input. A operates fully

IN

+

differentially with respect to A with a 1.25V to –1.25V

IN

+

differential swing with respect to A and a 0V to V

SDO (Pin 8): Three-State Serial Data Output. Each of

IN

DD

common mode swing.

output data words represents the difference between

+

–

A

and A analog inputs at the start of the previous

IN

V

REF

(Pin 3): 2.5V Internal Reference. Bypass to GND

conversion. The output format is 2’s complement.

and to a solid analog ground plane with a 10µF ceramic

capacitor(or10µFtantaluminparallelwith0.1µFceramic).

Can be overdriven by an external reference between 2.55V

SCK (Pin 9): External Clock Input. Advances the conver-

sion process and sequences the output data on the rising

edge. Responds to TTL (≤3V) and 3V CMOS levels. One

or more pulses wake from sleep.

and V .

DD

GND (Pins 4, 5, 6, Exposed Pad Pin 11): Ground. These

ground pins and the exposed pad must be tied directly to

the solid ground plane under the part. Keep in mind that

analog signal currents and digital output signal currents

flow through these pins.

CONV(Pin10):ConvertStart.Holdstheanaloginputsignal

and starts the conversion on the rising edge. Responds

to TTL (≤3V) and 3V CMOS levels. Two pulses with SCK

in fixed high or fixed low state start Nap mode. Four or

more pulses with SCK in fixed high or fixed low state start

Sleep mode.

V

(Pin 7): 3V Positive Supply. This single power pin

DD

supplies 3V to the entire chip. Bypass to GND and to a

14031fd

9

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

BLOCK DIAGRAM

10µF 3V

7

V

LTC1403A-1

DD

+

THREE-

STATE

SERIAL

OUTPUT

PORT

A

IN

1

2

+

–

14-BIT ADC

SDO

S & H

8

–

A

IN

14

V

REF

3

4

10

9

CONV

SCK

2.5V

REFERENCE

TIMING

LOGIC

10µF

GND

5

14031 BD

6

11

EXPOSED PAD

14031fd

10

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

TIMING DIAGRAM

LTC1403-1 Timing Diagram

t

2

t

7

t

3

t

1

17

18

1

2

3

4

5

6

7

8

9

10

11

12

13

15

t

16

17

18

1

14

SCK

t

4

5

CONV

t

6

t

ACQ

INTERNAL

S/H STATUS

SAMPLE

HOLD

SAMPLE

HOLD

t

9

t

8

SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1

Hi-Z

SDO

D0

X*

14031 TD01

14-BIT DATA WORD

CONV

t

THROUGHPUT

*BITS MARKED "X" AFTER D0 SHOULD BE IGNORED.

LTC1403A-1 Timing Diagram

t

2

t

7

t

3

t

1

17

18

1

2

3

4

5

6

7

8

9

10

11

12

13

15

t

16

17

18

1

14

SCK

t

4

5

CONV

t

6

t

ACQ

INTERNAL

S/H STATUS

SAMPLE

HOLD

SAMPLE

HOLD

t

8

t

9

t

8

SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3

Hi-Z

SDO

D2

D1

D0

14031 TD01b

14-BIT DATA WORD

CONV

t

THROUGHPUT

Nap Mode and Sleep Mode Waveforms

SLK

t

1

CONV

NAP

SLEEP

t

12

V

REF

14031 TD02

NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS

SCK to SDO Delay

SCK

V

IH

t

10

8

t

9

V

90%

10%

OH

OL

SDO

14031 TD03

14031fd

11

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

APPLICATIONS INFORMATION

DRIVING THE ANALOG INPUT

is available in the Linear Technology Databooks and our

website at www.linear.com.)

ThedifferentialanaloginputsoftheLTC1403-1/LTC1403A-1

®

LTC 1566-1: Low Noise 2.3MHz Continuous Time Low-

Pass Filter.

are easy to drive. The inputs may be driven differentially or

–

as a single-ended input (i.e., the A input is set to V ).

IN

CM

+

–

Bothdifferentialanaloginputs,A withA ,aresampled

IN

LT1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier.

at the same instant. Any unwanted signal that is common

to both inputs of each input pair will be reduced by the

common mode rejection of the sample-and-hold circuit.

Theinputsdrawonlyonesmallcurrentspikewhilecharging

the sample-and-hold capacitors at the end of conversion.

During conversion, the analog inputs draw only a small

leakage current. If the source impedance of the driving

circuit is low, then the LTC1403-1/LTC1403A-1 inputs can

be driven directly. As source impedance increases, so will

acquisition time. For minimum acquisition time with high

source impedance, a buffer amplifier must be used. The

main requirement is that the amplifier driving the analog

input(s) must settle after the small current spike before

the next conversion starts (settling time must be 39ns

for full throughput rate). Also keep in mind while choos-

ing an input amplifier, the amount of noise and harmonic

distortion added by the amplifier.

2.7V to 15V supplies. Very high A , 500µV offset and

VOL

520ns settling to 0.5LSB for a 4V swing. THD and noise

are –93dB to 40kHz and below 1LSB to 320kHz (A = 1,

V

2V into 1kΩ, V = 5V), making the part excellent for

P-P

S

AC applications (to 1/3 Nyquist) where rail-to-rail perfor-

mance is desired. Quad version is available as LT1631.

LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier.

2.7V to 15V supplies. Very high A , 1.5mV offset and

VOL

400ns settling to 0.5LSB for a 4V swing. It is suitable for

applications with a single 5V supply. THD and noise are

–93dB to 40kHz and below 1LSB to 800kHz (A = 1,

V

2V into 1kΩ, V = 5V), making the part excellent for

P-P

S

ACapplicationswhererail-to-railperformanceisdesired.

Quad version is available as LT1633.

LT1813: Dual 100MHz 750V/µs 3mA Voltage Feedback

Amplifier.5Vto 5Vsupplies.Distortionis–86dBto100kHz

and –77dB to 1MHz with 5V supplies (2V into 500Ω).

P-P

Excellent part for fast AC applications with 5V supplies.

CHOOSING AN INPUT AMPLIFIER

LT1801:80MHzGBWP,–75dBcat500kHz,2mA/Amplifier,

8.5nV/√Hz.

Choosing an input amplifier is easy if a few requirements are

taken into consideration. First, to limit the magnitude of the

voltagespikeseenbytheamplifierfromchargingthesampling

capacitor, choose an amplifier that has a low output imped-

ance (<100Ω) at the closed-loop bandwidth frequency. For

example, if an amplifier is used with a gain of 1 and has a

unity-gainbandwidthof50MHz,thentheoutputimpedance

at 50MHz must be less than 100Ω. The second require-

ment is that the closed-loop bandwidth must be greater

than 40MHz to ensure adequate small-signal settling for

full throughput rate. If slower op amps are used, more

time for settling can be provided by increasing the time

between conversions. The best choice for an op amp to

drive the LTC1403-1/LTC1403A-1 will depend on the ap-

plication. Generally, applications fall into two categories:

AC applications where dynamic specifications are most

critical and time domain applications where DC accuracy

and settling time are most critical. The following list is

a summary of the op amps that are suitable for driving

the LTC1403-1/LTC1403A-1. (More detailed information

LT1806/LT1807: 325MHz GBWP, –80dBc Distortion at

5MHz, Unity-Gain Stable, R-R In and Out, 10mA/Ampli-

fier, 3.5nV/√Hz.

LT1810: 180MHz GBWP, –90dBc Distortion at 5MHz,

Unity-Gain Stable, R-R In and Out, 15mA/Amplifier,

16nV/√Hz.

LT1818/LT1819: 400MHz, 2500V/µs,9mA, Single/Dual

Voltage Mode Operational Amplifier.

LT6200: 165MHz GBWP, –85dBc Distortion at 1MHz,

Unity-Gain Stable, R-R In and Out, 15mA/Amplifier,

0.95nV/√Hz.

LT6203: 100MHz GBWP, –80dBc Distortion at 1MHz,

Unity-Gain Stable, R-R In and Out, 3mA/Amplifier,

1.9nV/√Hz.

LT6600-10:Amplifier/FilterDifferentialIn/Outwith10MHz

Cutoff.

14031fd

12

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

APPLICATIONS INFORMATION

INPUT FILTERING AND SOURCE IMPEDANCE

1.25V range is also ideally suited for AC-coupled signals

in single supply applications. Figure 2 shows how to AC

couple signals in a single supply system without needing

a mid-supply 1.5V external reference. The DC common

modelevelissuppliedbythepreviousstagethatisalready

bounded by the single supply voltage of the system. The

The noise and the distortion of the input amplifier and

other circuitry must be considered since they will add

to the LTC1403-1/LTC1403A-1 noise and distortion. The

small-signal bandwidth of the sample-and-hold circuit is

50MHz. Any noise or distortion products that are pres-

ent at the analog inputs will be summed over this entire

bandwidth. Noisy input circuitry should be filtered prior

to the analog inputs to minimize noise. A simple 1-pole

common mode range of the inputs extend from ground to

+

the supply voltage V . If the difference between the A

DD

IN

–

and A inputs exceeds 1.25V, the output code will stay

fixed at zero and all ones and if this difference goes below

IN

RC filter is sufficient for many applications. For example,

–1.25V, the output code will stay fixed at one and all zeros.

+

Figure1showsa47pFcapacitorfromA togroundanda

IN

51Ωsourceresistortolimittheinputbandwidthto47MHz.

The 47pF capacitor also acts as a charge reservoir for the

input sample-and-hold and isolates the ADC input from

sampling-glitchsensitivecircuitry.Highqualitycapacitors

and resistors should be used since these components

can add distortion. NPO and silvermica type dielectric

capacitors have excellent linearity. Carbon surface mount

resistors can generate distortion from self heating and

from damage that may occur during soldering. Metal film

surface mount resistors are much less susceptible to both

problems.Whenhighamplitudeunwantedsignalsareclose

in frequency to the desired signal frequency, a multiple

pole filter is required. High external source resistance,

combined with the 13pF of input capacitance, will reduce

the rated 50MHz bandwidth and increase acquisition time

beyond 39ns.

C2

1µF

LTC1403-1/

R2

LTC1403A-1

1.6k

1

2

3

R3

+

–

A

V

IN

51Ω

V

IN

R1

1.6k

REF

+

C3

56pF

C1

1µF

C4

10µF

14031 F02

C1, C2: FILM TYPE

C3: COG TYPE

C4: CERAMIC BYPASS

Figure 2. AC Coupling of AC Signals with 1kHz Low Cut

INTERNAL REFERENCE

The LTC1403-1/LTC1403A-1 has an on-chip, temperature

compensated, bandgap reference that is factory trimmed

near 2.5V to obtain 1.25V input span. The reference

amplifier output V , (Pin 3) must be bypassed with a

REF

51Ω

1

2

+

A

V

IN

capacitor to ground. The reference amplifier is stable with

capacitorsof1µForgreater.Forthebestnoiseperformance,

a 10µF ceramic or a 10µF tantalum in parallel with a 0.1µF

47pF

V

–

CM

IN

1.5V DC

LTC1403-1/

LTC1403A-1

REF

ceramic is recommended. The V pin can be overdriven

3

REF

with an external reference as shown in Figure 3. The volt-

age of the external reference must be higher than the 2.5V

of the class A pull-up output of the internal reference. The

10µF

11

GND

1403A F01

Figure 1. RC Input Filter

3

3V

V

REF

INPUT RANGE

REF

LTC1403-1/

LTC1403A-1

10µF

The analog inputs of the LTC1403-1/LTC1403A-1 may be

driven fully differentially with a single supply. Each input

11

GND

may swing up to 3V

individually. In the conversion

P-P

14031 F03

range, each input is always up to 1.25V more positive or

morenegativethantheinvertinginputofeachchannel.The

Figure 3

14031fd

13

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

APPLICATIONS INFORMATION

recommended range for an external reference is 2.55V to

Figure 5 shows the ideal input/output characteristics for

the LTC1403-1/LTC1403A-1. The code transitions occur

midway between successive integer LSB values (i.e.,

0.5LSB, 1.5LSB, 2.5LSB, FS – 1.5LSB). The output code

is 2’s complement with 1LSB = 2.5V/16384 = 153µV for

the LTC1403A-1, and 1LSB = 2.5V/4096 = 610µV for the

LTC1403-1. The LTC1403A-1 has 1LSB RMS of random

white noise. Figure 6a shows the LTC1819 converting a

single ended input signal to differential input signals for

optimum THD and SFDR performance as shown in the

FFT plot (Figure 6b).

V . Anexternalreferenceat2.55VwillseeaDCquiescent

DD

load of 0.75mA and as much as 3mA during conversion.

INPUT SPAN VERSUS REFERENCE VOLTAGE

The differential input range has a unipolar voltage span

that equals the difference between the voltage at the ref-

erence buffer output V at Pin 3, and the voltage at the

REF

ground(ExposedPadGround).Thedifferentialinputrange

of the ADC is 1.25V when using the internal reference.

The internal ADC is referenced to these two nodes. This

relationship also holds true with an external reference.

LTC1403-1/LTC1403A-1 Transfer

Characteristic

DIFFERENTIAL INPUTS

011...111

011...110

011...101

The LTC1403-1/LTC1403A-1 have a unique differential

sample-and-hold circuit that allows inputs from ground

to V . The ADC will always convert the bipolar differ-

DD

+

–

ence of A – A , independent of the common mode

IN

voltage at the inputs. The common mode rejection holds

up at extremely high frequencies, see Figure 4. The only

requirement is that both inputs not go below ground or

100...010

100...001

100...000

exceed V . Integral nonlinearity errors (INL) and differ-

DD

ential nonlinearity errors (DNL) are largely independent

of the common mode voltage. However, the offset error

will vary. The change in offset error is typically less than

0.1% of the common mode voltage.

–FS

FS – 1LSB

INPUT VOLTAGE (V)

14031 F05

Figure 5

5V

C5

0.1µF

CMRR vs Frequency

0

C3

1µF

–

R1

–20

–40

51Ω

U1

1

+

A

IN

1/2 LT1819

V

P-P

MAX

C1

IN

+

1.25V

47pF TO

1000pF

C6

0.1µF

R5

1k

–60

R4

499Ω

R3

1.5V

CM

LTC1403A-1

–5V

499Ω

–80

R6

1k

C4

1µF

–

–100

R2

51Ω

U2

–

A

IN

1/2 LT1819

–120

C2

47pF TO

1000pF

+

1403A F06a

100

10k

100k 1M

10M 100M

1k

FREQUENCY (Hz)

14031 F04

Figure 6a. The LT1819 Driving the LTC1403A-1 Differentially

Figure 4

14031fd

14

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

APPLICATIONS INFORMATION

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0

185k

371k

556k

741k

FREQUENCY (Hz)

14031 F06b

Figure 6b. LTC1403-1 6MHz Sine Wave 4096 Point FFT Plot

with the LT1819 Driving the Inputs Differentially

Board Layout and Bypassing

Wire wrap boards are not recommended for high resolu-

tion and/or high speed A/D converters. To obtain the best

performance from the LTC1403-1/LTC1403A-1, a printed

circuit board with ground plane is required. Layout for

the printed circuit board should ensure that digital and

analog signal lines are separated as much as possible. In

particular, care should be taken not to run any digital track

alongside an analog signal track. If optimum phase match

between the inputs is desired, the length of the two input

wires should be kept matched.

14031 F07

Figure 7. Recommended Layout

common. In applications where the ADC data outputs and

control signals are connected to a continuously active

microprocessor bus, it is possible to get errors in the

conversion results. These errors are due to feedthrough

fromthemicroprocessortothesuccessiveapproximation

comparator. The problem can be eliminated by forcing the

microprocessor into a Wait state during conversion or

by using three-state buffers to isolate the ADC data bus.

High quality tantalum and ceramic bypass capacitors

should be used at the V and V pins as shown in the

DD

REF

Block Diagram on the first page of this data sheet. For

optimumperformance, a10µFsurfacemountAVXcapaci-

tor with a 0.1µF ceramic is recommended for the V and

DD

V

REF

pins.Alternatively,10µFceramicchipcapacitorssuch

as Murata GRM219R60J106M may be used. The capaci-

tors must be located as close to the pins as possible. The

tracesconnectingthepinsandthebypasscapacitorsmust

be kept short and should be made as wide as possible.

POWER-DOWN MODES

Upon power-up, the LTC1403-1/LTC1403A-1 is initialized

totheactivestateandisreadyforconversion. TheNapand

Sleep mode waveforms show the power-down modes for

the LTC1403-1/LTC1403A-1. The SCK and CONV inputs

control the power-down modes (see Timing Diagrams).

Two rising edges at CONV, without any intervening rising

edges at SCK, put the LTC1403-1/LTC1403A-1 in Nap

mode and the power drain drops from 14mW to 6mW.

Figure7showstherecommendedsystemgroundconnec-

tions. All analog circuitry grounds should be terminated at

theLTC1403-1/LTC1403A-1GND(Pins4,5,6andexposed

pad).ThegroundreturnfromtheLTC1403-1/LTC1403A-1

(Pins 4, 5, 6 and exposed pad) to the power supply

should be low impedance for noise free operation. Digital

circuitry grounds must be connected to the digital supply

The internal reference remains powered in Nap mode.

14031fd

15

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

APPLICATIONS INFORMATION

One or more rising edges at SCK wake up the LTC1403-1/

LTC1403A-1 for service very quickly, and CONV can start

an accurate conversion within a clock cycle. Four rising

edges at CONV, without any intervening rising edges at

SCK, put the LTC1403-1/LTC1403A-1 in Sleep mode and

the power drain drops from 16mW to 10µW. One or more

rising edges at SCK wake up the LTC1403-1/LTC1403A-1

of inverters to ensure the correct delay driving the frame

sync input of the processor serial port. It is good practice

to drive the LTC1403-1/LTC1403A-1 CONV input first to

avoid digital noise interference during the sample-to-hold

transition triggered by CONV at the start of conversion. It

is also good practice to keep the width of the low portion

of the CONV signal greater than 15ns to avoid introducing

glitches in the front end of the ADC just before the sample-

and-hold goes into hold mode at the rising edge of CONV.

for operation. The internal reference (V ) takes 2ms to

REF

slew and settle with a 10µF load. Note that, using sleep

mode more frequently than every 2ms, compromises the

settled accuracy of the internal reference. Note that, for

slower conversion rates, the Nap and Sleep modes can

be used for substantial reductions in power consumption.

Minimizing Jitter on the CONV Input

Inhighspeedapplicationswherehighamplitudesinewaves

above 100kHz are sampled, the CONV signal must have

as little jitter as possible (10ps or less). The square wave

output of a common crystal clock module usually meets

thisrequirementeasily.ThechallengeistogenerateaCONV

signalfromthiscrystalclockwithoutjittercorruptionfrom

other digital circuits in the system. A clock divider and

any gates in the signal path from the crystal clock to the

CONV input should not share the same integrated circuit

with other parts of the system. As shown in the interface

circuit examples, the SCK and CONV inputs should be

drivenfirst, withdigitalbuffersusedtodrivetheserialport

interface. Also note that the master clock in the DSP may

already be corrupted with jitter, even if it comes directly

from the DSP crystal. Another problem with high speed

processor clocks is that they often use a low cost, low

speed crystal (i.e., 10MHz) to generate a fast, but jittery,

phase-locked-loop system clock (i.e., 40MHz). The jitter

in these PLL-generated high speed clocks can be several

nanoseconds. Note that if you choose to use the frame

sync signal generated by the DSP port, this signal will

have the same jitter of the DSP’s master clock.

DIGITAL INTERFACE

The LTC1403-1/LTC1403A-1 has a 3-wire SPI (Serial

Protocol Interface) interface. The SCK and CONV inputs

and SDO output implement this interface. The SCK and

CONV inputs accept swings from 3V logic and are TTL

compatible, if the logic swing does not exceed V . A

detaileddescriptionofthethreeserialportsignalsfollows:

DD

Conversion Start Input (CONV)

The rising edge of CONV starts a conversion, but subse-

quent rising edges at CONV are ignored by the LTC1403-1/

LTC1403A-1 until the following 16 SCK rising edges have

occurred and track mode starts again. It is also necessary

to have a minimum of 17 rising edges of the clock input

SCK between rising edges of CONV for SDO to go to the

Hi-ZstateandtopreparetheinternalADClogicforthenext

conversion. But to obtain maximum conversion speed, it

is necessary to allow one more clock period between con-

versions to allow 39ns of acquisition time for the internal

ADC sample-and-hold circuit. With 17 clock periods per

conversion, the maximum conversion rate is limited to

2.8Msps to allow 39ns for acquisition time. In either case,

the output data stream comes out within the first 16 clock

periodstoensurecompatibilitywithprocessorserialports.

The duty cycle of CONV can be arbitrarily chosen to be

used as a frame sync signal for the processor serial port.

A simple approach to generate CONV is to create a pulse

that is one SCK wide to drive the LTC1403-1/LTC1403A-1

and then buffer this signal with the appropriate number

Serial Clock Input (SCK)

The rising edge of SCK advances the conversion process

and also updates each bit in the SDO data stream. After

CONV rises, the third rising edge of SCK starts clocking

out the 12/14 data bits with the MSB sent first. A simple

approach is to generate SCK to drive the LTC1403-1/

LTC1403A-1 first and then buffer this signal with the

appropriate number of inverters to drive the serial clock

input of the processor serial port. Use the falling edge of

14031fd

16

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

APPLICATIONS INFORMATION

the clock to latch data from the Serial Data Output (SDO)

into your processor serial port. The 14-bit Serial Data

will be received right justified, in a 16-bit word with 17 or

more clocks per frame sync. It is good practice to drive

the LTC1403-1/LTC1403A-1 SCK input first to avoid digi-

tal noise interference during the internal bit comparison

decision by the internal high speed comparator. Unlike the

CONVinput, theSCKinputisnotsensitivetojitterbecause

the input signal is already sampled and held constant.

HARDWARE INTERFACE TO TMS320C54x

The LTC1403-1/LTC1403A-1 is a serial output ADC whose

interface has been designed for high speed buffered serial

ports in fast digital signal processors (DSPs). Figure 8

shows an example of this interface using a TMS320C54x.

The buffered serial port in the TMS320C54x has direct

access to a 2kB segment of memory. The ADC’s serial

data can be collected in two alternating 1kB segments,

in real time, at the full 2.8Msps conversion rate of the

LTC1403-1/LTC1403A-1. The DSP assembly code sets

frame sync mode at the BFSR pin to accept an external

positive going pulse and the serial clock at the BCLKR

pin to accept an external positive edge clock. Buffers near

the LTC1403-1/LTC1403A-1 may be added to drive long

tracks to the DSP to prevent corruption of the signal to

LTC1403-1/LTC1403A-1.Thisconfigurationisadequateto

traverseatypicalsystemboard,but sourceresistorsatthe

buffer outputs and termination resistors at the DSP, may

be needed to match the characteristic impedance of very

long transmission lines. If you need to terminate the SDO

transmission line, buffer it first with one or two 74ACTxx

gates. The TTL threshold inputs of the DSP port respond

properly to the 3V swing from the SDO pin.

Serial Data Output (SDO)

Upon power-up, the SDO output is automatically reset to

the high impedance state. The SDO output remains in high

impedance until a new conversion is started. SDO sends

out 12/14 bits in 2’s complement format in the output data

stream beginning at the third rising edge of SCK after the

rising edge of CONV. SDO is always in high impedance

mode when it is not sending out data bits. Please note

the delay specification from SCK to a valid SDO. SDO is

always guaranteed to be valid by the next rising edge of

SCK. The 16-bit output data stream is compatible with the

16-bit or 32-bit serial port of most processors.

3V

7

5V

V

DD

V

CC

10

9

CONV

LTC1403-1/

LTC1403A-1

SCK

BFSR

BCLKR

BDR

B13 B12

8

6

SDO

GND

TMS320C54x

CONV

CLK

3-WIRE SERIAL

INTERFACELINK

14031 F08

0V TO 3V LOGIC SWING

Figure 8. DSP Serial Interface to TMS320C54x

14031fd

17

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

APPLICATIONS INFORMATION

; 10-23-03 ******************************************************************

; Files: 014SI.ASM -> 1403 bipolar Sine wave collection with Serial Port interface

;

bvectors.asm

s2k14ini.asm

buffered mode.

2k buffer size.

; first element at 1024, last element at 1023, two middles at 2047 and 0000

; bipolar mode

; negative edge BCLKR

; negative BFSR pulse

; -0 data shifted

; 1’ cable from counter to CONV at DUT

; 2’ cable from counter to CLK at DUT

; ***************************************************************************

.width

160

.length 110

.title “sineb0 BSP in auto buffer mode”

.mmregs

.setsect “.text”,

0x500,0

;Set address of executable

.setsect “vectors”, 0x180,0

.setsect “buffer”, 0x800,0

.setsect “result”, 0x1800,0

.text

;Set address of incoming 1403 data

;Set address of BSP buffer for clearing

;Set address of result for clearing

;.text marks start of code

start:

;this label seems necessary

;Make sure /PWRDWN is low at J1-9

;to turn off AC01 adc

tim=#0fh

prd=#0fh

tcr = #10h

tspc = #0h

pmst = #01a0h

sp = #0700h

dp = #0

; stop timer

; stop TDM serial port to AC01

; set up iptr. Processor Mode STatus register

; init stack pointer.

; data page

ar2 = #1800h

ar3 = #0800h

ar4 = #0h

; pointer to computed receive buffer.

; pointer to Buffered Serial Port receive buffer

; reset record counter

call sineinit

; Double clutch the initialization to insure a proper

sinepeek:

call sineinit

; reset. The external frame sync must occur 2.5 clocks

; or more after the port comes out of reset.

wait

goto wait

;

————————Buffered Receive Interrupt Routine —————————

breceive:

ifr = #10h

TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer

; clear interrupt flags

; if this still the first half get next half

if (NTC) goto bufull

bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15))

return_enable

;

———————mask and shift input data ——————————————

bufull:

b = *ar3+ << -0

b = #03FFFh & b

b = b ^ #2000h

; load acc b with BSP buffer and shift right -0

; mask out the TRISTATE bits with #03FFFh

; invert the MSB for bipolar operation

B

*ar2+ = data(#0bh)

; store B to out buffer and advance AR2 pointer

TC = (@ar2 == #02000h) ; output buffer is 2k starting at 1800h

if (TC) goto start

goto bufull

; restart if out buffer is at 1fffh

14031fd

18

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

APPLICATIONS INFORMATION

;

—————————dummy bsend return————————————

return_enable ;this is also a dummy return to define bsend

;in vector table file BVECTORS.ASM

bsend

;

——————————— end ISR ——————————————

.copy “c:\dskplus\1403\s2k14ini.asm”

;initialize buffered serial port

.space 16*32

;clear a chunk at the end to mark the end

;======================================================================

;

VECTORS

;======================================================================

.sect “vectors”

;The vectors start here

;get BSP vectors

.copy “c:\dskplus\1403\bvectors.asm”

.sect “buffer”

.space 16*0x800

.sect “result”

.space 16*0x800

;Set address of BSP buffer for clearing

;Set address of result for clearing

.end

; ***************************************************************************

; File: BVECTORS.ASM -> Vector Table for the ‘C54x DSKplus

10.Jul.96

;

BSP vectors and Debugger vectors

TDM vectors just return

; ***************************************************************************

; The vectors in this table can be configured for processing external and

; internal software interrupts. The DSKplus debugger uses four interrupt

; vectors. These are RESET, TRAP2, INT2, and HPIINT.

;

*

DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER

*

; All other vector locations are free to use. When programming always be sure

; the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and

; host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the

; DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally.

;

.title “Vector Table”

.mmregs

reset

nmi

goto #80h

;00; RESET * DO NOT MODIFY IF USING DEBUGGER *

nop

return_enable

;04; non-maskable external interrupt

nop

trap2

int0

int1

goto #88h

;08; trap2 * DO NOT MODIFY IF USING DEBUGGER *

nop

.space 52*16

;0C-3F: vectors for software interrupts 18-30

;40; external interrupt int0

return_enable

nop

return_enable

nop

;44; external interrupt int1

14031fd

19

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

APPLICATIONS INFORMATION

nop

int2

return_enable

;48; external interrupt int2

;4C; internal timer interrupt

;50; BSP receive interrupt

;54; BSP transmit interrupt

;58; TDM receive interrupt

nop

tint

return_enable

nop

brint

bxint

trint

goto breceive

nop

goto bsend

nop

return_enable

nop

txint

int3

return_enable

;5C; TDM transmit interrupt

;60; external interrupt int3

nop

return_enable

nop

hpiint

dgoto #0e4h

nop

;64; HPIint * DO NOT MODIFY IF USING DEBUGGER *

;68-7F; reserved area

nop

.space 24*16

**********************************************************************

*

**********************************************************************

*

* File: s2k14ini.ASM BSP initialization code for the ‘C54x DSKplus

*

for use with 1403 in buffered mode

BSPC and SPC are the same in the ‘C542

BSPCE and SPCE seem the same in the ‘C542

**********************************************************************

.title “Buffered Serial Port Initialization Routine”

ON

.set 1

OFF

.set !ON

.set 1

YES

NO

.set !YES

.set 2

BIT_8

BIT_10

BIT_12

BIT_16

GO

.set 1

.set 3

.set 0

.set 0x80

**********************************************************************

* This is an example of how to initialize the Buffered Serial Port (BSP).

* The BSP is initialized to require an external CLK and FSX for

* operation. The data format is 16-bits, burst mode, with autobuffering

* enabled.

*

14031fd

20

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

APPLICATIONS INFORMATION

*****************************************************************************************************

*LTC1403 timing from board with 10MHz crystal.

*

*10MHz, divided from 40MHz, forced to CLKIN by 1403 board.

*Horizontal scale is 25ns/chr or 100ns period at BCLKR

*Timing measured at DSP pins. Jxx pin labels for jumper cable.

*

*BFSR Pin J1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/~~~~~~~~~~~*

*BCLKR Pin J1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~*

*BDR

Pin J1-26 _—_—_—<B13-B12-B11-B10-B09-B08-B07-B06-B05-B04-B03-B02-B01-B00>—_—<B13-B12*

*CLKIN Pin J5-09 ~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~*

*C542 read

*

0

B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00

0

B13 B12*

*

* negative edge BCLKR

* negative BFSR pulse

* no data shifted

* 1’ cable from counter to CONV at DUT

* 2’ cable from counter to CLK at DUT

*No right shift is needed to right justify the input data in the main program

*the two msbs should also be masked

*

*****************************************************************************************************

*

Loopback

Format

IntSync

IntCLK

BurstMode

CLKDIV

PCM_Mode

FS_polarity

CLK_polarity

Frame_ignore

XMTautobuf

RCVautobuf

XMThalt

.set

NO

BIT_16

NO

YES

3

NO

YES

NO

!YES

NO

YES

NO

;(digital looback mode?)

;(Data format? 16,12,10,8)

;(internal Frame syncs generated?) TXM bit

;(internal clks generated?) MCM bit

;(if BurstMode=NO, then Continuous) FSM bit

;(3=default value, 1/4 CLOCKOUT)

;(Turn on PCM mode?)

;(change polarity)YES=^^^\_/^^^, NO=___/^\___

;(change polarity)for BCLKR YES=_/^, NO=~\_

;(inverted !YES -ignores frame)

;(transmit autobuﬀering)

DLB bit

FO bit

;(receive autobuﬀering)

;(transmit buﬀ halt if XMT buﬀ is full)

;(receive buﬀ halt if RCV buﬀ is full)

;(address of transmit buﬀer)

;(length of transmit buﬀer)

;(address of receive buﬀer)

RCVhalt

NO

XMTbufAddr

XMTbufSize

RCVbufAddr

RCVbufSize

*

0x800

0x000

0x800

;(length of receive buﬀer)works up to 800

* See notes in the ‘C54x CPU and Peripherals Reference Guide on setting up

* valid buﬀer start and length values. Page 9-44

*

**********************************************************************

.eval ((Loopback >> 1)|((Format & 2)<<1)|(BurstMode <<3)|(IntCLK <<4)|(IntSync <<5)) ,SPCval

.eval ((CLKDIV)|(FS_polarity <<5)|(CLK_polarity<<6)|((Format &

1)<<7)|(Frame_ignore<<8)|(PCM_Mode<<9)), SPCEval

.eval (SPCEval|(XMTautobuf<<10)|(XMThalt<<12)|(RCVautobuf<<13)|(RCVhalt<<15)), SPCEval

sineinit:

bspc = #SPCval

ifr = #10h

; places buﬀered serial port in reset

; clear interrupt ﬂags

imr = #210h

; Enable HPINT,enable BRINT0

intm = 0

; all unmasked interrupts are enabled.

; programs BSPCE and ABU

bspce = #SPCEval

axr = #XMTbufAddr

bkx = #XMTbufSize

arr = #RCVbufAddr

bkr = #RCVbufSize

bspc = #(SPCval | GO)

return

; initializes transmit buﬀer start address

; initializes transmit buﬀer size

; initializes receive buﬀer start address

; initializes receive buﬀer size

; bring buﬀered serial port out of reset

;for transmit and receive because GO=0xC0

14031fd

21

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC1403-1#packaging for the most recent package drawings.

MSE Package

10-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1664 Rev I)

BOTTOM VIEW OF

EXPOSED PAD OPTION

1.88

(.074)

1.88 ±0.102

(.074 ±.004)

0.889 ±0.127

(.035 ±.005)

1

0.29

REF

1.68

(.066)

0.05 REF

5.10

(.201)

MIN

1.68 ±0.102

3.20 – 3.45

DETAIL “B”

(.066 ±.004) (.126 – .136)

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

DETAIL “B”

10

NO MEASUREMENT PURPOSE

0.50

(.0197)

BSC

0.305 ± 0.038

(.0120 ±.0015)

TYP

3.00 ±0.102

(.118 ±.004)

(NOTE 3)

0.497 ±0.076

(.0196 ±.003)

10 9

8

7 6

RECOMMENDED SOLDER PAD LAYOUT

REF

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

4.90 ±0.152

(.193 ±.006)

DETAIL “A”

0.254

(.010)

0° – 6° TYP

1

2

3

4 5

GAUGE PLANE

0.53 ±0.152

(.021 ±.006)

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 ±0.0508

(.004 ±.002)

0.50

(.0197)

BSC

MSOP (MSE) 0213 REV I

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD

SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

14031fd

22

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

REVISION HISTORY

REV

DATE

1/10

6/10

6/12

2/17

DESCRIPTION

PAGE NUMBER

A

Revised Pin Configuration

2

B

Corrected transposed part numbers in Order Information section

Corrected output code from natural binary to 2’s complement

C

14

D

Updated Timing Characteristics, including t

minimum conversion time of 17 clocks

4, 11, 16, 17

CONV

14031fd

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

23

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC1403-1

LTC1403-1/LTC1403A-1

RELATED PARTS

PART NUMBER

ADCs

DESCRIPTION

COMMENTS

LTC1608

16-Bit, 500ksps Parallel ADC

16-Bit, 333ksps Parallel ADC

16-Bit, 200ksps Serial ADC

5V Supply, 2.5V Span, 90dB SINAD

LTC1604

5V Supply, 2.5V Span, 90dB SINAD

LTC1609

5V, Configurable Bipolar/Unipolar Inputs

5V, Selectable Spans, 80dB SINAD

LTC1411

14-Bit, 2.5Msps Parallel ADC

14-Bit, 2.2Msps Parallel ADC

12-/14-Bit, 2.8Msps Serial ADC

12-/14-Bit, 3Msps Simultaneous Sampling ADC

12-Bit, 10Msps Parallel ADC

LTC1414

5V Supply, 2.5V Span, 78dB SINAD

LTC1403/LTC1403A

LTC1407/LTC1407A

LTC1407-1/LTC1407A-1

LTC1420

3V, 14mW Unipolar Inputs, MSOP Package

3V, 2-Channel Differential, Unipolar Inputs, 14mW, MSOP Package

3V, 2-Channel Differential, Bipolar Inputs, 14mW, MSOP Package

5V, Selectable Spans, 71dB SINAD

LTC1405

12-Bit, 5Msps Parallel ADC

5V, Selectable Spans, 115mW

LTC1412

12-Bit, 3Msps Parallel ADC

5V Supply, 2.5V Span, 72dB SINAD

LTC1402

12-Bit, 2.2Msps Serial ADC

5V or 5V Supply, 4.096V or 2.048V Span

5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package

LTC1864/LTC1865

DACs

16-Bit, 250ksps Serial ADC

LTC1666/LTC1667/LTC1668 12-/14-/16-Bit, 50Msps DACs

87dB SFDR, 20ns Settling Time

LTC1592

16-Bit, Serial SoftSpan™ I

DAC

1LSB INL/DNL, Software Selectable Spans

OUT

References

LT1790-2.5

LT1461-2.5

LT1460-2.5

Micropower Series Reference in SOT-23

Precision Voltage Reference

0.05% Initial Accuracy, 10ppm Drift

0.04% Initial Accuracy, 3ppm Drift

0.075% Initial Accuracy, 10ppm Drift

Micropower Series Voltage Reference

14031fd

LT 0217 REV D • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

For more information www.linear.com/LTC1403-1

●

 LINEAR TECHNOLOGY CORPORATION 2004

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC1403-1


型号：	LTC1403CMSE-1#TRPBF
厂家：	Linear
描述：	LTC1403-1 - Serial 12-Bit, 2.8Msps Sampling ADCs with Shutdown; Package: MSOP; Pins: 10; Temperature Range: 0°C to 70°C 光电二极管转换器
文件：	总24页 (文件大小：550K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1403CMSE-1#TRPBF [Linear]

相关型号：

LTC1403HMSE

LTC1403HMSE#PBF

LTC1403HMSE#TR

LTC1403HMSE#TRPBF

LTC1403IMSE

LTC1403IMSE#PBF

LTC1403IMSE#TR

LTC1403IMSE#TRPBF

LTC1403IMSE-1

LTC1403IMSE-1#PBF

LTC1403IMSE-1#TR

LTC1403IMSE-1#TRPBF