LTC1403CMSE_技术文档

LTC1403/LTC1403A

Serial 12-Bit/14-Bit, 2.8Msps

Sampling ADCs with Shutdown

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FEATURES

DESCRIPTIO

The LTC^®1403/LTC1403A are 12-bit/14-bit, 2.8Msps se-

rial ADCs with differential inputs. The devices draw only

4.7mA from a single 3V supply and come in a tiny 10-lead

MS package. A Sleep shutdown feature lowers power

consumption to 10µW. The combination of speed, low

power and tiny package makes the LTC1403/LTC1403A

suitable for high speed, portable applications.

■

2.8Msps Conversion Rate

■

Low Power Dissipation: 14mW

■

3V Single Supply Operation

■

2.5V Internal Bandgap Reference can be Overdriven

■

3-Wire Serial Interface

■

Sleep (10µW) Shutdown Mode

■

Nap (3mW) Shutdown Mode

■

80dB Common Mode Rejection

The 80dB common mode rejection allows users to elimi-

nategroundloopsandcommonmodenoisebymeasuring

signals differentially from the source.

■

0V to 2.5V Unipolar Input Range

■

Tiny 10-Lead MS Package

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The devices convert 0V to 2.5V unipolar inputs differen-

tially. The absolute voltage swing for +A_INand –A_IN

extends from ground to the supply voltage.

APPLICATIO S

■

Communications

Data Acquisition Systems

■

The serial interface sends out the conversion results

during the 16 clock cycles following CONV↑ for compat-

ibility with standard serial interfaces. If two additional

clock cycles for acquisition time are allowed after the data

stream in between conversions, the full sampling rate of

2.8Msps can be achieved with a 50.4MHz clock.

■

Uninterrupted Power Supplies

■

Multiphase Motor Control

■

Multiplexed Data Acquisition

, LTC and LT are registered trademarks of Linear Technology Corporation.

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BLOCK DIAGRA

2nd, 3rd and SFDR

10µF 3V

vs Input Frequency

–44

7

V

–50

–56

LTC1403A

DD

+

–

THREE-

STATE

SERIAL

OUTPUT

PORT

A

THD

2nd, SFDR

IN

1

2

+

–62

14-BIT ADC

SDO

S & H

8

–68

–74

IN

–

3rd

–80

–86

14

V

REF

3

4

10

9

CONV

SCK

–92

2.5V

REFERENCE

TIMING

LOGIC

10µF

–98

GND

5

–104

0.1

1

10

100

1403A TA01

6

11

EXPOSED PAD

FREQUENCY (MHz)

1403A TA02

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LTC1403/LTC1403A

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ABSOLUTE AXI U RATI GS

(Notes 1, 2)

PACKAGE/ORDER I FOR ATIO

Supply Voltage (V_DD)................................................. 4V

Analog Input Voltage

ORDER PART

NUMBER

(Note 3) ....................................–0.3V to (V_DD+ 0.3V)

Digital Input Voltage ................... – 0.3V to (V_DD+ 0.3V)

Digital Output Voltage.................. –0.3V to (V_DD+ 0.3V)

Power Dissipation.............................................. 100mW

Operation Temperature Range

LTC1403C/LTC1403AC............................ 0°C to 70°C

LTC1403I/LTC1403AI ......................... –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

TOP VIEW

LTC1403CMSE

LTC1403IMSE

LTC1403ACMSE

LTC1403AIMSE

+

–

A

1

2

3

4

5

10 CONV

IN

9

8

7

6

SCK

SDO

DD

GND

V

11

REF

GND

V

MSE PACKAGE

10-LEAD PLASTIC MSOP

MSE PART MARKING

T_JMAX= 125°C, θ_JA= 150°C/ W

EXPOSED PAD IS GND (PIN 11)

MUST BE SOLDERED TO PCB

LTBDN

LTBDP

LTADF

LTAFD

Consult LTC Marketing for parts specified with wider operating temperature ranges.

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CO VERTER CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. With internal reference. V_DD= 3V

LTC1403

TYP MAX

LTC1403A

TYP MAX

PARAMETER

CONDITIONS

MIN

12

MIN

14

UNITS

Bits

Resolution (No Missing Codes)

Integral Linearity Error

Offset Error

●

(Notes 4, 5, 18)

(Notes 4, 18)

(Note 4, 18)

–2

±0.25

±1

2

–4

±0.5

±2

4

LSB

–10

–30

10

30

–20

–60

20

60

LSB

Gain Error

±5

±10

LSB

Gain Tempco

Internal Reference (Note 4)

External Reference

±15

±1

±15

±1

ppm/°C

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A ALOG I PUT

The ● denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. V_DD= 3V

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Analog Differential Input Range (Notes 3, 9)

2.7V ≤ V ≤ 3.3V

●

0 to 2.5

V

IN

DD

Analog Common Mode + Differential

Input Range (Note 10)

0 to V

CM

DD

I

Analog Input Leakage Current

●

1

µA

pF

ns

ps

IN

C

Analog Input Capacitance

13

IN

t

Sample-and-Hold Acquisition Time

Sample-and-Hold Aperture Delay Time

Sample-and-Hold Aperture Delay Time Jitter

Analog Input Common Mode Rejection Ratio

(Note 6)

39

ACQ

AP

1

0.3

JITTER

CMRR

f

= 1MHz, V = 0V to 3V

= 100MHz, V = 0V to 3V

–60

–15

dB

IN

1403af

2

LTC1403/LTC1403A

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DY A IC ACCURACY

The ● denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. V_DD= 3V

LTC1403

TYP MAX

LTC1403A

TYP MAX

SYMBOL PARAMETER

CONDITIONS

MIN

UNITS

SINAD

Signal-to-Noise Plus

Distortion Ratio

100kHz Input Signal

1.4MHz Input Signal

100kHz Input Signal, External V = 3.3V,

70.5

72

73.5

76.3

dB

●

68

70

REF

V

DD

≥ 3.3V

750kHz Input Signal, External V = 3.3V,

72

76.3

dB

REF

V

DD

≥ 3.3V

THD

SFDR

IMD

Total Harmonic

Distortion

100kHz First 5 Harmonics

1.4MHz First 5 Harmonics

–87

–83

–90

–86

dB

–76

–78

Spurious Free

Dynamic Range

100kHz Input Signal

1.4MHz Input Signal

–87

–83

–90

–86

dB

+

Intermodulation

Distortion

1.25V to 2.5V 1.25MHz into A , 0V to 1.25V,

–82

dB

IN

–

1.2MHz into A

IN

Code-to-Code

V

REF

= 2.5V (Note 18)

0.25

1

LSB

RMS

Transition Noise

Full Power Bandwidth

V

= 2.5V , SDO = 11585LSB (Note 15)

50

5

50

5

MHz

IN

P-P

Full Linear Bandwidth S/(N + D) ≥ 68dB

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I TER AL REFERE CE CHARACTERISTICS ^The● denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. V_DD= 3V

PARAMETER

CONDITIONS

= 0

MIN

TYP

2.5

15

MAX

UNITS

V

Output Voltage

Output Tempco

Line Regulation

Output Resistance

Settling Time

I

OUT

REF

ppm/°C

µV/V

Ω

V

= 2.7V to 3.6V, V = 2.5V

600

0.2

2

DD

REF

Load Current = 0.5mA

ms

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The ● denotes the specifications which apply over the

DIGITAL I PUTS A D DIGITAL OUTPUTS

full operating temperature range, otherwise specifications are at T_A= 25°C. V_DD= 3V

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

V

= 3.3V

= 2.7V

●

2.4

V

IH

IL

DD

IN

0.6

I

= 0V to V

±10

µA

pF

V

IN

DD

C

V

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

5

IN

V

= 3V, I = –200µA

OUT

●

2.5

2.9

OH

OL

DD

V

= 2.7V, I

= 160µA

= 1.6mA

0.05

0.10

V

DD

OUT

●

0.4

I

Hi-Z Output Leakage D

V

= 0V to V

DD

±10

µA

pF

OZ

OUT

C

Hi-Z Output Capacitance D

1

OZ

OUT

I

Output Short-Circuit Source Current

Output Short-Circuit Sink Current

V

= 0V, V = 3V

20

15

mA

SOURCE

SINK

OUT

DD

= V = 3V

DD

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3

LTC1403/LTC1403A

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POWER REQUIRE E TS

The ● denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 17)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Supply Voltage

2.7

3.6

V

DD

I

Positive Supply Voltage

Active Mode

Nap Mode

Sleep Mode (LTC1403)

Sleep Mode (LTC1403A)

●

4.7

1.1

2

7

mA

µA

DD

1.5

15

10

2

µA

P

Power Dissipation

Active Mode with SCK in Fixed State (Hi or Lo)

12

mW

D

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TI I G CHARACTERISTICS

The ● denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. V_DD= 3V

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

f

Maximum Sampling Frequency per Channel

(Conversion Rate)

●

2.8

MHz

SAMPLE(MAX)

t

Minimum Sampling Period (Conversion + Acquisiton Period)

Clock Period

●

357

ns

THROUGHPUT

(Note 16)

19.8

16

2

10000

ns

SCK

Conversion Time

(Note 6)

18

SCLK cycles

CONV

Minimum Positive or Negative SCLK Pulse Width

CONV to SCK Setup Time

(Note 6)

ns

ms

1

(Notes 6, 10)

(Note 6)

3

2

Nearest SCK Edge Before CONV

0

3

Minimum Positive or Negative CONV Pulse Width

SCK to Sample Mode

(Note 6)

4

(Note 6)

4

5

CONV to Hold Mode

(Notes 6, 11)

(Notes 6, 7, 13)

(Notes 6, 12)

(Notes 6, 14)

1.2

45

8

6

16th SCK↑ to CONV↑ Interval (Affects Acquisition Period)

Minimum Delay from SCK to Valid Bits 0 Through 13

SCK to Hi-Z at SDO

7

8

6

9

Previous SDO Bit Remains Valid After SCK

2

10

12

V

Settling Time After Sleep-to-Wake Transition

2

REF

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

cycle later. It is best for CONV to rise half a clock before SCK, when

running the clock at rated speed.

Note 2: All voltage values are with respect to GND.

Note 3: When these pins are taken below GND or above V , they will be

clamped by internal diodes. This product can handle input currents greater

Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns)

because the 2.2ns delay through the sample-and-hold is subtracted from

the CONV to Hold mode delay.

DD

than 100mA below GND or greater than V without latchup.

Note 12: The rising edge of SCK is guaranteed to catch the data coming

out into a storage latch.

Note 13: The time period for acquiring the input signal is started by the

DD

Note 4: Offset and full-scale specifications are measured for a single-

+

–

ended A input with A grounded and using the internal 2.5V reference.

IN

16th rising clock and it is ended by the rising edge of convert.

Note 14: The internal reference settles in 2ms after it wakes up from Sleep

mode with one or more cycles at SCK and a 10µF capacitive load.

Note 5: Integral linearity is tested with an external 2.55V reference and is

defined as the deviation of a code from the straight line passing through

the actual endpoints of a transfer curve. The deviation is measured from

the center of quantization band.

Note 15: The full power bandwidth is the frequency where the output code

Note 6: Guaranteed by design, not subject to test.

Note 7: Recommended operating conditions.

swing drops to 3dB with a 2.5V input sine wave.

Note 16: Maximum clock period guarantees analog performance during

conversion. Output data can be read without an arbitrarily long clock.

P-P

Note 8: The analog input range is defined for the voltage difference

+

–

between A and A

.

Note 17: V = 3V, f

= 2.8Msps.

SAMPLE

IN

DD

+

–

Note 9: The absolute voltage at A and A must be within this range.

Note 18: The LTC1403A is measured and specified with 14-bit Resolution

(1LSB = 152µV) and the LTC1403 is measured and specified with 12-bit

Resolution (1LSB = 610µV).

IN

Note 10: If less than 3ns is allowed, the output data will appear one clock

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LTC1403/LTC1403A

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TYPICAL PERFOR A CE CHARACTERISTICS

T_A= 25°C, V_DD= 3V (LTC1403A)

ENOBs and SINAD

vs Input Frequency

THD, 2nd and 3rd vs Input

Frequency

SFDR vs Input Frequency

–44

–50

–56

–62

104

98

92

86

80

74

68

62

56

50

44

12.0

11.5

11.0

10.5

10.0

9.5

74

71

68

65

62

59

56

53

50

THD

2nd

–68

–74

3rd

–80

–86

9.0

–92

8.5

–98

–104

8.0

0.1

1

10

100

0.1

1

10

100

0.1

1

10

100

FREQUENCY (MHz)

1403A G02

1403A G17

1403A G01

98kHz Sine Wave 4096 Point

FFT Plot

1.3MHz Sine Wave 4096 Point

FFT Plot

SNR vs Input Frequency

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

74

71

68

65

62

59

56

53

50

2.8Msps

0

350k

700k

1.05M

1.4M

0

350k

700k

1.05M

1.4M

0.1

1

10

100

FREQUENCY (Hz)

FREQUENCY (MHz)

1403A G03

1403A G04

1403A G05

1.4MHz Input Summed with

1.56MHz Input IMD 4096 Point

FFT Plot

Differential Linearity

vs Output Code

Integral Linearity

vs Output Code

4

3

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

1.0

0.8

2.8Msps

0.6

2

0.4

1

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1

–2

–3

–4

0

4096

8192

12288

16383

0

350k

700k

1.05M

1.4M

0

4096

8192

12288

16383

OUTPUT CODE

FREQUENCY (Hz)

OUTPUT CODE

1403A G14

1403A G06

1403A G13

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5

LTC1403/LTC1403A

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T_A= 25°C, V_DD= 3V (LTC1403A)

TYPICAL PERFOR A CE CHARACTERISTICS

Differential and Integral Linearity

vs Conversion Rate

SINAD vs Conversion Rate

80

79

78

77

76

75

74

73

72

71

70

5

4

18 CLOCKS PER CONVERSION

EXTERNAL V

= 3.3V f ~f /3

IN

MAX INL

REF

S

3

2

MAX DNL

EXTERNAL V

= 3.3V f ~f /40

IN

REF

S

1

0

–1

–2

–3

–4

–5

MIN DNL

MIN INL

INTERNAL V

= 2.5V f ~f /40

IN

REF

S

INTERNAL V

= 2.5V f ~f /3

IN

REF

S

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

CONVERSION RATE (Msps)

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

CONVERSION RATE (Msps)

1403A G16

1403A G15

T_A= 25°C, V_DD= 3V (LTC1403 and LTC1403A)

2.5V_P-PPower Bandwidth

CMRR vs Frequency

PSRR vs Frequency

0

–20

12

–25

–30

–35

–40

–45

–50

–55

–60

–65

6

0

–40

–6

–12

–18

–60

–80

–24

–30

–36

–100

–120

–70

100

10k

100k 1M

10M 100M

1k

1M

10M

100M

1G

1

10

100

1k

10k 100k

1M

FREQUENCY (Hz)

1403A G07

1403A G09

1403A G08

Reference Voltage vs Load

Current

V_DDSupply Current vs

Conversion Rate

Reference Voltage vs V_DD

2.4902

2.4900

2.4898

2.4896

2.4894

2.4892

2.4890

2.4902

2.4900

2.4898

2.4896

2.4894

2.4892

2.4890

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

LOAD CURRENT (mA)

2.6

2.8

3.0

3.2

(V)

3.4

3.6

0

0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0

CONVERSION RATE (Msps)

V

DD

1403A G10

1403A G11

1403A G12

1403af

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LTC1403/LTC1403A

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PI FU CTIO S

+

A_IN(Pin 1): Noninverting Analog Input. A_INoperates

fully differentially with respect to A_IN^–with a 0V to 2.5V

differential swing and a 0V to V_DDcommon mode swing.

10µF tantalum in parallel with 0.1µF ceramic). Keep in

mindthatinternalanalogcurrentsanddigitaloutputsignal

currents flow through this pin. Care should be taken to

place the 0.1µF bypass capacitor as close to Pins 6 and 7

as possible.

–

A_IN(Pin 2): Inverting Analog Input. A_INoperates fully

+

differentially with respect to A_INwith a –2.5V to 0V

differential swing and a 0V to V_DDcommon mode swing.

SDO (Pin 8): Three-State Serial Data Output. Each of

output data words represents the difference between

A_IN⁺and A_IN^–analog inputs at the start of the previous

conversion.

V_REF(Pin 3): 2.5V Internal Reference. Bypass to GND and

to a solid analog ground plane with a 10µF ceramic

capacitor (or 10µF tantalum in parallel with 0.1µF ce-

ramic). Can be overdriven by an external reference be-

tween 2.55V and V_DD.

SCK (Pin 9): External Clock Input. Advances the conver-

sion process and sequences the output data on the rising

edge. Responds to TTL (≤3V) and 3V CMOS levels. One

or more pulses wake from sleep.

GND (Pins 5, 6, 11): Ground and Exposed Pad. These

ground pins and the exposed pad must be tied directly to

the solid ground plane under the part. Keep in mind that

analog signal currents and digital output signal currents

flow through these pins.

CONV (Pin 10): Convert Start. Holds the analog input

signal and starts the conversion on the rising edge.

Responds to TTL (≤3V) and 3V CMOS levels. Two pulses

with SCK in fixed high or fixed low state start Nap mode.

Four or more pulses with SCK in fixed high or fixed low

state start Sleep mode.

V_DD(Pin 7): 3V Positive Supply. This single power pin

supplies3Vtotheentirechip.BypasstoGNDandtoasolid

analog ground plane with a 10µF ceramic capacitor (or

W

BLOCK DIAGRA

10µF 3V

7

V

LTC1403A

DD

+

–

THREE-

STATE

SERIAL

OUTPUT

PORT

A

IN

1

2

+

14-BIT ADC

SDO

S & H

8

IN

–

14

V

REF

3

4

10

9

CONV

SCK

2.5V

REFERENCE

TIMING

LOGIC

10µF

GND

5

1403A BD

6

11

EXPOSED PAD

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7

LTC1403/LTC1403A

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TI I G DIAGRA

LTC1403 Timing Diagram

t

2

t

7

t

3

t

1

16

17

1

2

3

4

5

6

7

8

9

10

11

12

13

15

t

16

17

18

1

14

SCK

t

4

5

CONV

t

6

t

ACQ

INTERNAL

S/H STATUS

SAMPLE

HOLD

SAMPLE

HOLD

t

9

t

8

t

8

10

SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

Hi-Z

SDO

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1

D0

X

1403A TD01

14-BIT DATA WORD

CONV

t

THROUGHPUT

*BITS MARKED "X" AFTER D0 SHOULD BE IGNORED.

LTC1403A Timing Diagram

t

2

t

7

t

1

3

16

17

1

2

3

4

5

6

7

8

9

10

11

12

13

15

t

16

17

18

1

14

SCK

t

4

5

CONV

t

6

t

ACQ

INTERNAL

S/H STATUS

SAMPLE

HOLD

SAMPLE

HOLD

t

8

t

8

9

10

SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

Hi-Z

SDO

D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3

D2

D1

D0

1403A TD01b

14-BIT DATA WORD

CONV

t

THROUGHPUT

Nap Mode and Sleep Mode Waveforms

SLK

t

1

t

1

CONV

NAP

SLEEP

t

12

V

1403A TD02

REF

NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS

SCK to SDO Delay

SCK

V

IH

t

10

8

t

9

V

90%

10%

OH

OL

SDO

1403A TD03

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LTC1403/LTC1403A

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APPLICATIO S I FOR ATIO

DRIVING THE ANALOG INPUT

detailed information is available in the Linear Technology

Databooks and on the LinearView^TMCD-ROM.)

The differential analog inputs of the LTC1403/LTC1403A are

easy to drive. The inputs may be driven differentially or as a

single-ended input (i.e., the A_IN^–input is grounded). Both

differential analog inputs, A_IN⁺with A_IN^–, are sampled at the

same instant. Any unwanted signal that is common to both

inputsofeachinputpairwillbereducedbythecommonmode

rejectionofthesample-and-holdcircuit.Theinputsdrawonly

one small current spike while charging the sample-and-hold

capacitors at the end of conversion. During conversion, the

analoginputsdrawonlyasmallleakagecurrent. Ifthesource

impedance of the driving circuit is low, then the LTC1403/

LTC1403A inputs can be driven directly. As source imped-

ance increases, so will acquisition time. For minimum acqui-

sition time with high source impedance, a buffer amplifier

must be used. The main requirement is that the amplifier

driving the analog input(s) must settle after the small current

spikebeforethenextconversionstarts(settlingtimemustbe

39ns for full throughput rate). Also keep in mind while

choosing an input amplifier, the amount of noise and har-

monic distortion added by the amplifier.

LTC^®1566-1: Low Noise 2.3MHz Continuous Time Low-

Pass Filter.

LT1630:Dual30MHzRail-to-RailVoltageFBAmplifier.2.7V

to ±15V supplies. Very high A_VOL, 500µV offset and 520ns

settling to 0.5LSB for a 4V swing. THD and noise are –93dB

to40kHzandbelow1LSBto320kHz(A_V=1,2V_P-Pinto1kΩ,

V_S=5V), makingthepartexcellentforACapplications(to1/

3 Nyquist) where rail-to-rail performance is desired. Quad

version is available as LT1631.

LT1632:Dual45MHzRail-to-RailVoltageFBAmplifier.2.7V

to ±15V supplies. Very high A_VOL, 1.5mV offset and 400ns

settling to 0.5LSB for a 4V swing. It is suitable for applica-

tions with a single 5V supply. THD and noise are

–93dB to 40kHz and below 1LSB to 800kHz (A_V= 1,

2V_P-Pinto 1kΩ, V_S= 5V), making the part excellent for AC

applications where rail-to-rail performance is desired.Quad

version is available as LT1633.

LT1813: Dual 100MHz 750V/µs 3mA Voltage Feedback

Amplifier. 5V to ±5V supplies. Distortion is –86dB to 100kHz

and –77dB to 1MHz with ±5V supplies (2V_P-Pinto 500Ω).

Excellent part for fast AC applications with ±5V supplies.

CHOOSING AN INPUT AMPLIFIER

Choosing an input amplifier is easy if a few requirements are

taken into consideration. First, to limit the magnitude of the

voltage spike seen by the amplifier from charging the sam-

pling capacitor, choose an amplifier that has a low output

impedance(<100Ω)attheclosed-loopbandwidthfrequency.

For example, if an amplifier is used in a gain of 1 and has a

unity-gain bandwidth of 50MHz, then the output impedance

at 50MHz must be less than 100Ω. The second requirement

is that the closed-loop bandwidth must be greater than

40MHz to ensure adequate small-signal settling for full

throughput rate. If slower op amps are used, more time for

settling can be provided by increasing the time between

conversions. The best choice for an op amp to drive the

LTC1403/LTC1403A will depend on the application. Gener-

ally, applications fall into two categories: AC applications

where dynamic specifications are most critical and time

domainapplicationswhereDCaccuracyandsettlingtimeare

most critical. The following list is a summary of the op amps

that are suitable for driving the LTC1403/LTC1403A. (More

LT1801: 80MHz GBWP, –75dBc at 500kHz, 2mA/Amplifier,

8.5nV/√Hz.

LT1806/LT1807:325MHzGBWP,–80dBcDistortionat5MHz,

Unity-GainStable,R-RInandOut,10mA/Amplifier,3.5nV/√Hz.

LT1810: 180MHz GBWP, –90dBc Distortion at 5MHz,

Unity-GainStable,R-RInandOut,15mA/Amplifier,16nV/√Hz.

LT1818/LT1819:400MHz,2500V/µs,9mA,Single/DualVolt-

age Mode Operational Amplifier.

LT6200: 165MHz GBWP, –85dBc Distortion at 1MHz, Unity-

Gain Stable, R-R In and Out, 15mA/Amplifier,

0.95nV/√Hz.

LT6203: 100MHz GBWP, –80dBc Distortion at 1MHz,

Unity-Gain Stable, R-R In and Out, 3mA/Amplifier,

1.9nV/√Hz.

LT6600-10: Amplifier/Filter Differential In/Out with 10MHz

Cutoff.

LinearView is a trademark of Linear Technology Corporation.

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51Ω

1

+

A

V

IN

47pF

3

3V

V

REF

2

–

IN

LTC1403/

LTC1403A

REF

LTC1403/

LTC1403A

10µF

3

11

GND

10µF

11

1403A F02

GND

1403A F01

Figure 1. RC Input Filter

Figure 2

INPUT FILTERING AND SOURCE IMPEDANCE

INPUT RANGE

The noise and the distortion of the input amplifier and

other circuitry must be considered since they will add to

the LTC1403/LTC1403A noise and distortion. The small-

signalbandwidthofthesample-and-holdcircuitis50MHz.

Any noise or distortion products that are present at the

analog inputs will be summed over this entire bandwidth.

Noisy input circuitry should be filtered prior to the analog

inputs to minimize noise. A simple 1-pole RC filter is

sufficient for many applications. For example, Figure 1

shows a 47pF capacitor from A_IN⁺to ground and a 51Ω

source resistor to limit the input bandwidth to 47MHz. The

47pF capacitor also acts as a charge reservoir for the input

sample-and-hold and isolates the ADC input from sam-

pling-glitchsensitivecircuitry.Highqualitycapacitorsand

resistors should be used since these components can add

distortion. NPO and silvermica type dielectric capacitors

have excellent linearity. Carbon surface mount resistors

can generate distortion from self heating and from dam-

age that may occur during soldering. Metal film surface

mount resistors are much less susceptible to both prob-

lems. When high amplitude unwanted signals are close in

frequency to the desired signal frequency, a multiple pole

filter is required. High external source resistance, com-

bined with the 13pF of input capacitance, will reduce the

rated 50MHz bandwidth and increase acquisition time

beyond 39ns.

The analog inputs of the LTC1403/LTC1403A may be

driven fully differentially with a single supply. Each input

may swing up to 3V_P-Pindividually. In the conversion

range, the noninverting input of each channel is always up

to 2.5V more positive than the inverting input of each

channel. The 0V to 2.5V range is also ideally suited for

single-ended input use with single supply applications.

The common mode range of the inputs extend from

ground to the supply voltage V_DD. If the difference be-

tween the A_IN⁺and A_IN^–inputs exceeds 2.5V, the output

code will stay fixed at all ones and if this difference goes

below 0V, the ouput code will stay fixed at all zeros.

INTERNAL REFERENCE

TheLTC1403/LTC1403Ahasanon-chip,temperaturecom-

pensated, bandgap reference that is factory trimmed near

2.5V to obtain 2.5V input span. The reference amplifier

output V_REF, (Pin 3) must be bypassed with a capacitor to

ground. The reference amplifier is stable with capacitors

of 1µF or greater. For the best noise performance, a 10µF

ceramicora10µFtantaluminparallelwitha0.1µFceramic

is recommended. The V_REFpin can be overdriven with an

external reference as shown in Figure 2. The voltage of the

external reference must be higher than the 2.5V of the

class A pull-up output of the internal reference. The

recommended range for an external reference is 2.55V to

V_DD. Anexternalreferenceat2.55VwillseeaDCquiescent

load of 0.75mA and as much as 3mA during conversion.

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LTC1403/LTC1403A Transfer

Characteristic

CMRR vs Frequency

0

111...111

111...110

111...101

–20

–40

–60

–80

000...010

000...001

000...000

–100

–120

100

10k

100k 1M

10M 100M

1k

0

FS – 1LSB

FREQUENCY (Hz)

INPUT VOLTAGE (V)

1403A F03

1403A F05

Figure 3

Figure 4

INPUT SPAN VERSUS REFERENCE VOLTAGE

the inputs. The common mode rejection holds up at

extremelyhighfrequencies,seeFigure3.Theonlyrequire-

ment is that both inputs not go below ground or exceed

V_DD. Integral nonlinearity errors (INL) and differential

nonlinearity errors (DNL) are largely independent of the

common mode voltage. However, the offset error will

vary. The change in offset error is typically less than 0.1%

of the common mode voltage.

The differential input range has a unipolar voltage span

that equals the difference between the voltage at the

referencebufferoutputV_REFatPin3, andthevoltageatthe

ground (Exposed Pad Ground). The differential input

range of the ADC is 0V to 2.5V when using the internal

reference. The internal ADC is referenced to these two

nodes. This relationship also holds true with an external

reference.

Figure 4 shows the ideal input/output characteristics for

the LTC1403/LTC1403A. The code transitions occur mid-

way between successive integer LSB values (i.e., 0.5LSB,

1.5LSB, 2.5LSB, FS – 1.5LSB). The output code is natural

binarywith1LSB=2.5V/16384=153µVfortheLTC1403A,

and 1LSB = 2.5V/4096 = 610µV for the LTC1403. The

LTC1403A has 1LSB RMS of random white noise.

DIFFERENTIAL INPUTS

The LTC1403/LTC1403A has a unique differential sample-

and-hold circuit that allows inputs from ground to V_DD.

The ADC will always convert the unipolar difference of

A_IN⁺– A_IN^–, independent of the common mode voltage at

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optimumperformance, a10µFsurfacemountAVXcapaci-

tor with a 0.1µF ceramic is recommended for the V_DDand

V_REFpins. Alternatively, 10µF ceramic chip capacitors

such as Murata GRM235Y5V106Z016 may be used. The

capacitorsmustbelocatedasclosetothepinsaspossible.

The traces connecting the pins and the bypass capacitors

must be kept short and should be made as wide as

possible.

Figure5showstherecommendedsystemgroundconnec-

tions. All analog circuitry grounds should be terminated at

the LTC1403/LTC1403A GND (Pins 4, 5, 6 and exposed

pad). The ground return from the LTC1403/LTC1403A

(Pins 4, 5, 6 and exposed pad) to the power supply should

belowimpedancefornoisefreeoperation.Digitalcircuitry

groundsmustbeconnectedtothedigitalsupplycommon.

In applications where the ADC data outputs and control

signals are connected to a continuously active micropro-

cessor bus, it is possible to get errors in the conversion

results. These errors are due to feedthrough from the

microprocessor to the successive approximation com-

parator. The problem can be eliminated by forcing the

microprocessor into a Wait state during conversion or by

using three-state buffers to isolate the ADC data bus.

Figure 5. Recommended Layout

Board Layout and Bypassing

POWER-DOWN MODES

Wire wrap boards are not recommended for high resolu-

tion and/or high speed A/D converters. To obtain the best

performance from the LTC1403/LTC1403A, a printed cir-

cuit board with ground plane is required. Layout for the

printed circuit board should ensure that digital and analog

signal lines are separated as much as possible. In particu-

lar, care should be taken not to run any digital track

alongside an analog signal track. If optimum phase match

between the inputs is desired, the length of the two input

wires should be kept matched.

Upon power-up, the LTC1403/LTC1403A is initialized to

the active state and is ready for conversion. The Nap and

Sleep mode waveforms show the power-down modes for

the LTC1403/LTC1403A. The SCK and CONV inputs con-

trol the power-down modes (see Timing Diagrams). Two

rising edges at CONV, without any intervening rising

edges at SCK, put the LTC1403/LTC1403A. in Nap mode

and the power drain drops from 14mW to 6mW. The

internal reference remains powered in Nap mode. One or

morerisingedgesatSCKwakeuptheLTC1403/LTC1403A

for service very quickly, and CONV can start an accurate

conversion within a clock cycle. Four rising edges at

High quality tantalum and ceramic bypass capacitors

should be used at the V_DDand V_REFpins as shown in the

Block Diagram on the first page of this data sheet. For

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CONV, without any intervening rising edges at SCK, put

the LTC1403/LTC1403A in Sleep mode and the power

drain drops from 16mW to 10µW. One or more rising

edges at SCK wake up the LTC1403/LTC1403A for opera-

tion. The internal reference (V_REF) takes 2ms to slew and

settle with a 10µF load. Note that, using sleep mode more

frequentlythanevery2ms, compromisesthesettledaccu-

racyoftheinternalreference. Notethat, forslowerconver-

sion rates, the Nap and Sleep modes can be used for

substantial reductions in power consumption.

sync input of the processor serial port. It is good practice

to drive the LTC1403/LTC1403A CONV input first to avoid

digital noise interference during the sample-to-hold tran-

sition triggered by CONV at the start of conversion. It is

also good practice to keep the width of the low portion of

the CONV signal greater than 15ns to avoid introducing

glitches in the front end of the ADC just before the sample-

and-hold goes into hold mode at the rising edge of CONV.

Minimizing Jitter on the CONV Input

Inhighspeedapplicationswherehighamplitudesinewaves

above 100kHz are sampled, the CONV signal must have as

little jitter as possible (10ps or less). The square wave

output of a common crystal clock module usually meets

this requirement easily. The challenge is to generate a

CONV signal from this crystal clock without jitter corrup-

tion from other digital circuits in the system. A clock

divider and any gates in the signal path from the crystal

clock to the CONV input should not share the same

integratedcircuitwithotherpartsofthesystem. Asshown

intheinterfacecircuitexamples, theSCKandCONVinputs

should be driven first, with digital buffers used to drive the

serial port interface. Also note that the master clock in the

DSP may already be corrupted with jitter, even if it comes

directly from the DSP crystal. Another problem with high

speed processor clocks is that they often use a low cost,

low speed crystal (i.e., 10MHz) to generate a fast, but

jittery, phase-locked-loop system clock (i.e., 40MHz). The

jitter in these PLL-generated high speed clocks can be

several nanoseconds. Note that if you choose to use the

frame sync signal generated by the DSP port, this signal

will have the same jitter of the DSP’s master clock.

DIGITAL INTERFACE

The LTC1403/LTC1403A has a 3-wire SPI (Serial Protocol

Interface) interface. The SCK and CONV inputs and SDO

output implement this interface. The SCK and CONV

inputs accept swings from 3V logic and are TTL compat-

ible, if the logic swing does not exceed V_DD. A detailed

description of the three serial port signals follows:

Conversion Start Input (CONV)

The rising edge of CONV starts a conversion, but subse-

quent rising edges at CONV are ignored by the LTC1403/

LTC1403A until the following 16 SCK rising edges have

occurred. It is necessary to have a minimum of 16 rising

edges of the clock input SCK between rising edges of

CONV. But to obtain maximum conversion speed, it is

necessary to allow two more clock periods between con-

versions to allow 39ns of acquisition time for the internal

ADC sample-and-hold circuit. With 16 clock periods per

conversion, the maximum conversion rate is limited to

2.8Msps to allow 39ns for acquisition time. In either case,

the output data stream comes out within the first 16 clock

periods to ensure compatibility with processor serial

ports. The duty cycle of CONV can be arbitrarily chosen to

be used as a frame sync signal for the processor serial

port. A simple approach to generate CONV is to create a

pulsethatisoneSCKwidetodrivetheLTC1403/LTC1403A

and then buffer this signal with the appropriate number of

inverters to ensure the correct delay driving the frame

Serial Clock Input (SCK)

The rising edge of SCK advances the conversion process

and also udpates each bit in the SDO data stream. After

CONVrises,thethirdrisingedgeofSCKstartsclockingout

the 12/14 data bits with the MSB sent first. A simple

approach is to generate SCK to drive the LTC1403/

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LTC1403A first and then buffer this signal with the appro-

priate number of inverters to drive the serial clock input of

the processor serial port. Use the falling edge of the clock

to latch data from the Serial Data Output (SDO) into your

processor serial port. The 14-bit Serial Data will be re-

ceived right justified, in a 16-bit word with 16 or more

clocks per frame sync. It is good practice to drive the

LTC1403/LTC1403A SCK input first to avoid digital noise

interference during the internal bit comparison decision

by the internal high speed comparator. Unlike the CONV

input, the SCK input is not sensitive to jitter because the

input signal is already sampled and held constant.

HARDWARE INTERFACE TO TMS320C54x

The LTC1403/LTC1403A is a serial output ADC whose

interface has been designed for high speed buffered serial

ports in fast digital signal processors (DSPs). Figure 6

shows an example of this interface using a TMS320C54X.

The buffered serial port in the TMS320C54x has direct

accesstoa2kBsegmentofmemory. TheADC’sserialdata

can be collected in two alternating 1kB segments, in real

time, at the full 2.8Msps conversion rate of the LTC1403/

LTC1403A.TheDSPassemblycodesetsframesyncmode

at the BFSR pin to accept an external positive going pulse

and the serial clock at the BCLKR pin to accept an external

positive edge clock. Buffers near the LTC1403/LTC1403A

may be added to drive long tracks to the DSP to prevent

corruption of the signal to LTC1403/LTC1403A. This con-

figuration is adequate to traverse a typical system board,

but source resistors at the buffer outputs and termination

resistors at the DSP, may be needed to match the charac-

teristic impedance of very long transmission lines. If you

need to terminate the SDO transmission line, buffer it first

with one or two 74ACTxx gates. The TTL threshold inputs

of the DSP port respond properly to the 3V swing from the

SDO pin.

Serial Data Output (SDO)

Upon power-up, the SDO output is automatically reset to

the high impedance state. The SDO output remains in high

impedance until a new conversion is started. SDO sends

out 12/14 bits in the output data stream beginning at the

thirdrisingedgeofSCKaftertherisingedgeofCONV.SDO

is always in high impedance mode when it is not sending

out data bits. Please note the delay specification from SCK

to a valid SDO. SDO is always guaranteed to be valid by the

next rising edge of SCK. The 16-bit output data stream is

compatible with the 16-bit or 32-bit serial port of most

processors.

3V

7

5V

V

CC

DD

10

9

CONV

SCK

BFSR

BCLKR

BDR

B13 B12

8

6

SDO

GND

LTC1403/

LTC1403A

TMS320C54x

CONV

CLK

3-WIRE SERIAL

INTERFACELINK

1403A F09

0V TO 3V LOGIC SWING

Figure 6. DSP Serial Interface to TMS320C54x

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; 01-08-01 ******************************************************************

; Files: 014SI.ASM -> 1403A Sine wave collection with Serial Port interface

;

bvectors.asm

s2k14ini.asm

buffered mode to avoid standard mode bug.

2k buffer size.

; first element at 1024, last element at 1023, two middles at 2047 and 0000

; unipolar mode

; Works 16 or 64 clock frames.

; negative edge BCLKR

; negative BFSR pulse

; -0 data shifted

; 1' cable from counter to CONV at DUT

; 2' cable from counter to CLK at DUT

; ***************************************************************************

.width

160

.length 110

.title "sineb0 BSP in auto buffer mode"

.mmregs

.setsect ".text",

0x500,0

;Set address of executable

.setsect "vectors", 0x180,0

.setsect "buffer", 0x800,0

.setsect "result", 0x1800,0

.text

;Set address of incoming 1403 data

;Set address of BSP buffer for clearing

;Set address of result for clearing

;.text marks start of code

start:

;this label seems necessary

;Make sure /PWRDWN is low at J1-9

;to turn off AC01 adc

tim=#0fh

prd=#0fh

tcr = #10h

tspc = #0h

pmst = #01a0h

sp = #0700h

dp = #0

; stop timer

; stop TDM serial port to AC01

; set up iptr. Processor Mode STatus register

; init stack pointer.

; data page

ar2 = #1800h

ar3 = #0800h

ar4 = #0h

; pointer to computed receive buffer.

; pointer to Buffered Serial Port receive buffer

; reset record counter

call sineinit

; Double clutch the initialization to insure a proper

sinepeek:

call sineinit

; reset. The external frame sync must occur 2.5 clocks

; or more after the port comes out of reset.

wait

;

goto

wait

----------------Buffered Receive Interrupt Routine ------------------

breceive:

ifr = #10h

TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer

if (NTC) goto bufull ; if this still the first half get next half

; clear interrupt flags

bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15))

return_enable

;

--------------mask and shift input data ----------------------------

bufull:

b = *ar3+ << -0

b = #03FFFh & b

; load acc b with BSP buffer and shift right -0

; mask out the TRISTATE bits with #03FFFh

;

*ar2+ = data(#0bh)

; store B to out buffer and advance AR2 pointer

TC = (@ar2 == #02000h) ; output buffer is 2k starting at 1800h

if (TC) goto start

goto bufull

; restart if out buffer is at 1fffh

1403af

15

LTC1403/LTC1403A

;

-------------------dummy bsend return------------------------

bsend

return_enable

;this is also a dummy return to define bsend

;in vector table file BVECTORS.ASM

;

----------------------- end ISR ----------------------------

.copy "c:\dskplus\1403\s2k14ini.asm"

;initialize buffered serial port

.space 16*32 ;clear a chunk at the end to mark the end

;======================================================================

;

VECTORS

;======================================================================

.sect "vectors" ;The vectors start here

.copy "c:\dskplus\1403\bvectors.asm" ;get BSP vectors

.sect "buffer"

.space 16*0x800

.sect "result"

.space 16*0x800

;Set address of BSP buffer for clearing

;Set address of result for clearing

.end

**********************************************************************

*

* File: s2k14ini.ASM BSP initialization code for the 'C54x DSKplus

*

for use with 1403A in standard mode

BSPC and SPC are the same in the 'C542

BSPCE and SPCE seem the same in the 'C542

**********************************************************************

.title "Buffered Serial Port Initialization Routine"

ON

.set 1

OFF

YES

.set !ON

.set 1

NO

.set !YES

.set 2

.set 1

.set 3

.set 0

BIT_8

BIT_10

BIT_12

BIT_16

GO

.set 0x80

**********************************************************************

* This is an example of how to initialize the Buffered Serial Port (BSP).

* The BSP is initialized to require an external CLK and FSX for

* operation. The data format is 16-bits, burst mode, with autobuffering

* enabled.

*

*****************************************************************************************************

*LTC1403 timing from LCC28 socket board with 10MHz crystal.

*10MHz, divided from 40MHz, forced to CLKIN by 1403 board.

*Horizontal scale is 25ns/chr or 100ns period at BCLKR

*Timing measured at DSP pins. Jxx pin labels for jumper cable.

*

*BFSR Pin J1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/~~~~~~~~~~~*

*BCLKR Pin J1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~*

*BDR

Pin J1-26 _---_---_---<B13-B12-B11-B10-B09-B08-B07-B06-B05-B04-B03-B02-B01-B00>---_---<B13-B12*

*CLKIN Pin J5-09 ~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~*

*C542 read

*

0

B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00

0

B13 B12*

*

1403af

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LTC1403/LTC1403A

* negative edge BCLKR

* negative BFSR pulse

* no data shifted

* 1' cable from counter to CONV at DUT

* 2' cable from counter to CLK at DUT

*No right shift is needed to right justify the input data in the main program

*the two msbs should also be masked

*

*****************************************************************************************************

*

Loopback

Format

IntSync

IntCLK

BurstMode

CLKDIV

PCM_Mode

FS_polarity

CLK_polarity

Frame_ignore

XMTautobuf

RCVautobuf

XMThalt

.set

NO

BIT_16

NO

YES

3

NO

YES

NO

!YES

NO

YES

NO

;(digital looback mode?)

;(Data format? 16,12,10,8)

;(internal Frame syncs generated?) TXM bit

;(internal clks generated?) MCM bit

;(if BurstMode=NO, then Continuous) FSM bit

;(3=default value, 1/4 CLOCKOUT)

;(Turn on PCM mode?)

;(change polarity)YES=^^^\_/^^^, NO=___/^\___

;(change polarity)for BCLKR YES=_/^, NO=~\_

;(inverted !YES -ignores frame)

;(transmit autobuffering)

DLB bit

FO bit

;(receive autobuffering)

;(transmit buff halt if XMT buff is full)

;(receive buff halt if RCV buff is full)

;(address of transmit buffer)

;(length of transmit buffer)

;(address of receive buffer)

RCVhalt

NO

XMTbufAddr

XMTbufSize

RCVbufAddr

RCVbufSize

*

0x800

0x000

0x800

;(length of receive buffer)works up to 800

* See notes in the 'C54x CPU and Peripherals Reference Guide on setting up

* valid buffer start and length values. Page 9-44

*

**********************************************************************

.eval ((Loopback >> 1)|((Format & 2)<<1)|(BurstMode <<3)|(IntCLK <<4)|(IntSync <<5)) ,SPCval

.eval (SPCEval|(XMTautobuf<<10)|(XMThalt<<12)|(RCVautobuf<<13)|(RCVhalt<<15)), SPCEval

sineinit:

bspc = #SPCval

ifr = #10h

; places buffered serial port in reset

; clear interrupt flags

imr = #210h

; Enable HPINT,enable BRINT0

intm = 0

; all unmasked interrupts are enabled.

; programs BSPCE and ABU

bspce = #SPCEval

axr = #XMTbufAddr

bkx = #XMTbufSize

arr = #RCVbufAddr

bkr = #RCVbufSize

bspc = #(SPCval | GO)

return

; initializes transmit buffer start address

; initializes transmit buffer size

; initializes receive buffer start address

; initializes receive buffer size

; bring buffered serial port out of reset

;for transmit and receive because GO=0xC0

; ***************************************************************************

; File: BVECTORS.ASM -> Vector Table for the 'C54x DSKplus 10.Jul.96

;

BSP vectors and Debugger vectors

TDM vectors just return

; ***************************************************************************

; The vectors in this table can be configured for processing external and

; internal software interrupts. The DSKplus debugger uses four interrupt

; vectors. These are RESET, TRAP2, INT2, and HPIINT.

;

*

DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER

*

1403af

17

LTC1403/LTC1403A

U

W U U

APPLICATIO S I FOR ATIO

; All other vector locations are free to use. When programming always be sure

; the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and

; host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the

; DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally.

;

.title "Vector Table"

.mmregs

reset

nmi

goto #80h

nop

;00; RESET * DO NOT MODIFY IF USING DEBUGGER *

;04; non-maskable external interrupt

return_enable

nop

trap2

int0

goto #88h

nop

.space 52*16

;08; trap2 * DO NOT MODIFY IF USING DEBUGGER *

;0C-3F: vectors for software interrupts 18-30

;40; external interrupt int0

return_enable

nop

int1

return_enable

nop

return_enable

nop

return_enable

nop

goto breceive

nop

;44; external interrupt int1

;48; external interrupt int2

;4C; internal timer interrupt

;50; BSP receive interrupt

;54; BSP transmit interrupt

;58; TDM receive interrupt

int2

tint

brint

bxint

trint

goto bsend

nop

return_enable

nop

txint

int3

return_enable

nop

;5C; TDM transmit interrupt

;60; external interrupt int3

return_enable

nop

hpiint

dgoto #0e4h

nop

;64; HPIint * DO NOT MODIFY IF USING DEBUGGER *

;68-7F; reserved area

.space 24*16

1403af

18

LTC1403/LTC1403A

U

PACKAGE DESCRIPTIO

MSE Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1663)

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.06 ± 0.102

2.794 ± 0.102

(.110 ± .004)

0.889 ± 0.127

(.035 ± .005)

(.081 ± .004)

1

1.83 ± 0.102

(.072 ± .004)

5.23

(.206)

MIN

2.083 ± 0.102 3.20 – 3.45

(.082 ± .004) (.126 – .136)

10

0.50

(.0197)

BSC

0.305 ± 0.038

(.0120 ± .0015)

TYP

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

0.497 ± 0.076

(.0196 ± .003)

REF

10 9

8

7 6

RECOMMENDED SOLDER PAD LAYOUT

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

4.90 ± 0.152

(.193 ± .006)

DETAIL “A”

0.254

(.010)

0° – 6° TYP

1

2

3

4 5

GAUGE PLANE

0.53 ± 0.152

(.021 ± .006)

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.127 ± 0.076

(.005 ± .003)

MSOP (MSE) 0603

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

1403af

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

19

LTC1403/LTC1403A

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

ADCs

LTC1608

16-Bit, 500ksps Parallel ADC

16-Bit, 333ksps Parallel ADC

16-Bit, 250ksps Serial ADC

14-Bit, 2.5Msps Parallel ADC

14-Bit, 2.2Msps Parallel ADC

±5V Supply, ±2.5V Span, 90dB SINAD

5V, Configurable Bipolar/Unipolar Inputs

5V, Selectable Spans, 80dB SINAD

±5V Supply, ±2.5V Span, 78dB SINAD

LTC1604

LTC1609

LTC1411

LCT1414

LTC1407/LTC1407A

LTC1420

12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, 14mW, MSOP Package

12-Bit, 10Msps Parallel ADC

12-Bit, 5Msps Parallel ADC

12-Bit, 3Msps Parallel ADC

12-Bit, 2.2Msps Serial ADC

16-Bit, 250ksps Serial ADC

5V, Selectable Spans, 72dB SINAD

LTC1405

5V, Selectable Spans, 115mW

LTC1412

±5V Supply, ±2.5V Span, 72dB SINAD

5V or ±5V Supply, 4.096V or ±2.5V Span

5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package

LTC1402

LTC1864/LTC1865

DACs

LTC1666/LTC1667/LTC1668 12-/14-/16-Bit, 50Msps DACs

87dB SFDR, 20ns Settling Time

LTC1592

16-Bit, Serial SoftSpan^TM

I

DAC

±1LSB INL/DNL, Software Selectable Spans

OUT

References

LT1790-2.5

LT1461-2.5

LT1460-2.5

Micropower Series Reference in SOT-23

Precision Voltage Reference

0.05% Initial Accuracy, 10ppm Drift

0.04% Initial Accuracy, 3ppm Drift

0.1% Initial Accuracy, 10ppm Drift

Micropower Series Voltage Reference

SoftSpan is a trademark of Linear Technology Corporation.

1403af

LT/TP 1203 1K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

LINEAR TECHNOLOGY CORPORATION 2002

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1403CMSE
厂家：	Linear
描述：	Serial 12-Bit/14-Bit, 2.8Msps Sampling ADCs with Shutdown 串行12位/ 14位， 2.8Msps采样ADC ，带有关断
文件：	总20页 (文件大小：324K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1403CMSE [Linear]

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LTC1403HMSE#PBF

LTC1403HMSE#TR

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