LTC1403_15_技术文档

LTC1403/LTC1403A

Serial 12-Bit/14-Bit, 2.8Msps

Sampling ADCs with Shutdown

FEATURES

DESCRIPTION

The LTC^®1403/LTC1403A are 12-bit/14-bit, 2.8Msps se-

rial ADCs with differential inputs. The devices draw only

4.7mA from a single 3V supply and come in a tiny 10-lead

MS package. A Sleep shutdown feature lowers power

■

2.8Msps Conversion Rate

■

Low Power Dissipation: 14mW

■

3V Single Supply Operation

–40°C to 125°C Guaranteed Operation

2.5V Internal Bandgap Reference can be Overdriven

3-Wire Serial Interface

Sleep (10μW) Shutdown Mode

Nap (3mW) Shutdown Mode

80dB Common Mode Rejection

0V to 2.5V Unipolar Input Range

Tiny 10-Lead MS Package

■

consumption to 10μW. The combination of speed, low

power and tiny package makes the LTC1403/LTC1403A

suitable for high speed, portable applications.

■

The80dBcommonmoderejectionallowsuserstoeliminate

ground loops and common mode noise by measuring

signals differentially from the source.

Thedevicesconvert0Vto2.5Vunipolarinputsdifferentially.

Theabsolutevoltageswingfor+A and–A extendsfrom

IN

APPLICATIONS

ground to the supply voltage.

■

Automotive

Theserialinterfacesendsouttheconversionresultsduring

the16clockcyclesfollowingCONV↑forcompatibilitywith

standard serial interfaces. If two additional clock cycles

for acquisition time are allowed after the data stream in

between conversions, the full sampling rate of 2.8Msps

can be achieved with a 50.4MHz clock.

■

Communications

■

Data Acquisition Systems

■

Uninterrupted Power Supplies

■

Multiphase Motor Control

■

Multiplexed Data Acquisition

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

BLOCK DIAGRAM

10μF 3V

2nd, 3rd and SFDR vs

Input Frequency

7

–44

V

LTC1403A

DD

–50

–56

+

–

THREE-

STATE

SERIAL

OUTPUT

PORT

A

IN

1

2

+

THD

2nd, SFDR

14-BIT ADC

SDO

–62

S & H

8

–68

–74

–

14

3rd

–80

–86

V

REF

3

4

10

9

CONV

SCK

2.5V

REFERENCE

TIMING

LOGIC

10μF

–92

GND

5

–98

1403A TA01

–104

6

11

EXPOSED PAD

0.1

1

10

100

FREQUENCY (MHz)

1403A TA02

1403fb

1

LTC1403/LTC1403A

ABSOLUTE MAXIMUM RATINGS

PACKAGE/ORDER INFORMATION

(Note 1, 2,)

TOP VIEW

+

–

Supply Voltage (V ) ..................................................4V

DD

A

1

2

3

4

5

10 CONV

IN

9

8

7

6

SCK

SDO

DD

GND

Analog Input Voltage

V

11

REF

GND

(Note 3) ....................................–0.3V to (V + 0.3V)

V

DD

Digital Input Voltage......................–0.3V to (V + 0.3V)

DD

MSE PACKAGE

10-LEAD PLASTIC MSOP

Digital Output Voltage ...................–0.3V to (V + 0.3V)

DD

T

JMAX

= 150°C, θ = 40°C/W

JA

Power Dissipation.............................................. 100mW

EXPOSED PAD IS GND (PIN 11)

MUST BE SOLDERED TO PCB

Operation Temperature Range

LTC1403C/LTC1403AC............................. 0°C to 70°C

LTC1403I/LTC1403AI........................... –40°C to 85°C

LTC1403H/LTC1403AH ...................... –40°C to 125°C

Storage Temperature Range................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

ORDER PART NUMBER

MSE PART MARKING

LTC1403CMSE

LTC1403IMSE

LTC1403HMSE

LTC1403ACMSE

LTC1403AIMSE

LTC1403AHMSE

LTBDN

LTBDP

LTADF

LTAFD

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

CONVERTER CHARACTERISTICS ^The● denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. With internal reference. V_DD= 3V

LTC1403

LTC1403H

LTC1403A

LTC1403AH

PARAMETER

CONDITIONS

UNITS

MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

●

Resolution (No Missing Codes)

Integral Linearity Error

Offset Error

12

–2

12

–2

14

–4

14

–4

Bits

LSB

(Notes 4, 5, 18)

(Notes 4, 18)

(Note 4, 18)

0.25

1

2

0.25

2

0.5

2

4

0.5

2

4

–10

–30

10 –20

30 –40

20 –20

40 –60

20 –30

30

Gain Error

5

10 60 –80

10 80

Gain Tempco

Internal Reference (Note 4)

External Reference

15

1

15

1

15

1

15

1

ppm/°C

ANALOG INPUT ^The● denotes the speciﬁcations which apply over the full operating temperature range, otherwise

speciﬁcations are at T_A= 25°C. V_DD= 3V

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

●

V

Analog Differential Input Range (Notes 3, 9)

Analog Common Mode + Differential Input Range (Note 10)

Analog Input Leakage Current

2.7V ≤ V ≤ 3.3V

0 to 2.5

IN

DD

0 to V

V

CM

DD

I

IN

1

μA

pF

C

IN

Analog Input Capacitance

13

t

Sample-and-Hold Acquisition Time

Sample-and-Hold Aperture Delay Time

Sample-and-Hold Aperture Delay Time Jitter

Analog Input Common Mode Rejection Ratio

(Note 6)

39

ns

ACQ

AP

1

ns

0.3

ps

JITTER

CMRR

f

IN

f

IN

= 1MHz, V = 0V to 3V

= 100MHz, V = 0V to 3V

–60

–15

dB

IN

1403fb

2

LTC1403/LTC1403A

DYNAMIC ACCURACY ^The● denotes the speciﬁcations which apply over the full operating temperature range,

otherwise speciﬁcations are at T_A= 25°C. V_DD= 3V

LTC1403/LTC1403H

LTC1403A/LTC1403AH

SYMBOL PARAMETER

CONDITIONS

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

SINAD

Signal-to-Noise Plus

Distortion Ratio

100kHz Input Signal

70.5

72

73.5

73.0

76.3

dB

●

1.4MHz Input Signal

68

67

70

69

1.4MHz Input Signal (H Grade)

100kHz Input Signal, External V = 3.3V,

REF

V

DD

≥ 3.3V

750kHz Input Signal, External V = 3.3V,

72

76.3

dB

REF

V

DD

≥ 3.3V

THD

SFDR

IMD

Total Harmonic

Distortion

100kHz First 5 Harmonics

1.4MHz First 5 Harmonics

–87

–83

–90

–86

dB

●

–76

–78

Spurious Free

Dynamic Range

100kHz Input Signal

1.4MHz Input Signal

–87

–83

–90

–86

dB

+

Intermodulation

Distortion

1.25V to 2.5V 1.25MHz into A , 0V to 1.25V,

–82

dB

IN

–

1.2MHz into A

IN

Code-to-Code

Transition Noise

V

REF

= 2.5V (Note 18)

0.25

1

LSB

RMS

Full Power Bandwidth

Full Linear Bandwidth

V

= 2.5V , SDO = 11585LSB (Note 15)

50

5

50

5

MHz

IN

P-P

S/(N + D) ≥ 68dB

INTERNAL REFERENCE CHHARACTERISTICS^The● denotes the speciﬁcations which apply over the

full operating temperature range, otherwise speciﬁcations are at T_A= 25°C. V_DD= 3V

PARAMETER

CONDITIONS

= 0

MIN

TYP

2.5

15

MAX

UNITS

V

Output Voltage

Output Tempco

Line Regulation

Output Resistance

Settling Time

I

OUT

REF

ppm//°C

μV/V

Ω

V

DD

= 2.7V to 3.6V, V = 2.5V

600

0.2

2

REF

Load Current = 0.5mA

ms

DIGITAL INPUTS AND DIGITAL OUTPUTS ^The● denotes the speciﬁcations which apply over the full

operating temperature range, otherwise speciﬁcations are at T_A= 25°C. V_DD= 3V

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

●

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

V

= 3.3V

= 2.7V

2.4

V

IH

IL

DD

IN

0.6

10

I

= 0V to V

μA

pF

V

IN

DD

C

V

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

5

IN

●

V

DD

= 3V, I = –200μA

OUT

2.5

2.9

OH

OL

V

DD

V

DD

= 2.7V, I

= 160μA

= 1.6mA

0.05

0.10

V

OUT

●

0.4

10

I

OZ

Hi-Z Output Leakage D

V

= 0V to V

DD

μA

pF

OUT

C

OZ

Hi-Z Output Capacitance D

1

OUT

I

Output Short-Circuit Source Current

Output Short-Circuit Sink Current

V

= 0V, V = 3V

20

15

mA

SOURCE

SINK

OUT

DD

I

= V = 3V

OUT

DD

1403fb

3

LTC1403/LTC1403A

POWER REQUIREMENTS ^The● denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. (Note 17)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Supply Voltage

2.7

3.6

V

DD

●

I

DD

Positive Supply Voltage

Active Mode

4.7

5.2

1.1

1.2

2

7

mA

μA

Active Mode (LTC1403H, LTC1403AH)

Nap Mode

8

1.5

1.8

15

10

Nap Mode (LTC1403H, LTC1403AH)

Sleep Mode (LTC1403, LTC1403H)

Sleep Mode (LTC1403A, LTC1403AH)

2

μA

P

D

Power Dissipation

Active Mode with SCK in Fixed State (Hi or Lo)

12

mW

TIMING CHARACTERISTICS ^The● denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. V_DD= 3V

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

●

f

t

Maximum Sampling Frequency per Channel (Conversion Rate)

Minimum Sampling Period (Conversion + Acquisiton Period)

Clock Period

2.8

MHz

SAMPLE(MAX)

357

ns

THROUGHPUT

(Notes 16)

(Note 6)

19.8

16

2

10000

ns

SCK

Conversion Time

18

SCLK cycles

CONV

Minimum Positive or Negative SCLK Pulse Width

CONV to SCK Setup Time

(Note 6)

ns

ms

1

(Notes 6, 10)

(Note 6)

3

1

Nearest SCK Edge Before CONV

0

3

Minimum Positive or Negative CONV Pulse Width

SCK to Sample Mode

(Note 6)

4

(Note 6)

4

5

CONV to Hold Mode

(Notes 6, 11)

(Notes 6, 7, 13)

(Notes 6, 12)

(Notes 6, 14)

1.2

45

8

6

16th SCK↑ to CONV↑ Interval (Affects Acquisition Period)

Minimum Delay from SCK to Valid Bits 0 Through 13

SCK to Hi-Z at SDO

7

8

6

9

Previous SDO Bit Remains Valid After SCK

2

10

12

V

Settling Time After Sleep-to-Wake Transition

2

REF

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device reliability

and lifetime.

Note 10: If less than 3ns is allowed, the output data will appear one clock

cycle later. It is best for CONV to rise half a clock before SCK, when running

the clock at rated speed.

Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns)

because the 2.2ns delay through the sample-and-hold is subtracted from

the CONV to Hold mode delay.

Note 2: All voltage values are with respect to GND.

Note 3: When these pins are taken below GND or above V , they will be

DD

clamped by internal diodes. This product can handle input currents greater

Note 12: The rising edge of SCK is guaranteed to catch the data coming out

into a storage latch.

than 100mA below GND or greater than V without latchup.

DD

Note 4: Offset and full-scale speciﬁcations are measured for a single-ended

Note 13: The time period for acquiring the input signal is started by the

16th rising clock and it is ended by the rising edge of convert.

+

–

A

input with A grounded and using the internal 2.5V reference.

IN

Note 5: Integral linearity is tested with an external 2.55V reference and is

deﬁned as the deviation of a code from the straight line passing through the

actual endpoints of a transfer curve. The deviation is measured from the

center of quantization band.

Note 6: Guaranteed by design, not subject to test.

Note 7: Recommended operating conditions.

Note 14: The internal reference settles in 2ms after it wakes up from Sleep

mode with one or more cycles at SCK and a 10μF capacitive load.

Note 15: The full power bandwidth is the frequency where the output code

swing drops to 3dB with a 2.5V input sine wave.

P-P

Note 16: Maximum clock period guarantees analog performance during

conversion. Output data can be read without an arbitrarily long clock.

Note 8: The analog input range is deﬁned for the voltage difference between

Note 17: V = 3V, f

= 2.8Msps.

DD

SAMPLE

+

–

A

and A

.

IN

Note 18: The LTC1403A is measured and speciﬁed with 14-bit Resolution

(1LSB = 152μV) and the LTC1403 is measured and speciﬁed with 12-bit

Resolution (1LSB = 610μV).

+

–

Note 9: The absolute voltage at A and A must be within this range.

IN

1403fb

4

LTC1403/LTC1403A

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, V_DD= 3V (LTC1403A)

ENOBs and SINAD

vs Input Frequency

THD, 2nd and 3rd vs Input

Frequency

SFDR vs Input Frequency

–44

–50

–56

–62

12.0

11.5

11.0

10.5

10.0

9.5

74

71

68

65

62

59

56

53

50

104

98

92

86

80

74

68

62

56

50

44

THD

2nd

–68

–74

3rd

–80

–86

9.0

–92

8.5

–98

–104

8.0

0.1

1

10

100

0.1

1

10

100

0.1

1

10

100

FREQUENCY (MHz)

1403A G02

1403A G01

1403A G17

98kHz Sine Wave 4096 Point

FFT Plot

1.3MHz Sine Wave 4096 Point

FFT Plot

SNR vs Input Frequency

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

74

71

68

65

62

59

56

53

50

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

2.8Msps

0

350k

700k

1.05M

1.4M

0.1

1

10

100

0

350k

700k

1.05M

1.4M

FREQUENCY (Hz)

FREQUENCY (MHz)

1403A G05

1403A G03

1403A G04

1.4MHz Input Summed with

1.56MHz Input IMD 4096 Point

FFT Plot

Differential Linearity

vs Output Code

Integral Linearity

vs Output Code

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

4

3

1.0

0.8

2.8Msps

0.6

2

0.4

1

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1

–2

–3

–4

0

350k

700k

1.05M

1.4M

0

4096

8192

12288

16383

0

4096

8192

12288

16383

FREQUENCY (Hz)

OUTPUT CODE

1403A G06

1403A G14

1403A G13

1403fb

5

LTC1403/LTC1403A

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, V_DD= 3V (LTC1403A)

SINAD vs Conversion Rate

Differential and Integral Linearity

vs Conversion Rate

80

79

78

77

76

75

74

73

72

71

70

5

4

18 CLOCKS PER CONVERSION

EXTERNAL V

= 3.3V f ~f /3

IN S

MAX INL

REF

3

2

MAX DNL

EXTERNAL V

= 3.3V f ~f /40

IN S

REF

1

0

–1

–2

–3

–4

–5

MIN DNL

MIN INL

INTERNAL V

= 2.5V f ~f /40

IN S

REF

INTERNAL V

= 2.5V f ~f /3

IN S

REF

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

CONVERSION RATE (Msps)

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

CONVERSION RATE (Msps)

1403A G16

1403A G15

T_A= 25°C, V_DD= 3V (LTC1403 and LTC1403A)

2.5V_P-PPower Bandwidth

CMRR vs Frequency

PSRR vs Frequency

0

–20

12

–25

–30

–35

–40

–45

–50

–55

–60

–65

6

0

–40

–6

–60

–12

–18

–80

–24

–30

–36

–100

–120

–70

100

10k

100k 1M

10M 100M

1k

1M

10M

100M

1G

1

10

100

1k

10k 100k

1M

FREQUENCY (Hz)

1403A G07

1403A G08

1403A G09

Reference Voltage vs Load

Current

V_DDSupply Current vs

Conversion Rate

Reference Voltage vs V_DD

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

2.4902

2.4900

2.4898

2.4896

2.4894

2.4892

2.4890

2.4902

2.4900

2.4898

2.4896

2.4894

2.4892

2.4890

0

0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0

CONVERSION RATE (Msps)

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

LOAD CURRENT (mA)

2.6

2.8

3.0

3.2

(V)

3.4

3.6

V

DD

1403A G12

1403A G10

1403A G11

1403fb

6

LTC1403/LTC1403A

PIN FUNCTIONS

+

A

(Pin 1): Noninverting Analog Input. A operates (or 10μF tantalum in parallel with 0.1μF ceramic). Keep in

IN

–

fully differentially with respect to A with a 0V to 2.5V mindthatinternalanalogcurrentsanddigitaloutputsignal

IN

differential swing and a 0V to V common mode swing. currents ﬂow through this pin. Care should be taken to

DD

place the 0.1μF bypass capacitor as close to Pins 6 and

7 as possible.

–

A

(Pin 2): Inverting Analog Input. A

operates

IN

+

fully differentially with respect to A with a –2.5V to 0V

IN

differential swing and a 0V to V common mode swing. SDO (Pin 8): Three-State Serial Data Output. Each of

DD

output data words represents the difference between

V

(Pin 3): 2.5V Internal Reference. Bypass to GND

REF

+

–

A

and A analog inputs at the start of the previous

IN

and to a solid analog ground plane with a 10μF ceramic

capacitor(or10μFtantaluminparallelwith0.1μFceramic).

conversion.

Can be overdriven by an external reference between 2.55V SCK (Pin 9): External Clock Input. Advances the conver-

and V .

sion process and sequences the output data on the rising

edge. Responds to TTL (≤3V) and 3V CMOS levels. One

or more pulses wake from sleep.

DD

GND (Pins 5, 6, 11): Ground and Exposed Pad. These

ground pins and the exposed pad must be tied directly to

the solid ground plane under the part. Keep in mind that CONV(Pin10):ConvertStart.Holdstheanaloginputsignal

analog signal currents and digital output signal currents and starts the conversion on the rising edge. Responds

ﬂow through these pins.

to TTL (≤3V) and 3V CMOS levels. Two pulses with SCK

in ﬁxed high or ﬁxed low state start Nap mode. Four or

more pulses with SCK in ﬁxed high or ﬁxed low state start

Sleep mode.

V

(Pin 7): 3V Positive Supply. This single power pin

DD

supplies 3V to the entire chip. Bypass to GND and to a

solid analog ground plane with a 10μF ceramic capacitor

BLOCK DIAGRAM

10μF 3V

7

V

LTC1403A

DD

+

–

THREE-

STATE

SERIAL

OUTPUT

PORT

A

IN

1

2

+

14-BIT ADC

SDO

S & H

8

–

14

V

REF

3

4

10

9

CONV

SCK

2.5V

REFERENCE

TIMING

LOGIC

10μF

GND

5

1403A BD

6

11

EXPOSED PAD

1403fb

7

LTC1403/LTC1403A

TIMING DIAGRAM

LTC1403 Timing Diagram

t

2

t

7

t

3

t

1

16

17

1

2

3

4

5

6

7

8

9

10

11

12

13

15

t

16

17

18

1

14

SCK

t

4

5

CONV

t

6

t

ACQ

INTERNAL

S/H STATUS

SAMPLE

HOLD

SAMPLE

HOLD

t

8

t

9

t

8

t

10

SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

Hi-Z

SDO

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1

D0

X

1403A TD01

14-BIT DATA WORD

CONV

t

THROUGHPUT

*BITS MARKED "X" AFTER D0 SHOULD BE IGNORED.

LTC1403A Timing Diagram

t

2

t

7

t

3

t

1

16

17

1

2

3

4

5

6

7

8

9

10

11

12

13

15

t

16

17

18

1

14

SCK

t

4

5

CONV

t

6

t

ACQ

INTERNAL

S/H STATUS

SAMPLE

HOLD

SAMPLE

HOLD

t

8

t

9

t

8

t

10

SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

Hi-Z

SDO

D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3

D2

D1

D0

1403A TD01b

14-BIT DATA WORD

CONV

t

THROUGHPUT

Nap Mode and Sleep Mode Waveforms

SLK

t

1

t

1

CONV

NAP

SLEEP

t

12

V

REF

1403A TD02

NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS

SCK to SDO Delay

SCK

V

IH

V

IH

t

10

8

t

9

V

90%

10%

OH

SDO

OL

1403A TD03

1403fb

8

LTC1403/LTC1403A

APPLICATIONS INFORMATION

DRIVING THE ANALOG INPUT

available in the Linear Technology Databooks and on the

LinearView^TMCD-ROM.)

LTC^®1566-1: Low Noise 2.3MHz Continuous Time Low-

Pass Filter.

The differential analog inputs of the LTC1403/LTC1403A

are easy to drive. The inputs may be driven differentially or

–

as a single-ended input (i.e., the A input is grounded).

IN

+

–

Bothdifferentialanaloginputs,A withA ,aresampled

IN

LT1630: Dual 30MHz Rail-to-Rail Voltage FB Ampliﬁer.

at the same instant. Any unwanted signal that is common

to both inputs of each input pair will be reduced by the

common mode rejection of the sample-and-hold circuit.

Theinputsdrawonlyonesmallcurrentspikewhilecharging

the sample-and-hold capacitors at the end of conversion.

During conversion, the analog inputs draw only a small

leakage current. If the source impedance of the driving

circuit is low, then the LTC1403/LTC1403A inputs can be

driven directly. As source impedance increases, so will

acquisition time. For minimum acquisition time with high

source impedance, a buffer ampliﬁer must be used. The

main requirement is that the ampliﬁer driving the analog

input(s) must settle after the small current spike before

the next conversion starts (settling time must be 39ns for

full throughput rate). Also keep in mind while choosing an

input ampliﬁer, the amount of noise and harmonic distor-

tion added by the ampliﬁer.

2.7V to 15V supplies. Very high A , 500μV offset and

VOL

520ns settling to 0.5LSB for a 4V swing. THD and noise

are –93dB to 40kHz and below 1LSB to 320kHz (A = 1,

V

2V into 1kΩ, V = 5V), making the part excellent for AC

P-P

S

applications(to1/3Nyquist)whererail-to-railperformance

is desired. Quad version is available as LT1631.

LT1632: Dual 45MHz Rail-to-Rail Voltage FB Ampliﬁer.

2.7V to 15V supplies. Very high A , 1.5mV offset and

VOL

400ns settling to 0.5LSB for a 4V swing. It is suitable

for applications with a single 5V supply. THD and noise

are –93dB to 40kHz and below 1LSB to 800kHz (A = 1,

V

2V into 1kΩ, V = 5V), making the part excellent for

P-P

S

AC applications where rail-to-rail performance is desired.

Quad version is available as LT1633.

LT1813: Dual 100MHz 750V/μs 3mA Voltage Feedback

Ampliﬁer. 5V to 5V supplies. Distortion is –86dB to

100kHz and –77dB to 1MHz with 5V supplies (2V

P-P

into 500Ω). Excellent part for fast AC applications with

CHOOSING AN INPUT AMPLIFIER

5V supplies.

Choosing an input ampliﬁer is easy if a few requirements

are taken into consideration. First, to limit the magnitude

of the voltage spike seen by the ampliﬁer from charging

the sampling capacitor, choose an ampliﬁer that has a low

output impedance (<100Ω) at the closed-loop bandwidth

frequency. For example, if an ampliﬁer is used in a gain

of 1 and has a unity-gain bandwidth of 50MHz, then the

output impedance at 50MHz must be less than 100Ω. The

secondrequirementisthattheclosed-loopbandwidthmust

be greater than 40MHz to ensure adequate small-signal

settling for full throughput rate. If slower op amps are

used, more time for settling can be provided by increasing

the time between conversions. The best choice for an op

amp to drive the LTC1403/LTC1403A will depend on the

application.Generally,applicationsfallintotwocategories:

AC applications where dynamic speciﬁcations are most

critical and time domain applications where DC accuracy

and settling time are most critical. The following list is

a summary of the op amps that are suitable for driving

the LTC1403/LTC1403A. (More detailed information is

LT1801:80MHzGBWP,–75dBcat500kHz,2mA/Ampliﬁer,

8.5nV/√Hz.

LT1806/LT1807: 325MHz GBWP, –80dBc Distortion at

5MHz, Unity-Gain Stable, R-R In and Out, 10mA/Ampli-

ﬁer, 3.5nV/√Hz.

LT1810:180MHzGBWP,–90dBcDistortionat5MHz,Unity-

Gain Stable, R-R In and Out, 15mA/Ampliﬁer, 16nV/√Hz.

LT1818/LT1819: 400MHz, 2500V/μs,9mA, Single/Dual

Voltage Mode Operational Ampliﬁer.

LT6200: 165MHz GBWP, –85dBc Distortion at 1MHz,

Unity-Gain Stable, R-R In and Out, 15mA/Ampliﬁer,

0.95nV/√Hz.

LT6203:100MHzGBWP,–80dBcDistortionat1MHz,Unity-

Gain Stable, R-R In and Out, 3mA/Ampliﬁer, 1.9nV/√Hz.

LT6600-10:Ampliﬁer/FilterDifferentialIn/Outwith10MHz

Cutoff.

LinearView is a trademark of Linear Technology Corporation.

1403fb

9

LTC1403/LTC1403A

APPLICATIONS INFORMATION

51Ω

1

+

A

V

IN

3

47pF

3V

REF

V

REF

2

–

IN

LTC1403/

LTC1403A

LTC1403/

LTC1403A

REF

10μF

3

11

GND

10μF

1403A F02

11

GND

1403A F01

Figure 1. RC Input Filter

Figure 2

INPUT FILTERING AND SOURCE IMPEDANCE

INPUT RANGE

Thenoiseandthedistortionoftheinputampliﬁerandother

circuitry must be considered since they will add to the

LTC1403/LTC1403Anoiseanddistortion.Thesmall-signal

bandwidth of the sample-and-hold circuit is 50MHz. Any

noise or distortion products that are present at the analog

inputs will be summed over this entire bandwidth. Noisy

input circuitry should be ﬁltered prior to the analog inputs

tominimizenoise. Asimple1-poleRCﬁlterissufﬁcientfor

The analog inputs of the LTC1403/LTC1403A may be

driven fully differentially with a single supply. Each input

may swing up to 3V

individually. In the conversion

P-P

range, the noninverting input of each channel is always

up to 2.5V more positive than the inverting input of each

channel. The 0V to 2.5V range is also ideally suited for

single-endedinputusewithsinglesupplyapplications.The

common mode range of the inputs extend from ground

many applications. For example, Figure 1 shows a 47pF

to the supply voltage V . If the difference between the

DD

+

–

capacitorfromA togroundanda51Ωsourceresistorto

A

and A inputs exceeds 2.5V, the output code will

IN

IN IN

limittheinputbandwidthto47MHz.The47pFcapacitoralso

acts as a charge reservoir for the input sample-and-hold

and isolates the ADC input from sampling-glitch sensitive

circuitry. High quality capacitors and resistors should be

used since these components can add distortion. NPO

and silvermica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

occurduringsoldering.Metalﬁlmsurfacemountresistors

are much less susceptible to both problems. When high

amplitude unwanted signals are close in frequency to the

desired signal frequency, a multiple pole ﬁlter is required.

Highexternalsourceresistance,combinedwiththe13pFof

input capacitance, will reduce the rated 50MHz bandwidth

and increase acquisition time beyond 39ns.

stay ﬁxed at all ones and if this difference goes below 0V,

the ouput code will stay ﬁxed at all zeros.

INTERNAL REFERENCE

The LTC1403/LTC1403A has an on-chip, temperature

compensated, bandgap reference that is factory trimmed

near2.5Vtoobtain2.5Vinputspan.Thereferenceampliﬁer

output V , (Pin 3) must be bypassed with a capacitor to

REF

ground. The reference ampliﬁer is stable with capacitors

of 1μF or greater. For the best noise performance, a 10μF

ceramicora10μFtantaluminparallelwitha0.1μFceramic

is recommended. The V pin can be overdriven with an

REF

external reference as shown in Figure 2. The voltage of

the external reference must be higher than the 2.5V of the

classApull-upoutputoftheinternalreference.Therecom-

mended range for an external reference is 2.55V to V .

DD

An external reference at 2.55V will see a DC quiescent load

of 0.75mA and as much as 3mA during conversion.

1403fb

10

LTC1403/LTC1403A

APPLICATIONS INFORMATION

LTC1403/LTC1403A Transfer

Characteristic

CMRR vs Frequency

0

111...111

111...110

111...101

–20

–40

–60

–80

000...010

000...001

000...000

–100

–120

100

10k

100k 1M

10M 100M

1k

0

FS – 1LSB

FREQUENCY (Hz)

INPUT VOLTAGE (V)

1403A F03

1403A F05

Figure 3

Figure 4

at the inputs. The common mode rejection holds up at

extremelyhighfrequencies,seeFigure3.Theonlyrequire-

ment is that both inputs not go below ground or exceed

INPUT SPAN VERSUS REFERENCE VOLTAGE

Thedifferentialinputrangehasaunipolarvoltagespanthat

equals the difference between the voltage at the reference

V . Integral nonlinearity errors (INL) and differential

DD

buffer output V at Pin 3, and the voltage at the ground

REF

nonlinearity errors (DNL) are largely independent of the

commonmodevoltage.However,theoffseterrorwillvary.

The change in offset error is typically less than 0.1% of

the common mode voltage.

(Exposed Pad Ground). The differential input range of

the ADC is 0V to 2.5V when using the internal reference.

The internal ADC is referenced to these two nodes. This

relationship also holds true with an external reference.

Figure 4 shows the ideal input/output characteristics for

the LTC1403/LTC1403A. The code transitions occur mid-

way between successive integer LSB values (i.e., 0.5LSB,

1.5LSB, 2.5LSB, FS – 1.5LSB). The output code is natural

binarywith1LSB=2.5V/16384=153μVfortheLTC1403A,

and 1LSB = 2.5V/4096 = 610μV for the LTC1403. The

LTC1403A has 1LSB RMS of random white noise.

DIFFERENTIAL INPUTS

The LTC1403/LTC1403A has a unique differential sample-

and-hold circuit that allows inputs from ground to V .

DD

The ADC will always convert the unipolar difference of

+

–

A

– A , independent of the common mode voltage

IN

1403fb

11

LTC1403/LTC1403A

APPLICATIONS INFORMATION

For optimum performance, a 10μF surface mount AVX

capacitor with a 0.1μF ceramic is recommended for

the V and V

pins. Alternatively, 10μF ceramic chip

DD

REF

capacitors such as Murata GRM235Y5V106Z016 may

be used. The capacitors must be located as close to the

pins as possible. The traces connecting the pins and the

bypass capacitors must be kept short and should be made

as wide as possible.

Figure5showstherecommendedsystemgroundconnec-

tions. All analog circuitry grounds should be terminated

at the LTC1403/LTC1403A GND (Pins 4, 5, 6 and exposed

pad).ThegroundreturnfromtheLTC1403/LTC1403A(Pins

4, 5, 6 and exposed pad) to the power supply should be

low impedance for noise free operation. Digital circuitry

grounds must be connected to the digital supply com-

mon. In applications where the ADC data outputs and

control signals are connected to a continuously active

microprocessor bus, it is possible to get errors in the

conversion results. These errors are due to feedthrough

fromthemicroprocessortothesuccessiveapproximation

comparator. The problem can be eliminated by forcing the

microprocessor into a Wait state during conversion or by

using three-state buffers to isolate the ADC data bus.

Figure 5. Recommended Layout

POWER-DOWN MODES

Board Layout and Bypassing

Upon power-up, the LTC1403/LTC1403A is initialized to

the active state and is ready for conversion. The Nap and

Sleep mode waveforms show the power-down modes for

theLTC1403/LTC1403A.TheSCKandCONVinputscontrol

thepower-downmodes(seeTimingDiagrams).Tworising

edgesatCONV,withoutanyinterveningrisingedgesatSCK,

put the LTC1403/LTC1403A in Nap mode and the power

drain drops from 14mW to 6mW. The internal reference

remains powered in Nap mode. One or more rising edges

at SCK wake up the LTC1403/LTC1403A for service very

quickly, andCONVcanstartanaccurateconversionwithin

a clock cycle. Four rising edges at CONV, without any

Wire wrap boards are not recommended for high resolu-

tion and/or high speed A/D converters. To obtain the best

performancefromtheLTC1403/LTC1403A,aprintedcircuit

boardwithgroundplaneisrequired. Layoutfortheprinted

circuit board should ensure that digital and analog signal

lines are separated as much as possible. In particular, care

should be taken not to run any digital track alongside an

analog signal track. If optimum phase match between the

inputs is desired, the length of the two input wires should

be kept matched.

High quality tantalum and ceramic bypass capacitors

should be used at the V and V

pins as shown in

DD

REF

the Block Diagram on the ﬁrst page of this data sheet.

1403fb

12

LTC1403/LTC1403A

APPLICATIONS INFORMATION

interveningrisingedgesatSCK,puttheLTC1403/LTC1403A

in Sleep mode and the power drain drops from 16mW

to 10μW. One or more rising edges at SCK wake up the

LTC1403/LTC1403A for operation. The internal reference

the processor serial port. It is good practice to drive the

LTC1403/LTC1403A CONV input ﬁrst to avoid digital noise

interferenceduringthesample-to-holdtransitiontriggered

by CONV at the start of conversion. It is also good practice

to keep the width of the low portion of the CONV signal

greater than 15ns to avoid introducing glitches in the front

end of the ADC just before the sample-and-hold goes into

hold mode at the rising edge of CONV.

(V ) takes 2ms to slew and settle with a 10μF load.

REF

Note that, using sleep mode more frequently than every

2ms, compromises the settled accuracy of the internal

reference. Note that, for slower conversion rates, the Nap

and Sleep modes can be used for substantial reductions

in power consumption.

Minimizing Jitter on the CONV Input

Inhighspeedapplicationswherehighamplitudesinewaves

above 100kHz are sampled, the CONV signal must have

as little jitter as possible (10ps or less). The square wave

output of a common crystal clock module usually meets

thisrequirementeasily.ThechallengeistogenerateaCONV

signalfromthiscrystalclockwithoutjittercorruptionfrom

other digital circuits in the system. A clock divider and

any gates in the signal path from the crystal clock to the

CONV input should not share the same integrated circuit

with other parts of the system. As shown in the interface

circuit examples, the SCK and CONV inputs should be

driven ﬁrst, with digital buffers used to drive the serial port

interface. Also note that the master clock in the DSP may

already be corrupted with jitter, even if it comes directly

from the DSP crystal. Another problem with high speed

processor clocks is that they often use a low cost, low

speed crystal (i.e., 10MHz) to generate a fast, but jittery,

phase-locked-loop system clock (i.e., 40MHz). The jitter

in these PLL-generated high speed clocks can be several

nanoseconds. Note that if you choose to use the frame

sync signal generated by the DSP port, this signal will

have the same jitter of the DSP’s master clock.

DIGITAL INTERFACE

The LTC1403/LTC1403A has a 3-wire SPI (Serial Protocol

Interface) interface. The SCK and CONV inputs and SDO

outputimplementthisinterface.TheSCKandCONVinputs

acceptswingsfrom3VlogicandareTTLcompatible, ifthe

logic swing does not exceed V . A detailed description

of the three serial port signals follows:

DD

Conversion Start Input (CONV)

The rising edge of CONV starts a conversion, but subse-

quent rising edges at CONV are ignored by the LTC1403/

LTC1403A until the following 16 SCK rising edges have

occurred. It is necessary to have a minimum of 16 rising

edgesoftheclockinputSCKbetweenrisingedgesofCONV.

But to obtain maximum conversion speed, it is necessary

to allow two more clock periods between conversions to

allow39nsofacquisitiontimefortheinternalADCsample-

and-hold circuit. With 16 clock periods per conversion,

the maximum conversion rate is limited to 2.8Msps to

allow 39ns for acquisition time. In either case, the output

data stream comes out within the ﬁrst 16 clock periods to

ensure compatibility with processor serial ports. The duty

cycle of CONV can be arbitrarily chosen to be used as a

frame sync signal for the processor serial port. A simple

approach to generate CONV is to create a pulse that is

one SCK wide to drive the LTC1403/LTC1403A and then

buffer this signal with the appropriate number of inverters

to ensure the correct delay driving the frame sync input of

Serial Clock Input (SCK)

The rising edge of SCK advances the conversion process

and also udpates each bit in the SDO data stream. After

CONVrises,thethirdrisingedgeofSCKstartsclockingout

the 12/14 data bits with the MSB sent ﬁrst. A simple ap-

proachistogenerateSCKtodrivetheLTC1403/LTC1403A

1403fb

13

LTC1403/LTC1403A

APPLICATIONS INFORMATION

ﬁrstandthenbufferthissignalwiththeappropriatenumber

of inverters to drive the serial clock input of the processor

serial port. Use the falling edge of the clock to latch data

from the Serial Data Output (SDO) into your processor

serial port. The 14-bit Serial Data will be received right

justiﬁed, ina16-bitwordwith16ormoreclocksperframe

sync. It is good practice to drive the LTC1403/LTC1403A

SCK input ﬁrst to avoid digital noise interference during

the internal bit comparison decision by the internal high

speed comparator. Unlike the CONV input, the SCK input

is not sensitive to jitter because the input signal is already

sampled and held constant.

HARDWARE INTERFACE TO TMS320C54X

The LTC1403/LTC1403A is a serial output ADC whose

interface has been designed for high speed buffered

serial ports in fast digital signal processors (DSPs).

Figure 6 shows an example of this interface using a

TMS320C54X.

The buffered serial port in the TMS320C54x has direct

access to a 2kB segment of memory. The ADC’s serial

data can be collected in two alternating 1kB segments,

in real time, at the full 2.8Msps conversion rate of the

LTC1403/LTC1403A. The DSP assembly code sets frame

sync mode at the BFSR pin to accept an external posi-

tive going pulse and the serial clock at the BCLKR pin to

accept an external positive edge clock. Buffers near the

LTC1403/LTC1403A may be added to drive long tracks to

the DSP to prevent corruption of the signal to LTC1403/

LTC1403A. This conﬁguration is adequate to traverse a

typical system board, but source resistors at the buffer

outputs and termination resistors at the DSP, may be

needed to match the characteristic impedance of very

long transmission lines. If you need to terminate the SDO

transmission line, buffer it ﬁrst with one or two 74ACTxx

gates. The TTL threshold inputs of the DSP port respond

properly to the 3V swing from the SDO pin.

Serial Data Output (SDO)

Upon power-up, the SDO output is automatically reset to

the high impedance state. The SDO output remains in high

impedance until a new conversion is started. SDO sends

out 12/14 bits in the output data stream beginning at the

third rising edge of SCK after the rising edge of CONV.

SDO is always in high impedance mode when it is not

sending out data bits. Please note the delay speciﬁcation

from SCK to a valid SDO. SDO is always guaranteed to

be valid by the next rising edge of SCK. The 16-bit output

data stream is compatible with the 16-bit or 32-bit serial

port of most processors.

3V

7

5V

V

CC

DD

10

9

CONV

SCK

BFSR

BCLKR

BDR

B13 B12

8

6

SDO

GND

LTC1403/

LTC1403A

TMS320C54x

CONV

CLK

3-WIRE SERIAL

INTERFACELINK

1403A F09

0V TO 3V LOGIC SWING

Figure 6. DSP Serial Interface to TMS320C54x

1403fb

14

LTC1403/LTC1403A

APPLICATIONS INFORMATION

; 01-08-01 ******************************************************************

; Files: 014SI.ASM -> 1403A Sine wave collection with Serial Port interface

;

bvectors.asm

s2k14ini.asm

buffered mode to avoid standard mode bug.

2k buffer size.

; ﬁrst element at 1024, last element at 1023, two middles at 2047 and 0000

; unipolar mode

; Works 16 or 64 clock frames.

; negative edge BCLKR

; negative BFSR pulse

; -0 data shifted

; 1’ cable from counter to CONV at DUT

; 2’ cable from counter to CLK at DUT

; ***************************************************************************

.width

160

.length 110

.title “sineb0 BSP in auto buffer mode”

.mmregs

.setsect “.text”,

0x500,0

;Set address of executable

.setsect “vectors”, 0x180,0

.setsect “buffer”, 0x800,0

.setsect “result”, 0x1800,0

.text

;Set address of incoming 1403 data

;Set address of BSP buffer for clearing

;Set address of result for clearing

;.text marks start of code

start:

;this label seems necessary

;Make sure /PWRDWN is low at J1-9

;to turn off AC01 adc

tim=#0fh

prd=#0fh

tcr = #10h

tspc = #0h

pmst = #01a0h

sp = #0700h

dp = #0

; stop timer

; stop TDM serial port to AC01

; set up iptr. Processor Mode STatus register

; init stack pointer.

; data page

ar2 = #1800h

ar3 = #0800h

ar4 = #0h

; pointer to computed receive buffer.

; pointer to Buffered Serial Port receive buffer

; reset record counter

call sineinit

; Double clutch the initialization to insure a proper

sinepeek:

call sineinit

; reset. The external frame sync must occur 2.5 clocks

; or more after the port comes out of reset.

wait

;

goto

wait

----------------Buffered Receive Interrupt Routine ------------------

breceive:

ifr = #10h

TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer

if (NTC) goto bufull ; if this still the ﬁrst half get next half

; clear interrupt ﬂags

bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15))

return_enable

;

--------------mask and shift input data ----------------------------

bufull:

b = *ar3+ << -0

b = #03FFFh & b

; load acc b with BSP buffer and shift right -0

; mask out the TRISTATE bits with #03FFFh

;

*ar2+ = data(#0bh)

; store B to out buffer and advance AR2 pointer

TC = (@ar2 == #02000h) ; output buffer is 2k starting at 1800h

if (TC) goto start

goto bufull

; restart if out buffer is at 1fffh

1403fb

15

LTC1403/LTC1403A

APPLICATIONS INFORMATION

;

-------------------dummy bsend return------------------------

bsend

return_enable

;this is also a dummy return to deﬁne bsend

;in vector table ﬁle BVECTORS.ASM

;

----------------------- end ISR ----------------------------

.copy “c:\dskplus\1403\s2k14ini.asm”

;initialize buffered serial port

.space 16*32 ;clear a chunk at the end to mark the end

;======================================================================

;

VECTORS

;======================================================================

.sect “vectors” ;The vectors start here

.copy “c:\dskplus\1403\bvectors.asm” ;get BSP vectors

.sect “buffer”

.space 16*0x800

.sect “result”

.space 16*0x800

;Set address of BSP buffer for clearing

;Set address of result for clearing

.end

**********************************************************************

*

* File: s2k14ini.ASM BSP initialization code for the ‘C54x DSKplus

*

for use with 1403A in standard mode

BSPC and SPC are the same in the ‘C542

BSPCE and SPCE seem the same in the ‘C542

**********************************************************************

.title “Buffered Serial Port Initialization Routine”

ON

.set 1

OFF

YES

.set !ON

.set 1

NO

.set !YES

.set 2

.set 1

.set 3

.set 0

BIT_8

BIT_10

BIT_12

BIT_16

GO

.set 0x80

**********************************************************************

* This is an example of how to initialize the Buffered Serial Port (BSP).

* The BSP is initialized to require an external CLK and FSX for

* operation. The data format is 16-bits, burst mode, with autobuffering

* enabled.

*

*****************************************************************************************************

*LTC1403 timing from LCC28 socket board with 10MHz crystal.

*10MHz, divided from 40MHz, forced to CLKIN by 1403 board.

*Horizontal scale is 25ns/chr or 100ns period at BCLKR

*Timing measured at DSP pins. Jxx pin labels for jumper cable.

*

*BFSR Pin J1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/~~~~~~~~~~~*

*BCLKR Pin J1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~*

*BDR

Pin J1-26 _---_---_---<B13-B12-B11-B10-B09-B08-B07-B06-B05-B04-B03-B02-B01-B00>---_---<B13-B12*

*CLKIN Pin J5-09 ~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~*

*C542 read

*

0

B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00

0

B13 B12*

*

1403fb

16

LTC1403/LTC1403A

APPLICATIONS INFORMATION

* negative edge BCLKR

* negative BFSR pulse

* no data shifted

* 1’ cable from counter to CONV at DUT

* 2’ cable from counter to CLK at DUT

*No right shift is needed to right justify the input data in the main program

*the two msbs should also be masked....................

*

*****************************************************************************************************

*

Loopback

Format

IntSync

IntCLK

BurstMode

CLKDIV

PCM_Mode

FS_polarity

CLK_polarity

Frame_ignore

XMTautobuf

RCVautobuf

XMThalt

.set

NO

BIT_16

NO

YES

3

NO

YES

NO

!YES

NO

YES

NO

;(digital looback mode?)

;(Data format? 16,12,10,8)

;(internal Frame syncs generated?) TXM bit

;(internal clks generated?) MCM bit

;(if BurstMode=NO, then Continuous) FSM bit

;(3=default value, 1/4 CLOCKOUT)

;(Turn on PCM mode?)

;(change polarity)YES=^^^\_/^^^, NO=___/^\___

;(change polarity)for BCLKR YES=_/^, NO=~\_

;(inverted !YES -ignores frame)

;(transmit autobuffering)

DLB bit

FO bit

;(receive autobuffering)

;(transmit buff halt if XMT buff is full)

;(receive buff halt if RCV buff is full)

;(address of transmit buffer)

;(length of transmit buffer)

;(address of receive buffer)

RCVhalt

NO

XMTbufAddr

XMTbufSize

RCVbufAddr

RCVbufSize

*

0x800

0x000

0x800

;(length of receive buffer)works up to 800

* See notes in the ‘C54x CPU and Peripherals Reference Guide on setting up

* valid buffer start and length values. Page 9-44

*

**********************************************************************

.eval ((Loopback >> 1)|((Format & 2)<<1)|(BurstMode <<3)|(IntCLK <<4)|(IntSync <<5)) ,SPCval

.eval (SPCEval|(XMTautobuf<<10)|(XMThalt<<12)|(RCVautobuf<<13)|(RCVhalt<<15)), SPCEval

sineinit:

bspc = #SPCval

ifr = #10h

; places buffered serial port in reset

; clear interrupt ﬂags

imr = #210h

; Enable HPINT,enable BRINT0

intm = 0

; all unmasked interrupts are enabled.

; programs BSPCE and ABU

bspce = #SPCEval

axr = #XMTbufAddr

bkx = #XMTbufSize

arr = #RCVbufAddr

bkr = #RCVbufSize

bspc = #(SPCval | GO)

return

; initializes transmit buffer start address

; initializes transmit buffer size

; initializes receive buffer start address

; initializes receive buffer size

; bring buffered serial port out of reset

;for transmit and receive because GO=0xC0

; ***************************************************************************

; File: BVECTORS.ASM -> Vector Table for the ‘C54x DSKplus 10.Jul.96

;

BSP vectors and Debugger vectors

TDM vectors just return

; ***************************************************************************

; The vectors in this table can be conﬁgured for processing external and

; internal software interrupts. The DSKplus debugger uses four interrupt

; vectors. These are RESET, TRAP2, INT2, and HPIINT.

;

*

DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER

*

1403fb

17

LTC1403/LTC1403A

APPLICATIONS INFORMATION

; All other vector locations are free to use. When programming always be sure

; the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and

; host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the

; DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally.

;

.title “Vector Table”

.mmregs

reset

nmi

goto #80h

nop

;00; RESET * DO NOT MODIFY IF USING DEBUGGER *

;04; non-maskable external interrupt

return_enable

nop

trap2

int0

goto #88h

nop

.space 52*16

;08; trap2 * DO NOT MODIFY IF USING DEBUGGER *

;0C-3F: vectors for software interrupts 18-30

;40; external interrupt int0

return_enable

nop

int1

return_enable

nop

return_enable

nop

return_enable

nop

goto breceive

nop

;44; external interrupt int1

;48; external interrupt int2

;4C; internal timer interrupt

;50; BSP receive interrupt

;54; BSP transmit interrupt

;58; TDM receive interrupt

int2

tint

brint

bxint

trint

goto bsend

nop

return_enable

nop

txint

int3

return_enable

nop

;5C; TDM transmit interrupt

;60; external interrupt int3

return_enable

nop

hpiint

dgoto #0e4h

nop

;64; HPIint * DO NOT MODIFY IF USING DEBUGGER *

;68-7F; reserved area

.space 24*16

1403fb

18

LTC1403/LTC1403A

PACKAGE DESCRIPTION

MSE Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1663)

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.06 0.102

(.081 .004)

2.794 0.102

(.110 .004)

0.889 0.127

(.035 .005)

1

1.83 0.102

(.072 .004)

5.23

(.206)

MIN

2.083 0.102 3.20 – 3.45

(.082 .004) (.126 – .136)

10

0.50

(.0197)

BSC

0.305 0.038

(.0120 .0015)

TYP

3.00 0.102

(.118 .004)

(NOTE 3)

0.497 0.076

(.0196 .003)

REF

10 9

8

7 6

RECOMMENDED SOLDER PAD LAYOUT

3.00 0.102

(.118 .004)

(NOTE 4)

4.90 0.152

(.193 .006)

DETAIL “A”

0.254

(.010)

0° – 6° TYP

1

2

3

4 5

GAUGE PLANE

0.53 0.152

(.021 .006)

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.127 0.076

(.005 .003)

MSOP (MSE) 0603

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

1403fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LTC1403/LTC1403A

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

ADCs

LTC1608

16-Bit, 500ksps Parallel ADC

16-Bit, 333ksps Parallel ADC

16-Bit, 250ksps Serial ADC

14-Bit, 2.5Msps Parallel ADC

14-Bit, 2.2Msps Parallel ADC

12-/14-Bit, 3Msps Simultaneous Sampling ADC

12-Bit, 10Msps Parallel ADC

12-Bit, 5Msps Parallel ADC

12-Bit, 3Msps Parallel ADC

12-Bit, 2.2Msps Serial ADC

16-Bit, 250ksps Serial ADC

5V Supply, 2.5V Span, 90dB SINAD

5V, Conﬁgurable Bipolar/Unipolar Inputs

5V, Selectable Spans, 80dB SINAD

LTC1604

LTC1609

LTC1411

LTC1414

5V Supply, 2.5V Span, 78dB SINAD

3V, 2-Channel Differential, 14mW, MSOP Package

5V, Selectable Spans, 72dB SINAD

LTC1407/LTC1407A

LTC1420

LTC1405

5V, Selectable Spans, 115mW

LTC1412

5V Supply, 2.5V Span, 72dB SINAD

5V or 5V Supply, 4.096V or 2.5V Span

5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package

LTC1402

LTC1864/LTC1865

DACs

LTC1666/LTC1667/LTC1668 12-/14-/16-Bit, 50Msps DACs

87dB SFDR, 20ns Settling Time

LTC1592

16-Bit, Serial SoftSpan^TM

I

DAC

1LSB INL/DNL, Software Selectable Spans

OUT

References

LT1790-2.5

LT1461-2.5

LT1460-2.5

Micropower Series Reference in SOT-23

Precision Voltage Reference

0.05% Initial Accuracy, 10ppm Drift

0.04% Initial Accuracy, 3ppm Drift

0.1% Initial Accuracy, 10ppm Drift

Micropower Series Voltage Reference

SoftSpan is a trademark of Linear Technology Corporation.

1403fb

LT 0407 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1403_15
厂家：	Linear
描述：	Serial 12-Bit/14-Bit, 2.8Msps Sampling ADCs with Shutdown
文件：	总20页 (文件大小：240K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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