LTC1405IGN [Linear]
12-Bit, 5Msps, Sampling ADC; 12位， 5Msps的符号，采样ADC
| 型号： | LTC1405IGN |
| 厂家： | 
Linear |
| 描述： | 12-Bit, 5Msps, Sampling ADC |
| 文件： | 总16页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fina l Ele c tric a l Sp e c ific a tio ns
LTC1405
12-Bit, 5Msp s,
Sa m p ling ADC
Ja nua ry 2000
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DESCRIPTIO
FEATURES
The LTC®1405 is a 5Msps, 12-bit sampling A/D converter
that draws only 115mW from either single 5V or dual ±5V
supplies. This easy-to-usedeviceincludes ahighdynamic
range sample-and-hold, a precision reference and a PGA
input circuit.
■
5Msps Sample Rate
Low Power Dissipation: 115mW
Single 5V Supply or ±5V Supplies
Integral Nonlinearity Error <0.35LSB
Differential Nonlinearity <0.25LSB
71.3dB S/(N + D) and 85dB SFDR at Nyquist
100MHz Full-Power Bandwidth Sampling
±2.048V, ±1.024V and ±0.512V Bipolar Input Range
Input PGA
Out-of-Range Indicator
True Differential Inputs with 75dB CMRR
28-Pin Narrow SSOP Package
■
■
■
■
■
The LTC1405 has a flexible input circuit that allows full-
scaleinputranges of±2.048V,±1.024Vand±0.512V. The
input common mode range is rail-to-rail and a common
mode bias voltage is provided for single supply applica-
tions. The input PGA has a digitally selectable 1x or 2x
gain.
■
■
■
■
■
■
■
Maximum DC specs include ±1LSB INL and ±1LSB DNL
over temperature. Outstanding AC performance includes
71.3dB S/(N + D) and 85dB SFDR at the Nyquist input
frequency of 2.5MHz.
Pin-Compatible 10Msps Version (LTC1420)
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APPLICATIO S
■
Telecommunications
Digital Signal Processing
Multiplexed Data Acquisition Systems
High Speed Data Acquisition
Spectral Analysis
Imaging Systems
Theuniquedifferentialinputsample-and-holdcanacquire
single-ended or differential input signals up to its 100MHz
bandwidth. The 75dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source. A
separate output logic supply allows direct connection to
3V components.
■
■
■
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
5V
5V
5V
Typical INL Curve
OPTIONAL 3V
1.00
0.75
0.50
0.25
0
LOGIC SUPPLY
1µF
1µF
1µF
GAIN
AV
DD
DV
DD
OV
DD
+
A
IN
S/H
PIPELINED 12-BIT ADC
OF
–A
IN
–0.25
–0.50
–0.75
–1.00
D11 (MSB)
OUTPUT
BUFFERS
V
CM
1µF
MODE SELECT
DIGITAL CORRECTION
LOGIC
D0 (LSB)
SENSE
0
1024
2048
3072
4096
2.5V
REFERENCE
5MHz CLK
CODE
1405 TA02
V
REF
1µF
1µF
2.048V
1405 TA01
V
AGND
DGND
OGND
SS
0V OR –5V
InformationfurnishedbyLinearTechnologyCorporationis believedtobeaccurateandreliable.However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the
interconnection of its circuits as described herein will not infringe on existing patent rights.
1
LTC1405
W W
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ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
AVDD = DVDD = 0VDD = VDD (Notes 1, 2)
TOP VIEW
ORDER PART
NUMBER
Supply Voltage (VDD)................................................. 6V
Negative Supply Voltage (V ) ................................ –6V
Total Supply Voltage (VDD to V ) ........................... 12V
1
2
GAIN
OF
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+A
IN
SS
–A
IN
SS
LTC1405CGN
LTC1405IGN
3
CLK
V
CM
Analog Input Voltage
4
V
SS
SENSE
(Note 3) ............................. (V – 0.3V) to (VDD + 0.3V)
5
DGND
SS
V
REF
Digital Input Voltage
6
DV
DD
AGND
(Note 4) ............................. (V – 0.3V) to (VDD + 0.3V)
Digital Output Voltage........ (V – 0.3V) to (VDD + 0.3V)
7
OV
DD
AV
DD
SS
8
OGND
D0
AGND
SS
9
D11 (MSB)
Power Dissipation.............................................. 500mW
Operating Temperature Range
LTC1405C ............................................... 0°C to 70°C
LTC1405I............................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
10
11
12
13
14
D1
D10
D9
D8
D7
D6
D2
D3
D4
D5
GN PACKAGE
28-LEAD PLASTIC SSOP
JMAX = 110°C, θJA = 110°C/W
T
Consult factory for Military grade parts.
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CO VERTER CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
With Internal 4.096V Reference. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)
PARAMETER
CONDITIONS
(Note 7)
MIN
TYP
MAX
UNITS
Bits
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
●
●
●
12
±0.35
±0.25
±5
±1
±1
LSB
LSB
(Note 8)
12
16
LSB
LSB
●
Full-Scale Error
±10
±15
30
LSB
Full-Scale Tempco
I
= 0
ppm/°C
OUT(REF)
U
U
The ● denotes the specifications which apply over the full operating temperature range, otherwise
A ALOG I PUT
specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)
SYMBOL PARAMETER
Analog Input Range (Note 9)
+A – (–A )
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
V
= 4.096V (SENSE = 0V), GAIN = 5V
V = 4.096V (SENSE = 0V), GAIN = 0V
REF
●
●
●
●
●
●
±2.048
±1.024
±1.024
±0.512
V
V
V
V
V
V
REF
IN
IN
V
REF
= 2.048V (SENSE = V ), GAIN = 5V
REF
V
REF
= 2.048V (SENSE = V ), GAIN = 0V
REF
External V (SENSE = 5V), GAIN = 5V
±V /2
REF
REF
External V (SENSE = 5V), GAIN = 0V
±V /4
REF
REF
I
Analog Input Leakage Current
Analog Input Capacitance
●
±10
µA
IN
C
Between Conversions
During Conversions
12
6
pF
pF
IN
t
Sample-and-Hold Acquisition Time
50
ns
ACQ
2
LTC1405
U
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The ● denotes the specifications which apply over the full operating temperature range, otherwise
A ALOG I PUT
specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
–250
0.6
MAX
UNITS
ps
t
t
Sample-and-Hold Aperture Delay Time
AP
Sample-and-Hold Aperture Delay Time Jitter
ps
jitter
CMRR
Analog Input Common Mode Rejection Ratio –2.048V < (–A = +A ) < 2.048V
75
dB
IN
IN
W
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The ● denotes the specifications which apply over the full operating temperature range,
DY
A IC
ACCURACY
otherwise specifications are at TA = 25°C. VDD = 5V, VSS = –5V, fSAMPLE = 5MHz, VREF = 4.096V. +A = –0.1dBFS single ended input,
IN
–A = 0V. (Note 6)
IN
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
S/(N + D) Signal-to-Noise Plus Distortion Ratio
1MHz Input Signal
2.5MHz Input Signal
●
●
69.0
68.7
71.6
71.3
dB
dB
THD
SFDR
IMD
Total Harmonic Distortion
1MHz Input Signal, First 5 Harmonics
2.5MHz Input Signal, First 5 Harmonics
●
●
–87
–83
–78.5
–77.0
dB
dB
Peak Harmonic or Spurious Noise
1MHz Input Signal
2.5MHz Input Signal
●
●
–89
–85
–79.5
–78.0
dB
dB
Intermodulation Distortion
Full-Power Bandwidth
Input Referred Noise
f
IN1
= 29.37kHz, f = 32.446kHz
–80
100
dB
IN2
MHz
±2.048V Input Range
±1.024V Input Range, 2x Mode (SENSE = GAIN = 0V)
0.22
0.33
LSB
RMS
LSB
RMS
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I TER AL REFERE CE CHARACTERISTICS
TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)
PARAMETER
CONDITIONS
MIN
TYP
2.500
±15
MAX
UNITS
V
V
Output Voltage
Output Tempco
Line Regulation
I
= 0
= 0
2.475
2.525
CM
OUT
V
I
ppm/°C
CM
OUT
V
4.75V ≤ V ≤ 5.25V
0.6
0.03
mV/V
mV/V
CM
DD
–5.25V ≤ V ≤ –4.75V
SS
V
Output Resistance
Output Voltage
0.1mA ≤
I
≤ 0.1mA
8
Ω
CM
OUT
V
REF
SENSE = GND, I
SENSE = V , I
SENSE = V
= 0
= 0
4.096
2.048
Drive V with
REF
V
V
V
OUT
REF OUT
DD
External Reference
V
REF
Output Tempco
±15
ppm/°C
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The ● denotes the specifications which apply over the full operating
DIGITAL I PUTS AND OUTPUTS
temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply
operation. (Note 5)
SYMBOL PARAMETER
CONDITIONS
= 5.25V, V = 0V
MIN
TYP
MAX
UNITS
V
High Level Input Voltage
V
DD
●
●
2.4
3.5
V
V
IH
SS
V
= 5.25V, V = –5V
SS
DD
V
IL
Low Level Input Voltage
V
V
DD
= 4.75V, V = 0V
= 4.75V, V = –5V
SS
●
●
0.8
1
V
V
DD
SS
3
LTC1405
U
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The ● denotes the specifications which apply over the full operating
DIGITAL I PUTS AND OUTPUTS
temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply
operation. (Note 5)
SYMBOL PARAMETER
CONDITIONS
= 0V to V
DD
MIN
TYP
MAX
UNITS
µA
I
Digital Input Current
V
●
±10
IN
IN
C
Digital Input Capacitance
High Level Output Voltage
1.8
pF
IN
V
OH
0V = 4.75V, I = –10µA
4.74
4.71
2.6
V
V
V
V
DD
O
0V = 4.75V, I = –200µA
●
●
4.0
2.3
DD
O
0V = 2.7V, I = –10µA
DD
O
0V = 2.7V, I = –200µA
DD
O
V
OL
Low Level Output Voltage
0V = 4.75V, I = 160µA
0.05
0.10
0.05
0.10
V
V
V
V
DD
O
0V = 4.75V, I = 1.6mA
●
●
0.4
0.4
DD
O
0V = 2.7V, I = 160µA
DD
O
0V = 2.7V, I = 1.6mA
DD
O
I
Output Source Current
Output Sink Current
V
= 0V
50
35
mA
mA
SOURCE
OUT
I
V
= V
SINK
OUT DD
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W
POWER REQUIRE E TS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation.
(Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
4.75
TYP
MAX
5.25
UNITS
V
Positive Supply Voltage
Negative Supply Voltage
(Note 10)
V
DD
V
SS
Dual Supply Mode
Single Supply Mode
–5.25
–4.75
V
V
0
I
Positive Supply Current
Negative Supply Current
Power Dissipation
●
●
●
23
28
1.2
145
mA
mA
DD
I
SS
0.8
115
P
mW
D
W U
The ● denotes the specifications which apply over the full operating temperature
TI I G CHARACTERISTICS
range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation.
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
5
UNITS
MHz
ns
f
Sampling Frequency
Conversion Time
●
●
●
●
●
0.02
SAMPLE
t
t
t
t
t
150
50
180
CONV
ACQ
H
Acquisition Time
20
20
20
ns
CLK High Time
(Note 9)
(Note 9)
100
100
–250
ns
CLK Low Time
ns
L
Aperture Delay of Sample-and-Hold
ps
AD
Note 1: Absolute Maximum Ratings are those values beyond which the life
Note 4: When these pin voltages are taken below V they will be clamped
SS
of a device may be impaired.
by internal diodes. This product can handle input currents greater than
100mA below V without latchup. GAIN is not clamped to V . When CLK
SS
DD
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
is taken above V , it will be clamped by an internal diode. The CLK pin
DD
can handle input currents of greater than 100mA above V without
DD
Note 3: When these pin voltages are taken below V or above V , they
SS
DD
latchup.
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V or above V without latchup.
Note 5: V = 5V, V = –5V or 0V, f
= 5MHz, t = t = 5ns unless
r f
DD
SS
SAMPLE
SS
DD
otherwise specified.
4
LTC1405
ELECTRICAL CHARACTERISTICS
Note 6: Dynamic specifications are guaranteed for dual supply operation
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB
with a single-ended +A input and –A grounded. For single supply
dynamic specifications, refer to the Typical Performance Characteristics.
when the output code flickers between 0000 0000 0000 and
1111 1111 1111.
IN
IN
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
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PI FU CTIO S
+A (Pin 1): Positive Analog Input.
OGND (Pin 21): Output Logic Ground. Tie to GND.
IN
–A (Pin 2): Negative Analog Input.
OVDD (Pin 22): Positive Supply for the Output Logic.
Connect to Pin 23 for 5V logic. If not shorted to Pin 23,
bypass to GND with a 1µF ceramic.
IN
VCM (Pin 3): 2.5V Reference Output.Optional input com-
mon mode for single supply operation. Bypass to GND
with a 1µF to 10µF ceramic.
VDD (Pin23):Analog5VSupply. Bypass toGNDwitha1µF
ceramic.
SENSE (Pin 4): Reference Programming Pin. Ground
selects VREF = 4.096V. Short to VREF for 2.048V. Connect
SENSE to VDD to drive VREF with an external reference.
GND (Pin 24): Analog Power Ground.
V (Pin 25): Negative Supply. Can be –5V or 0V. If V is
SS
SS
VREF (Pin 5): DAC Reference. Bypass to GND with a 1µF to
not shorted to GND, bypass to GND with a 1µF ceramic.
10µF ceramic.
CLK (Pin 26): Conversion Start Signal. This active high
GND (Pin 6): DAC Reference Ground.
signal starts a conversion on its rising edge.
VDD (Pin 7): Analog 5V Supply. Bypass to GND with a 1µF OF (Pin 27): Overflow Output. This signal is high when the
to 10µF ceramic.
digital output is 011111111111 or 100000000000.
GND (Pin 8): Analog Power Ground.
GAIN (Pin 28): Gain Select for Input PGA. 5V selects an
input gain of 1, 0V selects a gain of 2.
D11 to D0 (Pins 9 to 20): Data Outputs. The output format
is two’s complement.
5
LTC1405
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FU CTIO AL BLOCK DIAGRA
OPTIONAL 3V
LOGIC SUPPLY
5V
V
DD
V
DD
GAIN
(PIN 7)
(PIN 23)
OV
DD
+A
IN
S/H
PIPELINED 12-BIT ADC
OF
–A
IN
D11 (MSB)
OUTPUT
BUFFERS
V
CM
DIGITAL CORRECTION
LOGIC
MODE SELECT
D0 (LSB)
CLK
SENSE
2.5V
REFERENCE
V
REF
2.048V
1405 FBD
V
GND
(PIN 6)
GND
(PIN 8)
GND
(PIN 24)
OGND
SS
0V OR –5V
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TI I G DIAGRA
N + 1
N
ANALOG
INPUT
N + 2
N + 3
t
CLOCK
t
t
L
H
CLK
t
CONV
t
ACQ
DATA
OUTPUT
N – 3
N – 2
N – 1
N
1405 TD
6
LTC1405
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APPLICATIO S I FOR ATIO
Conversion Details
Analog Input Ranges
The LTC1405 is a high performance 12-bit A/D converter
that operates up to 5Msps. It is a complete solution with
an on-chip sample-and-hold, a 12-bit pipelined CMOS
ADC, a low drift programmable reference and an input
programmable gain amplifier. The digital output is paral-
lel, with a 12-bit two’s complement output and an out-of-
range (overflow) bit.
The LTC1405 has a flexible analog input with a wide
selection of input ranges. The input range is always
differential and is set by the voltages at the VREF and the
GAIN pins (Figure 1). The input range of the A/D core is
fixed at ±VREF/2. The reference voltage, VREF, is either set
by the on-chip voltage reference or directly driven by an
external voltage. The GAIN pin is a digital input that
controls the gain of a preamplifier in the sample-and-hold
circuit. The gain of this PGA can be set to 1x or 2x. Table 1
gives the input range in terms of VREF and GAIN.
The rising edge of the CLK begins a conversion. The
differential analog inputs are simultaneously sampled and
passed on to the pipelined A/D. After two more conversion
starts (plus a 150ns conversion time) the digital outputs
areupdatedwiththeconversionresultandwillbereadyfor
capture on the third rising clock edge. Thus even though
anewconversionis beguneverytimeCLKgoes high, each
result takes three clock cycles to reach the output.
Table 1
INPUT RANGE
+
–
GAIN PIN
PGA GAIN
(V = A – A
)
IN
IN
IN
5V (Logic H)
OV (Logic L)
1x
2x
–V /2 < V < V /2
REF IN REF
–V /4 < V < V /4
REF
IN
REF
The analog signals that are passed from stage to stage in
the pipelined A/D are stored on capacitors. The signals on
these capacitors will be lost if the delay between conver-
sions is too long. For accurate conversion results, the part
should be clocked faster than 20kHz.
GAIN
1x/2x
+A
IN
+
ADC
CORE
V
PGA
S/H
±V /2
REF
IN
–A
IN
–
In some pipelined A/D converters if there is no clock
present, dynamic logic on the chip will droop and the
power consumption sharply increases. The LTC1405
doesn’t have this problem. If the part is not clocked for
1ms, an internal timer will refresh the dynamic logic. Thus
the clock can be turned off for long periods of time to save
power.
V
REF
1405 F01
Figure 1. Analog Input Circuit
Internal Reference
Figure 2 shows a simplified schematic of the LTC1405
reference circuitry. An on-chip temperature compensated
Power Supplies
bandgap reference (V ) is factory trimmed to 2.500V.
CM
The voltage at the VREF pin sets the input span of the ADC
to ±VREF/2. An internal voltage divider converts VCM to
2.048V, which is connected to a reference amplifier. The
reference programming pin, SENSE, controls how the
reference amplifier drives the VREF pin. If SENSE is tied to
ground, the reference amplifier feedback is connected to
the R1/R2 voltage divider, thus making VREF = 4.096V. If
SENSE is tied to VREF, the reference amplifier feedback is
connectedtoSENSEthus makingVREF =2.048V. IfSENSE
is tiedtoVDD, thereferenceamplifieris disconnectedfrom
The LTC1405 will operate from either a single 5V or dual
±5V supply, making it easy to interface the analog input to
single or dual supply systems. The digital output drivers
have their own power supply pin (OVDD) which can be set
from 3V to 5V, allowing direct connection to either 3V or
5Vdigitalsystems.Forsinglesupplyoperation,V should
SS
beconnectedtoanalogground. Fordualsupplyoperation,
V should be connected to –5V. Both VDD pins should be
SS
connectedtoaclean5Vanalogsupply.(Don’tconnectVDD
to a noisy system digital supply.)
VREF and VREF can be driven by an external voltage. With
two additional resistors, VREF can be set to any voltage
between 2.048V and 4.5V.
7
LTC1405
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APPLICATIO S I FOR ATIO
An external reference or a DAC can be used to drive V
REF
over a 0V to 5V range (Figures 3a and 3b). The input
impedance of the VREF pin is 2kΩ, so a buffer may be
required for high accuracy. Driving VREF with a DAC is
useful in applications where the peak input signal ampli-
tude may vary. The input span of the ADC can then be
adjusted to match the peak input signal, maximizing the
signal-to-noise ratio.
TO
ADC
V
REF
1µF
+
–
2k
R1
10k
SENSE
R2
10k
Both the V and V
pins must be bypassed with
CM
REF
LOGIC
capacitors to ground. For best performance, 1µF or larger
ceramic capacitors are recommended. For the case of
external circuitry driving VREF, a smaller capacitor can be
used at VREF so the input range can be changed quickly. In
this case, a 0.05µF or larger ceramic capacitor is accept-
able.
2.5V
REFERENCE
2.048V
V
CM
1µF
1405 F02
The VCM pin is a low output impedance 2.5V reference that
can be used by external circuitry. For single 5V supply
Figure 2. Reference Circuit
applications it is convenient to connect A – directly to the
IN
VCM pin.
5V
Driving the Analog Inputs
V
IN
The differential inputs of the LTC1405 are easy to drive.
The inputs may be driven differentially or single-ended
(i. e., the A – input is held at a fixed value). The A – and
V
V
REF
OUT
1µF
LT1019A-2.5
LTC1405
SENSE
IN
IN
A
IN
+ inputs are simultaneously sampled and any common
5V
mode signal is reduced by the high common mode rejec-
tion of the sample-and-hold circuit. Any common mode
input value is acceptable as long as the input pins stay
V
CM
1µF
1405 F03a
between VDD and V . During conversion the analog
SS
Figure 3a. Using the LT1019-2.5 As an
External Reference; Input Range = ±1.25V
inputs are high impedance. At the end of conversion the
inputs draw a small current spike while charging the
sample-and-hold.
For superior dynamic performance in dual supply mode,
the LTC1405 should be operated with the analog inputs
centered at ground, and in single supply mode the inputs
should be centered at 2.5V. If required, the analog inputs
can be driven differentially via a transformer. Refer to
Table 2 for a summary of the analog input and reference
configurations and their relative advantages.
LTC1405
2.048V
+
V
REF
1µF
1µF
–
5k
5k
SENSE
V
CM
LTC1450
1405 F03b
Figure 3b. Driving VREF with a DAC
8
LTC1405
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APPLICATIO S I FOR ATIO
Table 2. Comparison of Analog Input Configurations
+
–
SUPPLIES
±5V
5V
COUPLING
V
GAIN
1x
A
IN
A
IN
COMMENTS
REF
DC
DC
DC
DC
DC
4.096V
4.096V
2.048V
4.096V
4.096V
4.096V
±2.048
2.5 ± 1.024
2.5 ± 1.024
2.5 ± 2.048
0 to 4.096
±1.024
0
Best SNR, THD
2x
2.5
2.5
Best SINAD, THD for Single Supply
Worse Noise than Above Case
Best Single Supply Noise, THD Is Not Optimal
Same As Above
5V
1x
5V
1x
2.5
5V
1x
2.048
±1.024
±5V
AC
1x
Very Best SNR, THD
(Transformer)
5V
AC
4.096V
1x
2.5 ± 1.024
2.5 ± 1.024
Very Best SNR, THD for Single Supply
(Transformer)
5V
DC Coupling the Input
4.096V
Inmostapplications theanaloginputsignalcanbedirectly
coupled to the LTC1405 inputs. If the input signal is
centered around ground, such as when dual supply op
+A
IN
V
IN
0V
5V
LTC1405
2.048V
–A
IN
amps are used, simply connect A – to ground and con-
IN
SENSE
nect V to –5V (Figure 4). In a single power supply
SS
V
SS
system with the input signal centered around 2.5V, con-
1405 F06
nect A – to VCM and V to ground (Figure 5). If the input
IN
SS
signal is not centered around ground or 2.5V, the voltage
Figure 6. DC Coupling a 0V to 4.096V Signal
for A – must be generated externally by a resistor divider
IN
or a voltage reference (Figure 6).
AC Coupling the Input
5V
The analog inputs to the LTC1405 can also be AC coupled
through a capacitor, though in most cases it is simpler to
directly couple the input to the ADC. Figure 7 shows an
example where the input signal is centered around ground
and the ADC operates from a single 5V supply. Note that
the performance would improve if the ADC was operated
from a dual supply and the input was directly coupled (as
in Figure 4). With AC coupling the DC resistance to ground
should be roughly matched for A + and A – to maintain
+A
0V
V
IN
IN
LTC1405
–A
IN
V
CM
V
SS
1µF
1405 F04
–5V
IN
IN
Figure 4. DC Coupling a Ground
Centered Signal (Dual Supply System)
offset accuracy.
5V
5V
C
+A
IN
2.5V
V
IN
0V
V
IN
+A
IN
LTC1405
LTC1405
–A
IN
–A
IN
C
R
R
V
CM
V
CM
V
SS
V
SS
1µF
1µF
1405 F05
1405 F07
Figure 5. DC Coupling a Signal Centered
Around 2.5V (Single Supply System)
Figure 7. AC Coupling to the LTC1405. Note That the Input Signal
Can Almost Always Be Directly Coupled with Better Performance
9
LTC1405
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APPLICATIO S I FOR ATIO
must be greater than 50MHz to ensure adequate small-
signal settling for full throughput rate. If slower op amps
areused, moresettlingtimecanbeprovidedbyincreasing
the time between conversions.
Differential Operation
The THD and SFDR performance of the LTC1405 can be
improved by using a center tap RF transformer to drive the
inputs differentially. Though the signal can no longer be
DC coupled, the improvement in dynamic performance
makes this an attractive solution for some applications.
Typical connections for single and dual supply systems
are shown in Figures 8a and 8b. Good choices for trans-
formers are the Mini Circuits T1-1T (1:1 turns ratio) and
T4-6T (1:4 turns ratio). For best results the transformer
should be located close to the LTC1405 on the printed
circuit board.
The best choice for an op amp to drive the LTC1405 will
depend on the application. Generally applications fall into
two categories: AC applications where dynamic specifica-
tions aremostcriticalandtimedomainapplications where
DC accuracy and settling time are most critical.
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1405 noise and distortion. The small-signal band-
widthofthesample-and-holdcircuitis 100MHz.Anynoise
ordistortionproducts thatarepresentattheanaloginputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications.
5V
MINI CIRCUITS
15Ω
T1-1T
+A
IN
V
IN
1000pF
LTC1405
–A
IN
15Ω
V
CM
V
SS
1µF
1405 F08a
For example, Figure 9 shows a 1000pF capacitor from
Figure 8a. Single Supply Transformer Coupled Input
+A to –A and a 30Ω source resistor to limit the input
IN
IN
5V
bandwidth to 5.3MHz. The 1000pF capacitor also acts as
a charge reservoir for the input sample-and-hold and
MINI CIRCUITS
15Ω
T1-1T
+A
IN
isolates the amplifier driving V from the ADC’s small
IN
V
IN
1000pF
LTC1405
current glitch. In undersampling applications, an input
capacitor this large may prohibitively limit the input band-
width. If this is the case, use as large an input capacitance
as possible. High quality capacitors and resistors should
be used since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self-heating and from damage that may
occur during soldering. Metal film surface mount resis-
tors are much less susceptible to both problems.
–A
IN
15Ω
V
CM
V
SS
1µF
1405 F08b
–5V
Figure 8b. Dual Supply Transformer Coupled Input
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (<100Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain of
1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz must be less than 100Ω. The
second requirement is that the closed-loop bandwidth
30Ω
+A
IN
V
IN
1000pF
LTC1405
–A
IN
1405 F09
Figure 9. RC Input Filter
10
LTC1405
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Digital Outputs and Overflow Bit (OF)
noisefromaffectingperformance, theloadcapacitanceon
the digital outputs should be minimized. Iflarge capacitive
loads are required, (>30pF) external buffers or 100Ω
resistors in series with the digital outputs are suggested.
Figure 10 shows the ideal input/output characteristics for
the LTC1405. The output data is two’s complement binary
for all input ranges and for both single and dual supply
operation. One LSB = VREF/4.096. To create a straight
binary output, invert the MSB (D11). The overflow bit (OF)
indicates when the analog input is outside the input range
of the converter. OF is high when the output code is 1000
0000 0000 or 0111 1111 1111.
5V
+A
IN
V
IN
5V
LTC1405
24k
R1
50k
–A
IN
100Ω
–5V
1
OVERFLOW
BIT
0
V
REF
011…111
011…110
011…101
1µF
10k
R2
1k
SENSE
V
SS
1405 F11
10k
–5V
Figure 11. Offset and Full-Scale Adjust Circuit
100…010
100…001
100…000
Timing
–(FS – 1LSB)
FS – 1LSB
The conversion start is controlled by the rising edge of the
CLK pin. Once a conversion is started it cannot be stopped
or restarted until the conversion cycle is complete. Output
data is updated at the end of conversion, or about 150ns
after a conversion is begun. There is an additional two
cycle pipeline delay, so the data for a given conversion is
output two full clock cycles plus 150ns after the convert
start. Thus output data can be latched on the third CLK
rising edge after the rising edge that samples the input.
INPUT VOLTAGE (V)
1405 F10
Figure 10. LTC1405 Transfer Characteristics
Full-Scale and Offset Adjustment
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error should be adjusted before full-scale error. Figure 11
shows a method for error adjustment for a dual supply,
4.096V application. For zero offset error apply –0.5mV
Clock Input
(i. e.,–0.5LSB)at+A andadjustR1untiltheoutputcode
IN
The LTC1405 only uses the rising edge of the CLK pin for
internal timing, and CLK doesn’t necessarily need to have
a 50% duty cycle. For optimal AC performance the rise
time of the CLK should be less than 5ns. If the available
clock has a rise time slower than 5ns, it can be locally sped
upwithalogicgate. Withsinglesupplyoperationtheclock
canbedrivenwith5VCMOS, 3VCMOSorTTLlogiclevels.
With dual power supplies the clock should be driven with
5V CMOS levels.
flickers between 0000 0000 0000 and 1111 1111 1111.
Forfull-scaleadjustment,applyaninputvoltageof2.0465V
(FS – 1.5LSBs) at +A and adjust R2 until the output code
IN
flickers between 0111 1111 1110 and 0111 1111 1111.
Digital Output Drivers
The LTC1405 output drivers can interface to logic operat-
ing from 3V to 5V by setting OVDD to the logic power
supply.If5Voutputis desired,OVDD canbeshortedtoVDD
and share its decoupling capacitor. Otherwise, OVDD re-
quires its own1µFdecouplingcapacitor.Topreventdigital
As with all fast ADCs, the noise performance of the
LTC1405is sensitivetoclockjitterwhenhighspeedinputs
11
LTC1405
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are present. The SNR performance of an ADC when the
performance is limited by jitter is given by:
connected to this ground plane. All bypass capacitors for
the LTC1405 should also be connected to this ground
plane (Figure 12). The digital system ground should be
connected to the analog ground plane at only one point,
near the OGND pin.
SNR = –20log (2π fINtJ)dB
where fIN is the frequency of an input sine wave and tJ is
the root-mean-square jitter due to the clock, the analog
input and the A/D aperture jitter. To minimize clock jitter,
use a clean clock source such as a crystal oscillator, treat
the clock signals as sensitive analog traces and use
dedicated packages with good supply bypassing for any
clock drivers.
The analog ground plane should be as close to the ADC as
possible.Careshouldbetakentoavoidmakingholes inthe
analog ground plane under and around the part. To ac-
complish this, we recommend placing vias for power and
signal traces outside the area containing the part and the
decoupling capacitors (Figure 13).
Board Layout
Supply Bypassing
To obtain the best performance from the LTC1405, a
printed circuit board with a ground plane is required.
Layout for the printed circuit board should ensure that
digital and analog signal lines are separated as much as
possible. In particular, care should be taken not to run any
digital track alongside an analog signal track.
High quality, low series resistance ceramic 1µF capacitors
should be used at both VDD pins, VCM and VREF. If V is
SS
connected to –5V it should also be bypassed to ground
with1µF. InsinglesupplyoperationV shouldbeshorted
SS
tothegroundplaneas closetothepartas possible.IfOVDD
is not shorted to Pin 23 (VDD) it also requires a 1µF
decoupling capacitor to ground. Surface mount capaci-
tors such as the AVX 0805ZC105KAT provide excellent
bypassing in a small board space. The traces connecting
the pins and the bypass capacitors must be kept short and
should be made as wide as possible.
An analog ground plane separate from the logic system
ground should be placed under and around the ADC.
Pins 6, 8 and 24 (GND), Pin 21 (OGND) and all other
analoggrounds shouldbeconnectedtothis groundplane.
In single supply mode, Pin 25 (V ) should also be
SS
1
DIGITAL
SYSTEM
LTC1405
+A
IN
1000pF
V
V
GND
6
V
GND
8
V
OV
GND
24
V
SS
OGND
21
–A
IN
ANALOG
INPUT
CIRCUITRY
CM
REF
DD
DD
DD
2
+
3
5
7
23
22
25
–
1µF
1µF
1µF
1µF
1µF
1µF
ANALOG GROUND PLANE
1405 F12
Figure 12. Power Supply Grounding
BYPASS
CAPACITOR
LTC1405
PLACE NON-GROUND
VIAS AWAY FROM
GROUND PLANE AND
BYPASS CAPACITORS
ANALOG
GROUND
PLANE
AVOID BREAKING GROUND PLANE
IN THIS AREA
1405 F13
Figure 13. Cross Section of LTC1405 Printed Circuit Board
12
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13
LTC1405
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Figure 15. Top Silkscreen Layer for
LTC1405/LTC1420 Demo Board
Figure 16. Top Layer for LTC1405/LTC1420 Demo Board
Figure 18. Power Plane Layer for LTC1405/LTC1420 Demo Board
Figure 17. Ground Plane Layer for
LTC1405/LTC1420 Demo Board
14
LTC1405
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Figure 19. Bottom Layer for LTC1405/LTC1420 Demo Board
U
TYPICAL APPLICATIO
Single Supply, 5Msps, 12-Bit ADC with 3V Logic Outputs
LTC1405
30Ω
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ANALOG INPUT
(2.5V ± 1.024V)
+A
GAIN
OF
IN
1000pF
NPO
–A
IN
3
V
CM
CLK
5MHz CLOCK
1µF
4
SENSE
V
SS
5
V
REF
GND
1µF
6
GND
V
DD
5V
1µF
7
V
DD
OV
DD
5V
3V
1µF
1µF
8
GND
D11
D10
D9
OGND
9
D0
D1
D2
D3
D4
D5
10
11
12
13
14
0V TO 3V
12-BIT
PARALLEL DATA
PLUS OVERFLOW
D8
D7
D6
1405 TA03
15
LTC1405
U
TYPICAL APPLICATIO
Dual Supply, 5Msps, 12-Bit ADC with 71.3dB SINAD
LTC1405
30Ω
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ANALOG INPUT
+A
GAIN
OF
5V
IN
(±2.048V)
1000pF, NPO
–A
IN
3
V
CM
CLK
5MHz CLOCK
1µF
4
SENSE
V
SS
–5V
1µF
5
V
REF
GND
1µF
6
GND
V
DD
7
V
DD
OV
DD
5V
5V
1µF
1µF
8
GND
D11
D10
D9
OGND
D0
9
10
11
12
13
14
D1
D2
12-BIT
PARALLEL DATA
PLUS OVERFLOW
D8
D3
D7
D4
D6
D5
1405 TA04
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PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise specified.
GN Package
28-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.386 – 0.393*
(9.804 – 9.982)
0.033
(0.838)
REF
0.015 ± 0.004
(0.38 ± 0.10)
28 27 26 25 24 23 22 21 20 19 18 17 1615
0.053 – 0.069
(1.351 – 1.748)
0.004 – 0.009
(0.102 – 0.249)
× 45°
0.0075 – 0.0098
(0.191 – 0.249)
0° – 8° TYP
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
0.016 – 0.050
(0.406 – 1.270)
0.008 – 0.012
(0.203 – 0.305)
0.0250
(0.635)
BSC
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN28 (SSOP) 1098
1
2
3
4
5
6
7
8
9 10 11 12 13 14
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
Pin Compatible with LTC1405
LTC1420
12-Bit, 10Msps, Sampling ADC
LTC1412
12-Bit, 3Msps, Sampling ADC with Parallel Output
Single 5V, 12-Bit, 1.25Msps with Parallel Output
Precision Bandgap Reference
Best Dynamic Performance, SINAD = 72dB at Nyquist
55mW Power Dissipation, 72dB SINAD
LTC1415
LT1019
0.05% Max Initial Accuracy, 5ppm/°C Max Drift
1405i LT/TP 0100 4K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
LINEAR TECHNOLOGY CORPORATION 2000
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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