LTC1406CGN#PBF [Linear]
LTC1406 - Low Power, 8-Bit, 20Msps, Sampling A/D Converter; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C;
| 型号： | LTC1406CGN#PBF |
| 厂家： | 
Linear |
| 描述： | LTC1406 - Low Power, 8-Bit, 20Msps, Sampling A/D Converter; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C 转换器 |
| 文件： | 总16页 (文件大小：451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1406
Low Power, 8-Bit, 20Msps,
Sampling A/D Converter
U
FEATURES
DESCRIPTION
TheLTC®1406isa20Msps, 8-bit, samplingA/Dconverter
which draws only 150mW from a single 5V supply. This
easy-to-usedeviceincludesahighdynamicrangesample-
and-hold with a 250MHz bandwidth.
■
Low Power, 8-Bit, 20Msps ADC
■
250MHz Internal Sample-and-Hold
■
7 Effective Bits at 70MHz Input Frequency
■
±1LSB DNL and INL Max
■
Single 5V Supply and 150mW Dissipation
The LTC1406’s full-scale input range is ±1V. The inputs
can be driven differentially or one input can be tied to a
fixed voltage and the other input driven with a ±1V bipolar
input. Maximum DC specifications include ±1LSB DNL
and INL over temperature. Outstanding AC performance
includes 48.5dB S/(N + D) and 62dB THD with a 1MHz
input; 47.5dB S/(N + D) and 59dB THD at the Nyquist input
frequency of 10MHz.
■
Power Down to 1µA
■
True Differential Inputs Reject Common Mode Noise
■
Accepts Single-Ended or Differential Input Signals
■
±1V Differential or 2V Single-Ended Input Span
■
Analog Inputs Common Mode to VDD and GND
■
24-Pin Narrow SSOP Package
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APPLICATIONS
Theuniquedifferentialinputsample-and-holdcanacquire
single-ended or differential input signals up to its 250MHz
bandwidth. The 60dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
■
Telecommunications
■
Wireless Communications
■
Digital Cellular Telephones
CCDs and Image Scanners
Video Digitizing and Digital Television
Digital Color Copiers
High Speed Undersampling
Personal Computer Video
High Speed Data Acquisition
■
■
The ADC has an 8-bit parallel output port with separate
power supply and ground allowing easy interface to 3V
digital systems. The pipelined architecture has five clock
cycles of data latency.
■
■
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATION
Effective Bits and Signal-to-Noise + Distortion
vs Input Frequency
Low Power, 20MHz, 8-Bit Sampling ADC
DV
DD
DGND
11
OV
DD
12
2
8
7
6
5
4
3
2
1
0
50
44
38
32
24
CLOCK
CLK
CIRCUITRY
23
22
21
20
19
18
17
16
15
OF/UF
D7
D6
7
8
DIGITAL
DATA
+
A
IN
D5
8-BIT
PIPELINE
ADC
TRACK-AND-
HOLD AMP
OUTPUT
DRIVERS
D4
–
D3
A
IN
D2
2.2V
D1
2.5k
1.95k
D0
100k
1M
10M
100M
9
4
10
3
5
6
1
INPUT FREQUENCY (Hz)
1406 TA02
1406 BD
AV
DD
V
BIAS
AGND
SHDN
AGND
V
REF
OGND
1
LTC1406
W W
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
AVDD = OVDD = DVDD = VDD (Notes 1, 2)
TOP VIEW
ORDER PART
Supply Voltage (VDD)................................................. 6V
Analog Input Voltage (Note 3) .... – 0.3V to (VDD + 0.3V)
Digital Input Voltage (Note 4) .................. – 0.3V to 10V
Digital Output Voltage................. – 0.3V to (VDD + 0.3V)
Power Dissipation.............................................. 500mW
Ambient Operation Temperature Range
LTC1406C................................................ 0°C to 70°C
LTC1406I............................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
NUMBER
1
2
CLK
OF/UF
D7
24
23
22
21
20
19
18
17
16
15
14
13
OGND
OV
DD
3
SHDN
LTC1406CGN
LTC1406IGN
4
D6
V
BIAS
5
D5
V
REF
6
D4
AGND
+
7
D3
A
A
IN
IN
–
8
D2
9
D1
AV
DD
10
11
12
D0
AGND
DGND
NC
NC
DV
DD
GN PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 110°C, θJA = 85°C/ W
Consult factory for Military grade parts.
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CO VERTER
CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
(Notes 5, 6)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
●
●
●
●
8
(Note 7)
±0.5
±0.25
±1
±1
±1
±8
±5
LSB
LSB
LSB
LSB
(Note 8)
Gain Error
With External 2.5V Reference
±1
U
U
(Note 5)
A ALOG I PUT
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
4.75V ≤ V ≤ 5.25V
MIN
TYP
MAX
UNITS
+
–
V
Analog Input Span [(A ) – (A )] (Note 9)
●
●
●
±1
V
V
IN
IN
IN
DD
+
–
+
–
Input (A or A ) Range
Voltage On Either A or A
0
V
DD
IN
IN
IN
IN
I
Analog Input Leakage Current
Analog Input Capacitance
CLK = 0
±5
µA
IN
C
CLK = 1
CLK = 0
4
2
pF
pF
IN
Input Bandwidth
250
3
MHz
ns
t
t
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Analog Input Common Mode Rejection Ratio
Internal Bias Voltage
AP
5
ps
RMS
jitter
–
+
CMRR
–2.5V < (A = A ) < 2.5V
60
2.2
dB
IN
IN
V
No Load
V
BIAS
2
LTC1406
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DY
A IC
ACCURACY
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
S/(N + D) Signal-to-Noise Plus Distortion Ratio
1MHz Input Signal
10MHz Input Signal
48.5
47.5
dB
dB
THD
SFDR
IMD
Total Harmonic Distortion
1MHz Input Signal, First 5 Harmonics
10MHz Input Signal, First 5 Harmonics
–62
–59
dB
dB
Spurious Free Dynamic Range
1MHz Input Signal
10MHz Input Signal
63
60
dB
dB
Intermodulation Distortion
f
= 3.500977MHz, f = 3.598633MHz
60
dB
IN1
IN2
U
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(Note 5)
DIGITAL I PUTS AND OUTPUTS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
V
= 5.25V
= 4.75V
= 0V to V
●
●
●
2.4
V
V
IH
IL
DD
DD
IN
0.8
I
±5
µA
pF
IN
DD
C
V
Digital Input Capacitance
High Level Output Voltage
5
IN
V
V
= 4.75V, I = –10µA
= 4.75V, I = –200µA
4.5
V
V
OH
DD
DD
O
O
●
●
4.0
V
Low Level Output Voltage
V
V
= 4.75V, I = 160µA
= 4.75V, I = 1.6mA
0.05
0.10
V
V
OL
DD
DD
O
O
0.4
I
I
Output Source Current
Output Sink Current
V
V
= 0V
–20
30
mA
mA
SOURCE
SINK
OUT
OUT
= V
DD
U
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(Note 5)
POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
(Note 10)
MIN
4.75
4.75
2.7
1.9
2
TYP
MAX
5.25
5.25
5.25
2.5
3
UNITS
V
AV
DV
OV
Analog Positive Supply Voltage
Digital Positive Supply Voltage
Output Positive Supply Voltage
Internal Bias Voltage
DD
DD
(Note 10)
V
(Note 10)
V
DD
V
V
When Externally Driven (Note 10)
(Note 10)
2.2
2.5
V
BIAS
REF
Reference Voltage
V
OGND
Output Ground
(Note 10)
0
2
V
I
Positive Supply Current
Power Dissipation
AV = DV = OV = 5V, f = 20MHz (Note 13)
SMPL
●
●
30
150
1
45
mA
mW
µA
µW
DD
DD
DD
DD
P
225
10
D
Power Down Positive Supply Current
Power Down Power Dissipation
SHDN = 0V, CLK = V or 0
DD
SHDN = 0V, CLK = V or 0
5
50
DD
3
LTC1406
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
20
TYP
MAX
UNITS
MHz
ns
f
t
t
t
t
t
t
Maximum Sampling Frequency
Clock Period
●
●
●
●
SMPL(MAX)
(Notes 11, 12)
(Notes 11, 12)
(Notes 11, 12)
50
1
2
3
4
5
6
Pulse Width High
Pulse Width Low
Output Delay
25
ns
25
ns
C = 15pF
L
15
5
25
ns
Pipeline Delay
Cycles
ns
Aperture Delay
3
Aperture Jitter
5
ps
RMS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, OGND
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
and AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above V
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB
when the output code flickers between 0111 1111 and 1000 0000.
,
DD
they will be clamped by internal diodes. This product can handle input
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CLK edge starts a conversion.
Note 12: At the maximum conversion rate, deviation from a 50% duty
cycle results in interstage settling times <25ns and performance may
be affected.
currents greater than 100mA below ground or above V without latchup.
DD
Note 4: When these pin voltages are taken below ground they will be
clamped by internal diodes. This product can handle input currents up to
100mA below ground without latchup. These pins are not clamped to V
.
DD
Note 5: V = 5V, f
= 20MHz and t = t = 2ns unless otherwise
r f
DD
SMPL
specified.
Note 13: V = –Full Scale.
IN
Note 6: Linearity, offset and full-scale specifications apply for a single-
+
–
ended A input with A tied to V = 2.5V.
IN
IN
REF
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TYPICAL PERFORMANCE CHARACTERISTICS
Signal-to-Noise Ratio vs
Input Frequency
S/(N + D) vs Input Frequency
Distortion vs Input Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
52
48
44
40
36
32
28
24
20
16
12
8
52
48
44
40
36
32
28
24
20
16
12
8
THD
3RD HARMONIC
2ND HARMONIC
4
0
100k
4
0
100k
100k
1M
10M
100M
1M
10M
100M
1M
10M
100M
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
1406 G03
1406 G02
1406 G01
4
LTC1406
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TYPICAL PERFORMANCE CHARACTERISTICS
Spurious-Free Dynamic Range
vs Input Frequency
Differential Nonlinearity
vs Output Code
Intermodulation Distortion Plot
70
60
50
40
30
20
10
0
1.0
0.5
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–0.5
–1.0
100k
1M
10M
100M
4
0
1
2
3
5
6
7
8
9
10
0
32
96 128 160 192
OUTPUT CODE
256
224
64
INPUT FREQUENCY (Hz)
FREQUENCY (MHz)
1406 G04
1406 G05
1406 G06
Input Common Mode Rejection
vs Input Frequency
Supply Current vs
Integral Nonlinearity
vs Output Code
Sampling Frequency
70
60
50
40
30
20
10
0
35
30
25
20
15
10
5
1.0
0.5
0
–0.5
–1.0
0
100k
1M
10M
100M
100k
1M
10M 20M
0
32
96 128 160 192
OUTPUT CODE
256
224
64
SAMPLING FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
1406 G08
1406 G09
1406 G07
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PIN FUNCTIONS
VREF (Pin 5): External 2.5V Reference Input. Bypass to
analog ground plane with 10µF tantalum in parallel with
0.1µF or 10µF ceramic.
OGND (Pin 1): Digital Data Output Ground. Tie to analog
ground plane. May be tied to logic ground if desired.
OVDD (Pin 2): Digital Data Output Supply. Normally tied to
5V, can be used to interface with 3V digital logic. Bypass
to OGND with 10µF tantalum in parallel with 0.1µF or 10µF
ceramic.
AGND(Pin6):AnalogGround. Tietoanaloggroundplane.
+
AIN (Pin 7): ±1V Input. The maximum output code
occurs when [(AIN+) – (AIN–)] = 1V. The minimum output
code occurs when [(AIN+) – (AIN–)] = –1V.
SHDN (Pin 3): Power Shutdown Input. Logic low selects
shutdown.
–
AIN (Pin 8): ±1V Input. The maximum output code
occurs when [(AIN+) – (AIN–)] = 1V. The minimum output
code occurs when [(AIN+) – (AIN–)] = –1V. For single-
ended operation, tie AIN– to a DC voltage (e.g., VREF).
VBIAS (Pin4):InternalBiasVoltage. Internallysetto2.2V.
Bypass to analog ground plane with 10µF tantalum in par-
allel with 0.1µF or 10µF ceramic.
5
LTC1406
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PIN FUNCTIONS
D7 to D0 (Pins 15 to 22): Digital Data Outputs. The out-
AVDD (Pin 9): Analog 5V Positive Supply. Bypass to ana-
log ground plane with 10µF tantalum in parallel with 0.1µF
or 10µF ceramic.
puts swing between OVDD and OGND.
OF/UF(Pin23):Overflow/UnderflowBit.OF/UFhighwith
D7 to D0 all high indicates an overrange, OF/UF high with
D7toD0alllowindicatesanunderrangecondition.OF/UF
lowindicatesaconversionwithinthenormalinputrange.
The outputs swing between OVDD and OGND.
AGND(Pin10):AnalogGround.Tietoanaloggroundplane.
DGND (Pin 11): Digital Ground for Internal Logic. Tie to
analog ground plane.
DVDD(Pin12):Digital5VPositiveSupply.BypasstoDGND
with 10µF tantalum in parallel with 0.1µF or 10µF ceramic.
CLK(Pin24):ClockInput.Internalsample-and-holdtracks
the input signal when CLK is high and samples the input
signal on the falling edge.
NC (Pins 13, 14): No Internal Connection.
AV = DV = V
NOMINAL (V)
ABSOLUTE MAXIMUM (V)
DD
DD
DD
PIN
NAME
DESCRIPTION
MIN
TYP
0
MAX
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
+ 0.3
1
OGND
Ground for Output Drivers
Supply for Output Drivers
Shutdown Input, Active Low
Internal Bias Voltage
V
DD
2
OV
DD
2.7
0
3 or 5
5.25
6
3
SHDN
V
10
DD
4
V
V
1.9
2
2.2
2.5
0
2.5
3
V
V
V
V
V
+ 0.3
BIAS
REF
DD
DD
DD
DD
DD
5
External Reference Input
Analog Ground, Clean Ground
Positive Analog Input, ±1V Span
Negative Analog Input
Analog Supply
+ 0.3
+ 0.3
+ 0.3
+ 0.3
6
AGND
+
7
A
A
0
0
V
V
IN
IN
DD
DD
–
8
9
AV
DD
4.75
5
0
0
5
5.25
6
10
AGND
DGND
Analog Ground, Substrate Ground
Digital Ground
V
V
+ 0.3
+ 0.3
DD
DD
11
12
DV
NC
Digital Supply
4.75
5.25
6
DD
13 to 14
15 to 22
23
No Connect, No Internal Connection
Data Outputs
D7 to D0
OF/UF
CLK
OGND
OGND
0
OV
OV
–0.3
–0.3
–0.3
V
V
+ 0.3
+ 0.3
DD
DD
DD
DD
Overflow/Underflow Output
Clock Input
24
V
10
DD
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TI I G DIAGRA
t
6
N
N + 1
ANALOG
SIGNAL
N + 2
N – 1
N + 6
N + 3
N + 5
N + 4
t
t
1
3
CLOCK
t
2
t
4
DATA OUT
N – 6
N – 5
N – 4
N – 3
N – 2
N – 1
N
1406 TD
t
5
6
LTC1406
U
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FUNCTIONAL BLOCK DIAGRA
DV
DD
DGND
11
OV
DD
12
2
24
CLOCK
CIRCUITRY
CLK
23
22
21
20
19
18
17
16
15
OF/UF
D7
D6
7
8
DIGITAL
DATA
+
A
IN
D5
8-BIT
PIPELINE
ADC
TRACK-AND-
HOLD AMP
OUTPUT
DRIVERS
D4
–
D3
A
IN
D2
2.2V
D1
2.5k
1.95k
D0
9
4
10
AGND
3
5
6
1
1406 BD
AV
V
SHDN
AGND
V
OGND
DD
BIAS
REF
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APPLICATIONS INFORMATION
capacitors CH resulting in a differential DC voltage on the
output of the track-and-hold amplifier that is proportional
to the input signal. This differential voltage is fed into a
comparator that determines the most significant bit and
subtracts the result. The residue is then amplified by two
andpassedtothenextstageviaasimilarsample-and-hold
circuit. This continues down the eight pipeline stages. The
comparator outputs are then combined in a digital error
correctioncircuit. The8-bitwordisavailableattheoutput,
five clock cycles after the sampling edge.
Conversion Details
TheLTC1406usesaninternalsample-and-holdcircuitand
a pipeline quantizing architecture to convert an analog
signal to an 8-bit parallel output. With CLK high the input
switches are closed and the analog input will be acquired
on the input sampling capacitors CS (see Figure 1).
OnthefallingedgeofCLKtheinputswitchesopen, captur-
ing the input signal. The sampling capacitors are then
shorted together and the charge is transferred to the hold
CLK
Dynamic Performance
C
H
The LTC1406 has excellent wideband sampling capability.
The sample-and-hold amplifier has a small-signal input
bandwidth of 250MHz allowing the ADC to undersample
input signals with frequencies well beyond the converter’s
Nyquistfrequency. FFT(FastFourierTransform)testtech-
niques are used to test the ADC’s frequency response,
distortion and noise at the rated throughput. By applying
a low distortion sine wave and analyzing the digital output
using an FFT algorithm, the ADC’s spectral content can be
examined for frequencies outside the fundamental. Figure
2 shows a typical LTC1406 FFT plot.
C
S
CLK
CLK
+
–
A
A
+
–
IN
IN
CLK
CLK
TO NEXT STAGE
C
S
C
H
1406 F01
CLK
Figure 1. Input Sample-and-Hold Amplifier
7
LTC1406
APPLICATIONS INFORMATION
U
W U U
0
where ENOB is the effective number of bits and S/(N + D)
isexpressedindB.Atthemaximumsamplingrateof20MHz
the LTC1406 maintains near ideal ENOBs up to and be-
yondtheNyquistinputfrequencyof10MHz(seeFigure3).
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
8
7
6
5
4
3
2
1
0
50
44
38
32
4
0
1
2
3
5
6
7
8
9
10
FREQUENCY (Hz)
1406 F02a
Figure 2a. Nonaveraged, 4096 Point FFT
Input Frequency = 1MHz
100k
1M
10M
100M
0
INPUT FREQUENCY (Hz)
1406 TA02
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Figure 3. Effective Bits and Signal-to-(Noise + Distortion)
vs Input Frequency
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonicsoftheinputsignaltothefundamentalitself.The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
4
0
1
2
3
5
6
7
8
9
10
FREQUENCY (Hz)
1406 F02b
Figure 2b. Nonaveraged, 4096 Point FFT
Input Frequency = 30MHz
V22 + V32 + V42 +. . .Vn2
THD = 20 log
V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the sec-
ond through nth harmonics. THD vs Input Frequency is
shown in Figure 4. The LTC1406 has good distortion per-
formance up to the Nyquist frequency and beyond.
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling fre-
quency. The effective number of bits (ENOBs) is a mea-
surementoftheresolutionofanADCandisdirectlyrelated
to the S/(N + D) by the equation:
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different fre-
quency (see Figure 5).
ENOB = [S/(N + D) – 1.76]/6.02
8
LTC1406
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APPLICATIONS INFORMATION
0
–10
–20
–30
–40
–50
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mf ±nfb, where m and n = 0, 1, 2, 3,
etc. Forexample, the2nadorderIMDtermsinclude(fa ±fb).
If the two input sine waves are equal in magnitude, the
value (in decibels) of the 2nd order IMD products can be
expressed by the following formula:
THD
–60
–70
–80
3RD HARMONIC
10M 100M
2ND HARMONIC
Amplitude at f ± f
(
)
b
a
100k
1M
IMD f ± f = 20 log
(
)
a
b
INPUT FREQUENCY (Hz)
Amplitude at f
1406 G03
a
Figure 4. Distortion vs Input Frequency
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibel relative to the RMS value of
a full-scale input signal (see Figure 6).
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full-scale input signal. The LTC1406 has been
designed for wide input bandwidth (250MHz), allowing
the ADC to undersample input signals with frequencies
above the converter’s Nyquist frequency. The noise floor
stays very low at high frequencies; S/(N + D) becomes
dominatedbydistortionatfrequenciesfarbeyondNyquist.
4
0
1
2
3
5
6
7
8
9
10
FREQUENCY (MHz)
1406 G05
Figure 5. Intermodulation Distortion Plot
Analog Inputs
70
60
50
40
30
20
10
0
The LTC1406 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The AIN and AIN
+
–
inputs are sampled at the same time and the ADC will
always convert the difference of [(AIN+) – (AIN–)] indepen-
dent of the common mode voltage. Any unwanted signal
that is common to both inputs will be rejected by the com-
mon mode rejection of the sample-and-hold circuit. The
common mode rejection holds up to extremely high fre-
quencies (see Figure 7).
100k
1M
10M
100M
INPUT FREQUENCY (Hz)
The inputs can be driven differentially or single-ended. In
differential mode, both inputs are driven ±0.5V out of
phase with each other. In single-ended mode, the nega-
tive input is tied to a fixed voltage and AIN+ is used as the
1406 G04
Figure 6. Spurious-Free Dynamic Range vs
Input Frequency
9
LTC1406
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APPLICATIONS INFORMATION
70
+
+
ANALOG INPUT
1.5V TO 3.5V
ANALOG INPUT
2V SPAN
A
A
V
A
A
V
IN
IN
60
50
40
30
20
10
0
LTC1406
–
LTC1406
–
IN
IN
2.5V
2.5V
REF
REF
1406 F08a
1406 F08b
Figure 8b. AC Coupled
Figure 8a. DC Coupled
100k
1M
10M
100M
While CLK is low the analog inputs draw only a small leak-
age current. If the source impedance of the driving circuit
is low, then the LTC1406 inputs can be driven directly. As
source impedance increases, so will acquisition time. For
minimum acquisition time with high source impedance, a
buffer amplifier should be used. The only requirement is
that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion
starts(settlingtimemustbe25nsforfullthroughputrate).
INPUT FREQUENCY (Hz)
1406 G08
Figure 7. Common Mode Rejection
vs Input Frequency
single input providing a±1V bipolar input range centered
around AIN–. Likewise, AIN+ can be tied to a fixed voltage
and AIN– used as the single input. In any configuration the
+
maximum output code (1111 1111) occurs when [(AIN
)
– (AIN–)] = 1V and the minimum output code (0000 0000)
occurs when [(AIN+) – (AIN–)] = –1V.
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (<50Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain of
1 and has a unity-gain bandwidth of 50MHz, then the out-
put impedance at 50MHz must be less than 50Ω. The
secondrequirementisthattheclosed-loopbandwidthmust
be greater than 70MHz to ensure adequate small-signal
settling for full throughput rate.
Each analog input can swing from ground to VDD but not
beyond. Therefore, the input common mode voltage can
range from 0.5V to 4.5V in differential mode and from 1V
to 4V in single-ended mode.
As an example, with AIN– connected to the VREF pin (2.5V)
the input range will be 1.5V to 3.5V (see Figure 8a). To
achieveotherrangestheinputmaybecapacitivelycoupled
to achieve a 2V span with virtually any common mode
voltage (see Figure 8b).
The 2V input span requires a 2.5V external reference be
connected to the VREF pin. The LT1460-2.5 micropower
precision series reference is recommended. To achieve
other input spans, the reference voltage (VREF) can vary
between 2V to 3V. The VREF pin can also be driven with a
DAC or other means. This is useful in applications where
the peak input signal amplitude may vary. The input span
of the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio.
The following list is a summary of the op amps that are
suitable for driving the LTC1406. More detailed informa-
tion is available in the Linear Technology Databooks and
on the LinearViewTM CD-ROM.
LT®1223:100MHzVideoCurrentFeedbackAmplifier.6mA
supply current. ±5V to ±15V supplies. Low noise.
LT1227:140MHzVideoCurrentFeedbackAmplifier.10mA
supply current. ±5V to ±15V supplies. Low distortion.
Low noise.
The analog inputs of the LTC1406 are easy to drive. The
inputs draw only one small current spike while charging
thesample-and-holdcapacitorsfollowingarisingCLKedge.
LinearView is a trademark of Linear Technology Corporation.
10
LTC1406
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APPLICATIONS INFORMATION
LT1229/LT1230: Dual and Quad 100MHz Current Feed-
back Amplifiers. ±2V to ±15V supplies. Low noise. 6mA
supply current each amplifier.
resistors can also generate distortion from self-heating
and from damage that may occur during soldering. Metal
film surface mount resistors are much less susceptible to
both problems.
LT1259/LT1260: Dual and Triple 130MHz Current Feed-
back Amplifiers. ±2V to ±14V supplies. 5mA supply cur-
rent. Low distortion. Low noise.
Input/Output Characteristics
Figure 10 shows the ideal input/output characteristics for
theLTC1406. Thecodetransitionsoccurmidwaybetween
successive integer LSB values (i.e., –FS + 0.5LSB, –FS +
1.5LSB, –FS + 2.5LSB...FS – 1.5LSB, FS – 0.5LSB). The
output is straight binary with 1LSB = FS – (–FS)/256 = 2V/
256=7.8125mV.TheOF/UFbitindicatesthattheinputhas
exceeded full scale and can be used to detect an overrange
or underrange condition. A logic high output on the OF/UF
pin with an output code of 0000 0000 indicates the input
is less than the negative full scale. A logic high output on
the OF/UF pin with an output code of 1111 1111 indicates
that the input is greater than the positive full scale. A logic
low output on the OF/UF pin indicates the input is within
the full-scale range of the converter.
LT1363: 70MHz Voltage Feedback Amplifier. ±2.5V to
±15V supplies. 7.5mA supply current. Low distortion.
LT1364/LT1365: DualandQuad70MHzVoltageFeedback
Amplifiers. ±2.5Vto±15Vsupplies. 7.5mAsupplycurrent
per amplifier. Low distortion.
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1406 noise and distortion. The small-signal band-
widthofthesample-and-holdcircuitis250MHz.Anynoise
ordistortionproductsthatarepresentattheanaloginputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For example, Figure 9 shows a 220pF
capacitor from AIN+ to AIN– and a 75Ω source resistor to
limit the input bandwidth to 9.6MHz. The 220pF capacitor
also acts as a charge reservoir for the input sample-and-
hold and isolates the ADC input from sampling glitch sen-
sitivecircuitry.Largervaluecapacitorsmaybesubstituted
to further limit the input bandwidth. High quality capaci-
torsandresistorsshouldbeusedsincethesecomponents
can add distortion. NPO and silver mica type dielectric
capacitors have excellent linearity. Carbon surface mount
In applications where absolute accuracy is important, off-
set and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Zero offset
isachievedbyadjustingtheoffsetappliedtotheAIN– input.
For zero offset error, apply a voltage equal to the input
OF/UF BIT
1111 1111
1111 1110
1111 1101
1000 0001
1000 0000
0111 1111
0111 1110
0000 0010
0000 0001
0000 0000
75Ω
+
ANALOG INPUT
1.5V TO 3.5V
A
A
V
IN
220pF
LTC1406
–
IN
–1
0
1
2.5V
–FS
FS – 1LSB
REF
LSB
LSB
1406 F09
INPUT VOLTAGE (V)
1406 F10
Figure 9. RC Input Filter
Figure 10. Transfer Characteristics
11
LTC1406
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APPLICATIONS INFORMATION
common mode voltage minus 3.90625mV (i.e., –0.5LSB)
and adjust the offset at the AIN– input until the output code
flickers between 0111 1111 and 1000 0000. For full-scale
adjustment, an input voltage equal to the input common
mode voltage plus 988.28125mV (i.e., FS – 1.5LSBs) is
applied to AIN and the VREF input is adjusted until the
output code flickers between 1111 1110 and 1111 1111.
While the falling edge starts the conversion, both rising
and falling edges are used internally during the conver-
sion. It is therefore important to provide a clock signal that
has low jitter and fast rise and fall times (<2ns). Much of
theinternalcircuitryoperatesdynamicallylimitingthemini-
mum conversion rate to 10kHz. To ensure proper opera-
tion afterpoweris firstapplied, ortheclock stops formore
than 100µs, typically 20 clock cycles must be performed
at a sample rate above 10kHz before the output data will
be valid.
+
Digital Inputs and Outputs
The LTC1406 is designed to easily interface with either 3V
or 5V logic. The digital input pins, SHDN and CLK, have
thresholds of nominally 1.9V and will accept a 3V or 5V
logic input. The data output pins, including OF/UF, are
connected to a separate supply and ground (OVDD and
OGND respectively). OVDD is normally connected to DVDD
but can be connected to an external supply as low as 2.7V.
OGND is normally connected to DGND but can be con-
nected to an external ground or an external voltage source
as high as 2V.
10
f
= 20MHz
SAMPLE
9
8
7
6
5
4
3
2
1
0
Clock
28 32 36 40 44 48 52 56 60 64 68 72
The LTC1406 requires a 50% duty cycle clock. The duty
cycle should be timed from the nominal threshold of the
CLK input which is 1.9V. At conversion speeds below the
maximum conversion rate of 20MHz, the duty cycle can
deviate from 50% with no degradation in performance as
long as each clock phase is at least 25ns long. At the
maximumconversionrate,deviationfroma50%dutycycle
clock results in interstage settling times of <25ns and
performance may be affected.
DUTY CYCLE (%)
1406 F11
Figure 11. Typical DNL vs Duty Cycle
Power Shutdown
The quiescent power of the LTC1406 can be further
reducedbetweenconversionsbytakingtheSHDNpinlow.
This powers down all of the internal amplifiers and bias
circuitry and the part draws only a small quiescent current
of 1µA from the 5V supply. There is a nominally 4k internal
resistorbetweenVREF andAGNDthatwillcontinuetodraw
currentduringshutdownaslongasVREFisdriven.Itshould
also be noted that the data output drivers are not three-
state devices and do not go into a high impedance state
during shutdown. If the data output pins will remain con-
nected to a load during shutdown, current may be drawn
through the OVDD supply pin. This can be prevented by
including a FET switch in series with OVDD or OGND con-
trolled by SHDN. If the data bus will remain active during
With the CLK pin high, the ADC will track the difference of
the two analog inputs. On the falling edge of CLK the input
is sampled and the conversion begins. At the end of five
clock cycles (on the fifth falling CLK edge following the
start of conversion) the data from the conversion will be
available at the digital outputs until the next falling CLK
edge. Each falling edge of CLK starts a new conversion so
successive conversion results are available on successive
falling CLK edges.
12
LTC1406
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APPLICATIONS INFORMATION
shutdown. It may also be desirable to isolate the data out-
put pins from the bus to reduce the load capacitance. To
resume normal operation the SHDN pin must be brought
high and typically 20 clock cycles must be performed at a
sample rate above 10kHz before the output data will be
valid.
microprocessor bus, it is possible to get errors in the con-
version results. These errors are due to feedthrough from
the microprocessor to the comparators. The problem can
be eliminated by forcing the microprocessor into a wait
state during conversion or by using three-state buffers to
isolate the ADC data bus.
TheLTC1406hasdifferentialinputstominimizenoisecou-
pling. Common mode noise on the AIN+ and AIN– leads will
be rejected by the input CMRR. The LTC1406 will hold and
convert the difference voltage between AIN+ and AIN–. The
Board Layout and Bypassing
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best per-
formance from the LTC1406, a printed circuit board with
ground plane is required. Layout for the printed circuit
boardshouldensurethatdigitalandanalogsignallinesare
separated as much as possible. In particular, care should
be taken not to run any digital track alongside an analog
signal track or underneath the ADC.
+
leads to AIN (Pin 7) and AIN– (Pin 8) should be kept as
short as possible. In applications where this is not pos-
sible, the AIN+ and AIN– traces should be run side by side
to equalize coupling.
Supply Bypassing
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 1 (OGND), Pin 6 (AGND), Pin 10 (AGND) and Pin 11
(DGND)andallotheranaloggroundsshouldbeconnected
to this single analog ground point. The VCM, VREF, DVDD
and OVDD bypass capacitors should also be connected to
this analog ground plane. No other digital grounds should
be connected to this analog ground plane. In some appli-
cationsitmaybedesirabletoconnecttheOVDD tothelogic
system supply and OGND to the logic system ground. In
these cases OVDD should be bypassed to OGND instead of
the analog ground plane.
High quality, low series resistance ceramic, 10µF bypass
capacitors should be used at the VDD, VCM and VREF pins
asshownintheTypicalApplicationonthefirstpageofthis
data sheet. Surface mount ceramic capacitors such as
Murata GRM235Y5V106Z016 provide excellent bypass-
ing in a small board space. Alternatively, 10µF tantalum
capacitorsinparallelwith0.1µFceramiccapacitorscanbe
used. Bypass capacitors must be located as close to the
pins as possible. The traces connecting the pins and the
bypass capacitors must be kept short and should be made
as wide as possible.
Example Layout
Low impedance analog and digital power supply common
returnsareessentialtolownoiseoperationoftheADCand
the foil width for these tracks should be as wide as pos-
sible. In applications where the ADC data outputs and
control signals are connected to a continuously active
Figures 12a, 12b, 12c and 12d show the schematic and
layoutofanevaluationboard.Thelayoutdemonstratesthe
proper use of decoupling capacitors and ground plane
with a 2-layer printed circuit board.
13
LTC1406
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APPLICATIONS INFORMATION
14
LTC1406
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APPLICATIONS INFORMATION
Figure 12b. Suggested Evaluation Circuit
Board—Component Side Silkscreen
Figure 12d. Suggested Evaluation Circuit
Board—Solder Side Layout
Figure 12c. Suggested Evaluation Circuit
Board—Component Side Layout
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
GN Package
24-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.337 – 0.344*
(8.560 – 8.738)
24 23 22 21 20 19 18 17 16 15 14 13
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
2
3
4
5
6
7
8
9 10 11 12
0.015 ± 0.004
(0.38 ± 0.10)
0.053 – 0.068
(1.351 – 1.727)
× 45°
0.004 – 0.0098
(0.102 – 0.249)
0.007 – 0.0098
(0.178 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.008 – 0.012
(0.203 – 0.305)
0.025
(0.635)
BSC
*
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
GN24 (SSOP) 1197
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will notinfringe onexisting patent rights.
15
LTC1406
TYPICAL APPLICATION
U
Low Power, 20MHz, 8-Bit Sampling ADC
LTC1406
5V
1
2
24
23
22
21
20
19
18
17
16
15
14
13
CLK
OF/UF
D7
CLOCK INPUT
OGND
OV
OVERFLOW/UNDERFLOW OUTPUT
DD
3
10µF
SHDN
4
D6
V
BIAS
REF
5
2.5V
D5
V
REFERENCE
6
10µF
10µF
8-BIT
PARALLEL
BUS
D4
AGND
+
7
D3
A
IN
ANALOG
INPUTS
8
–
D2
A
IN
9
D1
AV
DD
10
11
12
D0
AGND
DGND
NC
NC
NC
NC
DV
DD
1406 TA03
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
ADCs
LTC1196/LTC1198
LTC1197/LTC1199
LTC1410
Single Supply, 8-Bit, 1Msps/750ksps ADCs
Single Supply, 10-Bit, 500ksps/450ksps ADCs
Single 3V or 5V Supply, Low Power, Serial Interface, SO-8 Package
Single 3V or 5V Supply, Low Power, Serial Interface, SO-8 Package
Best Dynamic Performance, THD = 84dB and SINAD = 71dB at Nyquist
Single Supply 55mW Dissipation
12-Bit, 1.25Msps Sampling ADC with Shutdown
Single 5V, 12-Bit, 1.25Msps ADC
14-Bit, 800ksps Sampling ADC with Shutdown
16-Bit, 333ksps ADC
LTC1415
LTC1419
81.5dB SINAD, 150mW from ±5V Supplies
LTC1604
90dB SINAD, 100dB THD, 250mW Dissipation
Low Power, ±10V Inputs
LTC1605
Single 5V, 16-Bit, 100ksps ADC
DACs
LTC1446/LTC1446L
Dual 12-Bit V
DACs in SO-8 Package
LTC1446: V = 4.5V to 5.5V, V
= 0V to 4.095V
= 0V to 2.5V
OUT
OUT
CC
OUT
LTC1446L: V = 2.7V to 5.5V, V
CC
LTC1448
Dual 12-Bit Rail-to-Rail Output DAC in SO-8 Package
Quad 12-Bit Rail-to-Rail Output DACs
V
= 2.7V to 5.5V, Output Swings from GND to REF, REF Input Can Be
CC
Tied to V
CC
LTC1458/LTC1458L
LTC1458: V = 4.5V to 5.5V, V
0V to 4.095V
CC
OUT
LTC1458L: V = 2.7V to 5.5V, V
= 0V to 2.5V
OUT
CC
1406f LT/TP 0299 4K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1998
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