LTC1409ISW#PBF [Linear]
LTC1409 - 12-Bit, 800ksps Sampling A/D Converter with Shutdown; Package: SO; Pins: 28; Temperature Range: -40°C to 85°C;型号: | LTC1409ISW#PBF |
厂家: | Linear |
描述: | LTC1409 - 12-Bit, 800ksps Sampling A/D Converter with Shutdown; Package: SO; Pins: 28; Temperature Range: -40°C to 85°C 转换器 |
文件: | 总20页 (文件大小:411K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC1409
12-Bit, 800ksps Sampling
A/D Converter with Shutdown
U
DESCRIPTIO
EATURE
S
F
■
■
■
■
■
■
Sample Rate: 800ksps
The LTC®1409 is a 1µs, 800ksps, sampling 12-bit A/D
converter that draws only 80mW from ±5V supplies. This
easy-to-use device includes a high dynamic range sample-
and-holdandaprecisionreference.Twodigitallyselectable
power Shutdown modes provide flexibility for low power
systems.
Power Dissipation: 80mW
72.5dB S/(N + D) and 86dB THD at Nyquist
No Pipeline Delay
Nap (4mW) and Sleep (10µW) Shutdown Modes
Operates with Internal 15ppm/°C Reference
or External Reference
True Differential Inputs Reject Common Mode Noise
20MHz Full Power Bandwidth Sampling
±2.5V Bipolar Input Range
The LTC1409 full-scale input range is ±2.5V. Maximum
DC specs include ±1LSB INL and ±1LSB DNL over tem-
perature. Outstanding AC performance includes 72.5dB
S/(N + D) at the Nyquist input frequency of 400kHz.
■
■
■
■
28-Pin SO Wide and SSOP Package
Theuniquedifferentialinputsample-and-holdcanacquire
single-ended or differential input signals up to its 20MHz
bandwidth. The 60dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
O U
PPLICATI
S
A
■
■
■
■
■
■
Telecommunications
Digital Signal Processing
Multiplexed Data Acquisition Systems
High Speed Data Acquisition
Spectrum Analysis
The ADC has a µP compatible, 12-bit parallel output port.
There is no pipeline delay in the conversion results.
A separate convert start input and a data ready signal
(BUSY) ease connections to FIFOs, DSPs and micropro-
cessors. A digital output driver power supply pin allows
direct connection to 3V logic.
Imaging Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
O
TYPICAL APPLICATI
Effective Bits and Signal-to-(Noise + Distortion)
vs Input Frequency
800kHz, 12-Bit Sampling A/D Converter
LTC1409
12
10
8
74
68
62
56
50
5V
DIFFERENTIAL
ANALOG INPUT
(–2.5V TO 2.5V)
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+A
–A
AV
OV
IN
DD
NYQUIST
FREQUENCY
–5V
IN
DD
3
10µF
2.50V
OUTPUT
V
V
SS
REF
V
REF
4
10µF
REFCOMP
AGND
BUSY
CS
5
10µF
6
6
D11(MSB) CONVST
µP CONTROL
LINES
7
D10
D9
RD
SHDN
NAP/SLP
OGND
D0
8
4
9
D8
10
11
12
13
14
2
D7
12-BIT
PARALLEL
BUS
f
= 800ksps
10k
D6
SAMPLE
0
D5
D1
1k
100k
1M
10M
D4
D2
INPUT FREQUENCY (Hz)
DGND
D3
LTC1409 • TA02
LTC1409 • TA01
1
LTC1409
W
U
W W W
U
ABSOLUTE AXI U RATI GS
/O
PACKAGE RDER I FOR ATIO
AVDD = OVDD = VDD (Notes 1, 2)
TOP VIEW
ORDER
PART NUMBER
Supply Voltage (VDD) ................................................ 6V
Negative Supply Voltage (VSS)................................ –6V
Total Supply Voltage (VDD to VSS) .......................... 12V
Analog Input Voltage
(Note 3) .................................. VSS – 0.3V to VDD + 0.3V
Digital Input Voltage (Note 4) ............ VSS – 0.3V to 10V
Digital Output Voltage............. VSS – 0.3V to VDD + 0.3V
Power Dissipation............................................. 500mW
Operating Temperature Range
LTC1409C............................................... 0°C to 70°C
LTC1409I........................................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
+A
–A
V
1
2
3
4
5
6
7
8
9
28 AV
DD
IN
IN
27 OV
DD
LTC1409CG
LTC1409CSW
LTC1409IG
26
V
SS
REF
REFCOMP
25 BUSY
24 CS
AGND
D11(MSB)
D10
23 CONVST
22 RD
LTC1409ISW
D9
21 SHDN
20 NAP/SLP
19 OGND
18 D0
D8
D7 10
D6 11
D5 12
17 D1
D4 13
16 D2
DGND 14
15 D3
G PACKAGE
28-LEAD PLASTIC SO
SW PACKAGE
28-LEAD PLASTIC SO WIDE
TJMAX = 110°C, θJA = 95°C/W (G)
TJMAX = 110°C, θJA = 130°C/W (SW)
Consult factory for Military grade parts.
U
With Internal Reference (Notes 5, 6)
CO VERTER
CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
12
TYP
MAX
UNITS
Bits
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
●
●
●
(Note 7)
(Note 8)
±0.3
±0.3
±2
±1
±1
LSB
LSB
±6
±8
LSB
LSB
●
●
Full-Scale Error
±15
LSB
Full-Scale Tempco
I
= 0
±15
ppm/°C
OUT(REF)
U
U
(Note 5)
A ALOG I PUT
SYMBOL PARAMETER
CONDITIONS
4.75V ≤ V ≤ 5.25V, –5.25V ≤ V ≤ –4.75V
MIN
TYP
MAX
UNITS
V
V
Analog Input Range (Note 9)
●
±2.5
IN
DD
SS
I
Analog Input Leakage Current
Analog Input Capacitance
CS = High
●
±1
µA
IN
C
Between Conversions
During Conversions
17
5
pF
pF
IN
t
t
t
Sample-and-Hold Acquisition Time
●
50
–1.5
5
150
ns
ns
ACQ
AP
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Analog Input Common Mode Rejection Ratio
ps
RMS
jitter
CMRR
–2.5V < (–A = +A ) < 2.5V
60
dB
IN
IN
2
LTC1409
W
U
(Note 5)
DY
A IC
ACCURACY
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
S/(N + D)
Signal-to-Noise Plus Distortion Ratio 100kHz Input Signal (Note 12)
400kHz Input Signal (Note 12)
●
●
70
68
73.0
72.5
dB
dB
THD
IMD
Total Harmonic Distortion
100kHz Input Signal, First Five Harmonics
–90
–86
dB
dB
400kHz Input Signal, First Five Harmonics
●
●
–74
–74
Peak Harmonic or Spurious Noise
Intermodulation Distortion
Full Power Bandwidth
400kHz Input Signal
–90
–84
15
dB
dB
f
= 29.37kHz, f = 32.446kHz
IN2
IN1
MHz
MHz
Full Linear Bandwidth
S/(N + D) ≥ 68dB
1.6
U U
U
(Note 5)
I TER AL REFERE CE CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
TYP
2.500
±15
MAX
UNITS
V
V
REF
V
REF
V
REF
Output Voltage
Output Tempco
Line Regulation
I
I
= 0
= 0
2.480
2.520
OUT
OUT
ppm/°C
4.75V ≤ V ≤ 5.25V
–5.25V ≤ V ≤ –4.75V
0.01
0.01
LSB/V
LSB/V
DD
SS
V
REF
Output Resistance
–0.1mA ≤
|
I
|
≤ 0.1mA
4
kΩ
OUT
REFCOMP Output Voltage
I
= 0
4.06
V
OUT
U
U
(Note 5)
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
V
= 5.25V
= 4.75V
= 0V to V
●
●
●
2.4
V
V
IH
IL
DD
DD
IN
0.8
I
±10
µA
pF
IN
DD
C
V
Digital Input Capacitance
High Level Output Voltage
5
IN
V
V
V
= 4.75V
OH
DD
O
O
I = –10µA
4.5
V
V
I = –200µA
●
4.0
V
OL
Low Level Output Voltage
= 4.75V
DD
I = 160µA
0.05
0.10
V
V
O
I = 1.6mA
●
●
●
0.4
±10
15
O
I
High-Z Output Leakage D11 to D0
= 0V to V , CS High
µA
pF
OZ
OUT
DD
C
OZ
High-Z Output Capacitance D11 to D0 CS High (Note 9 )
I
I
Output Source Current
Output Sink Current
V
V
= 0V
–10
10
mA
mA
SOURCE
SINK
OUT
OUT
= V
DD
W U
POWER REQUIRE E TS (Note 5)
SYMBOL PARAMETER
CONDITIONS
(Notes 10, 11)
(Note 10)
MIN
4.75
TYP
MAX
5.25
UNITS
V
V
Positive Supply Voltage
Negative Supply Voltage
V
V
DD
SS
–4.75
–5.25
I
Positive Supply Current
Nap Mode
Sleep Mode
CS High
●
6.0
0.8
1.0
9.0
1.2
mA
mA
µA
DD
CONVST = CS = RD = SHDN = 0V, NAP/SLP = 5V
CONVST = CS = RD = SHDN = 0V, NAP/SLP = 0V
3
LTC1409
W U
POWER REQUIRE E TS (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Negative Supply Current
Nap Mode
CS High
●
●
10
10
1
15
mA
µA
µA
SS
CONVST = CS = RD = SHDN = 0V, NAP/SLP = 5V
CONVST = CS = RD = SHDN = 0V, NAP/SLP = 0V
Sleep Mode
P
Power Dissipation
Nap Mode
Sleep Mode
80
3.8
0.01
120
6
mW
mW
mW
DISS
CONVST = CS = RD = SHDN = 0V, NAP/SLP = 5V
CONVST = CS = RD = SHDN = 0V, NAP/SLP = 0V
W U
TI I G CHARACTERISTICS (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
kHz
ns
f
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Conversion Time
●
●
●
●
●
●
800
SAMPLE(MAX)
900
1250
150
CONV
Acquisition Time
ns
ACQ
1
CS to RD Setup Time
CS↓ to CONVST↓ Setup Time
NAP/SLP↓ to SHDN↓ Setup Time
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
0
ns
10
10
ns
2
ns
3
SHDN↑ to CONVST↓ Wake-Up Time (Note 10)
200
ns
4
CONVSTLow Time
(Notes 10, 11)
●
●
50
ns
5
CONVST to BUSY Delay
C = 25pF
L
10
35
ns
ns
6
60
t
Data Ready Before BUSY↑
20
15
ns
ns
7
●
●
●
t
t
t
Delay Between Conversions
Wait Time RD↓ After BUSY↑
Data Access Time After RD↓
(Note 10)
40
ns
ns
8
–5
9
C = 25pF
L
15
20
35
45
45
60
ns
ns
ns
ns
10
●
●
C = 100pF
L
t
Bus Relinquish Time
8
30
35
40
ns
ns
ns
11
0°C ≤ T ≤ 70°C
●
●
A
–40°C ≤ T ≤ 85°C
A
t
t
t
RD Low Time
●
●
t
ns
ns
ns
12
13
14
10
CONVST High Time
50
Aperture Delay of Sample-and-Hold
–1.5
The
●
indicates specifications which apply over the full operating
Note 5: V = 5V, f
specified.
= 800kHz, t = t = 5ns unless otherwise
SAMPLE r f
DD
temperature range; all other limits and typicals T = 25°C.
A
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended +A input with –A grounded.
IN
IN
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 3: When these pin voltages are taken below V or above V , they
SS
DD
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V or above V without latch-up.
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
SS
DD
Note 4: When these pin voltages are taken below V they will be clamped
by internal diodes. This product can handle input currents greater than
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
SS
100mA below V without latchup. These pins are not clamped to V
.
SS
DD
4
LTC1409
W U
TI I G CHARACTERISTICS
Note 11: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 650ns after
conversion start or after BUSY rises.
Note 12: Signal-to-noise ratio (SNR) is measured at 100kHz and distortion
is measured at 400kHz. These results are used to calculate signal-to-noise
plus distortion (SINAD).
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
S/(N + D) vs Input Frequency
and Amplitude
Signal-to-Noise Ratio vs
Input Frequency
Distortion vs Input Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
V
= 0dB
IN
IN
V
= 20dB
3RD
V
= 60dB
10k
IN
THD
2ND
1M
1k
10k
100k
10M
1k
100k
1M
10M
1k
10k
100k
1M
10M
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
LTC1409 • TPC03
LTC1409 • TPC01
LTC1409 • TPC02
Spurious-Free Dynamic Range vs
Input Frequency
Intermodulation Distortion Plot
0
–20
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
f
f
f
= 800kHz
= 88.19580078kHz
= 111.9995117kHz
SAMPLE
IN1
IN2
–40
–60
fb – fa
2fa + fb
fa + fb
fa + 2fb
3fb
3fa
2fa – fb
2fb – fa
2fa
–80
2fb
–100
–120
0
50k
100k
150k
200k
FREQUENCY (Hz)
250k
300k
350k
400k
10k
100k
1M
10M
INPUT FREQUENCY (Hz)
LTC1409 • TPC04
LTC1409 • TPC05
5
LTC1409
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity vs
Output Code
Differential Nonlinearity vs
Output Code
1.00
1.00
0.50
0
0.50
0
–0.50
–1.00
–0.50
–1.00
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
LT1409 • TPC07
LT1409 • TPC06
Power Supply Feedthrough vs
Ripple Frequency
Input Common Mode Rejection vs
Input Frequency
80
70
60
50
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
DGND
V
DD
V
SS
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
INPUT FREQUENCY (Hz)
RIPPLE FREQUENCY (Hz)
LTC1409 • TPC08
LT1409 • TPC09
U U
U
PI FU CTIO S
D3 to D0 (Pins 15 to 18): Three-State Data Outputs.
+A (Pin 1): Positive Analog Input, ±2.5V.
IN
OGND (Pin 19): Digital Ground for Output Drivers. Tie
–A (Pin 2): Negative Analog Input, ±2.5V.
IN
to AGND.
V
(Pin 3): 2.50V Reference Output.
REF
NAP/SLP (Pin 20): Power Shutdown Mode. Selects the
mode invoked by the SHDN pin. Low selects Sleep
mode and high selects quick wake-up Nap mode.
SHDN (Pin 21): Power Shutdown Input. A low logic
level will invoke the Shutdown mode selected by the
NAP/SLP pin.
REFCOMP (Pin 4): 4.06V Reference Output. Bypass to
AGND using 10µF tantalum in parallel with 0.1µF or
10µF ceramic.
AGND (Pin 5): Analog Ground.
D11 to D4 (Pins 6 to 13): Three-State Data Outputs.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
RD (Pin 22): Read Input. This enables the output
drivers when CS is low.
6
LTC1409
U U
U
PI FU CTIO S
CONVST (Pin 23):Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
V
(Pin 26): –5V Negative Supply. Bypass to AGND
SS
using 10µF tantalum in parallel 0.1µF or 10µF ceramic.
CS (Pin 24): Chip Select. The input must be low for the OV (Pin 27): Positive Supply for Output Drivers. For
DD
ADC to recognize CONVST and RD inputs.
BUSY (Pin 25): The BUSY output shows the converter
5V logic, short to Pin 28. For 3V logic, short to supply
of the logic being driven.
status. It is low when a conversion is in progress. Data AV (Pin 28): 5V Positive Supply. Bypass to AGND
DD
valid on the rising edge of BUSY.
10µF tantalum in parallel with 0.1µF or 10µF ceramic.
U
U
W
FU CTIO AL BLOCK DIAGRA
C
SAMPLE
SAMPLE
+A
IN
AV
DD
C
–A
V
IN
4k
ZEROING SWITCHES
2.5V REF
REF
+
REF AMP
COMP
12-BIT CAPACITIVE DAC
–
OV
DD
REFCOMP
(4.06V)
12
D11
D0
SUCCESSIVE APPROXIMATION
REGISTER
•
•
•
OUTPUT LATCHES
AGND
DGND
OGND
INTERNAL
CLOCK
CONTROL LOGIC
LTC1409 • BD
NAP/SLP SHDN RD CONVST CS BUSY
TEST CIRCUITS
Load Circuits for Bus Relinquish Time
Load Circuits for Access Timing
5V
5V
1k
1k
DBN
DBN
DBN
DBN
1k
C
L
C
L
1k
100pF
100pF
LTC1409 • TC01
LTC1409 • TC02
(a) Hi-Z to VOH
and VOL to VOH
(b) Hi-Z to VOL
and VOH to VOL
(a) VOH to Hi-Z
(b) VOL to Hi-Z
7
LTC1409
U
W U U
APPLICATIONS INFORMATION
differential capacitive DAC. Bit decisions are made by the
high speed comparator. At the end of a conversion, the
differential DACs output balances the +AIN and –AIN input
charges. The SAR contents (a 12-bit data word) which
represents the difference of +AIN and –AIN are loaded into
the 12-bit output latches.
CONVERSION DETAILS
The LTC1409 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
DYNAMIC PERFORMANCE
The LTC1409 has excellent high speed sampling capabil-
ity. FFT (Fast Four Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. Figure 2 shows typical
LTC1409 plots.
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 12-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). Referring to Figure 1, the +AIN and –AIN inputs are
0
connected to the sample-and-hold capacitors (CSAMPLE
)
f
f
= 800kHz
SAMPLE
= 97.45kHz
IN
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum delay of 150ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
Duringtheconvertphasethecomparatorzeroingswitches
open, putting the comparator into compare mode. The
input switches connect the CSAMPLE capacitors to ground,
transferring the differential analog input charge onto the
summingjunction. Thisinputchargeissuccessivelycom-
pared with the binary-weighted charges supplied by the
–20
–40
SFDR = 89.1dB
SINAD = 73.1dB
–60
–80
–100
–120
250 300
0
50 100 150 200
350 400
LT1409 • F02a
FREQUENCY (kHz)
Figure 2a. LTC1409 Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
+C
SAMPLE
+A
–A
IN
IN
HOLD
HOLD
0
ZEROING SWITCHES
HOLD
f
f
= 800kHz
SAMPLE
IN
–C
SAMPLE
= 375kHz
–20
–40
SFDR = 89dB
SINAD = 72.5dB
HOLD
+C
DAC
–60
+
–C
DAC
COMP
–80
+V
DAC
–
–100
–120
–V
DAC
12
D11
D0
OUTPUT
LATCHES
•
•
•
SAR
250 300
0
50 100 150 200
350 400
FREQUENCY (kHz)
LT1409 • F02b
LTC1409 • F01
Figure 2b. LTC1409 Nonaveraged, 4096 Point FFT,
Input Frequency = 375kHz
Figure 1. Simplified Block Diagram
8
LTC1409
U
W U U
APPLICATIONS INFORMATION
Signal-to-Noise Ratio
2
2
2
2
V2 + V3 + V4 +…Vn
THD = 20 Log
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure 2 shows a typical spectral content with
an800kHzsamplingrateanda100kHzinput. Thedynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 400kHz.
V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through Nth harmonics. THD vs inputfrequency is
shown in Figure 4. The LTC1409 has good distortion
performance up to the Nyquist frequency and beyond.
0
–10
–20
–30
–40
–50
–60
–70
Effective Number of Bits
TheEffectiveNumberofBits(ENOBs)isameasurementof
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
3RD
–80
–90
THD
N = [S/(N + D) – 1.76]/6.02
2ND
1M
–100
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 800kHz the LTC1409 maintains near ideal ENOBs
up to the Nyquist input frequency of 400kHz. Refer to
Figure 3.
1k
10k
100k
10M
INPUT FREQUENCY (Hz)
LTC1409 • F04
Figure 4. Distortion vs Input Frequency
Intermodulation Distortion
12
11
10
9
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
8
7
6
5
4
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the DC transfer function
can create distortion products at the sum and difference
frequencies of mfa + –nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa + fb). If
the two input sine waves are equal in magnitude, the value
(in decibels) of the 2nd order IMD products can be
expressed by the following formula:
3
2
1
0
f
= 800kHz
10k
SAMPLE
1k
100k
1M
10M
INPUT FREQUENCY (Hz)
LTC1409 • F03
Figure 3. Effective Bits and Signal/(Noise +
Distortion) vs Input Frequency
Total Harmonic Distortion
Amplitude at (fa + fb)
IMD fa + fb = 20 Log
(
)
Amplitude at fa
TotalHarmonicDistortion(THD)istheratiooftheRMSsum
ofallharmonicsoftheinputsignaltothefundamentalitself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
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LTC1409
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0
f
f
f
= 800kHz
= 88.19580078kHz
= 111.9995117kHz
SAMPLE
IN1
IN2
–20
–40
–60
fb – fa
2fa + fb
fa + fb
fa + 2fb
3fb
3fa
2fa – fb
–80
2fb – fa
2fa
2fb
–100
–120
0
50k
100k
150k
200k
FREQUENCY (Hz)
250k
300k
350k
400k
LTC1409 • F05
Figure 5. Intermodulation Distortion Plot
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
minimum acquisition time, with high source impedance,
a buffer amplifier should be used. The only requirement
is that the amplifier driving the analog input(s) must
settleafterthesmallcurrentspikebeforethenextconver-
sion starts (settling time must be 150ns for full through-
put rate).
Full Power and Full Linear Bandwidth
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
10
The full linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1409 has been designed to optimize input bandwidth,
allowing the ADC to undersample input signals with fre-
quencies above the converter’s Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
1
0.1
0.01
1
10
100
0.01
0.1
Driving the Analog Input
SOURCE RESISTANCE (kΩ)
LTC1409 • F06
The differential analog inputs of the LTC1409 are easy to
drive. The inputs may be driven differentially or as a
single-ended input (i.e., the –AIN input is grounded). The
+AIN and –AIN inputs are sampled at the same instant.
Any unwanted signal that is common mode to both
inputs will be reduced by the common mode rejection of
the sample-and-hold circuit. The inputs draw only one
small current spike while charging the sample-and-hold
capacitors at the end of conversion. During conversion
theanaloginputsdrawonlyasmallleakagecurrent. Ifthe
source impedance of the driving circuit is low then the
LTC1409 inputs can be driven directly. As source imped-
ance increases so will acquisition time (see Figure 6). For
Figure 6. Acquisition Time vs Source Resistance
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a
low output impedance (<100Ω) atthe closed-loop band-
width frequency. For example, if an amplifier is used in a
gain of 1 and has a unity-gain bandwidth of 50MHz, then
the output impedance at 50MHz should be less than
100Ω. The second requirement is that the closed-loop
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A
bandwidth must be greater than 20MHz to ensure
adequate small-signal settling for full throughput rate. If
slower op amps are used, more settling time can be
provided by increasing the time between conversions.
width of the sample-and-hold circuit is 20MHz. Any noise
ordistortionproductsthatarepresentattheanaloginputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For example, Figure 7 shows a 1000pF
capacitorfrom+AIN togroundanda100Ω sourceresistor
to limit the input bandwidth to 1.6MHz. The 1000pF
capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sam-
pling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors
have excellent linearity. Carbon surface mount resistors
can also generate distortion from self heating and from
damage that may occur during soldering. Metal film
surface mount resistors are much less susceptible to both
problems.
The best choice for an op amp to drive the LTC1409 will
dependontheapplication. Generallyapplicationsfallinto
two categories: AC applications where dynamic specifi-
cations are most critical, and time domain applications
where DC accuracy and settling time are most critical.
The following list is a summary of the op amps that are
suitable for driving the LTC1409, more detailed informa-
tion is available in the Linear Technology databooks and
the LinearViewTM CD-ROM.
LT ® 1220: 30MHz unity-gain bandwidth voltage feed-
back amplifier. ±5V to ±15V supplies. Excellent DC
specifications, 90ns settling to 0.5LSB.
LT1223: 100MHz video current feedback amplifier. 6mA
supply current. ±5V to ±15V supplies. Low distortion up
to and above 400kHz. Low noise. Good for AC
applications.
When high amplitude unwanted signals are close in fre-
quency to the desired signal frequency, a multiple pole filter
50Ω
1
2
3
4
5
ANALOG INPUT
+A
IN
LT1227:140MHzvideocurrentfeedbackamplifier.10mA
supply current ±5V to ±15V supplies. Lowest distortion
at frequencies above 400kHz. Low noise. Best for AC
applications.
1000pF
–A
IN
LTC1409
V
REF
LT1229/LT1230: Dual and quad 100MHz current feed-
back amplifiers. ±2V to ±15V supplies. Low noise. Good
AC specs. 6mA supply current for each amplifier.
REFCOMP
AGND
10µF
LT1360: 37MHz voltage feedback amplifier. 3.8mA sup-
ply current. Good AC/DC specs. ±5V to ±15V supplies.
70ns settling to 0.5LSB.
LTC1409 • F07b
Figure 7a. RC Input Filter
LT1363: 50MHz, 450V/µs op amps. 6.3mA supply cur-
1
2
8
7
6
1
2
3
4
rent. Good AC/DC specs. 60ns settling to 0.5LSB.
+A
IN
LT1364/LT1365: Dual and quad 50MHz, 450V/µs op
amps. 6.3mA supply current per amplifier. 60ns settling
to 0.5LSB.
V
IN
–A
IN
LTC1560-1
3
LTC1409
V
REF
4
5
–5V
5V
Input Filtering
REFCOMP
AGND
0.1µF
0.1µF
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1409 noise and distortion. The small-signal band-
LinearView is a trademark of Linear Technology Corporation.
10µF
5
LTC1409 • F07
Figure 7b. 500kHz 5th Order Elliptic Lowpass Filter
11
LTC1409
PPLICATI
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a LTC1560 5th order elliptic continuous time filter.
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1
2
3
4
5
+A
IN
5V
ANALOG INPUT
–A
IN
V
IN
Input Range
LTC1409
LT1019A-2.5
V
OUT
V
REF
The±2.5VinputrangeoftheLTC1409isoptimizedforlow
noise and low distortion. Most op amps also perform best
over this same range, allowing direct coupling to the
analog inputs and eliminating the need for special transla-
tion circuitry.
REFCOMP
AGND
10µF
LTC1409 • F08b
Some applications may require other input ranges. The
LTC1409 differential inputs and reference circuitry can ac-
commodate other input ranges often with little or no addi-
tionalcircuitry. Thefollowingsectionsdescribethereference
and input circuitry and how they affect the input range.
Figure 8b. Using the LT1019-2.5 as an External Reference
The VREF pin can be driven with a DAC or other means
shown in Figure 9. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1409 reference amplifier will limit the
bandwidth and settling time of this circuit. A settling time
of 5ms should be allowed for, after a reference adjust-
ment.
Internal Reference
The LTC1409 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmedto2.500V.Itisconnectedinternallytoareference
amplifier and is available at VREF (Pin 3) see Figure 8a. A
4k resistor is in series with the output so that it can be
easily overdriven by an external reference or other cir-
cuitry.ThereferenceamplifiergainsthevoltageattheVREF
pin by 1.625 to create the required internal reference
voltage. This provides buffering between the VREF pin and
the high speed capacitive DAC. The reference amplifier
compensation pin, REFCOMP (Pin 4), must be bypassed
with a capacitor to ground. The reference amplifier is
stable with capacitors of 1µF or greater. For the best noise
performance, a 10µF ceramic or 10µF tantalum in parallel
with 0.1µF ceramic is recommended (see Figure 8b).
1
+A
IN
ANALOG INPUT
2
–A
IN
LTC1409
LTC1450
12-BIT
RAIL-TO-RAIL DAC
3
4
5
1.25V TO 3V
V
REF
REFCOMP
AGND
10µF
LTC1409 • F09
Figure 9.Driving VREF with a DAC
R1
4k
V
BANGAP
3
4
REF
2.5V
Differential Inputs
REFERENCE
The LTC1409 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
convert the difference of +AIN – (–AIN) independent of the
common mode voltage. The common mode rejection
holds up to extremely high frequencies, see Figure 10a.
The only requirement is that both inputs can not exceed
the AVDD or AVSS power supply voltages. Integral
nonlinearity errors (INL) and differential nonlinearity er-
rors (DNL) are independent of the common mode voltage,
REFCOMP
REFERENCE
AMP
4.0625V
R2
40k
10µF
R3
64k
AGND
5
LTC1409
LTC1409 • F08a
Figure 8a. LTC1409 Reference Circuit
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80
70
60
50
40
30
20
10
The output is two’s complement binary with 1LSB =
FS – (–FS)/4096 = 5V/4096 = 1.22mV.
111...111
111...110
111...101
0
1
10
100
1000
10000
000...010
000...001
000...000
INPUT FREQUENCY (Hz)
LTC1409 • TPC09
Figure 10a. CMRR vs Input Frequency
–(FS – 1LSB)
FS – 1LSB
INPUT RANGE
1
LTC1409 • F11a
ANALOG INPUT
±2.5V RANGE
+A
IN
Figure 11a. LTC1409 Transfer Characteristics
2
–A
IN
LTC1409
0V TO 5V
RANGE
2.5V
1µF
3
4
5
V
REF
–5V
R3
1
2
3
4
5
ANALOG INPUT
+A
IN
24k
R1
50k
REFCOMP
AGND
R4
100Ω
10µF
–A
V
IN
LTC1409
R5 R2
47k 50k
LTC1409 • F10b
REF
Figure 10b. Selectable 0V to 5V or ±2.5V Input Range
R6
24k
REFCOMP
AGND
however,thebipolarzeroerror(BZE)willvary.Thechange
in BZE is typically less than 0.1% of the common mode
voltage. Dynamic performance is also affected by the
common mode voltage. THD will degrade as the inputs
approach either power supply rail, from 86dB with a
common mode of 0V to 75dB with a common mode of
2.5V or –2.5V.
10µF
LTC1409 • F11b
Figure 11b. Offset and Full-Scale Adjust Circuit
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 11b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the –AIN input. For zero offset error apply –
0.61mV (i.e., –0.5LSB) at +AIN and adjust the offset at the
–AIN input until the output code flickers between 0000
0000 0000 and 1111 1111 1111. For full-scale adjust-
ment, an input voltage of 2.49817V (FS/2 – 1.5LSBs) is
applied to AIN and R2 is adjusted until the output code
flickers between 0111 1111 1110 and 0111 1111 1111.
Differential inputs allow greater flexibility for accepting
different input ranges. Figure 10b shows a circuit that
converts a 0V to 5V analog input signal with no additional
translation circuitry.
Full-Scale and Offset Adjustment
Figure 11a shows the ideal input/output characteristics for
the LTC1409. The code transitions occur midway between
successive integer LSB values (i.e., –FS + 0.5LSB, –FS +
1.5LSB, –FS + 2.5LSB,. FS – 1.5LSB, FS – 0.5LSB).
13
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BOARD LAYOUT AND BYPASSING
The LTC1409 has differential inputs to minimize noise
coupling. Commonmodenoiseonthe+AIN and–AIN leads
will be rejected by the input CMRR. The –AIN input can be
used as a ground sense for the +AIN input; the LTC1409
will hold and convert the difference voltage between +AIN
and–AIN.Theleadsto+AIN (Pin1)and–AIN (Pin2)should
be kept as short as possible. In applications where this is
not possible, the +AIN and –AIN traces should be run side-
by-side to equalize coupling.
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1409, a printed circuit board
with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
linesareseparatedasmuchaspossible. Inparticular, care
should be taken not to run any digital track alongside an
analog signal track.
SUPPLY BYPASSING
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND), Pin 14 and Pin 19 (ADC’s DGND) and all
other analog grounds should be connected to this single
analog ground point. The REFCOMP bypass capacitor and
the OVDD bypass capacitor should also be connected to
this analog ground plane. No other digital grounds should
beconnectedtothisanaloggroundplane. Lowimpedance
analog and digital power supply common returns are
essential to low noise operation of the ADC and the foil
width for these tracks should be as wide as possible. In
applications where the ADC data outputs and control
signals are connected to a continuously active micropro-
cessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation com-
parator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversion or by
using three-state buffers to isolate the ADC data bus. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
High quality, low series resistance ceramic, 10µF bypass
capacitors should be used at the VDD and REFCOMP pins
asshownintheTypicalApplicationonthefirstpageofthis
data sheet. Surface mount ceramic capacitors such as
Murata GRM235Y5V106Z016 provide excellent bypass-
ing in a small board space. Alternatively 10µF tantalum
capacitorsinparallelwith0.1µFceramiccapacitorscanbe
used. Bypass capacitors must be located as close to the
pins as possible. The traces connecting the pins and
bypass capacitors must be kept short and should be made
as wide as possible.
Example Layout
Figure 13a, 13b, 13c and 13d show the schematic and
layoutofasuggestedevaluationboard.Thelayoutdemon-
stratestheproperuseofdecouplingcapacitorsandground
plane with a two layer printed circuit board.
1
DIGITAL
SYSTEM
LTC1409
+A
IN
–A
IN
REFCOMP AGND
V
AV
OV
DGND OGND
+
–
DD
DD
27
SS
ANALOG
INPUT
CIRCUITRY
2
4
5
26
28
14
19
LTC1409 • F12
+
+
+
10µF
0.1µF
10µF
0.1µF
10µF
0.1µF
ANALOG GROUND PLANE
Figure 12. Power Supply Grounding Practice
14
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Figure 13b. Suggested Evaluation Circuit Board Component Side Silkscreen
Figure 13c. Suggested Evaluation Circuit Board Component Side Layout
16
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Figure 13d. Suggested Evaluation Circuit Board Solder Side Layout
Digital Interface
from Nap to active is 200ns. In Sleep mode all bias
currents are shut down and only leakage current re-
mains, about 1µA. Wake-up time from Sleep mode is
much slower since the reference circuit must power up
and settle to 0.01% for full 12-bit accuracy. Sleep mode
wake-up time is dependent on the value of the capacitor
connected to the REFCOMP (Pin 4). The wake-up time is
10ms with the recommended 10µF capacitor.
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a con-
version.
Internal Clock
Shutdown is controlled by Pin 21 (SHDN). The ADC is in
shutdown when it is low. The Shutdown mode is selected
with Pin 20 (NAP/SLP); high selects Nap.
The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 0.9µs, and a maximum conversion time over the
full operating temperature range of 1.15µs. No external
adjustments are required. The guaranteed maximum ac-
quisition time is 150ns. In addition, a throughput time of
1250nsandaminimumsamplerateof800kspsisguaran-
teed.
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A logic “0”
appliedtotheCONVSTpinwillstartaconversionafterthe
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY
is low during a conversion.
Power Shutdown
TheLTC1409providestwopowerShutdownmodes,Nap
and Sleep, to save power during inactive periods. The
Nap mode reduces the power by 95% and leaves only the
digitallogicandreferencepoweredup. Thewake-uptime
Figures 16 through 20 show several different modes of
operation. In modes 1a and 1b (Figures 16 and 17) CS and
RDarebothtiedlow.ThefallingedgeofCONVSTstartsthe
conversion. The data outputs are always enabled and data
17
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can be latched with the BUSY rising edge. Mode 1a shows
operationwithanarrowlogiclowCONVSTpulse. Mode1b
shows a narrow logic high CONVST pulse.
NAP/SLP
t
3
SHDN
In mode 2 (Figure 18) CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the RD signal.
Mode 2 can be used for operation with a shared MPU
databus.
LTC1409 • F14a
Figure 14a. NAP/SLP to SHDN Timing
In slow memory and ROM modes (Figures 19 and 20) CS
istiedlowandCONVSTandRDaretiedtogether. TheMPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
SHDN
t
4
CONVST
LTC1409 • F14b
Figure 14b. SHDN to CONVST Wake-Up Timing
In slow memory mode the processor applies a logic low to
RD (= CONVST) starting the conversion. BUSY goes low
forcing the processor into a WAIT state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results ap-
pear on the data outputs; BUSY goes high releasing the
processor, and the processor takes RD (= CONVST) back
high and reads the new conversion data.
CS
t
2
CONVST
RD
t
1
In ROM mode, the processor takes RD (= CONVST) low,
startingaconversionandreadingthepreviousconversion
result. Aftertheconversioniscomplete, theprocessorcan
read the new result and initiate another conversion.
LTC1409 • F15
Figure 15. CS to CONVST Setup Timing
t
CONV
t
5
CONVST
BUSY
t
t
8
6
t
7
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
LTC1409 • F16
DATA
Figure 16. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
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A
t
CS = RD = 0
CONV
t
13
t
5
CONVST
BUSY
t
t
8
6
t
6
t
7
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
DATA
LTC1409 • F17
Figure 17. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
t
13
t
t
8
CONV
t
5
CONVST
BUSY
RD
t
6
t
t
11
9
t
12
t
10
DATA N
DB11 TO DB0
DATA
LTC1409 • F18
Figure 18. Mode 2. CONVST Starts a Conversion. Data is Read by RD
t
t
8
CONV
RD = CONVST
t
6
t
11
BUSY
DATA
t
t
7
10
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
LTC1409 • F19
Figure 19. Slow Memory Mode Timing
t
t
8
CONV
RD = CONVST
BUSY
t
t
11
6
t
10
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB0
DATA
LTC1409 • F20
Figure 20. ROM Mode Timing
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PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.397 – 0.407*
(10.07 – 10.33)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
0.205 – 0.212**
(5.20 – 5.38)
0.068 – 0.078
(1.73 – 1.99)
0.301 – 0.311
(7.65 – 7.90)
0° – 8°
0.0256
(0.65)
BSC
0.005 – 0.009
(0.13 – 0.22)
0.022 – 0.037
(0.55 – 0.95)
0.002 – 0.008
0.010 – 0.015
(0.05 – 0.21)
*
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
1
2
3
4
5
6 8
7
9 10 11 12 13 14
(0.25 – 0.38)
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
G28 SSOP 0694
SW Package
28-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.697 – 0.712*
(17.70 – 18.08)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
0.291 – 0.299**
(7.391 – 7.595)
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029
(0.254 – 0.737)
× 45°
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0° – 8° TYP
0.050
(1.270)
TYP
0.004 – 0.012
(0.102 – 0.305)
0.009 – 0.013
NOTE 1
(0.229 – 0.330)
0.014 – 0.019
0.016 – 0.050
(0.406 – 1.270)
2
3
5
7
8
9
10 11 12 13 14
1
4
6
(0.356 – 0.482)
TYP
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
S28 (WIDE) 0996
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PRODUCTS
PART NUMBER
LTC1273/75/76
LTC1274/77
LTC1278/79
LTC1282
DESCRIPTION
COMMENTS
300ksps, Single or Dual Supplies
Complete 5V Sampling 12-Bit ADCs with 70dB SINAD at Nyquist
Low Power 12-Bit ADCs with Nap and Sleep Mode Shutdown
High Speed Sampling 12-Bit ADCs with Shutdown
Complete 3V 12-Bit ADC with 12mW Power Dissipation
High Speed Sampling 12-Bit ADC
100ksps, 8-Bit or 12-Bit Digital I/O
500ksps/600ksps, Single or Dual Supplies
Fully Specified for 3V/±3V Supply
LTC1410
1.25Msps, 71dB SINAD at Nyquist, Low Power
1.25Msps, Single 5V Supply, Lowest Power
81.5dB SINAD, 150mW from ±5V Supplies
Single Supply, ±10V Input Range, Low Power
LTC1415
High Speed Sampling 12-Bit ADC
LTC1419
14-Bit, 800ksps Sampling ADC
LTC1605
16-Bit, 100ksps Sampling ADC
1409f LT/TP 0397 7K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1995
Linear Technology Corporation
●
1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900
20
●
●
FAX: (408) 434-0507 TELEX: 499-3977 www.linear-tech.com
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