LTC1412IG#TRPBF [Linear]
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| 型号： | LTC1412IG#TRPBF |
| 厂家： | 
Linear |
| 描述： | 暂无描述 |
| 文件： | 总18页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2356-12/LTC2356-14
Serial 12-Bit/14-Bit, 3.5Msps
Sampling ADCs with Shutdown
FEATURES
DESCRIPTION
TheLTC®2356-12/LTC2356-14are12-bit/14-bit, 3.5Msps
n
3.5Msps Conversion Rate
n
74.1dB SINAD at 14-Bits, 71.1dB SINAD at 12-Bits
Low Power Dissipation: 18mW
serial ADCs with differential inputs. The devices draw
only 5.5mA from a single 3.3V supply and come in a
tiny 10-lead MSOP package. A Sleep shutdown feature
further reduces power consumption to 13µW. The com-
bination of speed, low power and tiny package makes the
LTC2356-12/LTC2356-14suitableforhighspeed,portable
applications.
n
n
n
n
n
n
n
n
n
3.3V Single Supply Operation
2.5V Internal Bandgap Reference can be Overdriven
3-Wire SPI-Compatible Serial Interface
Sleep (13µW) Shutdown Mode
Nap (4mW) Shutdown Mode
80dB Common Mode Rejection
The80dBcommonmoderejectionallowsuserstoeliminate
ground loops and common mode noise by measuring
signals differentially from the source.
1.25V Bipolar Input Range
Tiny 10-Lead MSOP Package
The devices convert –1.25V to 1.25V bipolar inputs
APPLICATIONS
+
differentially. The absolute voltage swing for A
and
IN
–
n
A
extends from ground to the supply voltage.
Communications
IN
n
Data Acquisition Systems
Theserialinterfacesendsouttheconversionresultsduring
the 16 clock cycles following a CONV rising edge for com-
patibility with standard serial interfaces. If two additional
clock cycles for acquisition time are allowed after the data
stream in between conversions, the full sampling rate of
3.5Msps can be achieved with a 63MHz clock.
n
Uninterrupted Power Supplies
n
Multiphase Motor Control
n
Multiplexed Data Acquisition
n
RFID
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
BLOCK DIAGRAM
10µF 3.3V
THD, 2nd and 3rd vs Input Frequency
for Differential Input Signals
–50
7
V
LTC2356-14
DD
–56
+
–
THREE-
STATE
SERIAL
OUTPUT
PORT
A
A
–62
IN
IN
1
2
+
THD
2nd
3rd
14-BIT ADC
SDO
–68
–74
–80
–86
–92
S & H
8
–
14
V
REF
3
4
10
9
CONV
SCK
2.5V
REFERENCE
TIMING
LOGIC
10µF
GND
5
–98
–104
2356 BD
6
11
0.1
1
10
100
EXPOSED PAD
FREQUENCY (MHz)
2356 G02
2356fb
1
LTC2356-12/LTC2356-14
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
TOP VIEW
+
–
Supply Voltage (V )..................................................4V
DD
A
A
1
2
3
4
5
10 CONV
IN
IN
9
8
7
6
SCK
SDO
DD
GND
Analog and V
Input Voltages
REF
V
11
REF
GND
GND
(Note 3) ....................................–0.3V to (V + 0.3V)
V
DD
Digital Input Voltages................... – 0.3V to (V + 0.3V)
DD
MSE PACKAGE
10-LEAD PLASTIC MSOP
Digital Output Voltage...................–0.3V to (V + 0.3V)
DD
T
= 125°C, θ = 40°C/W
Power Dissipation...............................................100mW
JMAX
JA
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
Operation Temperature Range
LTC2356C-12/LTC2356C-14..................... 0°C to 70°C
LTC2356I-12/LTC2356I-14 ...................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2356CMSE-12#PBF
LTC2356IMSE-12#PBF
LTC2356CMSE-14#PBF
LTC2356IMSE-14#PBF
LTC2356CMSE-12#TRPBF LTCWN
LTC2356IMSE-12#TRPBF LTCWN
LTC2356CMSE-14#TRPBF LTCVF
LTC2356IMSE-14#TRPBF LTCVF
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With internal reference. VDD = 3.3V.
LTC2356-12
TYP
LTC2356-14
TYP
PARAMETER
CONDITIONS
MIN
12
MAX
MIN
14
MAX
UNITS
Bits
l
l
l
l
Resolution (No Missing Codes)
Integral Linearity Error
Offset Error
(Notes 4, 5, 18)
(Notes 4, 18)
(Note 4, 18)
–2
0.25
1
2
–4
0.5
2
4
LSB
–10
–40
10
40
–30
–80
30
80
LSB
Gain Error
5
10
LSB
Gain Tempco
Internal Reference (Note 4)
External Reference
15
1
15
1
ppm/°C
ppm/°C
2356fb
2
LTC2356-12/LTC2356-14
ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. With internal reference. VDD = 3.3V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
V
Analog Differential Input Range (Notes 3, 8, 9) 3.1V ≤ V ≤ 3.6V
–1.25 to 1.25
V
V
IN
DD
Analog Common Mode + Differential
Input Range (Note 10)
0 to V
CM
DD
l
l
I
Analog Input Leakage Current
1
µA
pF
ns
ns
ps
IN
C
Analog Input Capacitance
(Note 19)
(Note 6)
13
IN
t
t
t
Sample-and-Hold Acquisition Time
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Analog Input Common Mode Rejection Ratio
39
ACQ
AP
1
0.3
JITTER
CMRR
f
IN
f
IN
= 1MHz, V = 0V to 3V
= 100MHz, V = 0V to 3V
–60
–15
dB
dB
IN
IN
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C with external reference = 2.55V. VDD = 3.3V. Single-ended AIN+ signal drive with AIN– = 1.5V
+
–
DC. Differential signal drive with VCM = 1.5V at AIN and AIN
LTC2356-12
TYP
LTC2356-14
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
SINAD
Signal-to-Noise Plus 100kHz Input Signal (Note 19)
71.1
71.1
74.1
72.3
dB
dB
l
l
Distortion Ratio
1.4MHz Input Signal (Note 19)
68
70
THD
Total Harmonic
Distortion
100kHz First 5 Harmonics (Note 19)
1.4MHz First 5 Harmonics (Note 19)
–86
–82
–86
–82
dB
dB
–76
–78
SFDR
IMD
Spurious Free
100kHz Input Signal (Note 19)
1.4MHz Input Signal (Note 19)
86
82
86
82
dB
dB
Dynamic Range
Intermodulation
Distortion
0.625V to 1.4MHz Summed with 0.625V
–82
–82
dB
P-P
P-P
+
–
1.56MHz into A and Inverted into A
IN
IN
Code-to-Code
Transition Noise
V
REF
= 2.5V (Note 18)
0.25
1
LSB
RMS
Full Power Bandwidth
V
= 2.5V , SDO = 11585LSB (Note 15)
50
5
50
5
MHz
MHz
IN
P-P
P-P
Full Linear Bandwidth S/(N + D) ≥ 68dB
INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3.3V.
PARAMETER
CONDITIONS
I = 0
OUT
MIN
TYP
2.5
15
MAX
UNITS
V
V
V
V
V
V
Output Voltage
Output Tempco
Line Regulation
Output Resistance
Settling Time
REF
REF
REF
REF
REF
ppm/°C
µV/V
Ω
V
= 3.1V to 3.6V, V = 2.5V
600
0.2
2
DD
REF
Load Current = 0.5mA
= 10µF
C
ms
REF
External V Input Range
2.55
V
DD
V
REF
2356fb
3
LTC2356-12/LTC2356-14
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3.3V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
V
= 3.6V
= 3.1V
2.4
V
V
IH
IL
DD
DD
IN
0.6
10
I
= 0V to V
µA
pF
V
IN
DD
C
V
V
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
5
IN
l
V
DD
= 3.3V, I
= –200µA
2.5
2.9
OH
OL
OUT
V
DD
V
DD
= 3.1V, I = 160µA
= 3.1V, I
0.05
0.10
V
V
OUT
OUT
l
l
= 1.6mA
0.4
10
I
OZ
Hi-Z Output Leakage D
V
= 0V to V
DD
µA
pF
OUT
OUT
C
Hi-Z Output Capacitance D
1
OZ
OUT
I
I
Output Short-Circuit Source Current
Output Short-Circuit Sink Current
V
V
= 0V, V = 3.3V
20
15
mA
mA
SOURCE
SINK
OUT
DD
= V = 3.3V
OUT
DD
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 17)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Supply Voltage
Supply Current
3.1
3.3
3.6
V
DD
l
l
I
DD
Active Mode
5.5
1.1
4
8
mA
mA
µA
Nap Mode
1.5
15
12
Sleep Mode (LTC2356-12)
Sleep Mode (LTC2356-14)
4
µA
P
D
Power Dissipation
Active Mode with SCK in Fixed State (Hi or Lo)
18
mW
2356fb
4
LTC2356-12/LTC2356-14
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3.3V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
f
Maximum Sampling Rate per Channel
(Conversion Rate)
3.5
MHz
SAMPLE(MAX)
l
l
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Minimum Sampling Period (Conversion + Acquisiton Period)
Clock Period
286
ns
THROUGHPUT
(Note 16)
15.872
10000
ns
SCK
Conversion Time
(Note 6)
16
2
18
SCLK cycles
CONV
Minimum High or Low SCLK Pulse Width
CONV to SCK Setup Time
(Note 6)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
1
(Notes 6, 10)
(Note 6)
3
2
Nearest SCK Edge Before CONV
Minimum High or Low CONV Pulse Width
SCK↑ to Sample Mode
0
3
(Note 6)
4
4
(Note 6)
4
5
(Notes 6, 11)
(Notes 6, 7, 13)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 12)
(Note 14)
1.2
45
CONV↑ to Hold Mode
6
16th SCK↑ to CONV≠ Interval (Affects Acquisition Period)
Delay from SCK to Valid Data
7
8
6
8
SCK↑ to Hi-Z at SDO
9
Previous SDO Bit Remains Valid After SCK
2
10
12
V
Settling Time After Sleep-to-Wake Transition
2
REF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns)
because the 2.2ns delay through the sample-and-hold is subtracted from
the CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 2: All voltage values are with respect to GND.
Note 3: When these pins are taken below GND or above V , they will be
Note 13: The time period for acquiring the input signal is started by the
DD
clamped by internal diodes. This product can handle input currents greater
16th rising clock and it is ended by the rising edge of convert.
than 100mA below GND or greater than V without latchup.
DD
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load.
Note 4: Offset and full-gain specifications are measured for a single-ended
+
–
A
IN
input with A grounded and using the internal 2.5V reference.
IN
Note 15: The full power bandwidth is the frequency where the output code
Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
swing drops to 3dB with a 2.5V input sine wave.
P-P
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock.
Note 17: V = 3.3V, f
= 3.5Msps.
SAMPLE
DD
Note 18: The LTC2356-14 is measured and specified with 14-bit resolution
(1LSB = 152µV) and the LTC2356-12 is measured and specified with
12-bit resolution (1LSB = 610µV).
Note 19: The sampling capacitor at each input accounts for 4.1pF of the
input capacitance.
Note 8: The analog input range is defined for the voltage difference
+
–
–
between A and A . Performance is specified with A = 1.5V DC while
IN
IN
IN
+
driving A
.
IN
+
–
Note 9: The absolute voltage at A and A must be within this range.
IN
IN
Note 10: If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
2356fb
5
LTC2356-12/LTC2356-14
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 3.3V (LTC2356-14)
SINAD vs Input Frequency
THD, 2nd and 3rd vs Input Frequency
77
–50
74
71
68
65
62
59
56
–56
–62
–68
–74
–80
–86
–92
THD
2nd
3rd
53
50
–98
–104
0.1
1
10
100
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
2356 G01
2356 G02
SNR vs Input Frequency
SFDR vs Input Frequency
77
92
86
80
74
68
62
56
50
74
71
68
65
62
59
56
53
50
0.1
1
10
100
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
2356 G03
2356 G04
100kHz Sine Wave 8192 Point
FFT Plot
1.4MHz Sine Wave 8192 Point
FFT Plot
0
0
–10
–20
–10
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–100
–110
–120
0
500k 750k 1M 1.25M 1.5M 1.75M
FREQUENCY (Hz)
0
500k 750k 1M 1.25M 1.5M 1.75M
FREQUENCY (Hz)
250k
250k
2356 G05
2356 G06
2356fb
6
LTC2356-12/LTC2356-14
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 3.3V (LTC2356-14)
Differential Linearity vs Output Code
Integral Linearity vs Output Code
1.0
0.8
4
3
0.6
2
0.4
1
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1
–2
–3
–4
0
8192
12288
0
4096
8192
12288
16384
4096
16384
OUTPUT CODE
OUTPUT CODE
2356 G07
2356 G08
Differential and Integral Linearity
vs Conversion Rate
SINAD vs Conversion Rate, Input
Frequency = 1.4MHz
4
3
75
74
73
2
MAX INL
1
MAX DNL
MIN DNL
0
72
71
70
–1
–2
–3
–4
MIN INL
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
2.0 2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8 4.0
CONVERSION RATE (Msps)
CONVERSION RATE (Msps)
2356 G09
2356 G10
CMRR vs Frequency
2.5VP-P Power Bandwidth
12
0
–20
6
0
–40
–6
–12
–18
–60
–80
–24
–30
–36
–100
–120
1M
10M
100M
1G
100
10k
100k 1M
10M 100M
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
2356 G11
2356 G12
2356fb
7
LTC2356-12/LTC2356-14
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 3.3V (LTC2356-12 and LTC2356-14)
Internal Reference Voltage vs
Load Current
PSRR vs Frequency
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
2.4902
2.4900
2.4898
2.4896
2.4894
2.4892
2.4890
1
10
100
1k
10k 100k
1M
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (mA)
FREQUENCY (Hz)
2356 G13
2356 G14
VDD Supply Current vs
Conversion Rate
Internal Reference Voltage vs VDD
2.4902
2.4900
2.4898
2.4896
2.4894
2.4892
2.4890
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
2.6
2.8
3.0
3.2
(V)
3.4
3.6
0
0.5
1
1.5
2
2.5
3
3.5
4
V
CONVERSION RATE (Mps)
DD
2356 G15
2356 G16
2356fb
8
LTC2356-12/LTC2356-14
PIN FUNCTIONS
+
+
A
(Pin 1): Noninverting Analog Input. A operates
a solid analog ground plane with a 10µF ceramic capacitor
(or 10µF tantalum in parallel with 0.1µF ceramic). Keep in
mindthatinternalanalogcurrentsanddigitaloutputsignal
currents flow through this pin. Care should be taken to
place the 0.1µF bypass capacitor as close to Pins 6 and
7 as possible.
IN
IN
–
fully differentially with respect to A with a –1.25V to
IN
–
1.25V differential swing with respect to A and a 0V to
IN
V
DD
common mode swing.
–
–
A
(Pin 2): Inverting Analog Input. A operates fully
IN
IN
+
differentially with respect to A with a 1.25V to –1.25V
IN
+
differential swing with respect to A and a 0V to V
SDO (Pin 8): Three-State Serial Data Output. Each set
IN
DD
common mode swing.
of output data words represents the difference between
+
–
A
IN
and A analog inputs at the start of the previous
IN
V
(Pin 3): 2.5V Internal Reference. Bypass to GND
REF
conversion. The output format is 2’s complement.
and to a solid analog ground plane with a 10µF ceramic
capacitor(or10µFtantaluminparallelwith0.1µFceramic).
Can be overdriven by an external reference between 2.55V
SCK (Pin 9): External Clock Input. Advances the conver-
sion process and sequences the output data on the rising
edge. Responds to TTL (≤3.3V) and 3.3V CMOS levels.
One or more pulses wake from sleep.
and V .
DD
GND (Pins 4, 5, 6, 11): Ground and Exposed Pad. These
ground pins and the exposed pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
flow through these pins.
CONV(Pin10):ConvertStart.Holdstheanaloginputsignal
and starts the conversion on the rising edge. Responds
to TTL (≤3.3V) and 3.3V CMOS levels. Two CONV pulses
with SCK in fixed high or fixed low state start Nap mode.
Four or more CONV pulses with SCK in fixed high or fixed
low state start Sleep mode.
V
(Pin 7): 3.3V Positive Supply. This single power pin
DD
supplies 3.3V to the entire device. Bypass to GND and to
BLOCK DIAGRAM
10µF 3.3V
7
V
LTC2356-14
DD
+
–
THREE-
STATE
SERIAL
OUTPUT
PORT
A
A
IN
IN
1
2
+
14-BIT ADC
SDO
S & H
8
–
14
V
REF
3
4
10
9
CONV
SCK
2.5V
REFERENCE
TIMING
LOGIC
10µF
GND
5
2356 BD
6
11
EXPOSED PAD
2356fb
9
LTC2356-12/LTC2356-14
TIMING DIAGRAM
LTC2356-12 Timing Diagram
t
2
t
7
t
t
1
3
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
15
t
16
17
18
1
14
SCK
t
4
5
CONV
t
t
ACQ
6
INTERNAL
S/H STATUS
SAMPLE
HOLD
SAMPLE
HOLD
t
t
9
t
8
8
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
Hi-Z
Hi-Z
SDO
D0
X*
X*
2356 TD01
14-BIT DATA WORD
CONV
t
t
THROUGHPUT
*BITS MARKED "X" AFTER D0 SHOULD BE IGNORED.
LTC2356-14 Timing Diagram
t
2
t
7
t
t
1
3
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
15
t
16
17
18
1
14
SCK
t
4
5
CONV
t
t
6
ACQ
INTERNAL
S/H STATUS
SAMPLE
HOLD
SAMPLE
HOLD
t
t
9
t
8
8
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3
Hi-Z
Hi-Z
SDO
D2
D1
D0
2356 TD01b
14-BIT DATA WORD
CONV
t
t
THROUGHPUT
Nap Mode and Sleep Mode Waveforms
SCK
t
t
1
1
CONV
NAP
SLEEP
t
12
V
REF
2356 TD02
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS
SCK to SDO Delay
SCK
SCK
V
V
IH
IH
t
10
8
t
t
9
V
V
90%
10%
OH
OL
SDO
SDO
2356 TD03
2356fb
10
LTC2356-12/LTC2356-14
APPLICATIONS INFORMATION
DRIVING THE ANALOG INPUT
detailed information is available in the Linear Technology
Databooks and our website at www.linear.com.)
ThedifferentialanaloginputsoftheLTC2356-12/LTC2356-14
maybedrivendifferentiallyorasasingle-endedinput(i.e.,
LTC1566-1: Low Noise 2.3MHz Continuous Time Low-
Pass Filter.
–
theA inputissettoV ).Bothdifferentialanaloginputs,
IN
CM
+
–
A
and A , are sampled at the same instant. Any
LT®1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier.
IN
IN
unwanted signal that is common to both inputs of each
input pair will be reduced by the common mode rejec-
tion of the sample-and-hold circuit. The inputs draw
only one small current spike while charging the sample-
and-hold capacitors at the end of conversion. During
conversion, the analog inputs draw only a small leakage
current. If the source impedance of the driving circuit
is low, then the LTC2356-12/LTC2356-14 inputs can be
driven directly. As source impedance increases, so will
acquisition time. For minimum acquisition time with
high source impedance, a buffer amplifier must be used.
The main requirement is that the amplifier driving the
analog input(s) must settle after the small current spike
before the next conversion starts (settling time must be
39ns for full throughput rate). Also keep in mind while
choosing an input amplifier the amount of noise and
harmonic distortion added by the amplifier.
2.7V to 15V supplies. Very high A , 500µV offset and
VOL
520ns settling to 0.5LSB for a 4V swing. THD and noise
are –93dB to 40kHz and below 1LSB to 320kHz (A = 1,
V
2V into 1kΩ, V = 5V), making the part excellent for
P-P
S
AC applications (to 1/3 Nyquist) where rail-to-rail perfor-
mance is desired. Quad version is available as LT1631.
LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier.
2.7V to 15V supplies. Very high A , 1.5mV offset and
VOL
400ns settling to 0.5LSB for a 4V swing. It is suitable
for applications with a single 5V supply. THD and noise
are –93dB to 40kHz and below 1LSB to 800kHz (A = 1,
V
2V into 1kΩ, V = 5V), making the part excellent for
P-P
S
ACapplicationswhererail-to-railperformanceisdesired.
Quad version is available as LT1633.
LT1813: Dual 100MHz 750V/µs 3mA Voltage Feedback
Amplifier.5Vto 5Vsupplies.Distortionis–86dBto100kHz
and –77dB to 1MHz with 5V supplies (2V into 500Ω).
P-P
CHOOSING AN INPUT AMPLIFIER
Excellent part for fast AC applications with 5V supplies.
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude of
the voltage spike seen by the amplifier from charging the
samplingcapacitor,chooseanamplifierthathasalowoutput
impedance(<100Ω)attheclosed-loopbandwidthfrequency.
For example, if an amplifier is used with a gain of 1 and has a
unity-gainbandwidthof50MHz,thentheoutputimpedanceat
50MHz must be less than 100Ω. The second requirement is
thattheclosed-loopbandwidthmustbegreaterthan40MHz
to ensure adequate small-signal settling for full throughput
rate. If slower op amps are used, more time for settling can
be provided by increasing the time between conversions.
The best choice for an op amp to drive the LTC2356-12/
LTC2356-14 will depend on the application. Generally, ap-
plications fall into two categories: AC applications where
dynamic specifications are most critical and time domain
applications where DC accuracy and settling time are most
critical. The following list is a summary of the op amps that
are suitable for driving the LTC2356-12/LTC2356-14. (More
LT1801: 80MHz GBWP, –75dBc at 500kHz, 2mA/Amplifier,
8.5nV/√Hz.
LT1806/LT1807: 325MHz GBWP, –80dBc Distortion at
5MHz, Unity-Gain Stable, R-R In and Out, 10mA/Ampli-
fier, 3.5nV/√Hz.
LT1810:180MHzGBWP,–90dBcDistortionat5MHz,Unity-
Gain Stable, R-R In and Out, 15mA/Amplifier, 16nV/√Hz.
LT1818/LT1819: 400MHz, 2500V/µs,9mA, Single/Dual
Voltage Mode Operational Amplifier.
LT6200: 165MHz GBWP, –85dBc Distortion at 1MHz,
Unity-Gain Stable, R-R In and Out, 15mA/Amplifier,
0.95nV/√Hz.
LT6203: 100MHz GBWP, –80dBc Distortion at 1MHz,
Unity-Gain Stable, R-R In and Out, 3mA/Amplifier,
1.9nV/√Hz.
LT6600-10:Amplifier/FilterDifferentialIn/Outwith10MHz
Cutoff.
2356fb
11
LTC2356-12/LTC2356-14
APPLICATIONS INFORMATION
INPUT FILTERING AND SOURCE IMPEDANCE
inverting input. The 1.25V range is also ideally suited for
AC-coupled signals in single supply applications. Figure 2
shows how to AC couple signals in a single supply system
withoutneedingamid-supply1.5Vexternalreference.The
DC common mode level is supplied by the previous stage
that is already bounded by the single supply voltage of the
system. The common mode range of the inputs extend
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC2356-12/LTC2356-14 noise and distortion. The
small-signal bandwidth of the sample-and-hold circuit is
50MHz. Any noise or distortion products that are pres-
ent at the analog inputs will be summed over this entire
bandwidth. Noisy input circuitry should be filtered prior
to the analog inputs to minimize noise. A simple 1-pole
from ground to the supply voltage V . If the difference
DD
+
–
between the A
and A
inputs exceeds 1.25V, the
IN
IN
output code will stay fixed at zero and all ones and if this
difference goes below –1.25V, the output code will stay
fixed at one and all zeros.
RC filter is sufficient for many applications. For example,
+
Figure1showsa47pFcapacitorfromA togroundanda
IN
51Ωsourceresistortolimittheinputbandwidthto47MHz.
The 47pF capacitor also acts as a charge reservoir for the
input sample-and-hold and isolates the ADC input from
sampling-glitchsensitivecircuitry.Highqualitycapacitors
and resistors should be used since these components
can add distortion. NPO and silvermica type dielectric
capacitors have excellent linearity. Carbon surface mount
resistors can generate distortion from self heating and
from damage that may occur during soldering. Metal film
surface mount resistors are much less susceptible to both
problems.Whenhighamplitudeunwantedsignalsareclose
in frequency to the desired signal frequency, a multiple
pole filter is required. High external source resistance,
combined with the 13pF of input capacitance, will reduce
the rated 50MHz bandwidth and increase acquisition time
beyond 39ns.
C2
1µF
LTC2356-12/
R2
1.6k
LTC2356-14
1
2
3
R3
+
A
A
V
IN
51Ω
–
V
IN
IN
R1
1.6k
REF
+
C3
56pF
C1
C4
10µF
1µF
2356 F02
C1, C2: FILM TYPE
C3: COG TYPE
C4: CERAMIC BYPASS
Figure 2. AC Coupling of AC Signals with 1kHz
Low Cutoff Frequency
INTERNAL REFERENCE
TheLTC2356-12/LTC2356-14hasanon-chip,temperature
compensated, bandgap reference that is factory trimmed
to 2.5V to obtain a bipolar 1.25V input span. The refer-
51Ω
1
2
+
ence amplifier output V , (Pin 3) must be bypassed
A
A
V
REF
IN
47pF
with a capacitor to ground. The reference amplifier is
stable with capacitors of 1µF or greater. For the best noise
performance, a 10µF ceramic or a 10µF tantalum in paral-
V
–
CM
IN
1.5V DC
LTC2356-12/
LTC2356-14
REF
3
lel with a 0.1µF ceramic is recommended. The V
can be overdriven with an external reference as shown in
pin
REF
10µF
11
GND
2356 F01
3.5V TO 18V
Figure 1. RC Input Filter
3V
3
LT1790-3
V
REF
INPUT RANGE
LTC2356-12/
LTC2356-14
10µF
The analog inputs of the LTC2356-12/LTC2356-14 may be
driven fully differentially with a single supply. Each input
may swing up to 2.5V
11
GND
individually. When using the
P-P
2356 F03
internalreference, thenon-invertinginputshouldneverbe
more than 1.25V more positive or more negative than the
Figure 3. Overdriving VREF Pin with an External Reference
2356fb
12
LTC2356-12/LTC2356-14
APPLICATIONS INFORMATION
Figure 3. The voltage of the external reference must be
higher than the 2.5V output of the internal reference. The
recommended range for an external reference is 2.55V to
Figure 5 shows the ideal input/output characteristics for
the LTC2356-12/LTC2356-14. The code transitions occur
midway between successive integer LSB values (i.e.,
0.5LSB, 1.5LSB, 2.5LSB, FS – 1.5LSB). The output code
is 2’s complement with 1LSB = 2.5V/16384 = 153µV for
the LTC2356-14, and 1LSB = 2.5V/4096 = 610µV for the
LTC2356-12. The LTC2356-14 has 1LSB RMS of random
white noise. Figure 6a shows the LTC1819 converting a
single ended input signal to differential input signals for
optimum THD and SFDR performance as shown in the
FFT plot (Figure 6b).
V . An external reference at 2.55V will see a DC quiescent
DD
load of 0.75mA and as much as 3mA during conversion.
INPUT SPAN VERSUS REFERENCE VOLTAGE
The differential input range has a bipolar
V
/2
REF
voltage span that equals the difference between the
voltage at the reference buffer output V at Pin 3, and
REF
the voltage at the ground (Exposed Pad Ground). The
differential input range of the ADC is 1.25V when using
the internal reference. The internal ADC is referenced to
these two nodes. This relationship also holds true with
an external reference.
011...111
011...110
011...101
DIFFERENTIAL INPUTS
The LTC2356-12/LTC2356-14 have a unique differential
sample-and-holdcircuitthatmeasuresinputvoltagesfrom
100...010
100...001
100...000
ground to V . The ADC will always convert the bipolar
DD
+
–
difference of A – A , independent of the common
IN
IN
–FS
FS – 1LSB
mode voltage at the inputs. The common mode rejection
holds up at extremely high frequencies, see Figure 4. The
only requirement is that both inputs not go below ground
INPUT VOLTAGE (V)
2356 F05
Figure 5. LTC2356-12/LTC2356-14 Transfer Characteristic
or exceed V . Integral nonlinearity errors (INL) and dif-
DD
ferentialnonlinearityerrors(DNL)arelargelyindependent
of the common mode voltage. However, the offset error
will vary. The change in offset error is typically less than
0.1% of the common mode voltage.
5V
C5
0.1µF
0
C3
1µF
–
R1
–20
51Ω
U1
1
+
A
IN
1/2 LT1819
V
P-P
MAX
C1
IN
+
–40
1.25V
47pF TO
1000pF
C6
0.1µF
R5
1k
–60
R4
499Ω
R3
1.5V
LTC2356-14
CM
–5V
499Ω
–80
R6
1k
C4
1µF
–
–100
–120
R2
51Ω
U2
–
A
IN
1/2 LT1819
C2
47pF TO
1000pF
+
2356 F06a
100
10k
100k 1M
10M 100M
1k
FREQUENCY (Hz)
2356 F04
Figure 6a. The LT1819 Driving the LTC2356-14 Differentially
Figure 4. CMRR vs Frequency
2356fb
13
LTC2356-12/LTC2356-14
APPLICATIONS INFORMATION
0
–10
–20
V
BYPASS 0805 SIZE
REF
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
185k
371k
556k
741k
FREQUENCY (Hz)
2356 F06b
Figure 6b. LTC2356-12 6MHz Sine Wave 4096 Point FFT Plot
with the LT1819 Driving the Inputs Differentially
2356 F07
OPTIONAL INPUT FILTERING
V
DD
BYPASS 0805 SIZE
Board Layout and Bypassing
Figure 7. Recommended Layout
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performancefromtheLTC2356-12/LTC2356-14, aprinted
circuit board with ground plane is required. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track. If optimum phase match
between the inputs is desired, the length of the two input
wires should be kept matched.
and control signals are connected to a continuously ac-
tive microprocessor bus, it is possible to get errors in the
conversion results. These errors are due to feedthrough
fromthemicroprocessortothesuccessiveapproximation
comparator. The problem can be eliminated by forcing the
microprocessor into a Wait state during conversion or by
using three-state buffers to isolate the ADC data bus.
POWER-DOWN MODES
High quality tantalum and ceramic bypass capacitors
Upon power-up, the LTC2356-12/LTC2356-14 is initial-
ized to the active state and is ready for conversion. The
Nap and Sleep mode waveforms show the power-down
modes for the LTC2356-12/LTC2356-14. The SCK and
CONV inputs control the power-down modes (see Timing
Diagrams).TworisingedgesatCONV,withoutanyinterven-
ing rising edges at SCK, put the LTC2356-12/LTC2356-14
in Nap mode and the power consumption drops from
18mW to 4mW. The internal reference remains powered
in Nap mode. One or more rising edges at SCK wake up
the LTC2356-12/LTC2356-14 very quickly, and CONV
can start an accurate conversion within a clock cycle.
Four rising edges at CONV, without any intervening rising
edges at SCK, put the LTC2356-12/LTC2356-14 in Sleep
mode and the power consumption drops from 18mW
to 13µW. One or more rising edges at SCK wake up the
LTC2356-12/LTC2356-14foroperation. Theinternalrefer-
should be used at the V and V pins as shown in the
DD
REF
Block Diagram on the first page of this data sheet. For
optimum performance, a 10µF surface mount Tantalum
capacitor with a 0.1µF ceramic is recommended for the
V
and V
pins. Alternatively, 10µF ceramic chip
DD
REF
capacitors such as Murata GRM219R60J106M may
be used. The capacitors must be located as close to the
pins as possible. The traces connecting the pins and the
bypass capacitors must be kept short and should be made
as wide as possible.
Figure7showstherecommendedsystemgroundconnec-
tions. All analog circuitry grounds should be terminated
at the LTC2356-12/LTC2356-14 GND (Pins 4, 5, 6 and
exposed pad). The ground return from the LTC2356-
12/LTC2356-14 (Pins 4, 5, 6 and exposed pad) to the
power supply should be low impedance for noise free
operation. In applications where the ADC data outputs
ence (V ) takes 2ms to slew and settle with a 10µF load.
REF
2356fb
14
LTC2356-12/LTC2356-14
APPLICATIONS INFORMATION
Note that, using sleep mode more frequently than every
2ms, compromises the settled accuracy of the internal
reference. Note that, for slower conversion rates, the Nap
and Sleep modes can be used for substantial reductions
in power consumption.
Minimizing Jitter on the CONV Input
Inhighspeedapplicationswherehighamplitudesinewaves
above 100kHz are sampled, the CONV signal must have
as little jitter as possible (10ps or less). The square wave
output of a common crystal clock module usually meets
this requirement . The challenge is to generate a CONV
signalfromthiscrystalclockwithoutjittercorruptionfrom
other digital circuits in the system. A clock divider and
any gates in the signal path from the crystal clock to the
CONV input should not share the same integrated circuit
with other parts of the system. As shown in Figure 8, the
SCK and CONV inputs should be driven first, with digital
buffers used to drive the serial port interface. Also note
that the master clock in the DSP may already be corrupted
with jitter, even if it comes directly from the DSP crystal.
Another problem with high speed processor clocks is that
they often use a low cost, low speed crystal (i.e., 10MHz)
to generate a fast, but jittery, phase-locked-loop system
clock (i.e., 40MHz). The jitter in these PLL-generated high
speed clocks can be several nanoseconds. Note that if
you choose to use the frame sync signal generated by
the DSP port, this signal will have the same jitter of the
DSP’s master clock.
DIGITAL INTERFACE
The LTC2356-12/LTC2356-14 has a 3-wire SPI-compatible
(Serial Protocol Interface) interface. The SCK and CONV
inputs and SDO output implement this interface. The SCK
andCONVinputsacceptswingsfrom3.3VlogicandareTTL
compatible,ifthelogicswingdoesnotexceedV .Adetailed
DD
description of the three serial port signals follows.
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but subse-
quentrisingedgesatCONVareignoredbytheLTC2356-12/
LTC2356-14 until the following 16 SCK rising edges have
occurred. It is necessary to have a minimum of 16 rising
edges of the clock input SCK between rising edges of
CONV. But to obtain maximum conversion speed (with
a 63MHz SCK), it is necessary to allow two more clock
periods between conversions to allow 39ns of acquisition
time for the internal ADC sample-and-hold circuit. With 16
clock periods per conversion, the maximum conversion
rate is limited to 3.5Msps to allow 39ns for acquisition
time. In either case, the output data stream comes out
within the first 16 clock periods to ensure compatibility
with processor serial ports. The duty cycle of CONV can
be arbitrarily chosen to be used as a frame sync signal for
the processor serial port. A simple approach to generate
CONV is to create a pulse that is one SCK wide to drive the
LTC2356-12/LTC2356-14 and then buffer this signal with
the appropriate number of inverters to ensure the cor-
rect delay driving the frame sync input of the processor
serial port. It is good practice to drive the LTC2356-12/
LTC2356-14 CONV input first to avoid digital noise inter-
ference during the sample-to-hold transition triggered by
CONV at the start of conversion. It is also good practice
to keep the width of the low portion of the CONV signal
greater than 15ns to avoid introducing glitches in the front
end of the ADC just before the sample-and-hold goes into
hold mode at the rising edge of CONV.
The Typical Application Figure on page 16 shows a cir-
cuit for level-shifting and squaring the output from an
RF signal generator or other low-jitter source. A single
D-type flip flop is used to generate the CONV signal to
the LTC2356-12/LTC2356-14. Re-timing the master clock
signal eliminates clock jitter introduced by the controlling
device(DSP,FPGA,etc.)Boththeinverterandflipflopmust
be treated as analog components and should be powered
from a clean analog supply.
Serial Clock Input (SCK)
The rising edge of SCK advances the conversion process
and also udpates each bit in the SDO data stream. After
CONV rises, the third rising edge of SCK starts clocking
out the 12/14 data bits with the MSB sent first. A simple
approach is to generate SCK to drive the LTC2356-12/
LTC2356-14 first and then buffer this signal with the
appropriate number of inverters to drive the serial clock
input of the processor serial port. Use the falling edge of
the clock to latch data from the Serial Data Output (SDO)
2356fb
15
LTC2356-12/LTC2356-14
APPLICATIONS INFORMATION
into your processor serial port. The 14-bit serial data will
be received right justified, in a 16-bit word with 16 or
more clocks per frame sync. It is good practice to drive
the LTC2356-12/LTC2356-14 SCK input first to avoid digi-
tal noise interference during the internal bit comparison
decision by the internal high speed comparator. Unlike the
CONVinput, theSCKinputisnotsensitivetojitterbecause
the input signal is already sampled and held constant.
mode when it is not sending out data bits. Please note
the delay specification from SCK to a valid SDO. SDO is
always guaranteed to be valid by the next rising edge of
SCK. The 16-bit output data stream is compatible with the
16-bit or 32-bit serial port of most processors.
Loading on the SDO line must be minimized. SDO can
directly drive most fast CMOS logic inputs directly. How-
ever, the general purpose I/O pins on many programmable
logic devices (FPGAs, CPLDs) and DSPs have excessive
capacitance. In these cases, a 100Ω resistor in series
with SDO can isolate the input capacitance of the receiv-
ing device. If the receiving device has more than 10pF
of input capacitance or is located far from the LTC2356-
12/LTC2356-14, an NC7SVU04P5X inverter can be used
to provide more drive.
Serial Data Output (SDO)
Upon power-up, the SDO output is automatically reset to
the high impedance state. The SDO output remains in high
impedance until a new conversion is started. SDO sends
out 12/14 bits in 2’s complement format in the output data
stream beginning at the third rising edge of SCK after the
rising edge of CONV. SDO is always in high impedance
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev H)
BOTTOM VIEW OF
EXPOSED PAD OPTION
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
0.497 ±0.076
(.0196 ±.003)
1.88
(.074)
1.88 ±0.102
(.074 ±.004)
10 9
8
7 6
0.889 ±0.127
(.035 ±.005)
1
0.29
REF
REF
1.68
(.066)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
0.05 REF
5.23
(.206)
MIN
1.68 ±0.102
3.20 – 3.45
DETAIL “B”
(.066 ±.004) (.126 – .136)
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
1
2
3
4 5
10
NO MEASUREMENT PURPOSE
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ±.0015)
TYP
0.86
(.034)
REF
1.10
(.043)
MAX
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.254
SEATING
PLANE
(.010)
0° – 6° TYP
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ±0.0508
(.004 ±.002)
GAUGE PLANE
0.50
(.0197)
BSC
MSOP (MSE) 0911 REV H
0.53 ±0.152
(.021 ±.006)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
DETAIL “A”
0.18
(.007)
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
2356fb
16
LTC2356-12/LTC2356-14
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
01/10 Revise Values in Pin Configuration Section
06/12 Changed straight binary to 2’s complement
2
B
13
2356fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
17
LTC2356-12/LTC2356-14
TYPICAL APPLICATION
Low-Jitter Clock Timing with RF Sine Generator Using Clock
Squaring/Level Shifting Circuit and Re-Timing Flip-Flop
V
CC
1k
NC7SVU04P5X
0.1µF
MASTER CLOCK
CC
V
50Ω
1k
PRE
CLR
CONV
D
Q
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
Q
CONVERT ENABLE
NL17SZ74
CONV
LTC2356
SCK
NC7SVU04P5X
100Ω
SDO
2356 TA03
RELATED PARTS
PART NUMBER
ADCs
DESCRIPTION
COMMENTS
LTC1402
12-Bit, 2.2Msps Serial ADC
5V or 5V Supply, 4.096V or 2.048V Span
3V, 14mW, Unipolar Inputs, MSOP Package
3V, 14mW, Bipolar Inputs, MSOP Package
5V, Selectable Spans, 115mW
LTC1403/LTC1403A
LTC1403-1/LTC1403A-1
LTC1405
12-/14-Bit, 2.8Msps Serial ADC
12-/14-Bit, 2.8Msps Serial ADC
12-Bit, 5Msps Parallel ADC
LTC1407/LTC1407A
LTC1407-1/LTC1407A-1
LTC1411
12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, Unipolar Inputs, 14mW, MSOP Package
12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, Bipolar Inputs, 14mW, MSOP Package
14-Bit, 2.5Msps Parallel ADC
12-Bit, 3Msps Parallel ADC
14-Bit, 2.2Msps Parallel ADC
12-Bit, 10Msps Parallel ADC
16-Bit, 333ksps Parallel ADC
16-Bit, 500ksps Parallel ADC
16-Bit, 200ksps Serial ADC
16-Bit, 250ksps Serial ADCs
12-/14-Bit, 3.5Msps Serial ADC
5V, Selectable Spans, 80dB SINAD
LTC1412
5V Supply, 2.5V Span, 72dB SINAD
5V Supply, 2.5V Span, 78dB SINAD
5V, Selectable Spans, 71dB SINAD
LCT1414
LTC1420
LTC1604
5V Supply, 2.5V Span, 90dB SINAD
5V Supply, 2.5V Span, 90dB SINAD
5V, Configurable Bipolar/Unipolar Inputs
5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package
3.3V 14mW, 0V to 2.5V Span, MSOP Package
LTC1608
LTC1609
LTC1864/LTC1865
LTC2355-12/LTC2355-14
DACs
LTC1666/LTC1667/LTC1668 12-/14-/16-Bit, 50Msps DACs
87dB SFDR, 20ns Settling Time
LTC1592
16-Bit, Serial SoftSpan™ I
DAC
1LSB INL/DNL, Software Selectable Spans
OUT
References
LT1790-2.5
LT1461-2.5
LT1460-2.5
Micropower Series Reference in SOT-23
Precision Voltage Reference
0.05% Initial Accuracy, 10ppm Drift
0.04% Initial Accuracy, 3ppm Drift
0.075% Initial Accuracy, 10ppm Drift
Micropower Series Voltage Reference
2356fb
LT 0612 REV B • PRINTED IN USA
18 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
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LINEAR TECHNOLOGY CORPORATION 2006
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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