LTC1415ISW [Linear]
12-Bit, 1.25Msps, 55mW Sampling A/D Converter; 12位， 1.25MSPS ， 55MW采样A / D转换器
| 型号： | LTC1415ISW |
| 厂家： | 
Linear |
| 描述： | 12-Bit, 1.25Msps, 55mW Sampling A/D Converter |
| 文件： | 总24页 (文件大小：484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1415
12-Bit, 1.25Msps, 55mW
Sampling A/D Converter
U
DESCRIPTIO
EATURE
S
F
The LTC®1415 is a 700ns, 1.25Msps, 12-bit sampling
A/D converter that draws only 55mW from a single 5V
supply. This easy-to-use device includes a high dynamic
rangesample-and-hold,precisionreferenceandatrimmed
internal clock. Two power shutdown modes provide flex-
ibility for low power systems.
■
■
■
■
■
■
■
■
■
■
1.25Msps Sample Rate
Single 5V Supply
Power Dissipation: 55mW
Nap and Sleep Power Shutdown Modes
±
0.35LSB INL and ±0.25LSB DNL
72dB S/(N + D) and 80dB THD at 100kHz
External or Internal Reference Operation
True Differential Inputs Reject Common Mode Noise
Input Range: 4.096V (1mV/LSB)
The LTC1415’s full-scale input range is 4.096V. Low
linearity errors ±0.35LSB INL, ±0.25LSB DNL make it
ideal for imaging systems. Outstanding AC performance
includes 72dB S/(N + D) and 80dB THD with an input
frequency of 100kHz.
28-Pin SSOP and SO Packages
O U
PPLICATI
S
A
Theuniquedifferentialinputsample-and-holdcanacquire
single-ended or differential input signals up to its 18MHz
bandwidth. The 60dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
■
■
■
■
■
High Speed Data Acquisition
Imaging Systems
Digital Signal Processing
Multiplexed Data Acquisition Systems
Telecommunications
The ADC has a µP compatible, 12-bit parallel output port.
There is no pipeline delay in the conversion results. A
separate convert start input and data ready signal (BUSY)
ease connections to FIFOs, DSPs and microprocessors. A
separate output logic supply pin allows direct connection
to 3V components.
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
O
TYPICAL APPLICATI
1.25MHz, 12-Bit Sampling A/D Converter
Effective Bits and Signal-to-(Noise + Distortion)
vs Input Frequency
LTC1415
5V
DIFFERENTIAL
ANALOG INPUT
(0V TO 4.096V)
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
12
11
10
9
74
68
62
56
+A
–A
AV
DV
OV
IN
IN
DD
DD
DD
10µF
3
OUTPUT LOGIC
2.50V
OUTPUT
NYQUIST
FREQUENCY
V
REF
SUPPLY 3V OR 5V
V
REF
4
REFCOMP
AGND
BUSY
CS
5
8
10µF
6
7
D11(MSB) CONVST
µP CONTROL
LINES
7
6
D10
D9
RD
SHDN
NAP/SLP
OGND
D0
8
5
9
4
D8
10
11
12
13
14
3
D7
12-BIT
PARALLEL
BUS
2
D6
1
D5
D1
f
= 1.25Msps
10k
SAMPLE
0
D4
D2
1k
100k
1M 2M
DGND
D3
INPUT FREQUENCY (Hz)
LTC1415 • TA02
1415 TA01
1
LTC1415
W W W
U
ABSOLUTE AXI U RATI GS
/O
PACKAGE RDER I FOR ATIO
AVDD = DVDD =OVDD = VDD (Notes 1, 2)
TOP VIEW
ORDER
PART NUMBER
Supply Voltage (VDD) ................................................ 6V
Analog Input Voltage (Note 3) ...... – 0.3V to VDD + 0.3V
Digital Input Voltage (Note 4) .................. – 0.3V to 12V
Digital Output Voltage.................... – 0.3V to VDD + 0.3V
Power Dissipation............................................. 500mW
Operating Temperature Range
LTC1415C............................................... 0°C to 70°C
LTC1415I........................................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
+A
–A
V
1
2
3
4
5
6
7
8
9
28 AV
DD
IN
IN
27 DV
DD
DD
26 OV
LTC1415CG
LTC1415CSW
LTC1415IG
REF
REFCOMP
25 BUSY
24 CS
AGND
D11 (MSB)
D10
23 CONVST
22 RD
LTC1415ISW
D9
21 SHDN
20 NAP/SLP
19 OGND
18 D0
D8
D7 10
D6 11
D5 12
17 D1
D4 13
16 D2
DGND 14
15 D3
G PACKAGE
28-LEAD PLASTIC SSOP
SW PACKAGE
28-LEAD PLASTIC SO WIDE
TJMAX = 110°C, θJA = 95°C/W (G)
TJMAX = 110°C, θJA = 130°C/W (SW)
Consult factory for Military grade parts.
U
With Internal Reference (Notes 5, 6)
CO VERTER
CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
●
●
●
12
Bits
LSB
LSB
(Note 7)
(Note 8)
0.35
0.25
±1
±1
±1
±6
±8
LSB
LSB
●
Full-Scale Error
±20
LSB
Full-Scale Tempco
I
= 0
±15
ppm/°C
OUT(REF)
U
U
(Note 5)
A ALOG I PUT
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
IN
Analog Input Range (Note 9)
4.75V ≤ V ≤ 5.25V
●
●
4.096
DD
I
Analog Input Leakage Current
Analog Input Capacitance
CS = High
±1
µA
IN
C
Between Conversions
During Conversions
19
5
pF
pF
IN
t
t
t
Sample-and-Hold Acquisition Time
●
50
–1.5
2
150
ns
ns
ACQ
AP
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Analog Input Common Mode Rejection Ratio
ps
jitter
RMS
CMRR
0V < V < V , DC to MHz
60
dB
CM
DD
2
LTC1415
W
U
(Note 5)
DY
SYMBOL
A IC
ACCURACY
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
S/(N + D)
Signal-to-(Noise + Distortion) Ratio
100kHz Input Signal
600kHz Input Signal
72
69
dB
dB
THD
Total Harmonic Distortion
100kHz Input Signal, First 5 Harmonics
600kHz Input Signal, First 5 Harmonics
–80
–72
dB
dB
SFDR
IMD
Spurious Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
600kHz Input Signal
–75
–84
18
dB
dB
f
= 29.37kHz, f = 32.446kHz
IN2
IN1
MHz
MHz
Full-Linear Bandwidth
S/(N + D) ≥ 68dB
1
U U
U
I TER AL REFERE CE CHARACTERISTICS (Note 5)
PARAMETER
CONDITIONS
MIN
TYP
2.500
±15
0.01
2
MAX
UNITS
V
V
V
V
V
Output Voltage
Output Tempco
Line Regulation
Output Resistance
I
I
= 0
= 0
2.480
2.520
REF
REF
REF
REF
OUT
OUT
ppm/°C
LSB/V
kΩ
4.75V ≤ V ≤ 5.25V
DD
I
≤ 0.1mA
OUT
REFCOMP Output Voltage
I
= 0
4.096
V
OUT
U
U
DIGITAL I PUTS A D DIGITAL OUTPUTS
(Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
V
= 5.25V
= 4.75V
= 0V to V
●
●
●
2.4
V
V
IH
IL
DD
DD
IN
0.8
I
±10
µA
pF
IN
DD
C
V
Digital Input Capacitance
High Level Output Voltage
5
IN
V
V
V
= 4.75V
OH
DD
I = –10µA
4.5
V
V
O
O
I
= –200µA
●
4.0
V
Low Level Output Voltage
= 4.75V
= 160µA
= 1.6mA
OL
DD
I
I
0.05
0.10
V
V
O
O
●
●
●
0.4
±10
15
I
Hi-Z Output Leakage D11 to D0
Hi-Z Output Capacitance D11 to D0
Output Source Current
= 0V to V , CS High
µA
pF
OZ
OUT
DD
C
CS High (Note 9 )
OZ
I
I
V
V
= 0V
–10
10
mA
mA
SOURCE
SINK
OUT
OUT
Output Sink Current
= V
DD
W U
POWER REQUIRE E TS (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Supply Voltage
(Notes 10, 11)
4.75
5.25
V
DD
I
Supply Current
Nap Mode
CS High
●
●
11
1.5
1.0
20
2.3
mA
mA
µA
DD
SHDN = 0V, NAP/SLP = 5V (Note 12)
SHDN = 0V, NAP/SLP = 0V (Note 12)
Sleep Mode
P
Power Dissipation
Nap Mode
CS High
SHDN = 0V, NAP/SLP = 5V
SHDN = 0V, NAP/SLP = 0V
55
7.5
0.01
100
12
mW
mW
mW
D
Sleep Mode
3
LTC1415
W U
TI I G CHARACTERISTICS (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
Maximum Sampling Frequency
Conversion and Acquisition Time
●
●
1.25
MHz
ns
SAMPLE(MAX)
800
700
150
t
t
t
t
t
t
Conversion Time
●
●
●
●
ns
ns
ns
ns
ns
CONV
Acquisition Time
ACQ
CS to RD Setup Time
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
0
1
2
3
4
CS↓ to CONVST↓ Setup Time
NAP/SLP↑ to SHDN↓ Setup Time
10
200
SHDN↑ to CONVST↓ Wake-Up Time Nap Mode (Note 10)
200
10
ns
ms
Sleep Mode, C
= 10µF (Note 10)
REFCOMP
t
t
CONVSTLow Time
(Notes 10, 11)
●
●
50
ns
5
6
CONVST to BUSY Delay
C = 25pF
L
10
35
ns
ns
60
t
Data Ready Before BUSY↑
20
15
ns
ns
7
●
●
●
t
t
t
Delay Between Conversions
Wait Time RD↓ After BUSY↑
Data Access Time After RD↓
(Note 10)
50
ns
ns
8
–5
9
C = 25pF
L
20
25
10
35
45
ns
ns
10
●
●
C = 100pF
L
45
60
ns
ns
t
Bus Relinquish Time
30
35
40
ns
ns
ns
11
0°C = T = 70°C
●
●
A
–40°C = T = 85°C
A
t
t
t
RD Low Time
●
●
t
ns
ns
ns
12
13
14
10
CONVST High Time
50
Aperture Delay of Sample-and-Hold
–1.5
Note 6: Linearity, offset and full-scale specifications apply for a single-
The
● denotes specifications which apply over the full operating
ended +A input with – A grounded.
temperature range; all other limits and typicals T = 25°C.
IN
IN
A
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together unless otherwise noted.
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 3: When these pin voltages are taken below ground or above V
,
DD
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
they will be clamped by internal diodes. This product can handle input
currents greater than 100mA below ground or above V without latchup.
DD
Note 4: When these pin voltages are taken below ground, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below ground without latchup. These pins are not clamped
Note 11: The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion it can create small
errors. For best performance ensure that CONVST returns high either
within 425ns after the start of the conversion or after BUSY rises.
to V
.
DD
Note 5: V = 5V, f
specified.
= 1.25MHz, t = t = 5ns unless otherwise
r f
Note 12: CS = RD = CONVST = 0V.
DD
SAMPLE
4
LTC1415
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
S/(N + D) vs Input Frequency
and Amplitude
Signal-to-Noise Ratio vs
Input Frequency
Distortion vs Input Frequency
80
70
60
50
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
80
70
60
50
40
30
20
10
0
V
V
= 0dB
IN
IN
= –20dB
THD
3RD
V
= –60dB
IN
2ND
1k
10k
100k
1M 2M
1k
10k
100k
1M 2M
1k
10k
100k
1M 2M
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
LTC1415 • TPC01
LTC1415 • TPC03
LTC1415 • TPC02
Spurious-Free Dynamic Range vs
Input Frequency
Intermodulation Distortion Plot
0
–20
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
f
f
f
= 1.25MHz
= 86.97509766kHz
= 113.2202148kHz
SAMPLE
IN1
IN2
–40
fb – fa
2fb – fa
2fa
2fa + fb
fa + 2fb
fa + fb
2fb
–60
2fa – fb
3fa
3fb
–80
–100
–120
0
100k
200k
300k
FREQUENCY (Hz)
400k
500k
600k
10k
100k
1M 2M
INPUT FREQUENCY (Hz)
LTC1415 • TPC04
LTC1415 • TPC05
Integral Nonlinearity vs
Output Code
Differential Nonlinearity vs
Output Code
1.00
0.50
1.00
0.50
0.00
0.00
–0.50
–1.00
–0.50
–1.00
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
LTC1415 • TPC07
LTC1415 • TPC06
5
LTC1415
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Feedthrough vs
Ripple Frequency
Input Common Mode Rejection
vs Input Frequency
80
70
60
50
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
V
DD
DGND
100k
–90
OV
DD
–100
1k
10k
100k
1M 2M
1k
10k
1M 2M
INPUT FREQUENCY (Hz)
RIPPLE FREQUENCY (Hz)
LTC1415 • TPC09
LTC1415 • TPC08
U U
U
PI FU CTIO S
RD (Pin 22): Read Input. This enables the output
+A (Pin 1): Positive Analog Input, 0V to 4.096V.
IN
drivers when CS is low.
–A (Pin 2): Negative Analog Input, 0V to 4.096V.
IN
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
V
REF
(Pin 3): 2.50V Reference Output.
REFCOMP(Pin4):BypasstoAGNDwith10µFtantalum
in parallel with 0.1µF or 10µF ceramic.
CS (Pin 24): The Chip Select input must be low for the
ADC to recognize CONVST and RD inputs.
AGND (Pin 5): Analog Ground.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Its
rising edge may be used to latch the output data.
D11 to D4 (Pins 6 to 13): Three-State Data Outputs.
DGND (Pin 14): Digital Ground.
D3 to D0 (Pins 15 to 18): Three-State Data Outputs.
OGND (Pin 19): Digital Output Buffer Ground.
0V (Pin26):Digitaloutputbuffersupply.ShorttoPin
DD
28 for 5V output. Tie to 3V for driving 3V logic.
DV (Pin 27): 5V Positive Supply. Short to Pin 28.
NAP/SLP (Pin 20): Power Shutdown Mode. High for
DD
quick wake-up Nap mode.
AV (Pin 28): 5V Positive Supply. Bypass to AGND
DD
with 10µF tantalum in parallel with 0.1µF or 10µF
SHDN (Pin 21): Power Shutdown Input. A low logic
level will invoke the Shutdown mode selected by the
NAP/SLP pin. Tie high if unused.
ceramic.
6
LTC1415
U
U
W
FU CTIO AL BLOCK DIAGRA
C
C
SAMPLE
SAMPLE
+A
IN
AV
DD
–A
V
IN
DV
DD
2k
ZEROING SWITCHES
2.5V REF
REF AMP
REF
+
COMP
12-BIT CAPACITIVE DAC
–
REFCOMP
(4.096V)
OV
DD
12
AGND
DGND
D11
D0
SUCCESSIVE APPROXIMATION
REGISTER
•
•
•
OUTPUT LATCHES
OGND
INTERNAL
CLOCK
CONTROL LOGIC
1415 BD
NAP/SLP SHDN CONVST RD CS BUSY
TEST CIRCUITS
Load Circuits for Bus Relinquish Time
Load Circuits for Access Timing
5V
5V
1k
1k
DBN
DBN
DBN
DBN
1k
C
L
C
L
1k
100pF
100pF
(A) Hi-Z TO V AND V TO V
(B) Hi-Z TO V AND V TO V
(A) V TO Hi-Z
(B) V TO Hi-Z
OL
OH
OL
OH
OL
OH
OL
OH
1415 TC01
1415 TC02
7
LTC1415
U
W U U
APPLICATIONS INFORMATION
CONVERSION DETAILS
with the binary weighted charges supplied by the differen-
tial capacitive DAC. Bit decisions are made by the high
speed comparator. At the end of a conversion, the differ-
ential DAC output balances the +AIN and – AIN input
charges. The SAR contents (a 12-bit data word) which
represents the difference of +AIN and –AIN are loaded into
the 12-bit output latches.
The LTC1415 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs (please refer to Digital Interface section for
the data format).
DYNAMIC PERFORMANCE
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
The LTC1415 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
to testthe ADC’s frequency response, distortionandnoise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using a FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 2 shows a
typical LTC1415 FFT plot.
During the conversion, the internal differential 12-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
Referring to Figure 1, the +AIN and –AIN inputs are con-
nected to the sample-and-hold capacitors (CSAMPLE) dur-
ingtheacquirephase andthecomparatoroffsetisnulledby
the zeroing switches. In this acquire phase, a minimum
delay of 150ns will provide enough time for the sample-
and-hold capacitors to acquire the analog signal. During
the convert phase the comparator zeroing switches open,
putting the comparator into compare mode. The input
switchestheconnectCSAMPLE capacitorstoground,trans-
ferring the differential analog input charge onto the sum-
mingjunction.Thisinputchargeissuccessivelycompared
0
f
f
= 1.25MHz
SAMPLE
IN
= 99.792kHz
–20
–40
SFDR - 87.5
SINAD = 72.1
–60
–80
–100
–120
0
200
300
400
500
600
100
+C
SAMPLE
SAMPLE
SAMPLE
FREQUENCY (kHz)
+A
–A
IN
IN
LTC1415 • F02
HOLD
–C
ZEROING SWITCHES
HOLD
Figure 2. LTC1415 Nonaveraged, 4096 Point FFT
SAMPLE
HOLD
HOLD
Signal-to-Noise Ratio
+C
DAC
DAC
The signal-to-noise plus distortion ratio [S/(N + D)] or
SINAD is the ratio between the RMS amplitude of the
fundamental input frequency to the RMS amplitude of all
otherfrequencycomponentsattheA/Doutput.Theoutput
is band limited to frequencies from above DC and below
half the sampling frequency. Figure 2 shows a typical
spectral content with a 1.25MHz sampling rate and a
100kHz input. The dynamic performance is excellent for
input frequencies up to the Nyquist limit of 625kHz.
+
–C
COMP
+V
DAC
–
–V
DAC
12
D11
D0
OUTPUT
LATCHES
•
•
•
SAR
LTC1415 • F01
Figure 1. Simplified Block Diagram
8
LTC1415
U
W U U
APPLICATIONS INFORMATION
Effective Number of Bits
band between DC and half the sampling frequency. THD is
expressed as:
The effective number of bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
2
2
2
2
V2 + V3 + V4 +…Vn
THD = 20Log
V1
N = [S/(N + D) – 1.76]/6.02
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through nth harmonics. THD vs input frequency is
shown in Figure 4. The LTC1415 has good distortion
performance up to the Nyquist frequency and beyond.
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 1.25MHz the LTC1415 maintains very good ENOBs
up to the Nyquist input frequency of 625kHz (refer to
Figure 3).
Intermodulation Distortion
Total Harmonic Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
Total Harmonic Distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
12
11
10
9
74
68
62
56
0
–10
–20
–30
–40
–50
8
7
6
5
–60
THD
–70
4
3
–80
–90
2ND
3RD
2
1
–100
0
1k
10k
100k
1M 2M
1k
10k
100k
1M 2M
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
LT1415 • F03
LTC1415 • F04
Figure 3. Effective Bits and Signal/(Noise +
Distortion) vs Input Frequency
Figure 4. Distortion vs Input Frequency
0
–20
–40
f
f
f
= 1.25MHz
= 86.97509766kHz
= 113.2202148kHz
SAMPLE
IN1
IN2
fb – fa
2fb – fa
2fa
2fa + fb
fa + 2fb
fa + fb
2fb
–60
–80
2fa – fb
3fa
3fb
–100
–120
0
100k
200k
300k
FREQUENCY (Hz)
400k
500k
600k
LTC1415 • F05
Figure 5. Intermodulation Distortion Plot
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the presence of another sinusoidal input at a different
onlyasmallleakagecurrent.Ifthesourceimpedanceofthe
driving circuit is low, then the LTC1415 inputs can be
driven directly. As source impedance increases so will
acquisition time (see Figure 6). For minimum acquisition
timewithhighsourceimpedance,abufferamplifiershould
be used. The only requirement is that the amplifier driving
theanaloginput(s)mustsettleafterthesmallcurrentspike
before the next conversion starts (settling time must be
150ns for full throughput rate).
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa + –nfb, where m and n = 0, 1, 2,
3, etc. For example, the 2nd order IMD terms include
(fa + fb). If the two input sine waves are equal in magni-
tude, thevalue(indecibels)ofthe2ndorderIMDproducts
can be expressed by the following formula:
10
Amplitude at (fa + fb)
IMD fa + fb = 20Log
(
)
Amplitude at fa
1
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
0.1
0.01
1
10
100
0.01
0.1
Full-Power and Full-Linear Bandwidth
SOURCE RESISTANCE (kΩ)
1415 F06
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
Figure 6. Acquisition Time vs Source Resistance
Choosing an Input Amplifier
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1415 has been designed to optimize input bandwidth,
allowing the ADC to undersample input signals with fre-
quencies above the converter’s Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a
low output impedance (<100Ω) atthe closed-loop band-
width frequency. For example, if an amplifier is used in a
gainof+1andhasaunity-gainbandwidthof50MHz,then
the output impedance at 50MHz should be less than
100Ω. The second requirement is that the closed-loop
bandwidth must be greater than 20MHz to ensure
adequate small-signal settling for full throughput rate. If
slower op amps are used, more settling time can be
provided by increasing the time between conversions.
Driving the Analog Input
The differential analog inputs of the LTC1415 are easy to
drive.Theinputsmaybedrivendifferentiallyorasasingle-
endedinput(i.e.,the–AIN inputisgrounded).The+AIN and
–AIN inputsaresampledatthesameinstant.Anyunwanted
signalthatiscommonmodetobothinputswillbereduced
by the common mode rejection of the sample-and-hold
circuit. The inputs draw only one small current spike while
charging the sample-and-hold capacitors at the end of
conversion. During conversion the analog inputs draw
The best choice for an op amp to drive the LTC1415 will
dependontheapplication. Generallyapplicationsfallinto
two categories: AC applications where dynamic specifi-
cations are most critical and time domain applications
where DC accuracy and settling time are most critical.
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capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sam-
pling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors
haveexcellentlinearity.Carbonsurfacemountresistorscan
also generate distortion from self heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
The following list is a summary of the op amps that are
suitable for driving the LTC1415, more detailed informa-
tion is available in the Linear Technology databooks and
the LinearViewTM CD-ROM.
LT ®1215/LT1216: Dual and quad 23MHz, 50V/µs single
supply op amps. Single 5V to ±15V supplies, 6.6mA
specifications, 90ns settling to 0.5LSB.
LT1223: 100MHz video current feedback amplifier. ±5V
to±15Vsupplies, 6mAsupplycurrent. Lowdistortion up
to and above 400kHz. Low noise. Good for AC applica-
tions.
100Ω
1
2
3
4
5
ANALOG INPUT
+A
IN
1000pF
LT1227: 140MHz video current feedback amplifier. ±5V
to ±15V supplies, 10mA supply current. Lowest distor-
tion at frequencies above 400kHz. Low noise. Best for AC
applications.
–A
IN
LTC1415
V
REF
REFCOMP
AGND
LT1229/LT1230:Dualandquad100MHzcurrentfeedback
amplifiers. ±2V to ±15V supplies, 6mA supply current
each amplifier. Low noise. Good AC specs.
10µF
LTC1415 • F07
LT1360: 37MHz voltage feedback amplifier. ±5V to ±15V
supplies. 3.8mA supply current. Good AC and DC specs.
70ns settling to 0.5LSB.
Figure 7. RC Input Filter
Input Range
LT1363: 50MHz, 450V/µs op amps. ±5V to ±15V sup-
plies. 6.3mA supply current. Good AC and DC specs. 60ns
settling to 0.5LSB.
The 4.096V input range of the LTC1415 is optimized for
low noise. Most single supply op amps also perform well
over this same range, allowing direct coupling to the
analog inputs and eliminating the need for special transla-
tion circuitry.
LT1364/LT1365:Dualandquad50MHz,450V/µsopamps.
±5V to ±15V supplies, 6.3mA supply current per ampli-
fier. 60ns settling to 0.5LSB.
Some applications may require other input ranges. The
LTC1415 differential inputs and reference circuitry can
accommodate other input ranges often with little or no
additional circuitry. The following sections describe the
reference and input circuitry and how they affect the input
range.
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1415 noise and distortion. The small-signal band-
width of the sample-and-hold circuit is 20MHz. Any noise
ordistortionproductsthatarepresentattheanaloginputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For example Figure 7 shows a 1000pF
capacitor from +AIN to ground and a 100Ω source resistor
to limit the input bandwidth to 1.6MHz. The 1000pF
LinearView is a trademark of Linear Technology Corporation.
Internal Reference
The LTC1415 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmedto2.500V.Itisconnectedinternallytoareference
amplifier and is available at VREF (Pin 3) see Figure 8a. A
2k resistor is in series with the output so that it can be
easily overdriven by an external reference or other
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1
2
3
4
5
circuitry. The reference amplifier gains the voltage at the
REF pin by 1.638 to create the required internal reference
+A
IN
DIFFERENTIAL ANALOG INPUT
V
RANGE = (V )(1.638)
REF
voltage of 4.096V. This provides buffering between the
VREF pin and the high speed capacitive DAC. The reference
amplifier compensation pin (REFCOMP, Pin 4) must be
bypassedwith acapacitorto ground. Thereference ampli-
fier is stable with capacitors of 1µF or greater. For the best
noise performance a 10µF ceramic or tantalum in parallel
with a 0.1µF ceramic is recommended.
–A
IN
LTC1415
LTC1450
12-BIT
RAIL-TO-RAIL DAC
1.25V TO 3V
V
REF
REFCOMP
AGND
10µF
LTC1415 • F09
Figure 9. Driving VREF with a DAC to Adjust Full Scale
R1
2k
V
BANDGAP
REFERENCE
3
4
REF
2.500V
bandwidth and settling time of this circuit. A settling time
of 5ms should be allowed for after a reference adjustment.
REFCOMP
REFERENCE
AMP
4.096V
Differential Inputs
R2
40k
10µF
The LTC1415 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
convert the difference of +AIN – (–AIN) independent of the
common mode voltage. The common mode rejection is
constant from DC to 1MHz, see Figure 10a. The only
requirement is that both inputs can not exceed the AVDD
or AGND power supply voltages. Integral nonlinearity
errors (INL) and differential nonlinearity errors (DNL) are
independent of the common mode voltage, however, the
bipolar zero error (BZE) will vary. The change in BZE is
typically less than 0.1% of the common mode voltage.
R3
64k
AGND
5
LTC1415
LTC1415 • F08a
Figure 8a. LTC1415 Reference Circuit
5V
1
2
3
+A
–A
IN
IN
ANALOG
INPUT
V
IN
LT1019A-2.5
V
V
REF
OUT
LTC1415
Differential inputs allow greater flexibility for accepting
different input ranges. Figure 10b shows a circuit that
shifts the input range up in voltage by 200mV. This can be
useful in applications where the amplifier driving the ADC
input is not able to swing all the way to ground, because
of output loading or settling time issues.
4
5
REFCOMP
AGND
10µF
1415 F08b
Figure 8b. Using the LT1019-2.5 as an External Reference
The VREF pin can be driven with a DAC or other means
shown in Figure 9. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1415 reference amplifier will limit the
Some AC applications may have their performance limited
by distortion. Most circuits exhibit higher distortion when
signals approach the supply or ground. Distortion can be
reduced by reducing the signal amplitude and keeping the
common mode voltage at approximately midsupply. The
circuit of Figure 10c reduces the ADC full scale from
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4.096V to 2.048V and shifts the common mode voltage
from half of full scale to 2.274V.
ADC does need to be DC biased at midscale. Figures 10d
and 10e demonstrate AC coupling and the required bias-
ing. Figure 10d shows the ADC with a full scale of 4.096V,
a common mode voltage of 2.048V and an input that
swings from 0V to 4.096V. This circuit has the lowest
noise (SINAD = 72dB to 100kHz) but will have distortion
AC Coupled Inputs
The analog inputs can be AC coupled for applications
where the input has no DC information. The input of the
80
70
60
50
40
30
20
10
0
1
ANALOG INPUT
0.2V TO 4.296V
+A
IN
R1
200Ω
2
3
–A
IN
LTC1415
R2
3.9k
V
REF
4
5
REFCOMP
AGND
10µF
LTC1415 • F10b
1k
10k
100k
1M 2M
INPUT FREQUENCY (Hz)
LTC1415 • F10a
Figure 10a. CMRR vs Input Frequency
Figure 10b. Shifting the Input Range Up from Ground by 200mV
1
ANALOG INPUT
1.25V TO 3.298V
1
2
ANALOG INPUT
4.096V
+A
+A
IN
IN
P-P
2
3
–A
V
IN
–A
IN
24Ω
V
OUT
= 1.2V
REF
3
4
V
REF
1µF
LT1004-1.2
LTC1415
LTC1415
REFCOMP
4
5
2k
2k
REFCOMP
AGND
10µF
10µF
5
AGND
LTC1415 • F10c
LTC1415 • F10d
Figure 10c. 2.048V Input Range with a Common Mode
Voltage of 2.274V. For Low Distortion AC Applications
Figure 10d. 4.096VP-P Input Range with AC Coupling.
For Low Noise AC Applications
1
2
ANALOG INPUT
+A
IN
2.048V
P-P
–A
IN
25Ω
3
V
REF
1k
1µF
LT1004-1.2
LTC1415
4
REFCOMP
+
10µF
–
1k
9k
5
AGND
LTC1415 • F10e
Figure 10e. 2.048VP-P Input Range with AC Coupling. For Low Distortion AC Applications
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R1
limitations at high input frequencies (THD = 75dB at
600kHz). The ADC in Figure 10e has a full scale of 2.048V
and a common mode of 2.27V. The reduced signal swing
ofthiscircuitresultsinimproveddistortionathigherinput
frequencies (THD = 82dB at 600kHz) but with worse
SINAD at low frequencies (SINAD = 70dB at 100kHz).
100Ω
ANALOG
INPUT
R2
47k
R3
24k
1
2
5V
+A
–A
IN
R8
50k
R5
R4
100Ω
IN
47k
R7
50k
3
V
REF
LTC1415
Full-Scale and Offset Adjustment
R6
24k
4
5
Figure 11a shows the ideal input/output characteristics
for the LTC1415. The code transitions occur midway
between successive integer LSB values (i.e., 0.5LSB,
1.5LSB, 2.5LSB,... FS – 1.5LSB, FS – 0.5LSB). The output
is straight binary with 1LSB = FS/4096 = 4.096V/4096
= 1mV.
REFCOMP
AGND
0.1µF
10µF
LTC1415 • F11b
Figure 11b. Offset and Full-Scale Adjust Circuit
the output code flickers between 1111 1111 1110 and
1111 1111 1111.
111...111
111...110
111...101
BOARD LAYOUT AND GROUNDING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1415, a printed circuit board
with ground plane is required. The ground plane under the
ADC area should be as free of breaks and holes as
possible, such that a low impedance path between all ADC
grounds and all ADC decoupling capacitors is provided. It
iscriticaltopreventdigitalnoisefrombeingcoupledtothe
analog input, reference or analog power supply lines.
Layout should ensure that digital and analog signal lines
are separated as much as possible. Particular care should
be taken not to run any digital track alongside an analog
signal track.
000...010
000...001
000...000
1LSB
FS – 1LSB
INPUT VOLTAGE (V)
LTC1415 • F11a
Figure 11a. LTC1415 Transfer Characteristics
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 11b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the –AIN input. For zero offset error apply
0.5mV (i.e., 0.5LSB) at +AIN and adjust the offset at the
–AIN input (R8) until the output code flickers between
0000 0000 0000 and 0000 0000 0001. For full-scale
adjustment, an input voltage of 4.0945V (FS – 1.5LSBs)
is applied to the analog input and R7 is adjusted until
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND), Pin 14 and Pin 19 (ADC’s DGND) and all
other analog grounds should be connected to this single
analog ground point. The REFCOMP bypass capacitor and
the DVDD bypass capacitor should also be connected to
this analog ground plane. No other digital grounds should
beconnectedtothisanaloggroundplane. Lowimpedance
analog and digital power supply common returns are
essential to low noise operation of the ADC and the foil
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width for these tracks should be as wide as possible. In
applications where the ADC data outputs and control
signals are connected to a continuously active micropro-
cessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation com-
parator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversion or by
using three-state buffers to isolate the ADC data bus. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
SUPPLY BYPASSING
High quality, low series resistance ceramic, 10µF bypass
capacitors should be used at the VDD and REFCOMP pins
as shown in the Typical Application on the fist page of this
data sheet. Surface mount ceramic capacitors such as
Murata GRM235Y5V106Z016 provide excellent bypass-
ing in a small board space. Alternatively 10µF tantalum
capacitorsinparallelwith0.1µFceramiccapacitorscanbe
used. Bypass capacitors must be located as close to the
pins as possible. The traces connecting the pins and the
bypass capacitors must be kept short and should be made
as wide as possible.
The LTC1415 has differential inputs to minimize noise
coupling. Common mode noise on the +AIN and –AIN
leads will be rejected by the input CMRR. The –AIN input
can be used as a ground sense for the +AIN input; the
LTC1415 will hold and convert the difference voltage
between+AIN and–AIN.Theleadsto+AIN (Pin1)and–AIN
(Pin 2) should be kept as short as possible. In applications
wherethisisnotpossible,the+AINand–AIN tracesshould
be run side by side to equalize coupling.
Example Layout
Figures 13a, 13b, 13c and 13d show the schematic and
layoutofasuggestedevaluationboard.Thelayoutdemon-
stratestheproperuseofdecouplingcapacitorsandground
plane with a two layer printed circuit board.
1
DIGITAL
SYSTEM
LTC1415
+A
IN
–A
IN
REFCOMP AGND
AV
DD
DV
OV
DGND OGND
+
–
DD
27
DD
26
ANALOG
INPUT
CIRCUITRY
2
4
5
28
14
19
LTC1415 • F12
+
+
10µF
0.1µF
10µF
0.1µF
ANALOG GROUND PLANE
Figure 12. Power Supply Grounding Practice
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Figure 13b. Suggested Evaluation Circuit Board Component Side Silkscreen
Figure 13c. Suggested Evaluation Circuit Board Component Side Layout
17
LTC1415
APPLICATIONS INFORMATION
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Figure 13d. Suggested Evaluation Circuit Board Solder Side Layout
DIGITAL INTERFACE
Nap mode reduces the power by 87% and leaves only the
digitallogicandreferencepoweredup. Thewake-uptime
from Nap to active is 200ns. Follow the setup time shown
inFigure14atoavoidinadvertentlyinvokingSleepmode.
In Sleep mode all bias currents are shut down and only
leakage current remains, about 1µA. Wake-up time from
Sleep mode is much slower since the reference circuit
must power up and settle to 0.01% for full 12-bit accu-
racy. Sleepmodewake-uptimeisdependentonthevalue
of the capacitor connected to the REFCOMP (Pin 4). The
wake-up time is 10ms with the recommended 10µF
capacitor. Shutdown is controlled by Pin 21 (SHDN); the
ADC is in shutdown when it is low. The shutdown mode is
selected with Pin 20 (NAP/SLP); high selects Nap.
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a
conversion.
Internal Clock
The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 0.70µs and a maximum conversion time over the
full operating temperature range of 0.75µs. No external
adjustments are required. The guaranteed maximum
acquisitiontimeis150ns.Inaddition,athroughputtimeof
800ns and a minimum sampling rate of 1.25Msps are
guaranteed.
NAP/SLP
t
3
SHDN
1415 F14a
Power Shutdown
TheLTC1415providestwopowershutdownmodes, Nap
and Sleep, to save power during inactive periods. The
Figure 14a. NAP/SLP to SHDN Timing
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I FOR ATIO
SHDN
In slow memory and ROM modes (Figures 19 and 20) CS
istiedlowandCONVSTandRDaretiedtogether. TheMPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
t
4
CONVST
1415 F14b
Figure 14b. SHDN to CONVST Wake-Up Timing
In slow memory mode the processor applies a logic low to
RD (= CONVST), starting the conversion. BUSY goes low,
forcing the processor into a WAIT state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results ap-
pear on the data outputs; BUSY goes high, releasing the
processor and the processor takes RD (= CONVST) back
high and reads the new conversion data.
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A logic “0”
appliedtotheCONVSTpinwillstartaconversionafterthe
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY
is low during a conversion.
In ROM mode, the processor takes RD (= CONVST) low,
startingaconversionandreadingthepreviousconversion
result. Aftertheconversioniscomplete, theprocessorcan
read the new result and initiate another conversion.
Figures 16 through 20 show several different modes of
operation. In modes 1a and 1b (Figures 16 and 18) CS
and RD are both tied low. The falling edge of CONVST
startstheconversion.Thedataoutputsarealwaysenabled
and data can be latched with the BUSY rising edge. Mode
1a shows operation with a narrow logic low CONVST
pulse. Mode 1b shows a narrow logic high CONVST pulse.
CS
t
2
CONVST
RD
t
1
Inmode2(Figure18)CSistiedlow. Thefallingedgeofthe
CONVST signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the RD signal.
Mode 2 can be used for operation with a shared MPU
databus.
1415 • F15
Figure 15. CS to CONVST Setup Timing
t
CONV
t
5
CONVST
BUSY
t
t
8
6
t
7
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
DATA
1415 • F16
Figure 16. Mode 1a CONVST Starts a Conversion. Data Outputs Always Enabled
19
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t
t
CONV
8
t
t
5
13
CONVST
BUSY
t
t
t
6
6
6
t
7
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
DATA
1415 • F17
Figure 17. Mode 1b CONVST Starts a Conversion. Data is Read by RD
t
13
t
t
8
CONV
t
5
CONVST
t
6
BUSY
RD
t
t
11
9
t
12
t
10
DATA N
DB11 TO DB0
DATA
1415 F18
Figure 18. Mode 2 CONVST Starts a Conversion. Data is Read by RD
20
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A
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t
t
8
CONV
RD = CONVST
BUSY
t
11
t
6
t
t
7
10
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11-DB0
DATA
1415 • F19
Figure 19. Slow Memory Mode Timing
CS = 0
t
t
8
CONV
RD = CONVST
BUSY
t
t
11
6
t
10
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB0
DATA
1415 • F20
Figure 20. ROM Mode Timing
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LTC1415
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PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.397 – 0.407*
(10.07 – 10.33)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
0.301 – 0.311
(7.65 – 7.90)
5
7
8
1
2
3
4
6
9 10 11 12 13 14
0.205 – 0.212**
(5.20 – 5.38)
0.068 – 0.078
(1.73 – 1.99)
0° – 8°
0.0256
(0.65)
BSC
0.005 – 0.009
(0.13 – 0.22)
0.022 – 0.037
(0.55 – 0.95)
0.002 – 0.008
(0.05 – 0.21)
0.010 – 0.015
(0.25 – 0.38)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
G28 SSOP 0694
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LTC1415
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PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
SW Package
28-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.697 – 0.712*
(17.70 – 18.08)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.291 – 0.299**
(7.391 – 7.595)
2
3
5
7
8
9
10 11 12 13 14
1
4
6
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029
(0.254 – 0.737)
× 45°
0° – 8° TYP
0.050
(1.270)
TYP
0.004 – 0.012
(0.102 – 0.305)
0.009 – 0.013
NOTE 1
(0.229 – 0.330)
0.014 – 0.019
(0.356 – 0.482)
TYP
0.016 – 0.050
(0.406 – 1.270)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
S28 (WIDE) 0996
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC1415
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1273/75/76
Complete 5V Sampling 12-Bit ADCs
with 70dB SINAD at Nyquist
Lower Power 75mW and Cost Effective for f
≤ 300ksps
SAMPLE
LTC1274/77
LTC1278/79
LTC1282
Low Power 12-Bit ADCs with Nap
and Sleep Mode Shutdown
Lowest Power (10mW) for f
≤ 100ksps
SAMPLE
High Speed Sampling 12-Bit ADCs
with Shutdown
Cost Effective 12-Bit ADCs with Convert Start Input
Best for 300ksps < f ≤ 600ksps
SAMPLE
Complete 3V 12-Bit ADC with
12mW Power Dissipation
Fully Specified for 3V-Powered Applications, f
≤ 140ksps
SAMPLE
LTC1409
LTC1410
Low Power 12-Bit, 800ksps Sampling ADC
Best Dynamic Performance, f
≤ 800ksps, 80mW Dissipation
SAMPLE
12-Bit, 1.25Msps Sampling ADC
with Shutdown
Best Dynamic Performance, THD = 84 and SINAD = 71 at Nyquist
LTC1419
LTC1605
14-Bit, 800ksps Sampling ADC
16-Bit, 100ksps Sampling ADC
81.5dB SINAD, 150mW from ±5V Supplies
Single Supply, ±10V Input Range, Low Power
1415f LT/TP 0497 7K • PRINTED IN USA
Linear Technology Corporation
●
1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900
24
●
●
LINEAR TECHNOLOGY CORPORATION 1996
FAX: (408) 434-0507 TELEX: 499-3977 www.linear-tech.com
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