LTC1418I [Linear]
Low Power, 14-Bit, 200ksps ADC with Serial and Parallel I/O; 低功耗， 14位，串行和并行I位200ksps ADC / O
| 型号： | LTC1418I |
| 厂家： | 
Linear |
| 描述： | Low Power, 14-Bit, 200ksps ADC with Serial and Parallel I/O |
| 文件： | 总28页 (文件大小：715K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1418
Low Power, 14-Bit, 200ksps
ADC with Serial and Parallel I/O
U
FEATURES
DESCRIPTION
The LTC®1418 is a low power, 200ksps, 14-bit A/D
converter. Data output is selectable for 14-bit parallel or
serial format. This versatile device can operate from a
single 5V or ±5V supply. An onboard high performance
sample-and-hold, a precision reference and internal tim-
ing minimize external circuitry requirements. The low
15mW power dissipation is made even more attractive
with two user selectable power shutdown modes.
■
Single Supply 5V or ±5V Operation
■
Sample Rate: 200ksps
■
±1.25LSB INL and ±1LSB DNL Max
■
Power Dissipation: 15mW (Typ)
■
Parallel or Serial Data Output
■
No Missing Codes Over Temperature
■
Power Shutdown: Nap and Sleep
■
External or Internal Reference
■
Differential High Impedance Analog Input
The LTC1418 converts 0V to 4.096V unipolar inputs from
a single 5V supply and ±2.048V bipolar inputs from ±5V
supplies. DC specs include ±1.25LSB INL, ±1LSB DNL
and no missing codes over temperature. Outstanding AC
performanceincludes82dBS/(N+D)and94dBTHDatthe
Nyquist input frequency of 100kHz.
■
Input Range: 0V to 4.096V or ±2.048V
■
81.5dB S/(N + D) and –94dB THD at Nyquist
■
28-Pin Narrow PDIP and SSOP Packages
U
APPLICATIONS
■
The flexible output format allows either parallel or serial I/O.
The SPI/MICROWIRETM compatible serial I/O port can oper-
ate as either master or slave and can support clock frequen-
cies from DC to 10MHz. A separate convert start input and
a data ready signal (BUSY) allow easy control of conversion
start and data transfer.
Remote Data Acquisition
Battery Operated Systems
Digital Signal Processing
Isolated Data Acquisition Systems
Audio and Telecom Processing
Medical Instrumentation
■
■
■
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
U
TYPICAL APPLICATION
Low Power, 200kHz, 14-Bit Sampling A/D Converter
5V
10µF
Typical INL Curve
V
DD
1.0
SER/PAR
LTC1418
S/H
D13
+
A
IN
0.5
D5
14
14-BIT ADC
SELECTABLE
SERIAL/
PARALLEL
PORT
–
A
IN
D4 (EXTCLKIN)
D3 (SCLK)
D2 (CLKOUT)
D1 (D
0
4.096V
BUFFER
)
OUT
REFCOMP
D0 (EXT/INT)
10µF
–0.5
BUSY
CS
8k
TIMING AND
LOGIC
2.5V
REFERENCE
V
RD
REF
CONVST
SHDN
–1.0
1µF
0
4096
8192
12288
16384
OUTPUT CODE
AGND
V
DGND
SS
(0V OR –5V)
1418 TA02
1418 TA01
1
LTC1418
W W
U W
U
W U
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Notes 1, 2)
TOP VIEW
ORDER PART
Supply Voltage (VDD)................................................. 6V
Negative Supply Voltage (VSS)
Bipolar Operation Only ........................... –6V to GND
Total Supply Voltage (VDD to VSS)
Bipolar Operation Only ....................................... 12V
Analog Input Voltage (Note 3)
Unipolar Operation .................. –0.3V to (VDD + 0.3V)
Bipolar Operation...........(VSS – 0.3V) to (VDD + 0.3V)
Digital Input Voltage (Note 4)
+
NUMBER
1
2
V
V
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
A
DD
IN
–
SS
IN
LTC1418ACG
LTC1418ACN
LTC1418AIG
LTC1418AIN
LTC1418CG
LTC1418CN
LTC1418IG
LTC1418IN
3
BUSY
V
REF
4
CS
REFCOMP
AGND
D13 (MSB)
D12
5
CONVST
RD
6
7
SHDN
8
SER/PAR
D0 (EXT/INT)
D11
9
D10
Unipolar Operation ................................–0.3V to 10V
Bipolar Operation.........................(VSS – 0.3V) to 10V
Digital Output Voltage
10
11
12
13
14
D1 (D )
OUT
D9
D2 (CLKOUT)
D3 (SCLK)
D4 (EXTCLKIN)
D5
D8
D7
D6
Unipolar Operation .................. –0.3V to (VDD + 0.3V)
Bipolar Operation...........(VSS – 0.3V) to (VDD + 0.3V)
Power Dissipation.............................................. 500mW
Operation Temperature Range
LTC1418C................................................ 0°C to 70°C
LTC1418I............................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
DGND
G PACKAGE
N PACKAGE
28-LEAD PLASTIC SSOP 28-LEAD NARROW PDIP
TJMAX = 110°C, θJA = 95°C/ W (G)
T
JMAX = 110°C, θJA = 100°C/ W (N)
Consult factory for Military grade parts.
U
CO VERTER
CHARACTERISTICS
With internal reference (Notes 5, 6) unless otherwise noted.
LTC1418
TYP
LTC1418A
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
Bits
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
●
●
●
●
13
14
(Note 7)
±0.8
±0.7
±5
±2
±0.5 ±1.25
LSB
±1.5
±20
±0.35
±2
±1
LSB
(Note 8)
±10
LSB
Full-Scale Error
Internal Reference
External Reference = 2.5V
±10
±5
±60
±30
±20
±5
±60
±15
LSB
LSB
Full-Scale Tempco
I
I
I
= 0, Internal Reference, Commercial
= 0, Internal Reference, Industrial
= 0, External Reference
●
±15
±10
±20
±1
±45
ppm/°C
ppm/°C
ppm/°C
OUT(REF)
OUT(REF)
OUT(REF)
±5
U
U
(Note 5)
A ALOG I PUT
SYMBOL PARAMETER
CONDITIONS
4.75V ≤ V ≤ 5.25V (Unipolar)
MIN
TYP
MAX
UNITS
V
Analog Input Range (Note 9)
●
●
0 to 4.096
±2.048
V
V
IN
DD
4.75V ≤ V ≤ 5.25V, –5.25V ≤ V ≤ –4.75V (Bipolar)
DD
SS
I
Analog Input Leakage Current
Analog Input Capacitance
CS = High
●
±1
µA
IN
C
Between Conversions (Sample Mode)
During Conversions (Hold Mode)
25
5
pF
pF
IN
t
Sample-and-Hold Acquisition Time Commercial
Industrial
●
●
300
300
1000
1000
ns
ns
ACQ
2
LTC1418
W
U
(Note 5)
DY
A IC
ACCURACY
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
81.5
–94
95
MAX
UNITS
dB
S/(N + D) Signal-to-Noise Plus Distortion Ratio
97.5kHz Input Signal
●
●
●
79
THD
SFDR
IMD
Total Harmonic Distortion
Spurious Free Dynamic Range
Intermodulation Distortion
Full Power Bandwidth
100kHz Input Signal, First 5 Harmonics
100kHz Input Signal
–86
dB
86
dB
f
= 97.7kHz, f = 104.2kHz
–90
5
dB
IN1
IN2
MHz
MHz
Full Linear Bandwidth
S/(N + D) ≥ 77dB
0.5
U U
U
(Note 5)
I TER AL REFERE CE CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
TYP
MAX
2.520
±45
UNITS
V
V
Output Voltage
Output Tempco
I
= 0
2.480
2.500
V
REF
REF
OUT
I
I
= 0, Commercial
= 0, Industrial
●
±10
±20
ppm/°C
ppm/°C
OUT
OUT
V
V
Line Regulation
4.75V ≤ V ≤ 5.25V
0.05
0.05
LSB/V
LSB/V
REF
REF
DD
–5.25V ≤ V ≤ –4.75V
SS
Output ResistanceU
U
0.1mA ≤
I
≤ 0.1mA
8
kΩ
OUT
(Note 5)
DIGITAL I PUTS AND OUTPUTS
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
V
= 5.25V
= 4.75V
= 0V to V
●
●
●
2.4
V
V
IH
IL
DD
DD
IN
0.8
I
±10
µA
pF
IN
DD
C
V
Digital Input Capacitance
High Level Output Voltage
1.4
IN
V
V
= 4.75V, I = –10µA
= 4.75V, I = –200µA
4.74
V
V
OH
DD
DD
O
O
●
4.0
V
Low Level Output Voltage
V
V
= 4.75V, I = 160µA
0.05
0.10
V
V
OL
DD
DD
O
= 4.75V, I = 1.6mA
●
●
●
0.4
±10
15
O
I
Hi-Z Output Leakage D13 to D0
Hi-Z Output Capacitance D13 to D0
Output Source Current
V
= 0V to V , CS High
µA
pF
OZ
OUT
DD
C
CS High (Note 9)
OZ
I
I
V
V
= 0V
–10
10
mA
mA
SOURCE
SINK
OUT
OUT
Output Sink Current
= V
DD
U
W
(Note 5)
POWER REQUIRE E TS
SYMBOL PARAMETER
CONDITIONS
MIN
4.75
TYP
MAX
UNITS
V
V
Positive Supply Voltage (Notes 10, 11)
Negative Supply Voltage (Note 10)
Positive Supply Current
5.25
V
V
DD
SS
Bipolar Only (V = 0V for Unipolar)
–4.75
–5.25
SS
I
I
Unipolar, RD High (Note 5)
Bipolar, RD High (Note 5)
SHDN = 0V, CS = 0V (Note 12)
SHDN = 0V, CS = 5V (Note 12)
●
●
3.0
3.9
570
2
4.3
4.5
mA
mA
µA
DD
Nap Mode
Sleep Mode
µA
Negative Supply Current
Power Dissipation
Bipolar, RD High (Note 5)
SHDN = 0V, CS = 0V (Note 12)
SHDN = 0V, CS = 5V (Note 12)
●
1.4
0.1
0.1
1.8
mA
µA
µA
SS
Nap Mode
Sleep Mode
P
Unipolar
Bipolar
●
●
15.0
26.5
21.5
31.5
mW
mW
DIS
3
LTC1418
W U
TI I G CHARACTERISTICS (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
kHz
µs
f
t
t
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Conversion Time
●
●
●
●
●
●
●
200
SAMPLE(MAX)
CONV
3.4
0.3
3.7
4
1
5
Acquisition Time
µs
ACQ
+ t
Acquisition Plus Conversion Time
CS to RD Setup Time
µs
ACQ
1
CONV
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Note 10)
0
ns
CS↓ to CONVST↓ Setup Time
CS↓ to SHDN↓ Setup Time to Ensure Nap Mode
SHDN↑ to CONVST↓ Wake-Up Time from Nap Mode
CONVST Low Time
40
40
ns
2
ns
3
500
ns
4
(Notes 10, 11)
CL = 25pF
●
●
40
ns
5
CONVST to BUSY Delay
35
35
70
ns
6
Data Ready Before BUSY↑
20
15
ns
ns
7
●
●
●
t
t
t
Delay Between Conversions
Wait Time RD↓ After BUSY↑
Data Access Time After RD↓
(Note 10)
500
–5
ns
ns
8
9
C = 25pF
L
15
20
8
30
40
ns
ns
10
●
●
C = 100pF
L
40
55
ns
ns
t
Bus Relinquish Time
20
25
30
ns
ns
ns
11
Commercial
Industrial
●
●
t
t
t
t
f
f
t
t
t
t
t
RD Low Time
●
t
ns
ns
12
13
14
15
10
CONVST High Time
40
Delay Time, SCLK↓ to D
Valid
C = 25pF (Note 9)
●
●
35
25
70
ns
OUT
L
Time from Previous Data Remain Valid After SCLK↓
Shift Clock Frequency
C = 25pF (Note 9)
L
15
0
ns
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
12.5
4.5
MHz
MHz
µs
SCLK
External Conversion Clock Frequency
Delay Time, CONVST↓ to External Conversion Clock Input
SCLK High Time
0.03
EXTCLKIN
dEXTCLKIN
H SCLK
533
10
20
ns
SCLK Low Time
ns
L SCLK
EXTCLKIN High Time
250
250
ns
H EXTCLKIN
L EXTCLKIN
EXTCLKIN Low Time
ns
The
●
denotes specifications which apply over the full operating
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
temperature range; all other limits and typicals T = 25°C.
A
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion, it can create small
errors. For best performance ensure that CONVST returns high either
within 2.1µs after the conversion starts or after BUSY rises.
Note 3: When these pin voltages are taken below V or above V , they
SS
DD
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V or above V without latchup.
SS
CC
Note 4: When these pin voltages are taken below V they will be clamped
SS
by internal diodes. This product can handle input currents greater than
100mA below V without latchup. These pins are not clamped to V
.
SS
DD
Note 5: V = 5V, V = 0V or –5V, f
= 200kHz, t = t = 5ns unless
Note 12: Pins 16 (D4/EXTCLKIN), 17 (D3/SCLK) and 20 (DO/EXT/INT) at
0V or 5V. See Power Shutdown.
DD
SS
SAMPLE
r f
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
–
ended input with A grounded.
IN
4
LTC1418
U W
TYPICAL PERFORMANCE CHARACTERISTICS
Differential Nonlinearity
vs Output Code
S/(N + D) vs Input Frequency
and Amplitude
Typical INL Curve
90
80
70
60
50
40
30
20
10
0
1.0
0.5
1.0
0.5
0
V
= 0dB
IN
V
= –20dB
IN
0
V
IN
= –60dB
–0.5
–0.5
–1.0
–1.0
0
4096
8192
OUTPUT CODE
12288
16384
1k
10k
100k
1M
0
4096
8192
OUTPUT CODE
12288
16384
INPUT FREQUENCY (Hz)
1418 G01
1418 G06
1418 TA02
Signal-to-Noise Ratio
vs Input Frequency
Spurious-Free Dynamic Range
vs Input Frequency
Distortion vs Input Frequency
0
–20
90
80
70
60
50
40
30
20
10
0
0
–20
–40
–40
–60
–60
3RD
THD
–80
–80
2ND
–100
–120
–100
–120
10k
100k
1M
1k
10k
100k
1M
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
1418 G04
1418 G02
1418 G03
Nonaveraged, 4096 Point FFT,
Input Frequency = 10kHz
Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
Intermodulation Distortion Plot
0
0
–20
0
–20
f
f
f
= 200kHz
SAMPLE
IN1
IN2
f
f
= 200kHz
f
f
= 200kHz
SAMPLE
IN
SAMPLE
IN
= 97.65625kHz
= 97.509765kHz
= 9.9609375kHz
–20
–40
= 104.248046kHz
SFDR = 94.29
SINAD = 81.4
SFDR = 99.32
SINAD = 82.4
–40
–40
–60
–60
–60
–80
–80
–80
–100
–120
–100
–120
–100
–120
60 70
FREQUENCY (kHz)
0
10 20 30 40 50
80 90 100
0
10 20 30 40 50 60 70 80 90 100
FREQUENCY (kHz)
0
10 20 30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 G05
1418 F02b
1418 F02a
5
LTC1418
TYPICAL PERFORMANCE CHARACTERISTICS
U W
Power Supply Feedthrough
vs Ripple Frequency
Input Offset Voltage Shift
vs Source Resistance
Input Common Mode Rejection
vs Input Frequency
0
–20
10
9
8
7
6
5
4
3
2
1
0
90
80
70
60
50
40
30
20
10
0
–40
–60
V
V
SS
DD
–80
DGND
–100
–120
10
100
1k
10k
100k
1M
1k
10k
100k
1M
10M
1
10
100
1k
1M
10k 100k
INPUT SOURCE RESISTANCE (Ω)
FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
1418 G10
1418 G08
1418 G09
VDD Supply Current vs
Temperature (Bipolar Mode)
V
DD Supply Current vs
VSS Supply Current vs
Temperature (Bipolar Mode)
Temperature (Unipolar Mode)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
5
4
3
2
1
0
5
4
3
2
1
0
125
125
–75 –50
0
25 50
100
150
125
100 150
–75 –50
0
25 50
100
150
–25
75
–75 –50
0
25 50
–25
75
–25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1418 G12
1418 G11
1418 G13
VDD Supply Current vs Sampling
Frequency (Bipolar Mode)
VDD Supply Current vs Sampling
Frequency (Unipolar Mode)
VSS Supply Current vs Sampling
Frequency (Bipolar Mode)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
5
4
3
2
1
0
5
4
3
2
1
0
0
100
150
200
250
300
50
0
50
150
200
250
300
0
50
150
200
250
300
100
100
SAMPLING FREQUENCY (kHz)
SAMPLING FREQUENCY (kHz)
SAMPLING FREQUENCY (kHz)
1418 G14
1418 G15
1418 G16
6
LTC1418
U
U
U
PIN FUNCTIONS
AIN+ (Pin 1): Positive Analog Input.
AIN– (Pin 2): Negative Analog Input.
the internal conversion clock. An input high indicates an
external conversion clock will be assigned to Pin 16
(EXTCLKIN).
VREF (Pin 3): 2.50V Reference Output. Bypass to AGND
with 1µF.
SER/PAR (Pin 21): Data Output Mode.
SHDN (Pin 22): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for nap
mode and CS = 1 for sleep mode.
REFCOMP (Pin 4): 4.096V Reference Bypass Pin.
Bypass to AGND with 10µF tantalum in parallel with 0.1µF
ceramic.
RD (Pin 23): Read Input. This enables the output drivers
when CS is low.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs
(Parallel). D13 is the most significant bit.
CONVST(Pin24):ConversionStartSignal.Thisactivelow
signal starts a conversion on its falling edge.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
CS (Pin 25): Chip Select. This input must be low for the
ADC to recognize the CONVST and RD inputs. CS also sets
the shutdown mode when SHDN goes low. CS and SHDN
low select the quick wake-up nap mode. CS high and
SHDN low select sleep mode.
D5 (Pin 15): Three-State Data Output (Parallel).
D4 (EXTCLKIN) (Pin 16): Three-State Data Output
(Parallel). Conversion clock input (serial) when Pin 20
(EXT/INT) is tied high.
BUSY (Pin 26): The BUSY Output Shows the Converter
Status. It is low when a conversion is in progress.
D3 (SCLK) (Pin 17): Three-State Data Output (Parallel).
Data clock input (serial).
V
SS (Pin 27): Negative Supply, –5V for Bipolar Operation.
D2(CLKOUT)(Pin18):Three-StateDataOutput(Parallel).
Conversion clock output (serial).
Bypass to AGND with 10µF tantalum in parallel with 0.1µF
ceramic. Analog ground for unipolar operation.
D1 (DOUT) (Pin 19): Three-State Data Output (Parallel).
Serial data output (serial).
VDD (Pin 28): 5V Positive Supply. Bypass to AGND with
10µF tantalum in parallel with 0.1µF ceramic.
D0(EXT/INT)(Pin20): Three-StateDataOutput(Parallel).
Conversion clock selector (serial). An input low enables
TEST CIRCUITS
Load Circuits for Access Timing
Load Circuits for Output Float Delay
5V
5V
1k
1k
DBN
DBN
DBN
DBN
30pF
1k
C
L
C
1k
30pF
L
DGND
DGND
B) V TO HI-Z
OL
A) HI-Z TO V AND V TO V
B) HI-Z TO V AND V TO V
A) V TO HI-Z
OH
OH OL
OH
OL OH
OL
1418 TC02
1418 TC01
7
LTC1418
U
U
W
FUNCTIONAL BLOCK DIAGRA
C
SAMPLE
SAMPLE
+
A
IN
V
V
: 5V
DD
C
: 0V FOR UNIPOLAR MODE
–5V FOR BIPOLAR MODE
SS
–
A
IN
8k
2.5V
ZEROING SWITCHES
V
2.5V REF
REF
+
REF AMP
COMP
14-BIT CAPACITIVE DAC
–
4.096V
REFCOMP
AGND
14
D13
D0
SUCCESSIVE APPROXIMATION
REGISTER
SHIFT
REGISTER
•
•
•
D3/(SCLK)
D1/(D
INTERNAL
CLOCK
CONTROL LOGIC
MUX
DGND
)
OUT
1418 BD
D4 (EXTCLKIN) D0 (EXT/INT) SHDN CONVST RD CS SER/PAR D2/(CLKOUT) BUSY
NOTE: PIN NAMES IN PARENTHESES
REFER TO SERIAL MODE
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APPLICATIONS INFORMATION
+
–
CONVERSION DETAILS
C
SAMPLE
SAMPLE
SAMPLE
SAMPLE
+
–
A
A
IN
IN
ZEROING SWITCHES
HOLD
The LTC1418 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel or serial output. The ADC
is complete with a precision reference and an internal
clock. The control logic provides easy interface to micro-
processors and DSPs (please refer to Digital Interface
section for the data format).
HOLD
C
HOLD
HOLD
+
C
DAC
+
–
C
DAC
COMP
+
V
DAC
–
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
–
14
V
D13
DAC
OUTPUT
LATCH
SAR
D0
1418 F01
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
Figure 1. Simplified Block Diagram
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0
–20
+
–
Referring to Figure 1, the AIN and AIN inputs are con-
nected to the sample-and-hold capacitors (CSAMPLE) dur-
ingtheacquirephase andthecomparatoroffsetisnulledby
the zeroing switches. In this acquire phase, a minimum
delay of 1µs will provide enough time for the sample-and-
hold capacitors to acquire the analog signal. During the
convert phase the comparator zeroing switches open,
putting the comparator into compare mode. The input
switches the CSAMPLE capacitors to ground, transferring
the differential analog input charge onto the summing
junction. This input charge is successively compared with
the binary weighted charges supplied by the differential
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the differential
DAC output balances the AIN+ and AIN– input charges. The
SAR contents (a 14-bit data word) which represent the
f
f
= 200kHz
SAMPLE
IN
= 9.9609375kHz
SFDR = 99.32
SINAD = 82.4
–40
–60
–80
–100
–120
0
10 20 30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 F02a
Figure 2a. LTC1418 Nonaveraged, 4096 Point FFT,
Input Frequency = 10kHz
0
+
–
f
f
= 200kHz
SAMPLE
IN
difference of AIN and AIN are loaded into the 14-bit
output latches.
= 97.509765kHz
–20
–40
SFDR = 94.29
SINAD = 81.4
DYNAMIC PERFORMANCE
–60
The LTC1418 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
to testtheADC’sfrequencyresponse, distortionand noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 2 shows a
typical LTC1418 FFT plot.
–80
–100
–120
0
10 20 30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 F02b
Figure 2b. LTC1418 Nonaveraged, 4096 Point FFT,
Input Frequency = 97.5kHz
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure 2a shows a typical spectral content with
a 200kHz sampling rate and a 10kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 100kHz.
Effective Number of Bits
The effective number of bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 200kHz the LTC1418 maintains near ideal ENOBs
up to the Nyquist input frequency of 100kHz (refer to
Figure 3).
9
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14
13
12
11
10
9
shown in Figure 4. The LTC1418 has good distortion
performance up to the Nyquist frequency and beyond.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
8
7
6
5
4
3
2
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include
(fa + fb). If the two input sine waves are equal in magni-
tude, thevalue(indecibels)ofthe2ndorderIMDproducts
can be expressed by the following formula:
1418 F03
Figure 3. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
Amplitude at fa+ fb
(
)
IMD fa + fb = 20Log
Amplitude at fa
2
2
2
2
V2 + V3 + V4 +...Vn
0
–20
THD = 20Log
f
f
f
= 200kHz
SAMPLE
IN1
IN2
V1
= 97.65625kHz
= 104.248046kHz
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
secondthroughnthharmonics.THDvsInputFrequencyis
–40
–60
–80
0
–20
–40
–60
–100
–120
60 70
0
10 20 30 40 50
80 90 100
FREQUENCY (kHz)
1418 G05
3RD
–80
Figure 5. Intermodulation Distortion Plot
THD
2ND
–100
–120
Peak Harmonic or Spurious Noise
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
1418 G03
Figure 4. Distortion vs Input Frequency
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small-signal settling for full throughput rate. If slower op
amps are used, more settling time can be provided by
increasing the time between conversions.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
The best choice for an op amp to drive the LTC1418 will
depend on the application. Generally, applications fall into
two categories: AC applications where dynamic specifica-
tionsaremostcriticalandtimedomainapplicationswhere
DC accuracy and settling time are most critical. The
followinglistisasummaryoftheopampsthataresuitable
for driving the LTC1418. More detailed information is
available in the Linear Technology Databooks and on the
LinearViewTM CD-ROM.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 77dB (12.5 effective bits).
The LTC1418 has been designed to optimize input band-
width, allowingtheADCtoundersampleinputsignalswith
frequenciesabovetheconverter’sNyquistFrequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
LT®1354: 12MHz, 400V/µs Op Amp. 1.25mA maximum
supply current. Good AC and DC specifications. Suitable
for dual supply application.
DRIVING THE ANALOG INPUT
The differential analog inputs of the LTC1418 are easy to
drive.Theinputsmaybedrivendifferentiallyorasasingle-
ended input (i.e., theAIN– inputisgrounded). The AIN+ and
LT1357: 25MHz, 600V/µs Op Amp. 2.5mA maximum
supply current. Good AC and DC specifications. Suitable
for dual supply application.
–
AIN inputs are sampled at the same instant. Any
unwanted signal that is common mode to both inputs will
be reduced by the common mode rejection of the sample-
and-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low then the LTC1418
inputs can be driven directly. As source impedance
increases so will acquisition time (see Figure 6). For
minimum acquisition time, with high source impedance, a
bufferamplifiermustbeused.Theonlyrequirementisthat
the amplifier driving the analog input(s) must settle after
thesmallcurrentspikebeforethenextconversionstarts—
1µs for full throughput rate.
LT1366/LT1367: Dual/Quad Precision Rail-to-Rail Input
and Output Op Amps. 375µA supply current per amplifier.
1.8V to ±15V supplies. Low input offset voltage: 150µV.
Good for low power and single supply applications with
sampling rates of 20ksps and under.
LT1498/LT1499: 10MHz, 6V/µs, Dual/Quad Rail-to-Rail
Input and Output Op Amps. 1.7mA supply current per
100
10
1
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
aretakenintoconsideration.First,chooseanamplifierthat
has a low output impedance (<100Ω) at the closed-loop
bandwidth frequency. For example, if an amplifier is used
in a gain of 1 and has a closed-loop bandwidth of 10MHz,
then the output impedance at 10MHz must be less than
100Ω. The second requirement is that the closed-loop
bandwidth must be greater than 5MHz to ensure adequate
0.1
1
10
100
1k
10k
100k
SOURCE RESISTANCE (Ω)
1418 F06
Figure 6. tACQ vs Source Resistance
LinearView is a trademark of Linear Technology Corporation.
11
LTC1418
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amplifier. 2.2V to ±15V supplies. Good AC performance,
input noise voltage = 12nV/√Hz (typ).
Input Range
The ±2.048V and 0V to 4.096V input ranges of the
LTC1418 are optimized for low noise and low distortion.
Most op amps also perform well over these ranges,
allowing direct coupling to the analog inputs and eliminat-
ing the need for special translation circuitry.
LT1630/LT1631: 30MHz, 10V/µs, Dual/Quad Rail-to-Rail
Input and Output Precision Op Amps. 3.5mA supply
current per amplifier. 2.7V to ±15V supplies. Best AC
performance, input noise voltage = 6nV/√Hz (typ),
THD = –86dB at 100kHz.
Some applications may require other input ranges. The
LTC1418 differential inputs and reference circuitry can
accommodate other input ranges often with little or no
additional circuitry. The following sections describe the
reference and input circuitry and how they affect the input
range.
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1418 noise and distortion. The small-signal band-
widthofthesample-and-holdcircuitis5MHz. Anynoiseor
distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For example, Figure 7 shows a 2000pF
capacitorfrom +AIN togroundanda100Ωsourceresistor
to limit the input bandwidth to 800kHz. The 2000pF
capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sam-
pling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors
haveexcellentlinearity.Carbonsurfacemountresistorscan
also generate distortion from self heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
INTERNAL REFERENCE
The LTC1418 has an on-chip, temperature compensated,
curvature corrected, bandgap reference which is factory
trimmedto2.500V.Itisinternallyconnectedtoareference
amplifier and is available at Pin 3. A 8k resistor is in series
with the output so that it can be easily overdriven in
applications where an external reference is required, see
Figure 8. The reference amplifier compensation pin
(REFCOMP, Pin 4) must be connected to a capacitor to
ground. The reference is stable with capacitors of 1µF or
greater. For the best noise performance, a 10µF in parallel
with a 0.1µF ceramic is recommended.
The VREF pin can be driven with a DAC or other means
to provide input span adjustment. The reference should
be kept in the range of 2.25V to 2.75V for specified
linearity.
5V
100Ω
1
2
3
4
5
+
–
A
A
V
ANALOG INPUT
IN
IN
2000pF
V
DD
1
2
3
4
+
–
A
A
V
IN
5V
ANALOG
INPUT
LTC1418
IN
REF
V
IN
LTC1418
V
OUT
REFCOMP
AGND
REF
10µF
LT1460
REFCOMP
AGND
1418 F07
0.1µF
10µF
5
1418 F08
Figure 7. RC Input Filter
Figure 8. Using the LT1460 as an External Reference
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scale error adjustment. Zero offset is achieved by adjust-
ing the offset applied to the AIN– input. For zero offset
error apply 125µV (i.e., 0.5LSB) at the input and adjust
the offset at the AIN– input until the output code flickers
between00000000000000and00000000000001. For
full-scale adjustment, an input voltage of 4.095625V
(FS – 1.5LSBs) is applied to AIN+ and R2 is adjusted until
the output code flickers between 1111 1111 1111 10 and
1111 1111 1111 11.
UNIPOLAR / BIPOLAR OPERATION AND ADJUSTMENT
Figure 9a shows the ideal input/output characteristics for
theLTC1418. Thecodetransitionsoccurmidwaybetween
successive integer LSB values (i.e., 0.5LSB, 1.5LSB,
2.5LSB,…FS–1.5LSB).Theoutputcodeisnaturalbinary
with1LSB=FS/16384=4.096V/16384=250µV.Figure9b
shows the input/output transfer characteristics for the
bipolar mode in two’s complement format.
Unipolar Offset and Full-Scale Error Adjustment
Bipolar Offset and Full-Scale Error Adjustment
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figures
10aand10bshowtheextracomponentsrequiredforfull-
Bipolaroffsetandfull-scaleerrorsareadjustedinasimilar
fashion to the unipolar case. Again, bipolar offset error
must be adjusted before full-scale error. Bipolar offset
FS
4.096V
R7
R8
1LSB =
=
111...111
111...110
111...101
111...100
16384 16384
48k
5V
100Ω
ANALOG INPUT
R3
V
1
DD
R1
50k
+
–
A
IN
IN
R4
2
3
4
5
24k
100Ω
A
V
LTC1418
R5 R2
47k 50k
REF
UNIPOLAR
ZERO
R6
24k
REFCOMP
AGND
000...011
000...010
000...001
000...000
V
SS
0.1µF
10µF
1418 F10a
0V
1
LSB
FS – 1LSB
INPUT VOLTAGE (V)
1418 F9a
Figure 10a. Offset and Full-Scale Adjust Circuit
If –5V Is Not Available
Figure 9a. LTC1418 Unipolar Transfer Characteristics
–5V
5V
011...111
ANALOG INPUT
BIPOLAR
ZERO
V
DD
011...110
1
2
3
4
5
R1
50k
+
–
A
A
V
IN
IN
R3
24k
R4
100Ω
000...001
000...000
111...111
111...110
LTC1418
R5 R2
47k 50k
REF
R6
24k
REFCOMP
AGND
V
SS
0.1µF
100...001
100...000
10µF
FS = 4.096V
1LSB = FS/16384
1418 F10b
*
1N5817
*ONLY NEEDED IF V GOES
SS
ABOVE GROUND
–5V
–1 0V
LSB
1
LSB
–FS/2
FS/2 – 1LSB
INPUT VOLTAGE (V)
1418 F9b
Figure 10b. Offset and Full-Scale Adjust Circuit
If –5V Is Available
Figure 9b. LTC1418 Bipolar Transfer Characteristics
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nected to this analog ground plane. Low impedance ana-
loganddigitalpowersupplycommonreturnsareessential
to low noise operation of the ADC and the foil width for
these tracks should be as wide as possible. In applications
where the ADC data outputs and control signals are
connected to a continuously active microprocessor bus, it
is possible to get errors in the conversion results. These
errors are due to feedthrough from the microprocessor to
the successive approximation comparator. The problem
can be eliminated by forcing the microprocessor into a
wait state during conversion or by using three-state buff-
ers to isolate the ADC data bus. The traces connecting the
pins and bypass capacitors must be kept short and should
be made as wide as possible.
error adjustment is achieved by adjusting the offset
–
applied to the AIN input. For zero offset error apply
+
–125µV (i.e., –0.5LSB) at AIN and adjust the offset
–
at the AIN input until the output code flickers between
0000 0000 0000 00 and 1111 1111 1111 11. For
full-scale adjustment, an input voltage of 2.047625V
(FS – 1.5LSBs) is applied to AIN+ and R2 is adjusted until
the output code flickers between 0111 1111 1111 10 and
0111 1111 1111 11.
BOARD LAYOUT AND GROUNDING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1418, a printed circuit board
with ground plane is required. The ground plane under the
ADC area should be as free of breaks and holes as
possible, such that a low impedance path between all ADC
grounds and all ADC decoupling capacitors is provided. It
iscriticaltopreventdigitalnoisefrombeingcoupledtothe
analog input, reference or analog power supply lines.
Layout should ensure that digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track.
The LTC1418 has differential inputs to minimize noise
coupling. Common mode noise on the AIN+ and AIN– leads
will be rejected by the input CMRR. The AIN– input can be
usedasagroundsensefortheAIN+ input;theLTC1418will
hold and convert the difference voltage between AIN+ and
AIN–. The leads to AIN+ (Pin 1) and AIN– (Pin 2) should be
kept as short as possible. In applications where this is not
possible, the AIN+ and AIN– traces should be run side by
side to equalize coupling.
SUPPLY BYPASSING
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND) and Pin 14 (DGND) and all other analog
groundsshouldbeconnectedtothissingleanalogground
plane. The REFCOMP bypass capacitor and the VDD by-
pass capacitor should also be connected to this analog
ground plane. No other digital grounds should be con-
High quality, low series resistance ceramic, 10µF bypass
capacitors should be used at the VDD and REFCOMP pins.
Surface mount ceramic capacitors such as Murata
GRM235Y5V106Z016 provide excellent bypassing in a
small board space. Alternatively 10µF tantalum capacitors
in parallel with 0.1µF ceramic capacitors can be used.
1
+
DIGITAL
SYSTEM
LTC1418
REFCOMP AGND
A
IN
–
A
IN
V
V
V
DD
DGND
14
REF
SS
ANALOG
INPUT
CIRCUITRY
2
3
4
5
27
10µF
28
10µF
+
–
1µF
10µF
ANALOG GROUND PLANE
1418 F11
Figure 11. Power Supply Grounding Practice
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APPLICATIONS INFORMATION
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1418 F12b
Figure 12b. Suggested Evaluation Circuit Board— Component Side Top Silkscreen
1418 F12c
Figure 12c. Suggested Evaluation Circuit Board—Top Layer
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1418 F12d
Figure 12d. Suggested Evaluation Circuit Board—Solder Side Layout
Internal Clock
Bypass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitorsmustbekeptshortandshouldbemadeaswide
as possible.
The ADC has an internal clock. In parallel output mode the
internal clock is always used as the conversion clock. In
serial output mode either the internal clock or an external
clockmaybeusedastheconversionclock(seeFigure20).
The internal clock is factory trimmed to achieve a typical
conversion time of3.4µs and a maximumconversiontime
over the full operating temperature range of 4µs. No exter-
naladjustmentsarerequired,andwiththeguaranteedmaxi-
mum acquisition time of 1µs, throughput performance of
200ksps is assured.
Example Layout
Figures 12a, 12b, 12c and 12d show the schematic and
layoutofasuggestedevaluationboard.Thelayoutdemon-
stratestheproperuseofdecouplingcapacitorsandground
plane with a 2-layer printed circuit board.
DIGITAL INTERFACE
Power Shutdown
The LTC1418 can operate in serial or parallel mode. In
parallel mode the ADC is designed to interface with micro-
processors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. In serial mode only four digital interface lines
are required, SCLK, CONVST, EXTCLKIN and DOUT. SCLK,
the serial data shift clock can be an external input or
supplied by the LTC1418 internal clock.
The LTC1418 provides two power shutdown modes, nap
andsleep, tosavepowerduringinactiveperiods. Thenap
mode reduces the power by 80% and leaves only the
digitallogicandreferencepoweredup. Thewake-uptime
from nap to active is 500ns (see Figure 13a). In sleep
mode all bias currents are shut down and only leakage
current remains—about 2µA. Wake-up time from sleep
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mode is much slower since the reference circuit must
power up and settle to 0.005% for full 14-bit accuracy.
Sleep mode wake-up time is dependent on the value of
the capacitor connected to the REFCOMP (Pin 4). The
wake-up time is 30ms with the recommended 10µF
capacitor. Shutdown is controlled by Pin 22 (SHDN); the
ADC is in shutdown when it is low. The shutdown mode
is selected with Pin 25 (CS); low selects nap (see Figure
13b), high selects sleep.
CS
CONVST
RD
t
2
t
1
1418 F14
Figure 14. CS to CONVST Set-Up Timing
or serial data formats, outputs will be active only when CS
and RD are low. Any other combination of CS and RD will
three-state the output. In unipolar mode (VSS = 0V) the
datawillbeinstraightbinaryformat(correspondingtothe
unipolar input range). In bipolar mode (VSS = –5V), the
datawillbeintwo’scomplementformat(correspondingto
the bipolar input range).
SHDN
t
4
CONVST
1418 F13a
Figure 13a. SHDN to CONVST Wake-Up Timing
Parallel Output Mode
CS
Parallel mode is selected with a logic 0 applied to the
SER/PARpin.Figures15through19showdifferentmodes
of parallel output operation. In modes 1a and 1b (Figures
15 and 16) CS and RD are both tied low. The falling edge
of CONVST starts the conversion. The data outputs are
always enabled and data can be latched with the BUSY
rising edge. Mode 1a shows operation with a narrow logic
low CONVST pulse. Mode 1b shows a narrow logic high
CONVST pulse.
t
3
SHDN
1418 F13b
Figure 13b. CS to SHDN Timing
Conversion Control
Conversion start is controlled by the CS and CONVST
inputs.AfallingedgeofCONVSTpinwillstartaconversion
after the ADC has been selected (i.e., CS is low, see Figure
14). Once initiated, it cannot be restarted until the conver-
sion is complete. Converter status is indicated by the
BUSY output. BUSY is low during a conversion.
In mode 2 (Figure 17) CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the RD signal.
Mode 2 can be used for operation with a shared databus.
In slow memory and ROM modes (Figures 18 and 19), CS
istiedlowandCONVSTandRDaretiedtogether. TheMPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
Data Output
The data format is controlled by the SER/PAR input pin;
logic low selects parallel output format. In parallel mode
the14-bitdataoutputwordD0toD13isupdatedattheend
of each conversion on Pins 6 to 13 and Pins 15 to 20. A
logic high applied to SER/PAR selects the serial formatted
data output and Pins 16 to 20 assume their serial function,
Pins 6 to 13 and 15 are in the Hi-Z state. In either parallel
InslowmemorymodetheprocessortakesRD(=CONVST)
low and starts the conversion. BUSY goes low forcing the
processorintoawaitstate.Thepreviousconversionresult
appears on the data outputs. When the conversion is
complete, the new conversion results appear on the data
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CS = RD = 0
CONVST
t
CONV
(SAMPLE N)
t
5
t
t
8
6
BUSY
DATA
t
7
DATA (N – 1)
DB13 TO DB0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
1418 F15
Figure 15. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
t
13
t
CS = RD = 0
CONV
t
5
CONVST
t
t
8
6
t
6
BUSY
t
7
DATA (N – 1)
DB13 TO DB0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
DATA
1418 F16
Figure 16. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
t
(SAMPLE N)
CS = 0
12
t
t
8
CONV
t
5
CONVST
BUSY
RD
t
6
t
t
11
9
t
12
t
10
DATA N
DB13 TO DB0
DATA
1418 F17
Figure 17. Mode 2. CONVST Starts a Conversion. Data is Read by RD
19
LTC1418
U
W U U
APPLICATIONS INFORMATION
CS = 0
t
t
8
CONV
(SAMPLE N)
RD = CONVST
t
6
t
11
BUSY
DATA
t
t
7
10
DATA (N – 1)
DB13 TO DB0
DATA N
DB13 TO DB0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
1418 F18
Figure 18. Slow Memory Mode Timing
CS = 0
t
t
8
CONV
(SAMPLE N)
RD = CONVST
BUSY
t
t
11
6
t
10
DATA (N – 1)
DB13 TO DB0
DATA N
DB13 TO DB0
DATA
1418 F19
Figure 19. ROM Mode Timing
eitherbeforethenextconversionstartsoritcanbeclocked
out during the next conversion. To enable the serial data
output buffer and shift clock, CS and RD must be low.
outputs; BUSY goes high releasing the processor and the
processor takes RD (= CONVST) back high and reads the
new conversion data.
Figure 20 shows a function block diagram of the LTC1418
in serial mode. There are two pieces to this circuitry: the
conversion clock selection circuit (EXT/INT, EXTCLKIN
andCLKOUT)andtheserialport(SCLK,DOUT,CSandRD).
In ROM mode, the processor takes RD (= CONVST) low,
startingaconversionandreadingthepreviousconversion
result. Aftertheconversioniscomplete, theprocessorcan
read the new result and initiate another conversion.
Conversion Clock Selection (Serial Mode)
Serial Output Mode
In Figure 20, the conversion clock controls the internal
ADC operation. The conversion clock can be either inter-
nal or external. By connecting EXT/INT low, the internal
clock is selected. This clock generates 16 clock cycles
which feed into the SAR for each conversion.
Serial output mode is selected when the SER/PAR input
pin is high. In this mode, Pins 16 to 20, D0 (EXT/INT), D1
(DOUT), D2 (CLKOUT), D3 (SCLK) and D4 (EXTCLKIN)
assume their serial functions as shown in Figure 20.
(During this discussion these pins will be referred to by
their serial function names: EXT/INT, DOUT, CLKOUT,
SCLK and EXTCLKIN.) As in parallel mode, conversions
are started by a falling CONVST edge with CS low. After a
conversion is completed and the output shift register has
been updated, BUSY will go high and valid data will be
available on DOUT (Pin 19). This data can be clocked out
To select an external conversion clock, tie EXT/INT high
and apply an external conversion clock to EXTCLKIN (Pin
16). (When an external shift clock (SCLK) is used during
a conversion, the SCLK should be used as the external
conversion clock to avoid the noise generated by the
20
LTC1418
U
W U U
APPLICATIONS INFORMATION
• • •
17
23
25
SCLK*
RD
CLOCK
INPUT
DATA
IN
14
DATA
OUT
SHIFT
REGISTER
CS
THREE
STATE
BUFFER
19
D
OUT
*
SAR
16 CONVERSION CLOCK CYCLES
THREE
STATE
BUFFER
18
CLKOUT*
• • •
EOC
16
20
EXTCLKIN*
EXT/INT*
INTERNAL
CLOCK
26
BUSY
*PINS 16 TO 20 ARE LABELED WITH THEIR SERIAL FUNCTIONS
1418 F20
Figure 20. Functional Block Diagram for Serial Mode (SER/PAR = High)
asynchronous clocks. To maintain accuracy the external
conversion clock frequency must be between 30kHz and
4.5MHz.) The SAR sends an end of conversion signal,
EOC, thatgatestheexternalconversionclocksothatonly
16 clock cycles can go into the SAR, even if the external
clock, EXTCLKIN, contains more than 16 cycles.
The SCLK is used to clock the shift register. Data may be
clocked out with the internal conversion clock operating
asamasterbyconnectingCLKOUT(Pin18)toSCLK(Pin
17) or with an external data clock applied to D3 (SCLK).
The minimum number of SCLK cycles required to
transfer a data word is 14. Normally, SCLK contains 16
clockcyclesforawordlengthof16bits;14bitswithMSB
first, followed by two trailing zeros.
When CS and RD are low, these 16 cycles of conversion
clock (whether internally or externally generated) will
appear on CLKOUT during each conversion and then
CLKOUT will remain low until the next conversion. If
desired, CLKOUT can be used as a master clock to drive
the serial port. Because CLKOUT is running during the
conversion,itisimportanttoavoidexcessiveloadingthat
can cause large supply transients and create noise. For
the best performance, limit CLKOUT loading to 20pF.
A logic high on RD disables SCLK and three-states DOUT
.
IncaseofusingacontinuousSCLK, RDcanbecontrolled
to limit the number of shift clocks to the desired number
(i.e., 16 cycles) and to three-state DOUT after the data
transfer.
A logic high on CS three-states the DOUT output buffer. It
also inhibits conversion when it is tied high. In power
shutdown mode (SHDN = low), a high CS selects sleep
mode while a low CS selects nap mode. For normal serial
port operation, CS can be grounded.
Serial Port
The serial port in Figure 20 is made up of a 16-bit shift
register and a three-state output buffer that are con-
trolled by three inputs: SCLK, RD and CS. The serial port
has one output, DOUT, that provides the serial output
data.
DOUT outputs the serial data; 14 bits, MSB first, on the
falling edge of each SCLK (see Figures 21 and 22). If 16
SCLKs are provided, the 14 data bits will be followed by
21
LTC1418
U
W U U
APPLICATIONS INFORMATION
two zeros. The MSB (D13) will be valid on the first rising
and the first falling edge of the SCLK. D12 will be valid on
the second rising and the second falling edge as will all
the remaining bits. The data may be captured on either
edge. The largest hold time margin is achieved if data is
captured on the rising edge of SCLK.
SCLK
V
t
IL
t
14
15
V
V
OH
D
OUT
OL
1418 F21
BUSY gives the end of conversion indication. When the
LTC1418 is configured as a master serial device, BUSY
can be used as a framing pulse and to three-state the
Figure 21. SCLK to DOUT Delay
BUSY (= RD)
24
26
23
17
CONVST
CONVST
BUSY
RD
µP OR DSP
(CONFIGURED
AS SLAVE)
OR
SCLK
LTC1418
CLKOUT
SHIFT
CLKOUT ( = SCLK)
18
REGISTER
D
OUT
19
20
D
OUT
EXT/INT
CS
25
1418 F22a
(SAMPLE N)
CS = EXT/INT = 0
t
(SAMPLE N + 1)
5
CONVST
t
13
t
t
8
6
BUSY (= RD)
HOLD
9
SAMPLE
HOLD
t
10
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
1
2
3
CLKOUT (= SCLK)
t
7
Hi-Z
Hi-Z
FILL
ZEROS
D
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D13
D13
D12 D11
DATA N
OUT
DATA (N – 1)
t
CONV
t
1418 F22b
11
CLKOUT
(= SCLK)
V
IL
t
14
t
15
V
V
OH
OL
D
OUT
D13
D12
D11
CAPTURE ON
CAPTURE ON
RISING CLOCK FALLING CLOCK
Figure 22. Internal Conversion Clock Selected. Data Transferred During Conversion Using
the ADC Clock Output as a Master Shift Clock (SCLK Driven from CLKOUT)
22
LTC1418
U
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APPLICATIONS INFORMATION
serial port after transferring the serial output data by
tying it to the RD pin.
clock and the SCLK. The internal clock has been optimized
for the fastest conversion time, consequently this mode
can provide the best overall speed performance. To select
an internal conversion clock, tie EXT/INT (Pin 20) low. The
internal clock appears on CLKOUT (Pin 18) which can be
tied to SCLK (Pin 17) to supply the SCLK.
Figures 22 to 25 show several serial modes of operation,
demonstrating the flexibility of the LTC1418 serial port.
Serial Data Output During a Conversion
Using External Clock for Conversion and Data Transfer.
In Figure 23, data from the previous conversion is output
during the conversion with an external clock providing
both the conversion clock and the shift clock. To select an
external conversion clock, tie EXT/INT high and apply the
Using Internal Conversion Clock for Conversion and
Data Transfer. Figure 22 shows data from the previous
conversion being clocked out during the conversion with
the LTC1418 internal clock providing both the conversion
BUSY (= RD)
24
26
23
CONVST
CONVST
BUSY
RD
EXTCLKIN ( = SCLK)
16
EXTCLKIN
µP OR DSP
LTC1418
SCLK
17
D
OUT
19
20
D
OUT
EXT/INT
CS
25
5V
1418 F23a
(SAMPLE N)
CS = 0, EXT/INT = 5
t
(SAMPLE N + 1)
5
CONVST
t
13
t
6
t
8
BUSY (= RD)
HOLD
9
SAMPLE
HOLD
2
t
dEXTCLKIN
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
1
3
EXTCLKIN (= SCLK)
t
10
t
7
Hi-Z
Hi-Z
FILL
ZEROS
D
OUT
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D13
D13
D12 D11
DATA N
DATA (N – 1)
t
CONV
t
11
1418 F23b
EXTCLKIN
(= SCLK)
t
LEXTCLKIN
V
IL
t
HEXTCLKIN
t
14
t
15
V
OH
D
D13
D12
D11
OUT
V
OL
CAPTURE ON
CAPTURE ON
RISING CLOCK FALLING CLOCK
Figure 23. External Conversion Clock Selected. Data Transferred During Conversion Using
the External Clock (External Clock Drives Both EXTCLKIN and SCLK)
23
LTC1418
U
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APPLICATIONS INFORMATION
clocktoEXTCLKIN. ThesameclockisalsoappliedtoSCLK
to provide a data shift clock. To maintain accuracy the
conversion clock frequency must be between 30kHz and
4.5MHz.
Serial Data Output After a Conversion
UsingInternalConversionClockandExternalDataClock.
In this mode, data is output after the end of each conver-
sion but before the next conversion is started (Figure 24).
The internal clock is used as the conversion clock and an
external clock is used for the SCLK. This mode is useful in
applications where the processor acts as a master serial
device. This mode is SPI and MICROWIRE compatible. It
It is not recommended to clock data with an external clock
during a conversion that is running on an internal clock
because the asynchronous clocks may create noise.
24
26
23
17
INT
C0
CONVST
CONVST
BUSY
RD
SCK
SCLK
LTC1418
µP OR DSP
19
20
MISO
D
OUT
EXT/INT
CS
25
1418 F24a
t
5
CS = EXT/INT = 0
CONVST
t
13
t
6
t
8
SAMPLE
BUSY
RD
HOLD
t
9
1
2
3
4
5
9
6
8
7
7
8
6
9
5
10 11 12 13 14 15 16
SCLK
t
10
t
11
Hi-Z
FILL
Hi-Z
t
D
OUT
D13 12 11 10
4
3
2
1
0
ZEROS
(SAMPLE N)
DATA N
CONV
1418 F24b
t
LSCLK
SCLK
V
t
IL
HSCLK
t
14
t
15
V
V
OH
OL
D
D13
D12
D11
OUT
CAPTURE ON
CAPTURE ON
RISING CLOCK FALLING CLOCK
Figure 24. Internal Conversion Clock Selected. Data Transferred After Conversion
Using an External SCLK. BUSY↑ Indicates End of Conversion
24
LTC1418
U
W U U
APPLICATIONS INFORMATION
alsoallowsoperationwhentheSCLKfrequencyisverylow
(less than 30kHz). To select the internal conversion clock
tie EXT/INT low. The external SCLK is applied to SCLK. RD
can be used to gate the external SCLK, such that data will
clock only after RD goes low and to three-state DOUT after
data transfer. If more than 16 SCLKs are provided, more
zeros will be filled in after the data word indefinitely.
Using External Conversion Clock and External Data
Clock. In Figure 25, data is also output after each conver-
sion is completed and before the next conversion is
started. An external clock is used for the conversion clock
and either another or the same external clock is used for
the SCLK. This mode is identical to Figure 24 except that
an external clock is used for the conversion. This mode
24
16
26
23
CLKOUT
INT
CONVST
CONVST EXTCLKIN
BUSY
RD
C0
µP OR DSP
LTC1418
SCLK
17
19
20
SCK
MISO
D
OUT
EXT/INT
5V
1418 F25a
CS
25
1
5
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
CS = 0, EXT/INT = 5
EXTCLKIN
t
dEXTCLKIN
t
t
7
CONVST
t
13
t
6
t
8
SAMPLE
BUSY
RD
HOLD
t
9
1
2
3
4
5
6
8
7
7
8
6
9
5
10 11 12 13 14 15 16
SCLK
t
t
11
10
Hi-Z
FILL
Hi-Z
D
OUT
D13 12 11 10
9
4
3
2
1
0
ZEROS
(SAMPLE N)
t
CONV
DATA N
1418 F25b
t
LSCLK
SCLK
V
IL
t
HSCLK
t
14
t
15
V
OH
D
D13
D12
D11
OUT
V
OL
CAPTURE ON
CAPTURE ON
RISING CLOCK FALLING CLOCK
Figure 25. External Conversion Clock Selected. Data Transferred After Conversion
Using an External SCLK. BUSY↑ Indicates End of Conversion
25
LTC1418
U
W U U
APPLICATIONS INFORMATION
accuracy. If more than 16 SCLKs are provided, more zeros
will be filled in after the data word indefinitely. To select the
external conversion clock tie EXT/INT high. The external
SCLKisappliedtoSCLK.RDcanbeusedtogatetheexternal
SCLK such that data will clock only after RD goes low.
allows the user to synchronize the A/D conversion to an
external clock either to have precise control of the internal
bit test timing or to provide a precise conversion time. As in
Figure 24, this mode works when the SCLK frequency is
very low (less than 30kHz). However, the external conver-
sion clock must be between 30kHz and 4.5MHz to maintain
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.397 – 0.407*
(10.07 – 10.33)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
0.301 – 0.311
(7.65 – 7.90)
5
7
8
1
2
3
4
6
9 10 11 12 13 14
0.205 – 0.212**
(5.20 – 5.38)
0.068 – 0.078
(1.73 – 1.99)
0° – 8°
0.0256
(0.65)
BSC
0.005 – 0.009
(0.13 – 0.22)
0.022 – 0.037
(0.55 – 0.95)
0.002 – 0.008
(0.05 – 0.21)
0.010 – 0.015
(0.25 – 0.38)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
G28 SSOP 0694
26
LTC1418
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
N Package
28-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.370*
(34.789)
MAX
28 27 26 25 24
23 22 21 20
19 18 17 16 15
0.255 ± 0.015*
(6.477 ± 0.381)
1
2
3
4
5
6
7
8
9
10 11 12 13 14
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.020
(0.508)
MIN
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.125
(3.175)
MIN
0.005
(0.127)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
0.325
–0.015
+0.889
8.255
N28 1197
(
)
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.
27
LTC1418
TYPICAL APPLICATION
U
Single 5V Supply, 200kHz, 14-Bit Sampling A/D Converter
LTC1418
5V
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DIFFERENTIAL
ANALOG INPUT
(0V TO 4.096V)
+
–
A
A
V
V
DD
IN
IN
V
SS
10µF
V
REF
3
OUTPUT
2.5V
BUSY
CS
REF
1N5817*
4
REFCOMP
AGND
D13(MSB)
D12
5
1µF
10µF
CONVST
RD
µP CONTROL
LINES
6
7
SHDN
8
D11
SER/PAR
(EXT/INT)D0
9
D10
*REQUIRED ONLY IF V CAN BECOME
SS
POSITIVE WITH RESPECT TO GROUND
10
11
12
13
14
D9
(D )D1
OUT
D8
(CLKOUT)D2
(SCLK)D3
(EXTCLKIN )D4
D5
14-BIT
PARALLEL
BUS
D7
D6
DGND
1418 TA03
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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LTC1274/LTC1277
LTC1412
Low Power, 12-Bit, 100ksps ADCs
12-Bit, 3Msps Sampling ADC
10mW Power Dissipation, Parallel/Byte Interface
Best Dynamic Performance, SINAD = 72dB at Nyquist
55mW Power Dissipation, 72dB SINAD
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±2.5V Input, SINAD = 90dB, THD = 100dB
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16-Bit CMOS Multiplying DAC in SO-8
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LTC1596
Reference
LT1019-2.5
Precision Bandgap Reference
0.05% Max, 5ppm/°C Max
1418f LT/TP 0798 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1998
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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