LTC1520CS#PBF [Linear]

LTC1520 - 50Mbps Precision Quad Line Receiver; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C;


型号：	LTC1520CS#PBF
厂家：	Linear
描述：	LTC1520 - 50Mbps Precision Quad Line Receiver; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C 光电二极管接口集成电路
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LTC1520

50Mbps Precision Quad

Line Receiver

DESCRIPTION

FEATURES

The LTC^®1520 is a high speed, precision differential line

receiver that can operate at data rates as high as 50Mbps.

A unique architecture provides very stable propagation

delays and low skew over a wide input common mode,

input overdrive and ambient temperature range. Propaga-

tion delay is 18ns ±3ns, while typically t_PLH/t_PHLskew is

500ps and channel-to-channel skew is 400ps.

■

Precision Propagation Delay: 18ns ±3ns Over

Temperature

■

Data Rate: 50Mbps

■

Low t_PLH/t_PHLSkew: 500ps Typ

■

Low Channel-to-Channel Skew: 400ps Typ

■

Rail-to-Rail Input Common Mode Range

■

High Input Resistance: ≥18k, Even When Unpowered

■

Hot Swap Capable

Can Withstand Input DC Levels of ±10V

Each receiver translates differential input levels (V_ID

≥

■

100mV) into valid CMOS and TTL output levels. Its high

input resistance (≥18k) allows many receivers to be con-

nected to the same driver. The receiver outputs go into a

high impedance state when disabled.

■

Short-Circuit Protected

Single 5V Supply

LVDS Compatible

■

Will Not Oscillate with Slow Input Signals

Protection features include thermal shutdown and a con-

trolled maximum short-circuit current (50mA max) that

does not oscillate in and out of short-circuit mode. Input

resistance remains ≥18k when the device is unpowered or

disabled,thusallowingtheLTC1520tobehotswappedinto

a backplane without loading the data lines.

APPLICATIONS

■

High Speed Backplane Interface

■

Line Collision Detector

■

PECL and LVDS Line Receivers

■

Level Translator

Ring Oscillator

The LTC1520 operates from a single 5V supply and draws

12mA of supply current. The part is available in a 16-lead

narrow SO package.

■

Tapped Delay Line

, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATION

High Speed Backplane Receiver

Propagation Delay Guaranteed to Fall

Within Shaded Area (±3ns)

LTC1520

RECEIVER

INPUT

–

1V/DIV

= 500mV

RECEIVER

OUTPUT

OUT

5V/DIV

= 5V

–

3.3k

–5

10 15 20 25 30 35 40 45

TIME (ns)

0.01µF

LTC1520 TA02

1520 TA01

LTC1520

W W W

ABSOLUTE AXI U RATI GS

PACKAGE RDER I FOR ATIO

(Note 1)

TOP VIEW

Supply Voltage ....................................................... 10V

Digital Input Currents ..................... –100mA to 100mA

Digital Input Voltages ............................... –0.5V to 10V

Receiver Input Voltages ........................................ ±10V

Receiver Output Voltages ............. –0.5V to V_DD+ 0.5V

Short-Circuit Duration .................................... Indefinite

Operating Temperature Range .................... 0°C to 70°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

ORDER PART

NUMBER

LTC1520CS

OUT 1

ENABLE

OUT 2

OUT 4

OUT 3

GND

S PACKAGE

16-LEAD PLASTIC SO

T_JMAX= 150°C, θ_JA= 90°C/ W

Consult factory for Industrial and Military grade parts.

DC ELECTRICAL CHARACTERISTICS

V_DD= 5V ±5% (Notes 2, 3) per receiver, unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

A, B Inputs

MIN

– 0.2

TYP

MAX

+ 0.2

UNITS

Input Common Mode Voltage

Input High Voltage

Input Low Voltage

Input Current

●

Enable Input

0.8

–1

µA

IN1

IN2

Input Current (A, B)

V , V = 5V

●

250

µA

V , V = 0

–250

Input Resistance (Figure 5)

A, B Input Capacitance

–0.2V ≤ V ≤ V + 0.2V

●

kΩ

(Note 4)

= 5V (Note 4)

Open-Circuit Input Voltage (Figure 5)

Differential Input Threshold Voltage

Input Hysteresis

●

3.2

3.3

3.4

0.1

–0.2V < V < V + 0.2V

–0.1

ID(MIN)

= 2.5V

OUT

Output High Voltage

= –4mA, V = 0.1V, V = 5V

4.6

–10

–50

Output Low Voltage

= 4mA, V = 0.1V, V = 5V

0.4

OZR

Three-State Output Current

Total Supply Current All 4 Receivers

Short-Circuit Current

0V ≤ V

≤ V

µA

OUT

≥ 0.1V, No Load, Enable = 5V

= 0V, V

= V

OSR

OUT

CMRR

Common Mode Rejection Ratio

= 2.5V, f = 25MHz

LTC1520

U W

SWITCHI G TI E CHARACTERISTICS

V_DD= 5V ±5% (Notes 2, 3) V_ID= 500mV, V_CM= 2.5V, unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

C = 15pF (Figure 1)

MIN

TYP

MAX

UNITS

, t

Input-to-Output Propagation Delay

Rise/Fall Times

●

PLH PHL

t , t

C = 15pF

2.5

500

SKD

– t

PHL

Skew

C = 15pF, Same Receiver (Note 5)

●

PLH

Enable to Output Low

C = 15pF (Figure 2)

Enable to Output High

C = 15pF (Figure 2)

Disable from Output Low

Disable from Output High

Channel-to-Channel Skew

Package-to-Package Skew

C = 15pF (Figure 2)

C = 15pF (Figure 3) (Note 6)

400

1.5

CH-CH

C = 15pF, Same Temperature

PKG-PKG

(Figure 4, Note 4)

Minimum Input Pulse Width

Maximum Input Frequency

(Note 4)

MHz

The

●

denotes specifications which apply over the full operating

Note 3: All typicals are given for V = 5V, T = 25°C.

DD A

Note 4: Guaranteed by design, but not tested.

temperature range.

Note 1: Absolute Maximum Ratings are those values beyond which the

Note 5: Worst-case – t skew for a single receiver in a package

over the full operating temperature range.

PLH

PHL

safety of the device cannot be guaranteed. Recommended: V = 5V ±5%.

Note 2: All currents into the device pins are positive; all currents out of the

device pins are negative.

Note 6: Maximum difference between any two t

single package over the full operating temperature range.

or t

transitions in a

PHL

PLH

TYPICAL PERFORMANCE CHARACTERISTICS

Propagation Delay (t_PLH/t_PHL

vs Input Common Mode

)

Propagation Delay (t_PLH/t_PHL

vs Temperature

)

Propagation Delay (t_PLH/t_PHL

vs Input Overdrive

)

= 2.5V

= 25°C

= 500mV

= 25°C

= 2.5V

= 500mV

–50 –25

75 100 125

0.05 0.1

TEMPERATURE (°C)

INPUT OVERDRIVE (V)

INPUT COMMON MODE (V)

LTC1520 G01

1520 G02

LTC1520 G03

LTC1520

TYPICAL PERFORMANCE CHARACTERISTICS

Propagation Delay vs Load

Capacitance (t_PLH/t_PHL

)

CMRR vs Frequency

Supply Current vs Frequency

46.5

46.0

45.5

45.0

44.5

44.0

43.5

43.0

42.5

= 25°C

ALL 4

RECEIVERS

SWITCHING

= 500mV

= 2.5V

1 RECEIVER

SWITCHING

= 25°C

42.0

105

205

100k

FREQUENCY (Hz)

10M

LOAD CAPACITANCE (pF)

FREQUENCY (MHz)

1520 G06

1520 G05

LTC1520 G04

Supply Current vs Temperature

and Frequency

Skew vs Temperature (t_SKD

)

Output Duty Cycle vs Frequency

400

390

380

370

360

350

340

50.0

= 50% DUTY CYCLE

49.5

49.0

48.5

48.0

47.5

47.0

46.5

46.0

45.5

25°C

0°C

100°C

–45°C

1 RECEIVER SWITCHING

–10

110

TEMPERATURE (°C)

FREQUENCY (MHz)

1520 G07

1520 G08

1520 G09

PIN FUNCTIONS

B1 (Pin 1): Receiver 1 Inverting Input.

A1 (Pin 2): Receiver 1 Noninverting Input.

RO1 (Pin 3): Receiver 1 Output.

B3 (Pin 9): Receiver 3 Inverting Input.

A3 (Pin 10): Receiver 3 Noninverting Input.

RO3 (Pin 11): Receiver 3 Output.

Enable (Pin 4): Receiver Output Enable Pin. A logic high

input enables the receiver outputs. A logic low input

forces the receiver outputs into a high impedance state.

Do not float.

RO2 (Pin 5): Receiver 2 Output.

A2 (Pin 6): Receiver 2 Noninverting Input.

B2 (Pin 7): Receiver 2 Inverting Input.

NC (Pin 12): No Connection.

RO4 (Pin 13): Receiver 4 Output.

A4 (Pin 14): Receiver 4 Noninverting Input.

B4 (Pin 15): Receiver 4 Inverting Input.

V_DD(Pin16):5VSupplyPin. Thispinshouldbedecoupled

with a 0.1µF ceramic capacitor as close as possible to the

pin. Recommended: V_DD= 5V ±5%.

GND(Pin8):GroundPin.Agroundplaneisrecommended

for all LTC1520 applications.

LTC1520

U W

SWITCHI G TI E WAVEFOR S

2.5V

INPUT

2.5V

1/4 LTC1520

OUTPUT

PHL

PLH

–

15pF

OUTPUT

1520 F01b

1520 F01

Figure 1. Propagation Delay Test Circuit and Waveforms

B1, B2 = 2.5V

INPUT

A1, A2

ENABLE

OUT 1

1.5V

OUTPUT

CH1 OUT

CH2 OUT

1.5V

NORMALLY LOW

0.2V

CH-CH

OUTPUT

NORMALLY HIGH

OUT 1

1520 F03

Figure 3. Any Channel to Any Channel Skew, Same Package

RECEIVER

OUTPUT

INPUT

A1, B1

= 500mV

1520 F02

SAME INPUT FOR BOTH PACKAGES

Figure 2. Receiver Enable and Disable Timing

Test Circuit and Waveforms

PACKAGE 1

OUT 1

PKG-PKG

PACKAGE 2

OUT 1

1520 F04

Figure 4. Package-to-Package Propagation Delay Skew

U U

EQUIVALE T I PUT NETWORKS

≥18k

3.3V

≥18k

3.3V

RECEIVER ENABLED, V = 5V

RECEIVER DISABLED OR V = 0V

1520 F05

Figure 5. Input Thevenin Equivalent

LTC1520

W U U

APPLICATIONS INFORMATION

Theory of Operation

referencefortransmissionlineandterminationeffects. To

mitigate transmission errors and duty cycle distortion due

to driver ringing, a small output filter or a dampening

resistor on V_DDmay be needed as shown in Figure 6b. To

transmit single-ended data over distances up to 10 feet,

twisted pair is recommended with the unused wire

grounded at both ends (Figure 7).

Unlike typical line receivers whose propagation delay can

vary by as much as 500% from package to package and

show significant temperature drift, the LTC1520 employs

a novel architecture that produces a tightly controlled and

temperature compensated propagation delay. The differ-

ential timing skew is also minimized between rising and

falling output edges, and the propagation delays of any

two receivers within a package are very tightly matched.

MC74ACT04

(TTL INPUT)

PC TRACE

–

The precision timing features of the LTC1520 reduce

overall system timing constraints by providing a narrow

6ns window during which valid data appears at the re-

ceiver output. This output timing window applies to all

receiversinseparatepackagesoveralloperatingtempera-

tures thereby making the LTC1520 well suited for high

speed parallel data transmission applications such as

backplanes.

1/4 LTC1520

MC74AC04

(CMOS INPUT)

2.2k

0.01µF

1520 F06a

Figure 6a. Single-Ended Receiver

In clocked data systems, the low skew minimizes duty

cycle distortion of the clock signal. The LTC1520 can

propagate signals at frequencies up to 25MHz (50Mbps)

with less than 5% duty cycle distortion. When a clock

signalisusedtoretimeparalleldata, themaximumrecom-

mended data transmission rate is 25Mbps to avoid timing

errors due to clock distortion.

0.01µF

10Ω

MC74AC04

10Ω

PC TRACE OR

10pF

PC TRACE

1520 F06b

Figure 6b. Techniques to Minimize Driver Ringing

Rail-to-railinputcommonmoderangeenablestheLTC1520

to be used in both single-ended and differential applica-

tions with transmission distances up to 100 feet. Thermal

shutdown and short-circuit protection prevent latchup

damage to the LTC1520 during fault conditions.

MC74ACT04

MC74AC04

10-FT TWISTED PAIR

–

120Ω

1/4 LTC1520

3.3k

Single-Ended Applications

0.01µF

Over short distances, the LTC1520 can be configured to

receive single-ended data by tying one input to a fixed bias

voltageandconnectingtheotherinputtothedriveroutput.

In such applications, standard high speed CMOS logic

may be used as a driver for the LTC1520. The receiver trip

points may be easily adjusted to accommodate different

driveroutputswingsbychangingtheresistordivideratthe

fixed input. Figure 6a shows a single-ended receiver

configuration with the driver and receiver connected via

PC traces. Note that at very high speeds, transmission line

anddriverringingeffectshavetobeconsidered.Motorola’s

MECL System Design Handbook serves as an excellent

2.2k

1520 F07

Figure 7. Medium Distance Single-Ended Transmission

Using a CMOS Driver

Differential Transmission

The LTC1520 is well suited for medium distance differen-

tialtransmissionduetoitsrail-to-railinputcommonmode

range. Clock rates up to 25MHz can be transmitted over

100 feet of high quality twisted pair. Figure 8 shows the

LTC1520

W U U

APPLICATIONS INFORMATION

LTC1520receivingdifferentialdatafromaPECLdriver. As

in the single-ended configurations, care must be taken to

properly terminate the differential data lines to avoid

unwanted reflections, etc.

3.3k

0.01µF

9.3MHz

OSCILLATOR

1/4 LTC1520

WITH BETTER

THAN 45/55

DUTY CYCLE

–

100Ω

–

100-FT TWISTED PAIR

1/4 LTC1520

100Ω

1/4 LTC1520

120Ω

TYPICAL STABILITY

±5% OVER TEMPERATURE

100Ω

–

*MC10116

1520 F08

6.9MHz

0.01µF

OSCILLATOR

OUTPUT

1/4 LTC1520

Figure 8. Differential Transmission Over Long Distances

–

1/4 LTC1520

Alternate Uses

The tightly controlled propagation delay of the LTC1520

allows the part to serve as a fixed delay element. Figure 9

shows the LTC1520 used as a tapped delay line with 18ns

±3nssteps. SeveralLTC1520smaybeconnectedinseries

to form longer delay lines. Each tap in the delay line is

accurate to within ±17% over temperature.

1520 F10

Figure 10. Temperature Stable Ring Oscillators

Layout Considerations

A ground plane is recommended when using a high

frequency device like the LTC1520. A 0.1µF ceramic by-

pass capacitor less than 1/4 inch away from the V_DDpin is

also recommended. Good bypassing is especially needed

when all four channels are driven simultaneously by the

same input. Under these conditions, and with a bypass

capacitor more than 1 1/4 inches away from the V_DDpin,

the parasitic inductances will cause ringing in the V_DDand

output pins. This in turn can cause false triggering of the

output short-circuit detector (Figure 11). When the by-

pass capacitor is placed close to the V_DDpin, however, the

LTC1520 operates normally (Figure 12).

As shown in Figure 10, the LTC1520 can be used to create

a temperature stable ring oscillator with period incre-

ments of 36ns. Low skew and good channel-to-channel

matching enable this oscillator to achieve better than a 45/

55 duty cycle (the duty cycle approaches 50/50 as more

LTC1520s are used for lower frequencies). Note that the

fixed voltage bias may either be created externally with a

resistor divider or generated internally using a bypass

capacitor and the internal open circuit bias point (approxi-

mately 3.3V). The use of the internal bias point will result

in a 1% to 2% distortion of the duty cycle.

0ns DELAY

18ns DELAY

INPUT

36ns DELAY

1/4 LTC1520

54ns DELAY

1/4 LTC1520

–

1/4 LTC1520

–

1/4 LTC1520

72ns DELAY

–

3.3k

–

0.01µF

3.3k

1520 F09

Figure 9. Tapped Delay Line with 18ns Steps

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1520

W U U

APPLICATIONS INFORMATION

160

150

1V/1D4I0V

130

1V/DIV

120

110

100

ALL 4 RECEIVERS DRIVEN BY

THE SAME INPUT

ALL 4 RECEIVERS DRIVEN BY

THE SAME INPUT

INPUT VOLTAGE (V)

50ns/DIV

1520 F12

1520 F11

Figure 12. V_DDBypassing < 3/8” Away

Figure 11. V_DDBypassing > 1 1/4” Away

PACKAGE DESCRIPTION

S Package

16-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.386 – 0.394*

(9.804 – 10.008)

0.150 – 0.157**

(3.810 – 3.988)

0.228 – 0.244

(5.791 – 6.197)

0.010 – 0.020

(0.254 – 0.508)

× 45°

0.053 – 0.069

(1.346 – 1.752)

0.004 – 0.010

(0.101 – 0.254)

0.008 – 0.010

(0.203 – 0.254)

0° – 8° TYP

0.050

(1.270)

TYP

0.014 – 0.019

(0.355 – 0.483)

0.016 – 0.050

0.406 – 1.270

S16 0695

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

RELATED PARTS

PART NUMBER

LTC486/487

LTC488/489

LT^®1016

DESCRIPTION

COMMENTS

Low Power Quad RS485 Drivers

Low Power Quad RS485 Receivers

Ultrafast Precision Comparator

High Speed Quad RS485 Receiver

10Mbps, –7V to 12V Common Mode Range

Single 5V Supply, 10ns Propagation Delay

50Mbps, –7V to 12V Common Mode Range

LTC1518

LTC1519

1520fs, sn1520 LT/GP 0996 7K • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977

LINEAR TECHNOLOGY CORPORATION 1996

LTC1520CS#PBF [Linear]

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