LTC1594LCS#TR [Linear]
LTC1594L - 4- and 8-Channel, 3V Micropower Sampling 12-Bit Serial I/O A/D Converters; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C;
| 型号： | LTC1594LCS#TR |
| 厂家： | 
Linear |
| 描述： | LTC1594L - 4- and 8-Channel, 3V Micropower Sampling 12-Bit Serial I/O A/D Converters; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C 转换器 |
| 文件： | 总24页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1594/LTC1598
4- and 8-Channel,
Micropower Sampling
12-Bit Serial I/O A/D Converters
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FEATURES
DESCRIPTIO
TheLTC®1594/LTC1598aremicropower,12-bitsampling
A/Dconvertersthatfeature4-and8-channelmultiplexers,
respectively. They typically draw only 320μA of supply
currentwhenconvertingandautomaticallypowerdownto
a typical supply current of 1nA between conversions. The
LTC1594 is available in a 16-pin SO package and the
LTC1598 is packaged in a 24-pin SSOP. Both operate on
a 5V supply. The 12-bit, switched-capacitor, successive
approximation ADCs include a sample-and-hold.
■
12-Bit Resolution
■
Auto Shutdown to 1nA
■
Low Supply Current: 320μA Typ
■
Guaranteed ±3/4LSB Max DNL
■
Single Supply 5V Operation
(3V Versions Available: LTC1594L/LTC1598L)
■
Multiplexer: 4-Channel MUX (LTC1594)
8-Channel MUX (LTC1598)
■
Separate MUX Output and ADC Input Pins
■
MUX and ADC May Be Controlled Separately
On-chip serial ports allow efficient data transfer to a wide
rangeofmicroprocessorsandmicrocontrollersoverthree
or four wires. This, coupled with micropower consump-
tion, makes remote location possible and facilitates trans-
mitting data through isolation barriers.
■
Sampling Rate: 16.8ksps
I/O Compatible with QSPI, SPI and MICROWIRETM, etc.
Small Package: 16-Pin Narrow SO (LTC1594)
24-Pin SSOP (LTC1598)
■
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APPLICATIO S
The circuit can be used in ratiometric applications or with
an external reference. The high impedance analog inputs
and the ability to operate with reduced spans (to 1.5V full
scale) allow direct connection to sensors and transducers
in many applications, eliminating the need for gain stages.
■
Pen Screen Digitizing
■
Battery-Operated Systems
■
Remote Data Acquisition
■
Isolated Data Acquisition
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
■
Battery Monitoring
■
Temperature Measurement
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TYPICAL APPLICATIO
24μW, 4-Channel, 12-Bit ADC Samples at 200Hz and Runs Off a 5V Supply
OPTIONAL
ADC FILTER
Supply Current vs Sample Rate
5V
1k
1000
100
10
1μF
T
= 25°C
A
V
V
f
= 5V
CC
REF
18
MUXOUT
17
ADCIN
16
V
15, 19
1μF
= 5V
V
= 320kHz
REF
CC
CLK
20 CH0
21 CH1
22 CH2
23 CH3
24 CH4
SERIAL DATA LINK
MICROWIRE AND
SPI COMPATABLE
10
6
CSADC
CSMUX
CLK
ANALOG
INPUTS
0V TO 5V
RANGE
5, 14
7
12-BIT
SAMPLING
ADC
8-CHANNEL
MUX
+
MPU
D
IN
1
2
3
CH5
CH6
CH7
11
D
OUT
–
12
13
NC
NC
8
COM
1
GND
4, 9
0.1
1
10
100
1594/98 TA01
SAMPLE FREQUENCY (kHz)
1594/98 TA02
15948fb
1
LTC1594/LTC1598
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ABSOLUTE AXI U RATI GS
(Notes 1, 2)
Supply Voltage (VCC) to GND................................... 12V
Voltage
Power Dissipation.............................................. 500mW
Operating Temperature Range
LTC1594CS/LTC1598CG ......................... 0°C to 70°C
LTC1594IS/LTC1598IG ..................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Analog Reference .................... –0.3V to (VCC + 0.3V)
Analog Inputs .......................... –0.3V to (VCC + 0.3V)
Digital Inputs .........................................–0.3V to 12V
Digital Output .......................... –0.3V to (VCC + 0.3V)
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
ORDER PART
NUMBER
1
2
CH4
CH3
CH2
CH1
CH0
24
23
22
21
20
19
18
17
16
15
14
13
CH5
CH6
TOP VIEW
CH0
CH1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
LTC1594CS
LTC1594IS
LTC1598CG
LTC1598IG
CC
3
CH7
MUXOUT
4
GND
CH2
D
IN
5
CLK
CH3
CSMUX
CLK
6
V
CSMUX
CC
ADCIN
7
MUXOUT
ADCIN
D
IN
V
V
REF
CC
8
COM
GND
COM
GND
D
OUT
9
V
REF
CSADC
10
11
12
V
CSADC
CC
CLK
NC
D
S PACKAGE
16-LEAD PLASTIC SO
OUT
NC
TJMAX = 125°C, θJA = 120°C/ W
G PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 110°C/ W
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
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(Note 5)
RECO E DED OPERATI G CO DITIO S
SYMBOL
PARAMETER
CONDITIONS
MIN
4.5
(Note 4)
60
150
1
400
1
1
TYP
MAX
5.5
320
UNITS
V
kHz
μs
V
Supply Voltage (Note 3)
Clock Frequency
Total Cycle Time
CC
f
t
t
t
t
t
t
t
t
V
= 5V
CLK
CC
f
= 320kHz
= 5V
CYC
CLK
Hold Time, D After CLK↑
V
V
V
V
V
ns
μs
ns
μs
μs
μs
μs
hDI
IN
CC
CC
Setup Time CS↓ Before First CLK↑ (See Operating Sequence)
= 5V
= 5V
= 5V
= 5V
suCS
suDI
Setup Time, D Stable Before CLK↑
IN
CC
CLK High Time
CLK Low Time
CS High Time Between Data Transfer Cycles
CS Low Time During Data Transfer
WHCLK
WLCLK
WHCS
WLCS
CC
CC
f
f
= 320kHz
= 320kHz
16
44
CLK
CLK
15948fb
2
LTC1594/LTC1598
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CONVERTER AND MULTIPLEXER CHARACTERISTICS The ● denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1594CS/LTC1598CG
LTC1594IS/LTC1598IG
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Bits
LSB
LSB
LSB
LSB
V
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
REF Input Range
●
●
●
●
●
12
12
(Note 6)
±3
± 3/4
±3
±3
±1
±3
±8
±8
(Notes 7, 8)
(Notes 7, 8)
1.5V to V + 0.05V
CC
–0.05V to V + 0.05V
Analog Input Range
V
CC
MUX Channel Input Leakage Current Off Channel
●
●
●
±200
±200
±1
± 200
± 200
±1
nA
nA
μA
MUXOUT Leakage Current
Off Channel
(Note 9)
ADCIN Input Leakage Current
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DYNAMIC ACCURACY
(Note 5) fSMPL = 16.8kHz
SYMBOL
S/(N + D)
THD
PARAMETER
CONDITIONS
MIN
TYP
71
–78
80
MAX
UNITS
dB
Signal-to-Noise Plus Distortion Ratio
Total Harmonic Distortion (Up to 5th Harmonic)
Spurious-Free Dynamic Range
1kHz Input Signal
1kHz Input Signal
1kHz Input Signal
1kHz Input Signal
dB
dB
dB
SFDR
Peak Harmonic or Spurious Noise
–80
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DIGITAL AND DC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 5.25V
= 4.75V
●
●
●
●
2.6
IH
IL
CC
CC
IN
0.8
2.5
–2.5
V
μA
μA
V
V
I
I
= V
IH
IL
CC
= 0V
IN
V
V
V
= 4.75V, I = –10μA
= 4.75V, I = –360A
●
●
4.0
2.4
4.64
4.62
OH
CC
CC
O
O
V
Low Level Output Voltage
Hi-Z Output Leakage
Output Source Current
Output Sink Current
V
= 4.75V, I = 1.6mA
●
●
0.4
±3
V
μA
mA
mA
OL
CC
O
I
I
I
CS = High
V
V
OZ
= 0V
–25
45
SOURCE
SINK
OUT
= V
OUT
CC
R
REF
Reference Input Resistance
CS = V
CS = V
5000
55
MΩ
kΩ
IH
IL
I
I
Reference Current
Supply Current
CS = V
●
0.001
90
90
0.001
320
320
2.5
μA
μA
μA
μA
μA
μA
REF
CC
t
t
≥ 760μs, f
≥ 60μs, f
≤ 25kHz
CYC
CYC
CLK
≤ 320kHz
●
●
140
±7
CLK
CS = V , CLK = V , D = V
CC
CC
CC IN
CC
t
t
≥ 760μs, f
≥ 60μs, f
≤ 25kHz
≤ 320kHz
CYC
CYC
CLK
●
690
CLK
15948fb
3
LTC1594/LTC1598
The ● denotes the specifications which apply over the full operating temperature range,
AC CHARACTERISTICS
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
1.5
16.8
TYP
MAX
UNITS
CLK Cycles
kHz
t
f
Analog Input Sample Time
Maximum Sampling Frequency
See Figure 1 in Applications Information
See Figure 1 in Applications Information
SMPL
●
SMPL(MAX)
t
t
t
t
t
t
t
t
t
t
Conversion Time
Delay Time, CLK↓ to D
Delay Time, CS↑ to D
Delay Time, CLK↓ to D
See Figure 1 in Applications Information
See Test Circuits
See Test Circuits
12
250
135
75
230
50
CLK Cycles
CONV
dDO
dis
Data Valid
Hi-Z
Enabled
●
●
●
600
300
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
OUT
OUT
OUT
See Test Circuits
en
Time Output Data Remains Valid After CLK↓
C
LOAD
= 100pF
hDO
f
D
D
Fall Time
Rise Time
See Test Circuits
See Test Circuits
See Figure 1 in Applications Information
See Figure 2 in Applications Information
●
●
●
●
●
150
150
700
300
OUT
50
r
OUT
Enable Turn-On Time
Enable Turn-Off Time
Break-Before-Make Interval
Input Capacitance
260
100
160
20
5
ON
OFF
OPEN
35
C
Analog Inputs On-Channel
Off-Channel
Digital Input
pF
pF
pF
IN
5
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 6: Linearity error is specified between the actual end points of the
A/D transfer curve.
Note 7: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
Note 2: All voltage values are with respect to GND.
below GND or one diode drop above V . This spec allows 50mV forward
CC
bias of either diode for 4.5V ≤ V ≤ 5.5V. This means that as long as the
CC
Note 3: These devices are specified at 5V. Consult factory for 3V
specified devices (LTC1594L/LTC1598L).
Note 4: Increased leakage currents at elevated temperatures cause the S/H
reference or analog input does not exceed the supply voltage by more than
50mV, the output code will be correct. To achieve an absolute 0V to 5V
input voltage range, it will therefore require a minimum supply voltage of
4.950V over initial tolerance, temperature variations and loading.
to droop, therefore it is recommended that f
≥ 160kHz at 85°C,
CLK
f
≥ 75kHz at 70°C and f
≥ 1kHz at 25°C.
CLK
CLK
Note 8: Recommended operating condition. Not 100% production tested.
Note 9: Channel leakage current is measured after the channel selection.
Note 5: V = 5V, V = 5V and CLK = 320kHz unless otherwise specified.
CC
REF
CSADC and CSMUX pins are tied together during the test.
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TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Sample Rate
Supply Current vs Temperature
Reference Current vs Temperature
1000
100
10
95.0
94.5
450
400
V
f
CLK
= V
SMPL
= 5V
= 16.8kHz
T
= 25°C
T
= 25°C
CC
REF
A
A
V
V
f
= 5V
V
f
= V
= 5V
REF
CC
REF
CC
f
= 320kHz
= 5V
= 320kHz
= 16.8kHz
CLK
SMPL
= 320kHz
f
CLK
94.0
350
93.5
93.0
300
250
200
92.5
92.0
1
0.1
1
10
100
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
SAMPLE FREQUENCY (kHz)
TEMPERATURE (°C)
TEMPERATURE (°C)
1594/98 G01
1594/98 G02
1594/98 G03
15948fb
4
LTC1594/LTC1598
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TYPICAL PERFORMANCE CHARACTERISTICS
Change in Linearity
vs Reference Voltage
Change in Offset
Change in Offset vs Temperature
vs Reference Voltage
–0.50
–0.45
–0.40
–0.35
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
0
3.0
2.5
2.0
1.5
1.0
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
T
V
f
f
= 25°C
T = 25°C
A
V
A
= 5V
= 5V
CC
CLK
CC
= 320kHz
= 16.8kHz
f
f
= 320kHz
CLK
SMPL
= 16.8kHz
SMPL
V
= V
= 5V
REF
CC
f
f
= 320kHz
CLK
SMPL
= 16.8kHz
3.5 4.0
1.0 1.5 2.0 2.5 3.0
REFERENCE VOLTAGE (V)
4.5 5.0
3.5 4.0
1.0 1.5 2.0 2.5 3.0
REFERENCE VOLTAGE (V)
–55 –35 –15
5
25
45
TEMPERATURE (°C)
65
85
4.5 5.0
1594/98 G06
1594/98 G04
1594/98 G05
Change in Gain
vs Reference Voltage
Peak-to-Peak ADC Noise
vs Reference Voltage
Differential Nonlinearity vs Code
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1.0
0.8
0.6
0.4
0.2
0.0
2.0
1.5
1.0
0.5
0
T
V
= 25°C
T = 25°C
A
A
= 5V
V
CLK
= 5V
= 320kHz
CC
CC
f
f
= 320kHz
f
CLK
SMPL
= 16.8kHz
– 0.2
– 0.4
– 0.6
– 0.8
–1.0
3.5 4.0
1.0 1.5 2.0 2.5 3.0
4.5 5.0
0
2048
4096
3
4
1
5
2
REFERENCE VOLTAGE (V)
CODE
REFERENCE VOLTAGE (V)
1594/98 G07
1594/98 G09
1594/98 G08
Spurious Free Dynamic Range
vs Frequency
Effective Bits and S/(N + D)
vs Input Frequency
S/(N + D) vs Input Level
100
90
12
11
74
68
80
70
T
= 25°C
A
V
= V
= 5V
CC
REF
10
9
62
56
50
44
38
f
f
= 1kHz
IN
SMPL
80
= 16.8kHz
60
50
70
8
60
50
7
6
40
30
20
10
5
40
30
20
10
0
4
3
T
= 25°C
A
V
f
= 5V
T
= 25°C
CC
A
2
1
= 320kHz
= 16.8kHz
V
f
= V
= 5V
REF
CLK
SMPL
CC
f
= 16.8kHz
SMPL
0
0
1
10
100
1000
1
10
100
1000
– 40
–30
–20
INPUT LEVEL (dB)
–10
0
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
1594/98 G10
1594/98 G11
1594/98 G12
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LTC1594/LTC1598
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TYPICAL PERFORMANCE CHARACTERISTICS
4096 Point FFT Plot
Intermodulation Distortion
Attenuation vs Input Frequency
0
0
0
T
= 25°C
T = 25°C
A
A
10
V
= V
= 5V
V
= V
= 5kHz
= 6kHz
= 5V
REF
CC
REF
CC
–20
–20
f
f
f
= 5kHz
f
f
f
IN
1
2
20
30
= 320kHz
CLK
SMPL
–40
–60
– 40
– 60
= 12.5kHz
= 12.5kHz
SMPL
40
50
–80
–80
60
70
–100
–120
–100
–120
80
T
= 25°C
A
V
= V
= 5V
REF
CC
90
f
= 16.8kHz
SMPL
100
–140
–140
1
10
100
1000
10000
4
6
7
4
6
7
0
1
2
3
5
0
3
5
1
2
INPUT FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
1594/98 G13
1594/98 G14
1594/98 G15
Maximum Clock Frequency
vs Source Resistance
Sample-and-Hold Acquisition Time
vs Source Resistance
Power Supply Feedthrough
vs Ripple Frequency
360
300
240
180
120
60
0
10000
1000
100
T
= 25°C
T
= 25°C
A
A
V
V
V
= 5V (V
= 20mV)
RIPPLE
= V
= 5V
CC
CC
REF
= 5V
REF
CLK
f
= 320kHz
V
+INPUT
IN
–50
COM
–
+
R
R
SOURCE
SOURCE
V
IN
+INPUT
COM
T
= 25°C
CC
A
V
= V = 5V
REF
–100
0
0.1
1
10
1
10
100
1000
10000
0.1
1
10
100
1000
10000
SOURCE RESISTANCE (kΩ)
RIPPLE FREQUENCY (kHz)
SOURCE RESISTANCE (Ω)
1594/98 G17
1594/98 G16
1594/98 G18
Input Channel Leakage Current
vs Temperature
Minimum Clock Frequency for
0.1LSB Error vs Temperature
1000
320
240
160
80
V
= V
= 5V
REF
CC
V
V
= 5V
REF
CC
= 5V
100
10
ON CHANNEL
1
OFF CHANNEL
0.1
0.01
0
0
120
140
–15
5
–60 – 40 –20
20 40 60 80 100
– 55
25
45
65 85
– 35
TEMPERATURE (°C)
TEMPERATURE (°C)
1594/98 G20
1594/98 G19
15948fb
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LTC1594/LTC1598
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PIN FUNCTIONS
LTC1594
CH0 (Pin 1): Analog Multiplexer Input.
CH1 (Pin 2): Analog Multiplexer Input.
CH2 (Pin 3): Analog Multiplexer Input.
CH3 (Pin 4): Analog Multiplexer Input.
DOUT (Pin 10): Digital Data Output. The A/D conversion
result is shifted out of this output.
VCC (Pin 11): Power Supply Voltage. This pin provides
power to the ADC. It must be bypassed directly to the
analog ground plane.
ADCIN(Pin5):ADCInput. Thisinputisthepositiveanalog
input to the ADC. Connect this pin to MUXOUT for normal
operation.
CLK (Pin 12): Shift Clock. This clock synchronizes the
serial data transfer to both MUX and ADC.
CSMUX (Pin 13): MUX Chip Select Input. A logic high on
this input allows the MUX to receive a channel address. A
logic low enables the selected MUX channel and connects
it to the MUXOUT pin for A/D conversion. For normal
operation, drive this pin in parallel with CSADC.
V
REF (Pin 6): Reference Input. The reference input defines
the span of the ADC.
COM (Pin 7): Negative Analog Input. This input is the
negative analog input to the ADC and must be free of noise
with respect to GND.
DIN (Pin 14): Digital Data Input. The multiplexer address
is shifted into this input.
GND (Pin 8): Analog Ground. GND should be tied directly
to an analog ground plane.
MUXOUT (Pin 15): MUX Output. This pin is the output of
the multiplexer. Tie to ADCIN for normal operation.
CSADC (Pin 9):ADC Chip Select Input. A logic high on this
inputpowersdowntheADCandthree-statesDOUT. Alogic
low on this input enables the ADC to sample the selected
channel and start the conversion. For normal operation
drive this pin in parallel with CSMUX.
VCC (Pin 16): Power Supply Voltage. This pin should be
tied to Pin 11.
LTC1598
CH5 (Pin 1): Analog Multiplexer Input.
CH6 (Pin 2): Analog Multiplexer Input.
CH7 (Pin 3): Analog Multiplexer Input.
COM (Pin 8): Negative Analog Input. This input is the
negative analog input to the ADC and must be free of noise
with respect to GND.
GND (Pin 9): Analog Ground. GND should be tied directly
to an analog ground plane.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
CSADC (Pin 10): ADC Chip Select Input. A logic high on
this input deselects and powers down the ADC and three-
states DOUT. A logic low on this input enables the ADC to
sample the selected channel and start the conversion. For
normal operation drive this pin in parallel with CSMUX.
CLK(Pin5):ShiftClock. Thisclocksynchronizestheserial
data transfer to both MUX and ADC. It also determines the
conversion speed of the ADC.
CSMUX (Pin 6): MUX Chip Select Input. A logic high on
this input allows the MUX to receive a channel address. A
logic low enables the selected MUX channel and connects
it to the MUXOUT pin for A/D conversion. For normal
operation, drive this pin in parallel with CSADC.
DOUT (Pin 11): Digital Data Output. The A/D conversion
result is shifted out of this output.
NC (Pin 12): No Connection.
NC (Pin 13): No Connection.
DIN (Pin 7): Digital Data Input. The multiplexer address is
shifted into this input.
CLK (Pin 14): Shift Clock. This input should be tied to Pin 5.
15948fb
7
LTC1594/LTC1598
U
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PIN FUNCTIONS
VCC (Pin 15): Power Supply Voltage. This pin provides
power to the A/D Converter. It must be bypassed directly
to the analog ground plane.
VCC (Pin 19): Power Supply Voltage. This pin should be
tied to Pin 15.
CH0 (Pin 20): Analog Multiplexer Input.
CH1 (Pin 21): Analog Multiplexer Input.
CH2 (Pin 22): Analog Multiplexer Input.
CH3 (Pin 23): Analog Multiplexer Input.
CH4 (Pin 24): Analog Multiplexer Input.
V
REF (Pin 16): Reference Input. The reference input de-
fines the span of the ADC.
ADCIN (Pin 17): ADC Input. This input is the positive
analog input to the ADC. Connect this pin to MUXOUT for
normal operation.
MUXOUT (Pin 18): MUX Output. This pin is the output of
the multiplexer. Tie to ADCIN for normal operation.
W
BLOCK DIAGRA S
LTC1594
LTC1598
15
5
6
16
18
17
16
V
15, 19
V
V
MUXOUT
ADCIN
V
CC
MUXOUT
ADCIN
REF
CC
REF
9
20 CH0
21 CH1
22 CH2
23 CH3
24 CH4
CSADC
1
2
3
4
CH0
CH1
CH2
CH3
13
12
14
10
10
6
CSMUX
CLK
CSADC
CSMUX
CLK
12-BIT
SAMPLING
ADC
4-CHANNEL
MUX
+
5, 14
7
12-BIT
SAMPLING
ADC
D
IN
8-CHANNEL
MUX
+
D
OUT
–
D
IN
1
2
3
CH5
CH6
CH7
11
12
13
7
COM
D
OUT
–
GND
8
LTC1594
NC
NC
8
COM
GND
4, 9
LTC1598
1594/98 BD
TEST CIRCUITS
Load Circuit for tdDO, tr and tf
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
1.4V
3k
V
V
OH
OL
D
OUT
D
TEST POINT
OUT
t
t
1594/98 TC02
r
f
100pF
1594/98 TC01
15948fb
8
LTC1594/LTC1598
TEST CIRCUITS
Voltage Waveforms for ten
Voltage Waveforms for DOUT Delay Times, tdDO
LTC1594/LTC1598
CSMUX
CSADC
=
=
CS
CSADC
CLK
CLK
EN D2 D1 DO
D
DON‘T CARE
IN
D
OUT
B11 B10 B9 B8 B7
B6
B5 B4 B3 B2 B1 B0 B1 B2
1
2
MPU
TRANSMIT
WORD
0
?
0
?
0
?
0
EN D2 D1 D0
X
?
X
?
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
BYTE
1
BYTE
2
BYTE
3
MPU
RECEIVED
WORD
?
?
1
?
?
?
B11 B10 B9 B8 B7
BYTE
B6 B5 B4 B3 B2 B1 B0 B1
BYTE
BYTE
2
3
1594/98 TA03
B11
D
OUT
V
OL
t
en
1594/98 TC06
Load Circuit for tdis and ten
Voltage Waveforms for tdis
TEST POINT
3k
CSADC = CSMUX = CS
V
IH
V
t
WAVEFORM 2, t
en
CC dis
D
OUT
D
OUT
90%
WAVEFORM 1
(SEE NOTE 1)
t
dis
WAVEFORM 1
100pF
t
dis
1594/98 TC04
D
OUT
WAVEFORM 2
(SEE NOTE 2)
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
1594/98 TC05
15948fb
9
LTC1594/LTC1598
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APPLICATIONS INFORMATION
and can operate with reduced spans to 1.5V. Reducing
OVERVIEW
the spans allow them to achieve 366μV resolution.
TheLTC1594/LTC1598aremicropower,12-bitsampling
A/D converters that feature a 4- and 8-channel multi-
plexer respectively. They typically draw only 320μA of
supply current when sampling at 16.8kHz. Supply cur-
rent drops linearly as the sample rate is reduced (see
SupplyCurrentvsSampleRate). TheADCsautomatically
power down when not performing conversions, drawing
onlyleakagecurrent.TheLTC1594isavailableina16-pin
narrow SO package and the LTC1598 is packaged in a
24-pin SSOP. Both devices operate on a single supply
from 4.5V to 5.5V.
The LTC1594/LTC1598 provide separate MUX output
and ADC input pins to form an ideal MUXOUT/ADCIN
loop which economizes signal conditioning. The MUX
andADCofthedevicescanalsobecontrolledindividually
through separate chip selects to enhance flexibility.
SERIAL INTERFACE
For this discussion we will assume that CSMUX and
CSADC are tied together and will refer to them as simply
CS, unless otherwise specified.
The LTC1594/LTC1598 contain a 12-bit, switched-
capacitor ADC, sample-and-hold, serial port and an
externalreferenceinputpin.Inaddition,theLTC1594has
a 4-channel multiplexer and the LTC1598 provides an
8-channel multiplexer (see Block Diagram). They can
measure signals floating on a DC common mode voltage
TheLTC1594/LTC1598communicatewiththemicropro-
cessor and other external circuitry via a synchronous,
halfduplex, 4-wireinterface(seeOperatingSequencesin
Figures 1 and 2).
t
CYC
CSMUX = CSADC = CS
t
suCS
CLK
EN
D1
D
IN
DON’T CARE
D0
D2
NULL
BIT
Hi-Z
Hi-Z
D
OUT
B3 B2 B1 B0*
B11 B10 B9 B8 B7 B6 B5 B4
t
SMPL
t
CONV
CH0 TO
CH7
t
ON
ADCIN =
MUXOUT
COM = GND
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY
1594/98 F01
Figure 1. LTC1594/LTC1598 Operating Sequence Example: CH2, GND
15948fb
10
LTC1594/LTC1598
U
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APPLICATIONS INFORMATION
t
CYC
CSMUX = CSADC = CS
t
suCS
CLK
EN
D1
D
D0N‘T CARE
IN
D0
D2
NULL
BIT
Hi-Z
Hi-Z
D
OUT
DUMMY CONVERSION
t
CONV
CH0 TO
CH7
t
OFF
ADCIN =
MUXOUT
1594/98 F02
COM = GND
Figure 2. LTC1594/LTC1598 Operating Sequence Example: All Channels Off
Data Transfer
break-before-make interval, tOPEN. After a delay of tON
(tOFF + tOPEN), the selected channel is switched on,
allowing the ADC in the chip to acquire input signal and
start the conversion (see Figures 1 and 2). After 1 null bit,
the result of the conversion is output on the DOUT line.
The selected channel remains on, until the next falling
edge of CS. At the end of the data exchange CS should be
brought high. This resets the LTC1594/LTC1598 and
initiates the next data exchange.
The CLK synchronizes the data transfer with each bit
being transmitted on the falling CLK edge and captured
on the rising CLK edge in both transmitting and receiving
systems.
The LTC1594/LTC1598 first receive input data and then
transmit back the A/D conversion results (half duplex).
Because of the half duplex operation, DIN and DOUT may
be tied together allowing transmission over just 3 wires:
CS, CLK and DATA (DIN/DOUT).
CS
Data transfer is initiated by a rising chip select (CS)
signal. After CS rises the input data on the DIN pin is
latchedintoa4-bitregisterontherisingedgeoftheclock.
More than four input bits can be sent to the DIN pin
without problems, but only the last four bits clocked in
before CS falls will be stored into the 4-bit register. This
4-bit input data word will select the channel in the
multiplexer (see Input Data Word and Tables 1 and 2). To
ensure correct operation the CS must be pulled low
before the next rising edge of the clock.
D
D
IN2
IN1
D
D
OUT2
OUT1
SHIFT MUX
ADDRESS IN
SHIFT A/D CONVERSION
RESULT OUT
1594/98 AI01
t
+ 1 NULL BIT
SMPL
Break-Before-Make
The LTC1594/LTC1598 provide a break-before-make
interval from switching off all the channels simulta-
neously to switching on the next selected channel once
CS is pulled low. In other words, once CS is pulled low,
Once the CS is pulled low, all channels are simulta-
neously switched off after a delay of tOFF to ensure a
15948fb
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LTC1594/LTC1598
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Table 2. Logic Table for the LTC1598 Channel Selection
after a delay of tOFF, all the channels are switched off to
ensure a break-before-make interval. After this interval,
the selected channel is switched on allowing signal
transmission. The selected channel remains on until the
next falling edge of CS and the process repeats itself with
the “EN” bit being logic high. If the “EN” bit is logic low,
all the channels are switched off simultaneously after a
delay of tOFF from CS being pulled low and all the
channels remain off until the next falling edge of CS.
CHANNEL STATUS
EN
0
D2
X
0
D1
X
0
DO
X
0
All Off
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
Input Data Word
1
1
1
1
When CS is high, the LTC1594/LTC1598 clock data into
theDIN inputsontherisingedgeoftheclockandstorethe
dataintoa4-bitregister.Theinputdatawordsaredefined
as follows:
Transfer Curve
The LTC1594/LTC1598 are permanently configured for
unipolar only. The input span and code assignment for
this conversion type is illustrated below.
EN
D2
D1
D0
Transfer Curve
CHANNEL SELECTION
1594/98 AI02
“EN” Bit
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
The first bit in the 4-bit register is an “EN” bit. If the “EN”
bit is a logic high, as illustrated in Figure 1, it enables the
selectedchannelafteradelayoftON whentheCSispulled
low. If the “EN” bit is logic low, as illustrated in Figure 2,
it disables all channels after a delay of tOFF when the CS
is pulled low.
•
•
•
0 0 0 0 0 0 0 0 0 0 0 1
V
IN
0 0 0 0 0 0 0 0 0 0 0 0
V
REF
4096
1LSB =
1594/98 • AI03
Multiplexer (MUX) Address
The 3 bits of input word following the “EN” bit select the
channel in the MUX for the requested conversion. For a
given channel selection, the converter will measure the
voltage of the selected channel with respect to the voltage
on the COM pin. Tables 1 and 2 show the various bit
combinationsfortheLTC1594/LTC1598channelselection.
Output Code
INPUT VOLTAGE
(V = 5.000V)
OUTPUT CODE
INPUT VOLTAGE
REF
4.99878V
1 1 1 1 1 1 1 1 1 1 1 1 1 1
V
V
– 1LSB
REF
REF
4.99756V
1 1 1 1 1 1 1 1 1 1 1 1 1 0
– 2LSB
•
•
•
•
•
•
•
•
•
0.00122V
0V
0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
1LSB
0V
Table 1. Logic Table for the LTC1594 Channel Selection
1594/98 • AI04
CHANNEL STATUS
EN
0
D2
X
0
D1
X
0
DO
X
All Off
CH0
CH1
CH2
CH3
1
0
1
0
0
1
1
0
1
0
1
0
1
1
15948fb
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LTC1594/LTC1598
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Operation with DIN and DOUT Tied Together
Therefore the processor port line must be switched to an
input with CS being low to avoid a conflict.
The LTC1594/LTC1598 can be operated with DIN and
DOUT tied together. This eliminates one of the lines
required to communicate to the microprocessor (MPU).
Data is transmitted in both directions on a single wire.
The processor pin connected to this data line should be
configurableaseitheraninputoranoutput.TheLTC1594/
LTC1598 will take control of the data line after CS falling
and before the 6th falling CLK while the processor takes
control of the data line when CS is high (see Figure 3).
Separate Chip Selects for MUX and ADC
The LTC1594/LTC1598 provide separate chip selects,
CSMUXandCSADC, tocontrolMUXandADCseparately.
This feature not only provides the flexibility to select a
particular channel once for multiple conversions (see
Figure 4) but also maximizes the sample rate up to
20ksps (see Figure 5).
t
suCS
CS
1
2
3
4
5
6
CLK
DATA (D /D
)
EN
D2
D1
D0
B11
B10
IN OUT
• • •
MPU CONTROLS DATA LINE AND SENDS
MUX ADDRESS TO LTC1594/LTC1598
LTC1594/LTC1598 CONTROLS DATA LINE AND SENDS
A/D RESULT BACK TO MPU
PROCESSOR MUST RELEASE DATA
LINE AFTER CS FALLING AND
BEFORE THE 6TH FALLING CLK
LTC1594/LTC1598 TAKES CONTROL OF DATA
LINE AFTER CS FALLING AND BEFORE THE
6TH FALLING CLK
1594/98 F03
Figure 3. LTC1594/LTC1598 Operation with DIN and DOUT Tied Together
CSMUX
CSADC
CLK
t
t
suCS
suCS
EN
D1
D
IN
DON’T CARE
DON’T CARE
D0
D0
D2
NULL
BIT
NULL
BIT
Hi-Z
Hi-Z
Hi-Z
D
OUT
B3 B2 B1 B0
B3 B2 B1 B0
B11 B10 B9 B8 B7 B6 B5 B4
B11 B10 B9 B8 B7 B6 B5 B4
t
t
SMPL
SMPL
t
t
CONV
CONV
CH0 TO
CH7
t
ON
ADCIN =
MUXOUT
1594 TD01
COM = GND
Figure 4. Select Certain Channel Once for Mulitple Conversions
15948fb
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LTC1594/LTC1598
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APPLICATIONS INFORMATION
CSADC
CSMUX
t
t
suCS
suCS
CLK
EN
D1
EN
D1
EN
D1
D
IN
DON’T CARE
DON’T CARE
D0
D2
B3 B2 B1 B0
D0
D2
D0
D2
B3 B2 B1 B0
NULL
BIT
NULL
BIT
D
OUT
B3 B2 B1 B0
B4
B11 B10 B9 B8 B7 B6 B5 B4
B11 B10 B9 B8 B7 B6 B5 B4
t
t
SMPL
SMPL
t
t
CONV
CONV
CH0 TO
CH7
t
t
ON
ON
ADCIN =
MUXOUT
1594/98 F05
COM = GND
Figure 5. Use Separate Chip Selects to Maximize Sample Rate
1000
MUXOUT/ADCIN Loop Economizes
Signal Conditioning
T
= 25°C
A
V
V
= 5V
CC
REF
CLK
= 5V
= 320kHz
f
The MUXOUT and ADCIN pins of the LTC1594/LTC1598
form a very flexible external loop that allows Program-
mable Gain Amplifier (PGA) and/or processing analog
input signals prior to conversion. This loop is also a cost
effective way to perform the conditioning, because only
one circuit is needed instead of one for each channel.
100
10
1
In the Typical Applications section, there are a few
examplesillustratinghowtousetheMUXOUT/ADCINloop
to form a PGA and to antialias filter several analog inputs.
0.1
1
10
100
SAMPLE FREQUENCY (kHz)
1594/98 F06
Figure 6. Automatic Power Shutdown Between Conversions
Allows Power Consumption to Drop with Sample Rate
ACHIEVING MICROPOWER PERFORMANCE
With typical operating currents of 320μA and automatic
shutdown between conversions, the LTC1594/LTC1598
achieve extremely low power consumption over a wide
range of sample rates (see Figure 6). The auto shutdown
allows the supply current to drop with reduced sample
rate.Severalthingsmustbetakenintoaccounttoachieve
such a low power consumption.
leaving the CLK running to clock the input data word into
MUX.IftheCS,DIN andCLKarenotrunningrail-to-rail,the
input logic buffers will draw currents. These currents may
be large compared to the typical supply current. To obtain
the lowest supply current, run the CS, DIN and CLK pins
rail-to-rail.
DOUT Loading
Shutdown
Capacitive loading on the digital output can increase
power consumption. A 100pF capacitor on the DOUT pin
can add more than 80mA to the supply current at a
320kHz clock frequency. An extra 80mA or so of current
goes into charging and discharging the load capacitor.
The same goes for digital lines driven at a high frequency
by any logic. The (C)(V)(f) currents must be evaluated
TheLTC1594/LTC1598areequippedwithautomaticshut-
down features. They draw power when the CS pin is low.
The bias circuits and comparator of the ADC powers down
and the reference input becomes high impedance at the
end of each conversion leaving the CLK running to clock
outtheLSBfirstdataorzeroes(seeFigures1and2).When
the CS pin is high, the ADC powers down completely
and the troublesome ones minimized.
15948fb
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LTC1594/LTC1598
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BOARD LAYOUT CONSIDERATIONS
SAMPLE-AND-HOLD
Both the LTC1594/LTC1598 provide a built-in sample-
and-hold (S&H) function to acquire signals through the
selected channel, assuming the ADCIN and MUXOUT
pins are tied together. The S & H of these parts acquire
input signals through the selected channel relative to
COM input during the tSMPL time (see Figure 7).
Grounding and Bypassing
The LTC1594/LTC1598 are easy to use if some care is
taken. They should be used with an analog ground plane
and single point grounding techniques. The GND pin
should be tied directly to the ground plane.
The VCC pin should be bypassed to the ground plane with
a10μFtantalumcapacitorwithleadsasshortaspossible.
If the power supply is clean, the LTC1594/LTC1598 can
also operate with smaller 1μF or less surface mount or
ceramic bypass capacitors. All analog inputs should be
referenced directly to the single point ground. Digital
inputs and outputs should be shielded from and/or
routed away from the reference and analog circuitry.
Single-Ended Inputs
The sample-and-hold of the LTC1594/LTC1598 allows
conversion of rapidly varying signals. The input voltage
is sampled during the tSMPL time as shown in Figure 7.
The sampling interval begins after tON time once the CS
is pulled low and continues until the second falling CLK
edge after the CS is low (see Figure 7). On this falling CLK
SAMPLE
HOLD
“ANALOG” INPUT MUST
SETTLE DURING
THIS TIME
t
ON
CSADC = CSMUX = CS
CLK
t
t
CONV
SMPL
DON‘T CARE
D
IN
EN
D2
D1
D0
D
OUT
B11
1ST BIT TEST “COM” INPUT MUST
SETTLE DURING THIS TIME
MUXOUT = ADCIN
CH0 TO CH7
COM
1594/98 F07
Figure 7. LTC1594/LTC1598 ADCIN and COM Input Settling Windows
15948fb
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LTC1594/LTC1598
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During the conversion, the “analog” input voltage is
effectively “held” by the sample-and-hold and will not
affecttheconversionresult. However, itiscriticalthatthe
“COM” input voltage settles completely during the first
CLK cycle of the conversion time and be free of noise.
Minimizing RSOURCE– and C2 will improve settling time.
If a large “COM” input source resistance must be used,
the time allowed for settling can be extended by using a
slower CLK frequency.
edge, the S & H goes into hold mode and the conversion
begins. The voltage on the “COM” input must remain
constant and be free of noise and ripple throughout the
conversion time. Otherwise, the conversion operation
may not be performed accurately. The conversion time is
12 CLK cycles. Therefore, a change in the “COM” input
voltage during this interval can cause conversion errors.
For a sinusoidal voltage on the “COM” input this error
would be:
V
ERROR(MAX) = VPEAK(2π)(f)(“COM”)12/fCLK
Input Op Amps
Where f(“COM”) is the frequency of the “COM” input
voltage, VPEAK is its peak amplitude and fCLK is the
frequency of the CLK. In most cases VERROR will not be
significant. For a 60Hz signal on the “COM” input to
generate a 1/4LSB error (305μV) with the converter
running at CLK = 320kHz, its peak value would have to be
8.425mV.
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 7). Again, the “analog” and “COM” input
sampling times can be extended as described above to
accommodatesloweropamps. Mostopamps, including
the LT®1006 and LT1413 single supply op amps, can be
made to settle well even with the minimum settling
windows of 4.8μs (“analog” input) which occur at the
maximum clock rate of 320kHz.
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1594/
LTC1598 have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem. However, if large source resistances are used
or if slow settling op amps drive the inputs, care must be
taken to insure that the transients caused by the current
spikes settle completely before the conversion begins.
Source Resistance
The analog inputs of the LTC1594/LTC1598 look like a
20pF capacitor (CIN) in series with a 500Ω resistor (RON)
and a 45Ω channel resistance as shown in Figure 8.
CIN gets switched between the selected “analog” and
“COM” inputs once during each conversion cycle. Large
external source resistors and capacitances will slow the
settling of the inputs. It is important that the overall RC
time constants be short enough to allow the analog
inputs to completely settle within the allowed time.
“Analog” Input Settling
The input capacitor of the LTC1594/LTC1598 is switched
onto the selected channel input during the tSMPL time (see
Figure7)andsamplestheinputsignalwithinthattime.The
sample phase is at least 1 1/2 CLK cycles before conver-
sion starts. The voltage on the “analog” input must settle
completely within tSMPL. Minimizing RSOURCE+ and C1 will
improve the input settling time. If a large “analog” input
source resistance must be used, the sample time can be
increased by using a slower CLK frequency.
MUX
“ANALOG”
+
R
45Ω
ON
INPUT
R
SOURCE
MUXOUT
ADCIN
LTC1594
LTC1598
V
+
IN
R
ON
C1
500Ω
C
“COM”
INPUT
IN
20pF
–
R
SOURCE
V
–
IN
1594/98 • F08
C2
“COM” Input Settling
Figure 8. Analog Input Equivalent Circuit
AttheendofthetSMPL,theinputcapacitorswitchestothe
“COM” input and conversion starts (see Figures 1 and 7).
15948fb
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Input Leakage Current
Offset with Reduced VREF
Inputleakagecurrentscanalsocreateerrorsifthesource
resistance gets too large. For instance, the maximum
input leakage specification of 200nA (at 85°C) flowing
through a source resistance of 1.2k will cause a voltage
drop of 240μV or 0.2LSB. This error will be much
reduced at lower temperatures because leakage drops
rapidly (see typical curve Input Channel Leakage Current
vs Temperature).
TheoffsetoftheLTC1594/LTC1598hasalargereffecton
the output code when the ADCs are operated with
reduced reference voltage. The offset (which is typically
afixedvoltage)becomesalargerfractionofanLSBasthe
size of the LSB is reduced. The typical curve of Change in
Offset vs Reference Voltage shows how offset in LSBs is
related to reference voltage for a typical value of VOS. For
example, a VOS of 122μV which is 0.1LSB with a 5V
reference becomes 0.5LSB with a 1V reference and
2.5LSBs with a 0.2V reference. If this offset is unaccept-
able, it can be corrected digitally by the receiving system
orbyoffsettingthe“COM”inputoftheLTC1594/LTC1598.
REFERENCE INPUTS
The reference input of the LTC1594/LTC1598 is effec-
tively a 50k resistor from the time CS goes low to the end
of the conversion. The reference input becomes a high
impedance node at any other time (see Figure 9). Since
the voltage on the reference input defines the voltage
span of the A/D converter, the reference input should be
driven by a reference with low ROUT(ex. LT1004, LT1019
Noise with Reduced VREF
The total input referred noise of the LTC1594/LTC1598
can be reduced to approximately 400μV peak-to-peak
using a ground plane, good bypassing, good layout
techniquesandminimizingnoiseonthereferenceinputs.
This noise is insignificant with a 5V reference but will
become a larger fraction of an LSB as the size of the LSB
is reduced.
and LT1021) or a voltage source with low ROUT
.
+
REF
LTC1594
LTC1598
1
R
OUT
Foroperationwitha5Vreference,the400μVnoiseisonly
0.33LSBpeak-to-peak.Inthiscase,theLTC1594/LTC1598
noisewillcontributevirtuallynouncertaintytotheoutput
code. However, for reduced references the noise may
become a significant fraction of an LSB and cause
undesirable jitter in the output code. For example, with a
2.5V reference this same 400μV noise is 0.66LSB peak-
to-peak. This will reduce the range of input voltages over
which a stable output code can be achieved by 1LSB. If
the reference is further reduced to 1V, the 400μV noise
becomes equal to 1.65LSBs and a stable code may be
difficult to achieve. In this case averaging multiple read-
ings may be necessary.
V
REF
GND
4
1594/98 F09
Figure 9. Reference Input Equivalent Circuit
Reduced Reference Operation
The effective resolution of the LTC1594/LTC1598 can be
increased by reducing the input span of the converters.
The LTC1594/LTC1598 exhibit good linearity and gain
over a wide range of reference voltages (see typical
curves Change in Linearity vs Reference Voltage and
Change in Gain vs Reference Voltage). However, care
must be taken when operating at low values of VREF
because of the reduced LSB step size and the resulting
higher accuracy requirement placed on the converters.
The following factors must be considered when operat-
ing at low VREF values:
Thisnoisedatawastakeninaverycleansetup. Anysetup
induced noise (noise or ripple on VCC, VREF or VIN) will
add to the internal noise. The lower the reference voltage
to be used the more critical it becomes to have a clean,
noise free setup.
1. Offset
2. Noise
3. Conversion speed (CLK frequency)
15948fb
17
LTC1594/LTC1598
U
W U U
APPLICATIONS INFORMATION
Conversion Speed with Reduced VREF
Effective Number of Bits
With reduced reference voltages, the LSB step size is
reduced and the LTC1594/LTC1598 internal comparator
overdrive is reduced. Therefore, it may be necessary to
reduce the maximum CLK frequency when low values of
TheEffectiveNumberofBits(ENOBs)isameasurementof
the resolution of an ADC and is directly related to S/(N + D)
by the equation:
ENOB = [S/(N + D) – 1.76]/6.02
V
REF are used.
where S/(N + D) is expressed in dB. At the maximum
sampling rate of 16.8kHz with a 5V supply, the LTC1594/
LTC1598 maintain above 11 ENOBs at 10kHz input
frequency. Above 10kHz the ENOBs gradually decline, as
shown in Figure 11, due to increasing second harmonic
distortion. The noise floor remains low.
DYNAMIC PERFORMANCE
The LTC1594/LTC1598 have exceptional sampling capa-
bility. Fast Fourier Transform (FFT) test techniques are
used to characterize the ADC’s frequency response,
distortion and noise at the rated throughput. By applying
a low distortion sine wave and analyzing the digital
output using an FFT algorithm, the ADC’s spectral con-
tent can be examined for frequencies outside the funda-
mental. Figure 10 shows a typical LTC1594/LTC1598
plot.
12
11
74
68
10
9
62
56
50
44
38
8
7
6
0
5
T
= 25°C
CC
= 5kHz
= 320kHz
= 12.5kHz
A
4
3
V
f
= V
= 5V
REF
–20
T
= 25°C
A
IN
CLK
SMPL
V
f
= 5V
f
f
CC
2
1
= 320kHz
–40
–60
CLK
SMPL
f
= 16.8kHz
0
1
10
100
1000
INPUT FREQUENCY (kHz)
–80
1594/98 G10
–100
–120
Figure 11. Effective Bits and S/(N + D) vs Input Frequency
–140
Total Harmonic Distortion
4
6
7
0
1
2
3
5
FREQUENCY (kHz)
Total Harmonic Distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamen-
tal itself. The out-of-band harmonics alias into the fre-
quency band between DC and half of the sampling
frequency. THD is defined as:
1594/98 G14
Figure 10. LTC1594/LTC1598 Nonaveraged, 4096 Point FFT Plot
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio (S/N + D) is the
ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other fre-
quency components at the ADC’s output. The output is
band limited to frequencies above DC and below one half
the sampling frequency. Figure 11 shows a typical spec-
tral content with a 16.8kHz sampling rate.
V2 + V32 + V42 + ... + V2
2
N
THD = 20log
V
1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through the Nth harmonics. The typical THD
15948fb
18
LTC1594/LTC1598
U
W U U
APPLICATIONS INFORMATION
specification in the Dynamic Accuracy table includes the
2nd through 5th harmonics. With a 7kHz input signal, the
LTC1594/LTC1598havetypicalTHDof80dBwithVCC =5V.
For input frequencies of 5kHz and 6kHz, the IMD of the
LTC1594/LTC1598 is 73dB with a 5V supply.
Peak Harmonic or Spurious Noise
Intermodulation Distortion
The peak harmonic or spurious noise is the largest
If the ADC input signal consists of more than one spectral component excluding the input signal and DC.
spectral component, the ADC transfer function nonlin- This value is expressed in dBs relative to the RMS value
earity can produce intermodulation distortion (IMD)
in addition to THD. IMD is the change in one sinusoi-
dal input caused by the presence of another sinusoidal
input at a different frequency.
of a full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer
functioncancreatedistortionproductsatsumanddiffer-
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include (fa +
fb) and (fa – fb) while 3rd order IMD terms include (2fa +
fb), (2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine
waves are equal in magnitudes, the value (in dB) of the
2nd order IMD products can be expressed by the follow-
ing formula:
The full-linear bandwidth is the input frequency at which
the effective bits rating of the ADC falls to 11 bits. Beyond
this frequency, distortion of the sampled input signal
increases.TheLTC1594/LTC1598havebeendesignedto
optimize input bandwidth, allowing the ADCs to
undersample input signals with frequencies above the
converters’ Nyquist Frequency.
⎡
⎤
⎥
amplitude f ± f
(
)
a
b
⎢
IMD f ± f = 20log
(
)
a
b
⎢
⎣
⎥
⎦
amplitude at fa
U
TYPICAL APPLICATIONS N
Microprocessor Interfaces
Motorola SPI (MC68HC05)
The LTC1594/LTC1598 can interface directly (without
external hardware) to most popular microprocessors’
(MPU) synchronous serial formats including
MICROWIRE, SPI and QSPI. If an MPU without a dedi-
cated serial port is used, then three of the MPU’s parallel
port lines can be programmed to form the serial link to the
LTC1594/LTC1598. Included here is one serial interface
example.
TheMC68HC05hasbeenchosenasanexampleofanMPU
withadedicatedserialport. ThisMPUtransfersdataMSB-
first and in 8-bit increments. The DIN word sent to the data
register starts the SPI process. With three
8-bit transfers the A/D result is read into the MPU. The
second 8-bit transfer clocks B11 through B7 of the A/D
conversion result into the processor. The third 8-bit trans-
fer clocks the remaining bits B6 through B0 into the MPU.
ANDing the second byte with 1FHEX clears the three most
significantbitsandANDingthethirdbytewithFEHEX clears
theleastsignificantbit. Shiftingthedatatotherightbyone
bit results in a right justified word.
15948fb
19
LTC1594/LTC1598
U
TYPICAL APPLICATIONS N
MC68HC05 CODE
BPL LOOP1 Loop if not done with transfer to previous instruction
LDA #$52 Configuration data for serial peripheral
control register (Interrupts disabled, output
enabled, master, Norm = 0, Ph = 0, Clk/16)
BCLR 0,$02 Bit 0 Port C ($02) goes low (CS goes low)
LDA $0C
STA $0C
Load contents of SPI data register into Accumulator
Start next SPI cycle
STA $0A
Load configuration data into location $0A (SPCR)
LDA #$FF Configuration data for I/O ports
(all bits are set as outputs)
LOOP2 TST $0B
Test status of SPIF
BPL LOOP2 Loop if not done
STA $04
STA $05
STA $06
Load configuration data into Port A DDR ($04)
LDA $0C
STA $0C
Load contents of SPI data register into Accumulator
Start next SPI cycle
Load configuration data into Port B DDR ($05)
Load configuration data into Port C DDR ($06)
AND #$IF
Clear 3 MSBs of first D
word
OUT
LDA #$08 Put D word for LTC1598 into Accumulator
STA $00
Load Port A ($00) with MSBs
Test status of SPIF
IN
(CH0 with respect to GND)
LOOP3 TST $0B
STA $50
Load D word into memory location $50
IN
BPL LOOP3 Loop if not done
START BSET 0,$02 Bit 0 Port C ($02) goes high (CS goes high)
LDA $0C
Load contents of SPI data register into Accumulator
LDA $50
STA $0C
Load D word at $50 into Accumulator
AND #$FE Clear LSB of second D
word
IN
IN
OUT
Load D word into SPI data register ($0C) and
STA $01
Load Port B ($01) with LSBs
start clocking data
JMP START Go back to start and repeat program
LOOP1 TST $0B
Test status of SPIF bit in SPI status register ($0B)
Data Exchange Between LTC1598 and MC68HC05
CSMUX
= CSADC
= CS
CLK
EN D2 D1 DO
DON‘T CARE
D
IN
D
OUT
B11 B10 B9 B8 B7
B6
B5 B4 B3 B2 B1 B0 B1 B2
MPU
TRANSMIT
WORD
0
?
0
?
0
?
0
EN D2 D1 D0
X
?
X
?
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
BYTE 2
BYTE 1
BYTE 3
MPU
RECEIVED
WORD
?
?
?
?
?
B11 B10 B9 B8 B7
BYTE 2
B6 B5 B4
B2 B1 B0
BYTE 3
B3
B1
BYTE 1
1594/98 TA03
Hardware and Software Interface to Motorola MC68HC05
D
FROM LTC1598 STORED IN MC68HC05 RAM
OUT
MSB
C0
MC68HC05
CSMUX
CSADC
0
BYTE 1
BYTE 2
B11 B10
B8
B7
0
0
0
B9
B1
#00
#01
ANALOG
INPUTS
SCK
LTC1598 CLK
LSB
B0
D
MOSI
MISO
IN
B6
B5
B4
B2
B3
D
OUT
1594/98 TA04
15948fb
20
LTC1594/LTC1598
U
TYPICAL APPLICATIONS N
MULTICHANNEL A/D USES A SINGLE ANTIALIASING
FILTER
than 1LSB of error due to offsets and bias currents. The
filter’s noise and distortion are less than –72dB for a
100Hz, 2VP-P offset sine input.
This circuit demonstrates how the LTC1598’s indepen-
dent analog multiplexer can simplify design of a 12-bit
dataacquisitionsystem.AlleightchannelsareMUXedinto
a single 1kHz, 4th order Sallen-Key antialiasing filter,
which is designed for single supply operation. Since the
LTC1598’s data converter accepts inputs from ground to
the positive supply, rail-to-rail op amps were chosen for
thefiltertomaximizedynamicrange.TheLT1368dualrail-
to-rail op amp is designed to operate with 0.1μF load
capacitors (C1 and C2). These capacitors provide fre-
quency compensation for the amplifiers and help reduce
the amplifier’s output impedance and improve supply
rejection at high frequencies. The filter contributes less
The combined MUX and A/D errors result in an integral
nonlinearity error of ± 3LSB (maximum) and a differential
nonlinearity error of ±3/4LSB (maximum). The typical
signal-to-noise plus distortion ratio is 71dB, with approxi-
mately –78dB of total harmonic distortion. The LTC1598
is programmed through a 4-wire serial interface that is
compatable with MICROWIRE, SPI and QSPI. Maximum
serial clock speed is 320kHz, which corresponds to a
16.8kHz sampling rate.
The complete circuit consumes approximately 800μA
from a single 5V supply.
Simple Data Acquisition System Takes Advantage of the LTC1598’s
MUXOUT/ADCIN Pins-to-Filter Analog Signals Prior to A/D Conversion
ANALOG INPUTS
0V TO 5V
5V
RANGE
1
2
24
CH4
0.015μF
CH5
CH6
CH7
GND
CLK
1μF
23
CH3
7.5k
7.5k
3
22
+
CH2
1/2
LT1368
4
21
0.03μF
CH1
CH0
C2
5
20
19
18
17
16
15
14
13
–
LTC1598
5V
0.1μF
6
CSMUX
V
CC
7
1μF
D
MUXOUT
ADCIN
IN
8
COM
7.5k
7.5k
9
GND
V
+
REF
10
11
12
1/2
LT1368
0.015μF
0.03μF
CSADC
V
CC
C1
D
CLK
NC
OUT
–
0.1μF
NC
DATA OUT
DATA IN
1594/98 TA05
CHIP SELECT
CLOCK
15948fb
21
LTC1594/LTC1598
U
TYPICAL APPLICATIONS N
is the summation of the resistors below the selected MUX
channel. If CH0 is selected, the loop gain is 1 since RS1 is
0. Table 1 shows the gain for each MUX channel. The
LT1368dualrail-to-railopampisdesignedtooperatewith
0.1μFloadcapacitors.Thesecapacitorsprovidefrequency
compensation for the amplifiers, help reduce the amplifi-
ers’ output impedance and improve supply rejection at
high frequencies. Because the LT1368’s IB is low, the RON
of the selected channel will not affect the loop gain given
by the formula above.
Using MUXOUT/ADCIN Loop as PGA
This figure shows the LTC1598’s MUXOUT/ADCIN loop
and an LT1368 being used to create a single channel PGA
witheightnoninvertinggains.CombinedwiththeLTC1391,
the system can expand to eight channels and eight gains
for each channel. Using the LTC1594, the PGA is reduced
to four gains. The output of the LT1368 drives the ADCIN
and the resistor ladder. The resistors above the selected
MUX channel form the feedback for the LT1368. The loop
gainforthisamplifierisRS1/RS2 +1. RS1 isthesummation
of the resistors above the selected MUX channel and RS2
Using the MUXOUT/ADCIN Loop of the LTC1598 to Form a PGA with Eight Gains in a Noninverting Configuration
5V
5V
1 F
LTC1391
1
2
3
4
5
6
7
8
16
+
V
1 F
CH0
CH1
CH2
CH3
CH4
CH5
CH6
15
14
13
12
11
10
9
D
+
–
V
1/2 LT1368
5V
0.1 F
D
OUT
–
D
IN
CS
CLK
17
ADCIN
16
V
15, 19
1 F
V
REF
CC
64R
32R
16R
8R
4R
2R
R
20 CH0
21 CH1
22 CH2
23 CH3
24 CH4
CH7 GND
10
6
CSADC
CSMUX
CLK
5, 14
11
8-CHANNEL
MUX
12-BIT
SAMPLING
ADC
+
P/ C
D
OUT
1
2
3
CH5
CH6
CH7
7
D
IN
–
R
LTC1598
12
13
18 MUXOUT
COM
NC
NC
8
GND
4, 9
1594/98 TA06
15948fb
22
LTC1594/LTC1598
U
PACKAGE DESCRIPTION
G Package
24-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
7.90 – 8.50*
(.311 – .335)
1.25 ±0.12
24 23 22 21 20 19 18 17 16 15 14
13
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
RECOMMENDED SOLDER PAD LAYOUT
0.65 BSC
5
7
8
1
2
3
4
6
9 10 11 12
2.0
5.00 – 5.60**
(.197 – .221)
(.079)
MAX
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.25
0.55 – 0.95
(.0035 – .010)
(.022 – .037)
0.05
0.22 – 0.38
(.009 – .015)
TYP
(.002)
NOTE:
MIN
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
G24 SSOP 0204
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
S Package
16-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.386 – .394
(9.804 – 10.008)
.045 ±.005
NOTE 3
.050 BSC
16
N
15
14
13
12
11
10
9
N
1
.245
MIN
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
2
3
N/2
N/2
.030 ±.005
TYP
RECOMMENDED SOLDER PAD LAYOUT
5
6
7
8
1
2
3
4
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0° – 8° TYP
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
.016 – .050
(0.406 – 1.270)
S16 0502
NOTE:
1. DIMENSIONS IN
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
15948fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC1594/LTC1598
TYPICAL APPLICATION
U
Using the LTC1598 and LTC1391 as an 8-Channel Differential 12-Bit ADC System
5V
18
MUXOUT
17
ADCIN
16
V
15, 19
1μF
V
REF
CC
20 CH0
21 CH1
22 CH2
23 CH3
24 CH4
10
6
CSADC
CSMUX
CLK
5V
5, 14
7
12-BIT
SAMPLING
ADC
8-CHANNEL
MUX
+
1μF
D
IN
1
2
3
CH5
CH6
CH7
11
D
OUT
–
LTC1391
12
13
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
NC
+
V
CH0
CH7
CH0
LTC1598
8
COM
CH1
CH2
CH3
CH4
CH5
CH6
D
–
GND
4, 9
V
D
OUT
D
IN
CS
CLK
CH7 GND
D
IN
CLK
CS
D
OUT
1594/98 TA07
RELATED PARTS
PART NUMBER
LTC1096/LTC1098
LTC1096L/LTC1098L
LTC1196/LTC1198
LTC1282
DESCRIPTION
COMMENTS
8-Pin SO, Micropower 8-Bit ADC
8-Pin SO, 2.65V Micropower 8-Bit ADC
8-Pin SO, 1Msps 8-Bit ADC
Low Power, Small Size, Low Cost
Low Power, Small Size, Low Cost
Low Power, Small Size, Low Cost
3V High Speed Parallel 12-Bit ADC
8-Pin SO, 3V, Micropower 12-Bit ADC
8-Pin SO, 5V, Micropower 12-Bit ADC
Multiplexed 3V, 12-Bit ADC
140ksps, Complete with V , CLK, Sample-and-Hold
REF
LTC1285/LTC1288
LTC1286/LTC1298
LTC1289
1- or 2-Channel, Auto Shutdown
1- or 2-Channel, Auto Shutdown
8-Channel 12-Bit Serial I/O
LTC1290
Multiplexed 12-Bit ADC
8-Channel 12-Bit Serial I/O
LTC1415
5V High Speed Parallel 12-Bit ADC
4-Channel, 3V Micropower 12-Bit ADC
8-Channel, 3V Micropower 12-Bit ADC
1.25Msps, Complete with V , CLK, Sample-and-Hold
REF
LTC1594L
Low Power, Small Size, Low Cost
Low Power, Small Size, Low Cost
LTC1598L
15948fb
LT 0507 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 1996
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