LTC1594L [Linear]
4- and 8-Channel, 3V Micropower Sampling 12-Bit Serial I/O A/D Converters; 4和8通道， 3V微功率采样12位串行I / OA / D转换器
| 型号： | LTC1594L |
| 厂家： | 
Linear |
| 描述： | 4- and 8-Channel, 3V Micropower Sampling 12-Bit Serial I/O A/D Converters |
| 文件： | 总24页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1594L/LTC1598L
4- and 8-Channel,
3V Micropower Sampling
12-Bit Serial I/O A/D Converters
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FEATURES
DESCRIPTIO
The LTC®1594L/LTC1598L are 3V micropower, 12-bit
sampling A/D converters that feature 4- and 8-channel
multiplexers,respectively.Theytypicallydrawonly160µA
of supply current when converting and automatically
power down to a typical supply current of 1nA between
conversions. The LTC1594L is available in a 16-pin SO
package and the LTC1598L is packaged in a 24-pin
SSOP.Bothoperateona3Vsupply.The12-bit,switched-
capacitor, successive approximation ADCs include a
sample-and-hold.
■
12-Bit Resolution on 3V Supply
■
Low Supply Current: 160µA Typ
■
Auto Shutdown to 1nA
■
Guaranteed ±3/4LSB Max DNL
■
Guaranteed 2.7V Operation
(5V Versions Available: LTC1594/LTC1598)
■
Multiplexer: 4-Channel MUX (LTC1594L)
8-Channel MUX (LTC1598L)
■
Separate MUX Output and ADC Input Pins
■
MUX and ADC May Be Controlled Separately
■
Sampling Rate: 10.5ksps
On-chip serial ports allow efficient data transfer to a wide
I/O Compatible with QSPI, SPI and MICROWIRETM, etc.
Small Package: 16-Pin Narrow SO (LTC1594L)
■
rangeofmicroprocessorsandmicrocontrollersoverthree
or four wires. This, coupled with micropower consump-
tion, makes remote location possible and facilitates trans-
mitting data through isolation barriers.
■
24-Pin SSOP (LTC1598L)
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APPLICATIO S
The circuit can be used in ratiometric applications or with
an external reference. The high impedance analog inputs
and the ability to operate with reduced spans (to 1.5V full
scale) allow direct connection to sensors and transducers
in many applications, eliminating the need for gain stages.
■
Pen Screen Digitizing
■
Battery-Operated Systems
■
Remote Data Acquisition
■
Isolated Data Acquisition
■
Battery Monitoring
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
■
Temperature Measurement
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TYPICAL APPLICATION
12µW, 8-Channel, 12-Bit ADC Samples at 200Hz and Runs Off a 3V Supply
OPTIONAL
ADC FILTER
Supply Current vs Sample Rate
3V
1k
1µF
1000
100
10
T
= 25°C
A
V
V
= 2.7V
CC
REF
CLK
18
MUXOUT
17
ADCIN
16
V
15, 19
1µF
= 2.5V
= 200kHz
V
REF
CC
f
20 CH0
21 CH1
22 CH2
23 CH3
24 CH4
SERIAL DATA LINK
MICROWIRE AND
SPI COMPATABLE
10
6
CSADC
CSMUX
CLK
ANALOG
INPUTS
0V TO 3V
RANGE
5, 14
7
12-BIT
SAMPLING
ADC
8-CHANNEL
MUX
+
MPU
D
IN
1
2
3
CH5
CH6
CH7
11
D
OUT
–
12
13
NC
NC
LTC1598L
8
COM
1
GND
4, 9
0.1
1
10
100
1594L/98L TA01
SAMPLE FREQUENCY (kHz)
1594L/98L TA02
1
LTC1594L/LTC1598L
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ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCC) to GND................................... 12V
Voltage
Power Dissipation.............................................. 500mW
Operating Temperature Range
LTC1594LCS/LTC1598LCG ..................... 0°C to 70°C
LTC1594LIS/LTC1598LIG ................. –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Analog Reference .................... –0.3V to (VCC + 0.3V)
Analog Inputs .......................... –0.3V to (VCC + 0.3V)
Digital Inputs .........................................–0.3V to 12V
Digital Output .......................... –0.3V to (VCC + 0.3V)
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PACKAGE/ORDER INFORMATION
ORDER PART
ORDER PART
TOP VIEW
NUMBER
NUMBER
1
2
CH4
CH3
CH2
CH1
CH0
24
23
22
21
20
19
18
17
16
15
14
13
CH5
CH6
TOP VIEW
LTC1594LCS
LTC1594LIS
LTC1598LCG
LTC1598LIG
CH0
CH1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
3
CC
CH7
MUXOUT
4
GND
CH2
D
5
IN
CLK
CH3
CSMUX
CLK
6
V
CSMUX
CC
ADCIN
7
MUXOUT
ADCIN
D
IN
V
V
8
REF
COM
GND
CC
COM
GND
D
9
V
OUT
REF
CSADC
10
11
12
V
CSADC
CC
CLK
NC
D
OUT
NC
S PACKAGE
16-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 120°C/ W
G PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 110°C/ W
Consult factory for Military grade parts.
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RECOM ENDED OPERATING CONDITIONS The ● denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
2.7
(Note 4)
95
450
2
600
1.5
TYP
MAX
3.6
200
UNITS
V
kHz
µs
V
Supply Voltage (Note 3)
Clock Frequency
Total Cycle Time
CC
f
t
t
t
t
t
t
t
t
V
= 2.7V
CLK
CC
f
= 200kHz
= 2.7V
= 2.7V
= 2.7V
= 2.7V
CYC
CLK
Hold Time, D After CLK↑
V
V
V
V
V
ns
µs
ns
µs
µs
µs
µs
hDI
IN
CC
CC
Setup Time CS↓ Before First CLK↑ (See Operating Sequence)
Setup Time, D Stable Before CLK↑
CLK High Time
CLK Low Time
CS High Time Between Data Transfer Cycles
CS Low Time During Data Transfer
suCS
suDI
IN
CC
WHCLK
WLCLK
WHCS
WLCS
CC
= 2.7V
1.5
25
70
CC
f
f
= 200kHz
= 200kHz
CLK
CLK
2
LTC1594L/LTC1598L
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CONVERTER AND MULTIPLEXER CHARACTERISTICS
The ● denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1594LCS/LTC1598LCG
LTC1594LIS/LTC1598LIG
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Bits
LSB
LSB
LSB
LSB
V
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
REF Input Range
●
●
●
●
●
12
12
(Note 6)
±3
± 3/4
±3
±3
±1
±3
±8
±8
(Notes 7, 8)
(Notes 7, 8)
1.5V to V + 0.05V
CC
–0.05V to V + 0.05V
Analog Input Range
V
CC
MUX Channel Input Leakage Current Off Channel
●
●
●
±200
±200
±1
±200
±200
±1
nA
nA
µA
MUXOUT Leakage Current
Off Channel
(Note 9)
ADCIN Input Leakage Current
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DYNAMIC ACCURACY
TA = 25°C, fSMPL = 10.5kHz. (Note 5)
CONDITIONS
SYMBOL
S/(N + D)
THD
PARAMETER
MIN
TYP
68
MAX
UNITS
dB
Signal-to-Noise Plus Distortion Ratio
Total Harmonic Distortion (Up to 5th Harmonic)
Spurious-Free Dynamic Range
Peak Harmonic or Spurious Noise
1kHz Input Signal
1kHz Input Signal
1kHz Input Signal
1kHz Input Signal
–78
80
dB
dB
SFDR
–80
dB
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DIGITAL AND DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 3.6V
= 2.7V
●
●
●
●
2.0
IH
IL
CC
CC
IN
0.8
2.5
–2.5
V
µA
µA
V
V
I
I
= V
IH
IL
CC
= 0V
IN
V
V
V
= 2.7V, I = 10µA
●
●
2.4
2.1
2.64
2.30
OH
CC
CC
O
= 2.7V, I = 360µA
O
V
Low Level Output Voltage
Hi-Z Output Leakage
Output Source Current
Output Sink Current
V
= 2.7V, I = 400µA
●
●
0.4
±3
V
µA
mA
mA
OL
CC
O
I
I
I
CS = High
V
V
OZ
= 0V
–10
15
SOURCE
SINK
OUT
= V
OUT
CC
R
REF
Reference Input Resistance
CS = V
CS = V
2700
60
MΩ
kΩ
IH
IL
I
I
Reference Current
Supply Current
CS = V
●
0.001
50
50
0.001
160
160
2.5
µA
µA
µA
µA
µA
µA
REF
CC
t
t
≥ 760µs, f
≥ 60µs, f
≤ 25kHz
≤ 200kHz
CYC
CYC
CLK
●
●
70
±3
CLK
CS = V , CLK = V , D = V
CC
CC
CC IN
≤ 25kHz
≤ 200kHz
CC
t
t
≥ 760µs, f
≥ 60µs, f
CYC
CYC
CLK
●
320
CLK
3
LTC1594L/LTC1598L
The ● denotes the specifications which apply over the full operating temperature range,
AC CHARACTERISTICS
otherwise specifications are at TA = 25°C.(Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
1.5
10.5
TYP
MAX
UNITS
CLK Cycles
kHz
t
f
Analog Input Sample Time
Maximum Sampling Frequency
Conversion Time
Delay Time, CLK↓ to D
Delay Time, CS↑ to D
See Figure 1 in Applications Information
See Figure 1 in Applications Information
SMPL
●
SMPL(MAX)
t
t
t
t
t
t
t
t
t
t
See Figure 1 in Applications Information
See Test Circuits
See Test Circuits
12
600
220
180
520
60
CLK Cycles
CONV
dDO
dis
Data Valid
Hi-Z
Enabled
●
●
●
1500
600
500
ns
ns
ns
ns
ns
ns
ns
ns
ns
OUT
OUT
Delay Time, CLK↓ to D
Time Output Data Remains Valid After CLK↓
See Test Circuits
en
OUT
C
LOAD
= 100pF
hDO
f
D
D
Fall Time
Rise Time
See Test Circuits
See Test Circuits
See Figure 1 in Applications Information
See Figure 2 in Applications Information
●
●
●
●
●
180
180
1200
500
OUT
80
r
OUT
Enable Turn-On Time
Enable Turn-Off Time
Break-Before-Make Interval
Input Capacitance
540
190
350
20
5
ON
OFF
OPEN
125
C
IN
Analog Inputs On-Channel
Off-Channel
Digital Input
pF
pF
pF
5
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 7: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
below GND or one diode drop above V . This spec allows 50mV forward
CC
Note 2: All voltage values are with respect to GND.
Note 3: These devices are specified at 3V. Consult factory for 5V
specified devices (LTC1594/LTC1598).
Note 4: Increased leakage currents at elevated temperatures cause the S/H
bias of either diode for 2.7V ≤ V ≤ 3.6V. This means that as long as the
CC
reference or analog input does not exceed the supply voltage by more than
50mV, the output code will be correct. To achieve an absolute 0V to 3V
input voltage range, it will therefore require a minimum supply voltage of
2.950V over initial tolerance, temperature variations and loading.
Note 8: Recommended operating condition.
Note 9: Channel leakage current is measured after the channel selection.
to droop, therefore it is recommended that f
≥ 200kHz at 85°C,
CLK
f
≥ 75kHz at 70°C and f
≥ 1kHz at 25°C.
CLK
CLK
Note 5: V = 2.7V, V = 2.5V and CLK = 200kHz unless otherwise
CC
REF
specified. CSADC and CSMUX pins are tied together during the test.
Note 6: Linearity error is specified between the actual end points of the
A/D transfer curve.
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TYPICAL PERFORMANCE CHARACTERISTICS
Reference Current vs Temperature
Supply Current vs Sample Rate
Supply Current vs Temperature
53
52
51
50
49
48
47
46
45
44
43
1000
100
10
260
220
V
V
f
= 2.7V
= 2.5V
= 200kHz
= 10.5kHz
T
= 25°C
CC
REF
CLK
T
= 25°C
A
A
V
V
f
= 2.7V
V
V
f
= 2.7V
CC
CC
REF
= 2.5V
= 2.5V
= 200kHz
REF
f
= 200kHz
SMPL
CLK
CLK
SMPL
f
= 10.5kHz
180
140
100
60
1
0.1
1
10
100
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
SAMPLE FREQUENCY (kHz)
TEMPERATURE (°C)
TEMPERATURE (°C)
1594L/98L G01
1594L/98L G03
1594L/98L G02
4
LTC1594L/LTC1598L
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TYPICAL PERFORMANCE CHARACTERISTICS
Change in Linearity
vs Reference Voltage
0.50
Change in Offset
Change in Offset vs Temperature
vs Reference Voltage
3.0
2.5
0.20
T
= 25°C
T
= 25°C
V
V
f
= 2.7V
= 2.5V
= 200kHz
= f
A
A
CC
CLK
SMPL
CC
REF
CLK
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
V
f
= 2.7V
V
f
f
= 2.7V
= 200kHz
= 10.5kHz
CC
0.15
0.10
= 200kHz
= 10.5kHz
CLK
SMPL
f
f
SMPL SMPL(MAX)
2.0
1.5
0.05
0
–0.05
–0.10
–0.15
1.0
0.5
0
–0.20
0.5
1.0
1.5
2.0
2.5
3.0
10
20
40
50
60
70
1.0 1.2 1.4 1.6
2.0
2.4 2.6 2.8
2.2
0
30
1.8
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
1594L/98L G04
1594L/98L G06
1594L/98L G05
Effective Bits and S/(N + D)
vs Input Frequency
Change in Gain
vs Reference Voltage
Differential Nonlinearity vs Code
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
12
11
10
9
74
68
62
56
50
1
0.5
T
= 25°C
T
= 25°C
A
A
V
f
= 2.7V
V
V
f
= 2.7V
CC
CC
= 200kHz
= 10.5kHz
= 2.5V
CLK
SMPL
REF
f
= 200kHz
CLK
8
7
0
6
5
4
–0.5
3
T
= 25°C
A
V
= 2.7V
CC
2
f
f
= 200kHz
CLK
SMPL
1
= 10.5kHz
–1
0
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8
REFERENCE VOLTAGE (V)
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
1
10
INPUT FREQUENCY (kHz)
100
1594L/98L G09
1594L/98L G07
1594L/98L G08
Spurious Free Dynamic Range
vs Input Frequency
S/(N + D) vs Input Level
Frequency Response
0
10
20
30
40
50
60
70
80
90
100
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
T
V
V
= 25°C
A
= 2.7V
CC
REF
= 1kHz
= 2.5V
f
f
IN
SMPL SMPL(MAX)
= f
(MUX + A
)
DC
T
= 25°C
A
CC
REF
T
V
V
= 25°C
A
V
V
f
= 2.7V
= 2.7V
CC
= 2.5V
= 2.5V
REF
= f
SMPL SMPL(MAX)
f
= f
SMPL SMPL(MAX)
100
1k
10k
100k
1M
10M
1
10
INPUT FREQUENCY (kHz)
100
–25 –20
–15 –10 –5
–45 –40 –35 –30
0
INPUT FREQUENCY (Hz)
INPUT LEVEL (dB)
1594L/98L G10
1594L/98L G12
1594L/98/ G11
5
LTC1594L/LTC1598L
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TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Feedthrough
vs Ripple Frequency
4096 Point FFT Plot
Intermodulation Distortion
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–20
0
–20
T
= 25°C
T
= 25°C
A
A
V
V
f
= 2.7V
V
V
f
= 2.7V (V
= 1mV)
RIPPLE
CC
REF
CC
REF
= 2.5V
= 2.5V
= 200kHz
= 3.05kHz
= 120kHz
IN
CLK
SMPL
CLK
f
f
–40
–40
= 7.5kHz
–60
–60
–80
–80
–100
–120
–100
–120
2.5 3.0
FREQUENCY (kHz)
2.5 3.0
FREQUENCY (kHz)
0
0.5 1.0 1.5 2.0
3.5 4.0
0
0.5 1.0 1.5 2.0
3.5 4.0
1k
10k
100k
1M
10M
RIPPLE FREQUENCY (Hz)
1594L/98L G15
1594L/98L G13
1594L/98L G14
Maximum Clock Frequency
vs Source Resistance
Sample-and-Hold Acquisition Time
vs Source Resistance
10000
1000
100
200
190
180
170
160
150
140
130
120
T
V
V
= 25°C
T
A
= 25°C
A
= 2.7V
V
= 2.7V
CC
CC
= 2.5V
V
= 2.5V
REF
REF
V
IN
+INPUT
–INPUT
+
R
SOURCE
V
+INPUT
–INPUT
IN
–
R
SOURCE
1
10
100
1000
10000
10
100
SOURCE RESISTANCE (Ω)
1000
SOURCE RESISTANCE (Ω)
1594L/98L G16
1594L/98L G17
Input Channel Leakage Current
vs Temperature
Minimum Clock Frequency for
0.1LSB Error vs Temperature
1000
100
10
120
100
V
V
= 2.7V
REF
CC
V
V
= 2.7V
REF
CC
= 2.5V
= 2.5V
80
60
40
20
1
0.1
ON CHANNEL
OFF CHANNEL
2
0
0.01
20
30
50
0
10
40
60
70
–55 –35 –15
5
65 85 105 125
25 45
TEMPERATURE (°C)
TEMPERATURE (°C)
1594L/98L G18
1594L/98L G19
6
LTC1594L/LTC1598L
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PIN FUNCTIONS
LTC1594L
CH0 (Pin 1): Analog Multiplexer Input.
CH1 (Pin 2): Analog Multiplexer Input.
CH2 (Pin 3): Analog Multiplexer Input.
CH3 (Pin 4): Analog Multiplexer Input.
DOUT (Pin 10): Digital Data Output. The A/D conversion
result is shifted out of this output.
VCC (Pin 11): Power Supply Voltage. This pin provides
power to the ADC. It must be bypassed directly to the
analog ground plane.
ADCIN(Pin5):ADCInput. Thisinputisthepositiveanalog
input to the ADC. Connect this pin to MUXOUT for normal
operation.
CLK (Pin 12): Shift Clock. This clock synchronizes the
serial data transfer to both MUX and ADC.
CSMUX (Pin 13): MUX Chip Select Input. A logic high on
this input allows the MUX to receive a channel address. A
logic low enables the selected MUX channel and connects
it to the MUXOUT pin for A/D conversion. For normal
operation, drive this pin in parallel with CSADC.
V
REF (Pin 6): Reference Input. The reference input defines
the span of the ADC.
COM (Pin 7): Negative Analog Input. This input is the
negative analog input to the ADC and must be free of noise
with respect to GND.
DIN (Pin 14): Digital Data Input. The multiplexer address
is shifted into this input.
GND (Pin 8): Analog Ground. GND should be tied directly
to an analog ground plane.
MUXOUT (Pin 15): MUX Output. This pin is the output of
the multiplexer. Tie to ADCIN for normal operation.
CSADC (Pin 9):ADC Chip Select Input. A logic high on this
inputpowersdowntheADCandthree-statesDOUT. Alogic
low on this input enables the ADC to sample the selected
channel and start the conversion. For normal operation,
drive this pin in parallel with CSMUX.
VCC (Pin 16): Power Supply Voltage. This pin should be
tied to Pin 11.
LTC1598L
CH5 (Pin 1): Analog Multiplexer Input.
CH6 (Pin 2): Analog Multiplexer Input.
CH7 (Pin 3): Analog Multiplexer Input.
COM (Pin 8): Negative Analog Input. This input is the
negative analog input to the ADC and must be free of noise
with respect to GND.
GND (Pin 9): Analog Ground. GND should be tied directly
to an analog ground plane.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
CSADC (Pin 10): ADC Chip Select Input. A logic high on
this input deselects and powers down the ADC and three-
states DOUT. A logic low on this input enables the ADC to
sample the selected channel and start the conversion. For
normal operation drive this pin in parallel with CSMUX.
CLK(Pin5):ShiftClock. Thisclocksynchronizestheserial
data transfer to both MUX and ADC. It also determines the
conversion speed of the ADC.
CSMUX (Pin 6): MUX Chip Select Input. A logic high on
this input allows the MUX to receive a channel address. A
logic low enables the selected MUX channel and connects
it to the MUXOUT pin for A/D conversion. For normal
operation, drive this pin in parallel with CSADC.
DOUT (Pin 11): Digital Data Output. The A/D conversion
result is shifted out of this output.
NC (Pin 12): No Connection.
NC (Pin 13): No Connection.
DIN (Pin 7): Digital Data Input. The multiplexer address is
shifted into this input.
CLK (Pin 14): Shift Clock. This input should be tied to Pin 5.
7
LTC1594L/LTC1598L
U
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PIN FUNCTIONS
VCC (Pin 15): Power Supply Voltage. This pin provides
power to the A/D Converter. It must be bypassed directly
to the analog ground plane.
VCC (Pin 19): Power Supply Voltage. This pin should be
tied to Pin 15.
CH0 (Pin 20): Analog Multiplexer Input.
CH1 (Pin 21): Analog Multiplexer Input.
CH2 (Pin 22): Analog Multiplexer Input.
CH3 (Pin 23): Analog Multiplexer Input.
CH4 (Pin 24): Analog Multiplexer Input.
VREF (Pin 16): Reference Input. The reference input
defines the span of the ADC.
ADCIN (Pin 17): ADC Input. This input is the positive
analog input to the ADC. Connect this pin to MUXOUT for
normal operation.
MUXOUT (Pin 18): MUX Output. This pin is the output of
the multiplexer. Tie to ADCIN for normal operation.
W
BLOCK DIAGRA S
LTC1594L
LTC1598L
15
5
6
16
18
17
16
V
15, 19
V
V
V
CC
LTC1594L
MUXOUT
ADCIN
LTC1598L
20
MUXOUT
ADCIN
REF
CC
REF
9
CSADC
1
2
3
4
CH0
CH1
13
12
14
10
21
22
23
24
10
6
CSMUX
CLK
CSADC
CSMUX
CLK
12-BIT
SAMPLING
ADC
4-CHANNEL
MUX
+
CH2
CH3
5, 14
7
12-BIT
SAMPLING
ADC
D
8-CHANNEL
MUX
IN
D
OUT
–
D
IN
1
2
3
7
COM
11
12
13
D
OUT
GND
8
1594L BD
NC
NC
8
COM
GND
4, 9
1598L BD
TEST CIRCUITS
Load Circuit for tdDO, tr and tf
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
1.4V
3k
V
V
OH
OL
D
OUT
D
TEST POINT
OUT
t
t
1594L/98L TC02
r
f
100pF
1594L/98L TC01
8
LTC1594L/LTC1598L
TEST CIRCUITS
Voltage Waveforms for ten
Voltage Waveforms for DOUT Delay Times, tdDO
LTC1594L/LTC1598L
CLK
CSADC
CLK
V
IL
t
dDO
V
OH
1
2
D
OUT
V
OL
1594L/98L TC03
B11
D
OUT
V
OL
t
en
1594L/98L TC06
Load Circuit for tdis and ten
Voltage Waveforms for tdis
TEST POINT
3k
CSADC = CSMUX = CS
V
IH
V
t
WAVEFORM 2, t
CC dis
en
D
OUT
D
OUT
90%
10%
WAVEFORM 1
(SEE NOTE 1)
t
dis
WAVEFORM 1
100pF
t
dis
1594L/98L TC04
D
OUT
WAVEFORM 2
(SEE NOTE 2)
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
1594L/98L TC05
9
LTC1594L/LTC1598L
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and can operate with reduced spans to 1.5V. Reducing
the spans allow them to achieve 366µV resolution.
OVERVIEW
The LTC1594L/LTC1598L are 3V micropower, 12-bit
sampling A/D converters that feature 4- and 8-channel
multiplexersrespectively.Theytypicallydrawonly160µA
of supply current when sampling at 10.5kHz. Supply
current drops linearly as the sample rate is reduced (see
SupplyCurrentvsSampleRate). TheADCsautomatically
power down when not performing conversions, drawing
only leakage current. The LTC1594L is available in a
16-pin narrow SO package and the LTC1598L is pack-
aged in a 24-pin SSOP. Both devices operate on a single
supply from 2.7V to 3.6V.
The LTC1594L/LTC1598L provide separate MUX output
and ADC input pins to form an ideal MUXOUT/ADCIN
loop which economizes signal conditioning. The MUX
andADCofthedevicescanalsobecontrolledindividually
through separate chip selects to enhance flexibility.
SERIAL INTERFACE
For this discussion, we will assume that CSMUX and
CSADC are tied together and will refer to them as simply
CS, unless otherwise specified.
The LTC1594L/LTC1598L contain a 12-bit, switched-
capacitor ADC, sample-and-hold, serial port and an
external reference input pin. In addition, the LTC1594L
has a 4-channel multiplexer and the LTC1598L provides
an 8-channel multiplexer (see Block Diagram). They can
measure signals floating on a DC common mode voltage
The LTC1594L/LTC1598L communicate with the micro-
processorandotherexternalcircuitryviaasynchronous,
halfduplex, 4-wireinterface(seeOperatingSequencesin
Figures 1 and 2).
t
CYC
CSMUX = CSADC = CS
t
suCS
CLK
EN
D1
D
IN
DON’T CARE
D0
D2
NULL
BIT
Hi-Z
Hi-Z
D
OUT
B3 B2 B1 B0*
B11 B10 B9 B8 B7 B6 B5 B4
t
SMPL
t
CONV
CH0 TO
CH7
t
ON
ADCIN =
MUXOUT
COM = GND
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY
1594F/98F F01
Figure 1. LTC1594L/LTC1598L Operating Sequence Example: CH2, GND
10
LTC1594L/LTC1598L
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t
CYC
CSMUX = CSADC = CS
t
suCS
CLK
EN
D1
D
D0N‘T CARE
IN
D0
D2
NULL
BIT
Hi-Z
Hi-Z
D
OUT
DUMMY CONVERSION
t
CONV
CH0 TO
CH7
t
OFF
ADCIN =
MUXOUT
1594L/98L F02
COM = GND
Figure 2. LTC1594L/LTC1598L Operating Sequence Example: All Channels Off
Data Transfer
break-before-make interval, tOPEN. After a delay of tON
(tOFF + tOPEN), the selected channel is switched on,
allowing the ADC in the chip to acquire input signal and
start the conversion (see Figures 1 and 2). After 1 null bit,
the result of the conversion is output on the DOUT line.
The selected channel remains on, until the next falling
edge of CS. At the end of the data exchange, CS should
be brought high. This resets the LTC1594L/LTC1598L
and initiates the next data exchange.
The CLK synchronizes the data transfer with each bit
being transmitted on the falling CLK edge and captured
on the rising CLK edge in both transmitting and receiving
systems.
The LTC1594L/LTC1598L first receive input data and
then transmit back the A/D conversion results (half
duplex). Because of the half duplex operation, DIN and
DOUT may be tied together allowing transmission over
just 3 wires: CS, CLK and DATA (DIN/DOUT).
CS
Data transfer is initiated by a rising chip select (CS)
signal. After CS rises, the input data on the DIN pin is
latchedintoa4-bitregisterontherisingedgeoftheclock.
More than four input bits can be sent to the DIN pin
without problems, but only the last four bits clocked in
before CS falls will be stored into the 4-bit register. This
4-bit input data word will select the channel in the
muliplexer (see Input Data Word and Tables 1 and 2). To
ensure correct operation, the CS must be pulled low
before the next rising edge of the clock.
D
D
IN2
IN1
D
D
OUT2
OUT1
SHIFT MUX
ADDRESS IN
SHIFT A/D CONVERSION
RESULT OUT
1594L/98L AI01
t
+ 1 NULL BIT
SMPL
Break-Before-Make
The LTC1594L/LTC1598L provide a break-before-make
interval from switching off all the channels simulta-
neously to switching on the next selected channel once
CS is pulled low. In other words, once CS is pulled low,
Once the CS is pulled low, all channels are simulta-
neously switched off after a delay of tOFF to ensure a
11
LTC1594L/LTC1598L
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Table 2. Logic Table for the LTC1598L Channel Selection
after a delay of tOFF, all the channels are switched off to
ensure a break-before-make interval. After this interval,
the selected channel is switched on allowing signal
transmission. The selected channel remains on until the
next falling edge of CS and the process repeats itself with
the “EN” bit being logic high. If the “EN” bit is logic low,
all the channels are switched off simultaneously after a
delay of tOFF from CS being pulled low and all the
channels remain off until the next falling edge of CS.
CHANNEL STATUS
EN
0
D2
X
0
D1
X
0
DO
X
0
All Off
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
Input Data Word
1
1
1
1
When CS is high, the LTC1594L/LTC1598L clock data
into the DIN inputs on the rising edge of the clock and
store the data into a 4-bit register. The input data words
are defined as follows:
Transfer Curve
The LTC1594L/LTC1598L are permanently configured
for unipolar only. The input span and code assignment
for this conversion type is illustrated below.
EN
D2
D1
D0
Transfer Curve
CHANNEL SELECTION
1594L/98L AI02
“EN” Bit
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
The first bit in the 4-bit register is an “EN” bit. If the “EN”
bit is a logic high, as illustrated in Figure 1, it enables the
selectedchannelafteradelayoftON whentheCSispulled
low. If the “EN” bit is logic low, as illustrated in Figure 2,
it disables all channels after a delay of tOFF when the CS
is pulled low.
•
•
•
0 0 0 0 0 0 0 0 0 0 0 1
V
IN
0 0 0 0 0 0 0 0 0 0 0 0
V
4096
REF
1LSB =
Multiplexer (MUX) Address
1594L/98L • AI03
The 3 bits of input word following the “EN” bit select the
channel in the MUX for the requested conversion. For a
given channel selection, the converter will measure the
voltageoftheselectedchannelwithrespecttothevoltage
on the COM pin. Tables 1 and 2 show the various bit
combinations for the LTC1594L/LTC1598L channel
selection.
Output Code
INPUT VOLTAGE
(V = 2.500V)
OUTPUT CODE
INPUT VOLTAGE
REF
2.49939V
1 1 1 1 1 1 1 1 1 1 1 1 1 1
V
REF
V
REF
– 1LSB
2.49878V
1 1 1 1 1 1 1 1 1 1 1 1 1 0
– 2LSB
•
•
•
•
•
•
•
•
•
0.00061V
0V
0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
1LSB
0V
1594L/98L • AI04
Table 1. Logic Table for the LTC1594L Channel Selection
CHANNEL STATUS
EN
0
D2
X
0
D1
X
0
DO
X
All Off
CH0
CH1
CH2
CH3
1
0
1
0
0
1
1
0
1
0
1
0
1
1
12
LTC1594L/LTC1598L
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APPLICATIONS INFORMATION
Operation with DIN and DOUT Tied Together
(see Figure 3). Therefore the processor port line must be
switchedtoaninputwithCSbeinglowtoavoidaconflict.
The LTC1594L/LTC1598L can be operated with DIN and
DOUT tied together. This eliminates one of the lines
required to communicate to the microprocessor (MPU).
Data is transmitted in both directions on a single wire.
The processor pin connected to this data line should be
configurable as either an input or an output. The
LTC1594L/LTC1598L will take control of the data line
after CS falling and before the 6th falling CLK while the
processor takes control of the data line when CS is high
Separate Chip Selects for MUX and ADC
The LTC1594L/LTC1598L provide separate chip selects,
CSMUXandCSADC, tocontrolMUXandADCseparately.
This feature not only provides the flexibility to select a
particular channel once for multiple conversions (see
Figure 4) but also maximizes the sample rate up to
20ksps (see Figure 5).
t
suCS
CS
1
2
3
4
5
6
CLK
DATA (D /D
IN OUT
)
EN
D2
D1
D0
B11
B10
• • •
MPU CONTROLS DATA LINE AND SENDS
MUX ADDRESS TO LTC1594L/LTC1598L
LTC1594L/LTC1598L CONTROLS DATA LINE AND SENDS
A/D RESULT BACK TO MPU
PROCESSOR MUST RELEASE DATA
LINE AFTER CS FALLING AND
BEFORE THE 6TH FALLING CLK
LTC1594L/LTC1598L TAKES CONTROL OF DATA
LINE AFTER CS FALLING AND BEFORE THE
6TH FALLING CLK
1594L/98L F03
Figure 3. LTC1594L/LTC1598L Operation with DIN and DOUT Tied Together
CSMUX
CSADC
CLK
t
t
suCS
suCS
EN
D1
D
IN
DON’T CARE
DON’T CARE
D0
D0
D2
NULL
BIT
NULL
BIT
Hi-Z
Hi-Z
Hi-Z
D
OUT
B3 B2 B1 B0
B3 B2 B1 B0
B11 B10 B9 B8 B7 B6 B5 B4
B11 B10 B9 B8 B7 B6 B5 B4
t
t
SMPL
SMPL
t
t
CONV
CONV
CH0 TO
CH7
t
ON
ADCIN =
MUXOUT
1594L/98L F04
COM = GND
Figure 4. Selecting a Channel Once for Multiple Conversions
13
LTC1594L/LTC1598L
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CSADC
CSMUX
t
t
suCS
suCS
CLK
EN
D1
EN
D1
EN
D1
D
IN
DON’T CARE
DON’T CARE
D0
D2
B3 B2 B1 B0
D0
D2
B3 B2 B1 B0
D0
D2
B3 B2 B1 B0
NULL
BIT
NULL
BIT
D
OUT
B4
B11 B10 B9 B8 B7 B6 B5 B4
B11 B10 B9 B8 B7 B6 B5 B4
t
t
SMPL
SMPL
t
t
CONV
CONV
CH0 TO
CH7
t
t
ON
ON
ADCIN =
MUXOUT
1594L/98L F05
COM = GND
Figure 5. Use Separate Chip Selects to Maximize Sample Rate
1000
MUXOUT/ADCIN Loop Economizes
Signal Conditioning
T
= 25°C
A
V
V
= 2.7V
CC
REF
CLK
= 2.5V
= 200kHz
f
TheMUXOUTandADCINpinsoftheLTC1594L/LTC1598L
form a very flexible external loop that allows Program-
mable Gain Amplifier (PGA) and/or processing analog
input signals prior to conversion. This loop is also a cost
effective way to perform the conditioning, because only
one circuit is needed instead of one for each channel.
100
10
1
In the Typical Applications section, there are a few
examplesillustratinghowtousetheMUXOUT/ADCINloop
to form a PGA and to antialias filter several analog inputs.
0.1
1
10
100
SAMPLE FREQUENCY (kHz)
1594L/98L G01
Figure 6. Automatic Power Shutdown Between Conversions
Allows Power Consumption to Drop with Sample Rate
ACHIEVING MICROPOWER PERFORMANCE
With typical operating currents of 160µA and automatic
shutdown between conversions, the LTC1594L/
LTC1598L achieve extremely low power consumption
overawiderangeofsamplerates(seeFigure6). Theauto
shutdownallowsthesupplycurrenttodropwithreduced
samplerate. Severalthingsmustbetakenintoaccountto
achieve such a low power consumption.
leaving the CLK running to clock the input data word into
MUX.IftheCS,DIN andCLKarenotrunningrail-to-rail,the
input logic buffers will draw currents. These currents may
be large compared to the typical supply current. To obtain
the lowest supply current, run the CS, DIN and CLK pins
rail-to-rail.
DOUT Loading
Shutdown
Capacitive loading on the digital output can increase
power consumption. A 100pF capacitor on the DOUT pin
canaddmorethan50µAtothesupplycurrentata200kHz
clock frequency. An extra 50µA or so of current goes into
charging and discharging the load capacitor. The same
goes for digital lines driven at a high frequency by any
logic. The (C)(V)(f) currents must be evaluated and the
troublesome ones minimized.
The LTC1594L/LTC1598L are equipped with automatic
shutdown features. They draw power when the CS pin is
low. The bias circuits and comparator of the ADC powers
down and the reference input becomes high impedance at
the end of each conversion leaving the CLK running to
clockouttheLSBfirstdataorzeroes(seeFigures1and2).
WhentheCSpinishigh,theADCpowersdowncompletely
14
LTC1594L/LTC1598L
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BOARD LAYOUT CONSIDERATIONS
SAMPLE-AND-HOLD
BoththeLTC1594L/LTC1598Lprovideabuilt-insample-
and-hold (S&H) function to acquire signals through the
selected channel, assuming the ADCIN and MUXOUT
pins are tied together. The S & H of these parts acquire
input signals through the selected channel relative to
COM input during the tSMPL time (see Figure 7).
Grounding and Bypassing
The LTC1594L/LTC1598L are easy to use if some care is
taken. They should be used with an analog ground plane
and single point grounding techniques. The GND pin
should be tied directly to the ground plane.
The VCC pin should be bypassed to the ground plane with
a10µFtantalumcapacitorwithleadsasshortaspossible.
If the power supply is clean, the LTC1594L/LTC1598L
can also operate with smaller 1µF or less surface mount
or ceramic bypass capacitors. All analog inputs should
be referenced directly to the single point ground. Digital
inputs and outputs should be shielded from and/or
routed away from the reference and analog circuitry.
Single-Ended Inputs
Thesample-and-holdoftheLTC1594L/LTC1598Lallows
conversion of rapidly varying signals. The input voltage
is sampled during the tSMPL time as shown in Figure 7.
The sampling interval begins after tON time once the CS
is pulled low and continues until the second falling CLK
edge after the CS is low (see Figure 7). On this falling CLK
SAMPLE
HOLD
“ANALOG” INPUT MUST
SETTLE DURING
THIS TIME
t
ON
CSADC = CSMUX = CS
CLK
t
t
CONV
SMPL
DON‘T CARE
D
IN
EN
D2
D1
D0
D
OUT
B11
1ST BIT TEST “COM” INPUT MUST
SETTLE DURING THIS TIME
MUXOUT = ADCIN
CH0 TO CH7
COM
1594L/98L F07
Figure 7. LTC1594L/LTC1598L ADCIN and COM Input Settling Windows
15
LTC1594L/LTC1598L
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“COM” Input Settling
edge, the S & H goes into hold mode and the conversion
begins. The voltage on the “COM” input must remain
constant and be free of noise and ripple throughout the
conversion time. Otherwise, the conversion operation
may not be performed accurately. The conversion time is
12 CLK cycles. Therefore, a change in the “COM” input
voltage during this interval can cause conversion errors.
For a sinusoidal voltage on the “COM” input this error
would be:
AttheendofthetSMPL,theinputcapacitorswitchestothe
“COM” input and conversion starts (see Figures 1 and 7).
During the conversion, the “analog” input voltage is
effectively “held” by the sample-and-hold and will not
affecttheconversionresult. However, itiscriticalthatthe
“COM” input voltage settles completely during the first
CLK cycle of the conversion time and be free of noise.
Minimizing RSOURCE– and C2 will improve settling time.
If a large “COM” input source resistance must be used,
the time allowed for settling can be extended by using a
slower CLK frequency.
V
ERROR(MAX) = VPEAK(2π)(f)(“COM”)12/fCLK
Where f(“COM”) is the frequency of the “COM” input
voltage, VPEAK is its peak amplitude and fCLK is the
frequency of the CLK. In most cases, VERROR will not be
significant. For a 60Hz signal on the “COM” input to
generate a 0.5LSB error (305µV) with the converter
running at CLK = 200kHz, its peak value would have to be
5.266mV.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 7). Again, the “analog” and “COM” input
sampling times can be extended as described above to
accommodatesloweropamps. Mostopamps, including
the LT®1006 and LT1413 single supply op amps, can be
made to settle well even with the minimum settling
windows of 7.5µs (“analog” input) which occur at the
maximum clock rate of 200kHz.
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1594L/
LTC1598Lhavecapacitiveswitchinginputcurrentspikes.
These current spikes settle quickly and do not cause a
problem. However, if large source resistances are used
or if slow settling op amps drive the inputs, care must be
taken to insure that the transients caused by the current
spikes settle completely before the conversion begins.
Source Resistance
The analog inputs of the LTC1594L/LTC1598L look like a
20pFcapacitor(CIN)inserieswitha1kresistor(RON)and
a 90Ω channel resistance as shown in Figure 8. CIN gets
switched between the selected “analog” and “COM”
inputsonceduringeachconversioncycle. Largeexternal
source resistors and capacitances will slow the settling
of the inputs. It is important that the overall RC time
constants be short enough to allow the analog inputs to
completely settle within the allowed time.
“Analog” Input Settling
TheinputcapacitoroftheLTC1594L/LTC1598Lisswitched
onto the selected channel input during the tSMPL time (see
Figure7)andsamplestheinputsignalwithinthattime.The
sample phase is at least 1 1/2 CLK cycles before conver-
sion starts. The voltage on the “analog” input must settle
completely within tSMPL. Minimizing RSOURCE+ and C1 will
improve the input settling time. If a large “analog” input
source resistance must be used, the sample time can be
increased by using a slower CLK frequency.
MUX
“ANALOG”
+
R
ON
INPUT
R
90Ω
SOURCE
MUXOUT
ADCIN
LTC1594L
LTC1598L
V
+
IN
R
ON
C1
1k
C
“COM”
INPUT
IN
20pF
–
R
SOURCE
V
–
IN
1594L/98L F08
C2
Figure 8. Analog Input Equivalent Circuit
16
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Input Leakage Current
Offset with Reduced VREF
Inputleakagecurrentscanalsocreateerrorsifthesource
resistance gets too large. For instance, the maximum
input leakage specification of 200nA (at 85°C) flowing
through a source resistance of 600Ω will cause a voltage
drop of 120µV or 0.2LSB. This error will be much
reduced at lower temperatures because leakage drops
rapidly (see typical curve Input Channel Leakage Current
vs Temperature).
The offset of the LTC1594L/LTC1598L has a larger effect
on the output code when the ADCs are operated with
reduced reference voltage. The offset (which is typically
afixedvoltage)becomesalargerfractionofanLSBasthe
size of the LSB is reduced. The typical curve of Change in
Offset vs Reference Voltage shows how offset in LSBs is
related to reference voltage for a typical value of VOS. For
example, a VOS of 122µV which is 0.2LSB with a 2.5V
reference becomes 0.5LSB with a 1V reference and
2.5LSBs with a 0.2V reference. If this offset is unaccept-
able, it can be corrected digitally by the receiving system
or by offsetting the “COM” input of the LTC1594L/
LTC1598L.
REFERENCE INPUTS
The reference input of the LTC1594L/LTC1598L is effec-
tively a 50k resistor from the time CS goes low to the end
of the conversion. The reference input becomes a high
impedance node at any other time (see Figure 9). Since
the voltage on the reference input defines the voltage
span of the A/D converter, the reference input should be
driven by a reference with low ROUT(ex. LT1004, LT1019
Noise with Reduced VREF
ThetotalinputreferrednoiseoftheLTC1594L/LTC1598L
can be reduced to approximately 400µV peak-to-peak
using a ground plane, good bypassing, good layout
techniquesandminimizingnoiseonthereferenceinputs.
This noise is insignificant with a 5V reference but will
become a larger fraction of an LSB as the size of the LSB
is reduced.
and LT1021) or a voltage source with low ROUT
.
+
REF
LTC1594L
LTC1598L
1
R
OUT
V
REF
GND
4
For operation with a 2.5V reference, the 400µV noise is
only 0.66LSB peak-to-peak. In this case, the LTC1594L/
LTC1598Lnoisewillcontributevirtuallynouncertaintyto
the output code. However, for reduced references the
noise may become a significant fraction of an LSB and
cause undesirable jitter in the output code. For example,
witha1.25Vreferencethissame400µVnoiseis1.32LSB
peak-to-peak. Thiswillreducetherangeofinputvoltages
overwhichastableoutputcodecanbeachievedby1LSB.
If the reference is further reduced to 1V, the 400µV noise
becomes equal to 1.65LSBs and a stable code may be
difficult to achieve. In this case, averaging multiple
readings may be necessary.
1594L/98L F09
Figure 9. Reference Input Equivalent Circuit
Reduced Reference Operation
The effective resolution of the LTC1594L/LTC1598L can
be increased by reducing the input span of the convert-
ers. The LTC1594L/LTC1598L exhibit good linearity and
gain over a wide range of reference voltages (see typical
curves Change in Linearity vs Reference Voltage and
Change in Gain vs Reference Voltage). However, care
must be taken when operating at low values of VREF
because of the reduced LSB step size and the resulting
higher accuracy requirement placed on the converters.
The following factors must be considered when operat-
ing at low VREF values:
Thisnoisedatawastakeninaverycleansetup. Anysetup
induced noise (noise or ripple on VCC, VREF or VIN) will
add to the internal noise. The lower the reference voltage
to be used the more critical it becomes to have a clean,
noise free setup.
1. Offset
2. Noise
3. Conversion speed (CLK frequency)
17
LTC1594L/LTC1598L
U
W U U
APPLICATIONS INFORMATION
Conversion Speed with Reduced VREF
Effective Number of Bits
With reduced reference voltages, the LSB step size is
reducedandtheLTC1594L/LTC1598Linternalcompara-
tor overdrive is reduced. Therefore, it may be necessary
to reduce the maximum CLK frequency when low values
of VREF are used.
TheEffectiveNumberofBits(ENOBs)isameasurementof
the resolution of an ADC and is directly related to S/(N + D)
by the equation:
ENOB = [S/(N + D) – 1.76]/6.02
where S/(N + D) is expressed in dB. At the maximum
samplingrateof10.5kHzwitha5Vsupply,theLTC1594L/
LTC1598L maintain above 10.7 ENOBs at 10kHz input
frequency. Above 10kHz the ENOBs gradually decline, as
shown in Figure 11, due to increasing second harmonic
distortion. The noise floor remains low.
DYNAMIC PERFORMANCE
The LTC1594L/LTC1598L have exceptional sampling
capability. Fast Fourier Transform (FFT) test techniques
are used to characterize the ADC’s frequency response,
distortion and noise at the rated throughput. By applying
a low distortion sine wave and analyzing the digital
output using an FFT algorithm, the ADC’s spectral con-
tent can be examined for frequencies outside the funda-
mental. Figure 10 shows a typical LTC1594L/LTC1598L
plot.
12
11
10
9
74
68
62
56
50
8
7
6
0
5
T
V
V
= 25°C
A
= 2.7V
4
CC
REF
= 3.05kHz
–20
–40
= 2.5V
3
T
= 25°C
A
f
f
f
IN
CLK
SMPL
V
f
= 2.7V
CC
2
= 120kHz
= 200kHz
CLK
SMPL
= 7.5kHz
1
f
= 10.5kHz
0
–60
1
10
INPUT FREQUENCY (kHz)
100
1594L/98L G09
–80
Figure 11. Effective Bits and S/(N + D) vs Input Frequency
–100
–120
2.5 3.0
0.5 1.0 1.5 2.0
FREQUENCY (kHz)
0
3.5 4.0
Total Harmonic Distortion
1594L/98L G13
Total Harmonic Distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamen-
tal itself. The out-of-band harmonics alias into the fre-
quency band between DC and half of the sampling
frequency. THD is defined as:
Figure 10. LTC1594L/LTC1598L Nonaveraged,
4096 Point FFT Plot
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio (S/N + D) is the
ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other fre-
quency components at the ADC’s output. The output is
band limited to frequencies above DC and below one half
the sampling frequency. Figure 11 shows a typical spec-
tral content with a 10.5kHz sampling rate.
V2 + V32 + V42 +... + V2
2
N
THD = 20log
V
1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through the Nth harmonics. The typical THD
18
LTC1594L/LTC1598L
U
W U U
APPLICATIONS INFORMATION
specification in the Dynamic Accuracy table includes the
2nd through 5th harmonics. With a 1kHz input signal, the
LTC1594L/LTC1598L have typical THD of 78dB with
amplitude f ± f
(
)
b
a
IMD f ± f = 20log
(
)
a
b
amplitude at fa
VCC = 2.7V.
Peak Harmonic or Spurious Noise
Intermodulation Distortion
The peak harmonic or spurious noise is the largest
spectral component excluding the input signal and DC.
This value is expressed in dBs relative to the RMS value
of a full-scale input signal.
If the ADC input signal consists of more than one
spectral component, the ADC transfer function nonlin-
earity can produce intermodulation distortion (IMD)
in addition to THD. IMD is the change in one sinusoi-
dal input caused by the presence of another sinusoidal
input at a different frequency.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer
functioncancreatedistortionproductsatsumanddiffer-
ence frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include (fa +
fb) and (fa – fb) while 3rd order IMD terms include (2fa +
fb), (2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine
waves are equal in magnitudes, the value (in dB) of the
2nd order IMD products can be expressed by the follow-
ing formula:
The full-linear bandwidth is the input frequency at which
the effective bits rating of the ADC falls to 11 bits. Beyond
this frequency, distortion of the sampled input signal
increases.TheLTC1594L/LTC1598Lhavebeendesigned
to optimize input bandwidth, allowing the ADCs to
undersample input signals with frequencies above the
converters’ Nyquist Frequency.
U
TYPICAL APPLICATIONS N
Microprocessor Interfaces
Motorola SPI (MC68HC05)
The LTC1594L/LTC1598L can interface directly (without
external hardware) to most popular microprocessors’
(MPU) synchronous serial formats including
MICROWIRE, SPI and QSPI. If an MPU without a dedi-
cated serial port is used, then three of the MPU’s parallel
port lines can be programmed to form the serial link to the
LTC1594L/LTC1598L.Includedhereisoneserialinterface
example.
TheMC68HC05hasbeenchosenasanexampleofanMPU
withadedicatedserialport. ThisMPUtransfersdataMSB-
first and in 8-bit increments. The DIN word sent to the data
register starts the SPI process. With three
8-bit transfers the A/D result is read into the MPU. The
second 8-bit transfer clocks B11 through B7 of the A/D
conversion result into the processor. The third 8-bit trans-
fer clocks the remaining bits B6 through B0 into the MPU.
ANDing the second byte with 1FHEX clears the three most
significantbitsandANDingthethirdbytewithFEHEX clears
theleastsignificantbit. Shiftingthedatatotherightbyone
bit results in a right justified word.
19
LTC1594L/LTC1598L
U
TYPICAL APPLICATIONS N
MC68HC05 CODE
BPL LOOP1 Loop if not done with transfer to previous instruction
LDA #$52 Configuration data for serial peripheral
control register (Interrupts disabled, output
enabled, master, Norm = 0, Ph = 0, Clk/16)
BCLR 0,$02 Bit 0 Port C ($02) goes low (CS goes low)
LDA $0C
STA $0C
Load contents of SPI data register into Accumulator
Start next SPI cycle
STA $0A
Load configuration data into location $0A (SPCR)
LDA #$FF Configuration data for I/O ports
(all bits are set as outputs)
LOOP2 TST $0B
Test status of SPIF
BPL LOOP2 Loop if not done
STA $04
STA $05
STA $06
Load configuration data into Port A DDR ($04)
LDA $0C
STA $0C
Load contents of SPI data register into Accumulator
Start next SPI cycle
Load configuration data into Port B DDR ($05)
Load configuration data into Port C DDR ($06)
AND #$IF
Clear 3 MSBs of first D
word
OUT
LDA #$08 Put D word for LTC1598L into Accumulator
STA $00
Load Port A ($00) with MSBs
Test status of SPIF
IN
(CH0 with respect to GND)
LOOP3 TST $0B
STA $50
Load D word into memory location $50
IN
BPL LOOP3 Loop if not done
START BSET 0,$02 Bit 0 Port C ($02) goes high (CS goes high)
LDA $0C
Load contents of SPI data register into Accumulator
LDA $50
STA $0C
Load D word at $50 into Accumulator
AND #$FE Clear LSB of second D
word
IN
IN
OUT
Load D word into SPI data register ($0C) and
STA $01
Load Port B ($01) with LSBs
start clocking data
JMP START Go back to start and repeat program
LOOP1 TST $0B
Test status of SPIF bit in SPI status register ($0B)
Data Exchange Between LTC1598L and MC68HC05
CSMUX
= CSADC
= CS
CLK
EN D2 D1 DO
DON‘T CARE
D
IN
D
OUT
B11 B10 B9 B8 B7
B6
B5 B4 B3 B2 B1 B0 B1 B2
MPU
TRANSMIT
WORD
0
?
0
?
0
?
0
EN D2 D1 D0
X
?
X
?
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
BYTE 2
BYTE 1
BYTE 3
MPU
RECEIVED
WORD
?
?
?
?
?
B11 B10 B9 B8 B7
BYTE 2
B6 B5 B4
B2 B1 B0
B3
B1
1594L/98L TA03
BYTE 1
BYTE 3
Hardware and Software Interface to Motorola MC68HC05
D
FROM LTC1598L STORED IN MC68HC05 RAM
OUT
MSB
C0
MC68HC05
CSMUX
CSADC
0
BYTE 1
BYTE 2
B11 B10
B8
B7
0
0
0
B9
B1
#00
#01
ANALOG
INPUTS
SCK
LTC1598L CLK
LSB
B0
D
IN
MOSI
MISO
B6
B5
B4
B2
B3
D
OUT
1594L/98L TA04
20
LTC1594L/LTC1598L
U
TYPICAL APPLICATIONS N
MULTICHANNEL A/D USES A SINGLE
ANTIALIASING FILTER
than 1LSB of error due to offsets and bias currents. The
filter’s noise and distortion are less than –72dB for a
100Hz, 2VP-P offset sine input.
This circuit demonstrates how the LTC1598L’s indepen-
dent analog multiplexer can simplify design of a 12-bit
dataacquisitionsystem.AlleightchannelsareMUXedinto
a single 1kHz, 4th order Sallen-Key antialiasing filter,
which is designed for single supply operation. Since the
LTC1598L’s data converter accepts inputs from ground to
the positive supply, rail-to-rail op amps were chosen for
thefiltertomaximizedynamicrange.TheLT1368dualrail-
to-rail op amp is designed to operate with 0.1µF load
capacitors (C1 and C2). These capacitors provide fre-
quency compensation for the amplifiers and help reduce
the amplifier’s output impedance and improve supply
rejection at high frequencies. The filter contributes less
The combined MUX and A/D errors result in an integral
nonlinearity error of ±3LSB (maximum) and a differential
nonlinearity error of ±3/4LSB (maximum). The typical
signal-to-noise plus distortion ratio is 68dB, with approxi-
mately –78dB of total harmonic distortion. The LTC1598L
is programmed through a 4-wire serial interface that is
compatible with MICROWIRE, SPI and QSPI. Maximum
serial clock speed is 200kHz, which corresponds to a
10.5kHz sampling rate.
The complete circuit consumes approximately 600µA
from a single 3V supply.
Simple Data Acquisition System Takes Advantage of the LTC1598L’s
MUXOUT/ADCIN Pins to Filter Analog Signals Prior to A/D Conversion
3.3V
R1
7.5k
R2
R3
R4
C8
0.01µF
7.5k
7.5k
7.5k
3
2
5
6
8
+
+
C5
0.015µF
1
7
C1
0.03µF
C2
0.015µF
C4
0.03µF
1/2 LT1368
1/2 LT1368
C6
0.1µF
C3
0.1µF
–
–
4
3.3V
C7
1µF
18
MUXOUT
17
16
15, 19
V
REF
V
CC
LTC1598L
ADCIN
20 CH0
21 CH1
22 CH2
23 CH3
24 CH4
10
CSADC
CSMUX
6
5, 14
7
12-BIT
SAMPLING
ADC
8-CHANNEL
MUX
SERIAL DATA LINK
MICROWIRE AND SPI
COMPATIBLE
CLK
+
D
IN
1
2
3
CH5
CH6
CH7
11
D
OUT
–
12
13
NC
NC
8
COM
GND
4, 9
1594L/98L TA05
21
LTC1594L/LTC1598L
U
TYPICAL APPLICATIONS N
Using MUXOUT/ADCIN Loop as PGA
the summation of the resistors below the selected MUX
channel. If CH0 is selected, the gain is 1 since RS1 is 0.
Table1showsthegainforeachMUXchannel. TheLT1368
dual rail-to-rail op amp is designed to operate with 0.1µF
loadcapacitors. Thesecapacitorsprovidefrequencycom-
pensation for the amplifiers, help reduce the amplifiers’
output impedance and improve supply rejection at high
frequencies.BecausetheLT1368’sIB islow,theRON ofthe
selected channel will not affect the gain given by the
formula above.
This figure shows the LTC1598L’s MUXOUT/ADCIN pins
and an LT1368 being used to create a single channel PGA
witheightnoninvertinggains.CombinedwiththeLTC1391,
the system can expand to eight channels and eight gains
foreachchannel. UsingtheLTC1594L, thePGAisreduced
to four gains. The output of the LT1368 drives the ADCIN
and the resistor ladder. The resistors above the selected
MUX channel form the feedback for the LT1368. The gain
for this amplifier is RS1/RS2 + 1. RS1 is the summation of
the resistors above the selected MUX channel and RS2 is
Using the MUXOUT/ADCIN Pins of the LTC1598L to Form a PGA.
The LTC1391 MUX Allows Eight Input Channels to be Digitized
3V
3V
1µF
LTC1391
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
V
1µF
1(7)
CH0
3(5)
2(6)
8
CH1
CH2
CH3
CH4
CH5
CH6
D
+
–
V
1/2 LT1368
3V
0.1µF
D
OUT
–
4
D
IN
17
ADCIN
16
V
15, 19
1µF
CS
CLK
V
REF
CC
64R
20 CH0
21 CH1
22 CH2
23 CH3
24 CH4
CH7 GND
32R
16R
8R
4R
2R
R
10
6
CSADC
CSMUX
CLK
5, 14
11
8-CHANNEL
MUX
12-BIT
SAMPLING
ADC
+
D
OUT
µP/µC
1
2
3
CH5
CH6
CH7
7
D
IN
–
R
LTC1598L
12
13
18 MUXOUT
COM
NC
NC
8
GND
4, 9
1594L/98L TA06
= DAISY CHAIN CONFIGURATION FOR THE LTC1391 AND THE LTC1598L
22
LTC1594L/LTC1598L
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTION
G Package
24-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
8.07 – 8.33*
(0.318 – 0.328)
24 23 22 21 20 19 18 17 16 15 14
13
7.65 – 7.90
(0.301 – 0.311)
5
7
8
1
2
3
4
6
9 10 11 12
5.20 – 5.38**
(0.205 – 0.212)
1.73 – 1.99
(0.068 – 0.078)
0° – 8°
0.65
(0.0256)
BSC
0.13 – 0.22
0.55 – 0.95
(0.005 – 0.009)
(0.022 – 0.037)
0.05 – 0.21
(0.002 – 0.008)
0.25 – 0.38
(0.010 – 0.015)
NOTE: DIMENSIONS ARE IN MILLIMETERS
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
G24 SSOP 1098
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
16
15
14
13
12
11
10
9
0.150 – 0.157**
0.228 – 0.244
(3.810 – 3.988)
(5.791 – 6.197)
5
7
8
1
2
3
4
6
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0° – 8° TYP
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
TYP
0.016 – 0.050
(0.406 – 1.270)
S16 1098
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC1594L/LTC1598L
U
TYPICAL APPLICATION
Using the LTC1598L and LTC1391 as an 8-Channel Differential 12-Bit ADC System
3V
18
MUXOUT
17
ADCIN
16
V
15, 19
1µF
V
REF
CC
20 CH0
21 CH1
22 CH2
23 CH3
24 CH4
10
6
CSADC
CSMUX
CLK
3V
5, 14
7
12-BIT
SAMPLING
ADC
8-CHANNEL
MUX
+
1µF
D
IN
1
2
3
CH5
CH6
CH7
11
D
OUT
–
LTC1391
12
13
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
NC
+
V
CH0
CH7
CH0
LTC1598L
8
COM
CH1
CH2
CH3
CH4
CH5
CH6
D
–
GND
4, 9
V
D
OUT
D
IN
CS
CLK
CH7 GND
D
IN
CLK
CS
D
OUT
1594L/98L TA07
= DAISY CHAIN CONFIGURATION FOR THE LTC1391 AND THE LTC1598L
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1096/LTC1098
LTC1096L/LTC1098L
LTC1196/LTC1198
LTC1282
8-Pin SO, Micropower 8-Bit ADCs
Low Power, Small Size, Low Cost
Low Power, Small Size, Low Cost
Low Power, Small Size, Low Cost
8-Pin SO, 2.65V Micropower 8-Bit ADCs
8-Pin SO, 1Msps 8-Bit ADCs
3V High Speed Parallel 12-Bit ADC
8-Pin SO, 3V, Micropower ADCs
8-Pin SO, 5V, Micropower ADCs
Multiplexed 3V, 12-Bit ADC
140ksps, Complete with V , CLK, Sample-and-Hold
REF
LTC1285/LTC1288
LTC1286/LTC1298
LTC1289
1- or 2-Channel, Auto Shutdown
1- or 2-Channel, Auto Shutdown
8-Channel 12-Bit Serial I/O
LTC1296
Multiplexed 5V, 12-Bit ADC
8-Channel 12-Bit Serial I/O
LTC1415
5V High Speed Parallel 12-Bit ADC
4-Channel, 5V Micropower 12-Bit ADC
8-Channel, 5V Micropower 12-Bit ADC
1.25Msps, Complete with V , CLK, Sample-and-Hold
REF
LTC1594
Low Power, Small Size, Low Cost
Low Power, Small Size, Low Cost
LTC1598
15948lfa LT/TP 0500 2K REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1997
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