LTC1599ACG#PBF [Linear]
LTC1599 - 16-Bit Byte Wide, Low Glitch Multiplying DAC with 4-Quadrant Resistors; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C;型号: | LTC1599ACG#PBF |
厂家: | Linear |
描述: | LTC1599 - 16-Bit Byte Wide, Low Glitch Multiplying DAC with 4-Quadrant Resistors; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C 光电二极管 转换器 |
文件: | 总20页 (文件大小:239K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC1599
16-Bit Byte Wide,
Low Glitch Multiplying DAC with
4-Quadrant Resistors
U
FEATURES
DESCRIPTIO
■
True 16-Bit Performance over Industrial
The LTC®1599 is a 2-byte parallel input 16-bit multiplying
current output DAC that operates from a single 5V supply.
INL and DNL are accurate to 1LSB over the industrial
temperature range in both 2- and 4-quadrant multiplying
modes. True 16-bit 4-quadrant multiplication is achieved
with on-chip 4-quadrant multiplication resistors.
Temperature Range
■
DNL and INL: 1LSB Max
■
On-Chip 4-Quadrant Resistors Allow Precise
0V to 10V, 0V to –10V or ±10V Outputs
2µ
s Settling Time to 0.0015% (with LT®1468)
■
■
Asynchronous Clear Pin Resets to Zero Scale
or Midscale
Glitch Impulse: 1.5nV-s
24-Lead SSOP Package
Low Power Consumption: 10µW Typ
Power-On Reset to Zero Scale or Midscale
2-Byte Parallel Digital Interface
Available in 24-LUead SSOP and PDIP Packages
TheLTC1599isavailablein24-pinPDIPandSSOPpackages
and is specified over the commercial and industrial tempera-
ture ranges. The device includes an internal deglitcher circuit
that reduces the glitch impulse to 1.5nV-s (typ). The asyn-
chronousCLR pinresetstheLTC1599tozeroscalewhen the
CLVL pin is at a logic low and to midscale when the CLVL pin
is at a logic high.
■
■
■
■
■
■
For a full 16-bit wide parallel interface current output DAC,
refer to the LTC1597 data sheet. For serial interface 16-bit
current output DACs, refer to the LTC1595/LTC1596 data
sheet.
APPLICATIO S
■
Process Control and Industrial Automation
■
Direct Digital Waveform Generation
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Software-Controlled Gain Adjustment
■
Automatic Test Equipment
U
TYPICAL APPLICATIO
A 16-Bit, 4-Quadrant Multiplying DAC with a Minimum of External Components
V
REF
–V
5V
REF
3
2
+
–
0.1µF
6
LT1468
15pF
Integral Nonlinearity
1.0
0.8
6
4
3
2
1
20
5
0.6
R1
R
R2 REF
V
CC
R
R
COM
R2
OFS
FB
15pF
0.4
R
R
OFS
FB
R1
0.2
8
I
–
OUT1
I
2
3
7
DATA
V
0
REF
INPUTS
6
–0.2
–0.4
–0.6
–0.8
–1.0
16-BIT DAC
V
=
OUT
LTC1599
LT1468
+
OUT2F
14 TO 18,
21 TO 23
8
–V
REF
I
9
OUT2S
13
MLBYTE
MLBYTE
WR LD CLR CLVL
12 11 24
10
19
DGND
0
32768
DIGITAL INPUT CODE
49152
16384
65535
WR
LD
CLR
CLVL
1599 G08
1599 TA01
sn1599 1599fs
1
LTC1599
W W U W
U
W U
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
VCC to DGND .............................................. –0.3V to 7V
REF, ROFS, RFB, R1, R2 to DGND .......................... ±25V
RCOM ........................................................ –0.3V to 12V
Digital Inputs to DGND ............... –0.3V to (VCC + 0.3V)
ORDER PART
TOP VIEW
NUMBER
REF
R2
1
2
CLR
24
23 D0
LTC1599ACG
LTC1599BCG
LTC1599AIG
LTC1599BIG
LTC1599ACN
LTC1599BCN
LTC1599AIN
LTC1599BIN
R
3
D1
D2
V
22
21
20
19
18
17
16
15
14
13
COM
R1
4
I
OUT1, IOUT2F, IOUT2S to DGND .... –0.3V to( VCC + 0.3V)
R
5
OFS
CC
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
LTC1599C ............................................... 0°C to 70°C
LTC1599I............................................ –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
R
6
DGND
D3
FB
I
7
OUT1
I
8
D4
OUT2F
I
9
D5
OUT2S
CLVL
10
11
12
D6
LD
D7
WR
MLBYTE
G PACKAGE
24-LEAD PLASTIC SSOP
N PACKAGE
24-LEAD PDIP
TJMAX = 125°C, θJA = 95°C/ W (G)
TJMAX = 125°C, θJA = 58°C/ W (N)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V ±10%, VREF = 10V, IOUT1 = IOUT2F = IOUT2S = DGND = 0V,
TA = TMIN to TMAX unless otherwise noted.
LTC1599B
TYP
LTC1599A
TYP
SYMBOL PARAMETER
Accuracy
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
Resolution
●
●
16
16
16
16
Bits
Bits
Monotonicity
INL
DNL
GE
Integral Nonlinearity
T = 25°C (Note 2)
±2
±2
±0.25
±0.35
±1
±1
LSB
LSB
A
T
to T
●
●
MIN
MAX
Differential Nonlinearity
Gain Error
T = 25°C
±1
±1
±0.2
±0.2
±1
±1
LSB
LSB
A
T
to T
MIN
MAX
Unipolar Mode
T = 25°C (Note 3)
±16
±24
2
3
±16
±16
LSB
LSB
A
T
to T
●
MIN
MAX
Bipolar Mode
T = 25°C (Note 3)
±16
±24
2
3
±16
±16
LSB
LSB
A
T
to T
●
●
MIN
MAX
Gain Temperature Coefficient
Bipolar Zero Error
∆Gain/∆Temperature (Note 4)
1
3
1
3
ppm/°C
T = 25°C
±10
±16
±5
±8
LSB
LSB
A
T
to T
●
MIN
MAX
I
OUT1 Leakage Current
Power Supply Rejection
T = 25°C (Note 5)
±5
±15
±5
±15
nA
nA
LKG
A
T
to T
●
●
MIN
MAX
PSRR
V
= 5V ±10%
±1
±2
±1
±2
LSB/V
CC
sn1599 1599fs
2
LTC1599
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V ±10%, VREF = 10V, IOUT1 = IOUT2F = IOUT2S = DGND = 0V,
TA = TMIN to TMAX unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Input
R
DAC Input Resistance (Unipolar)
R1, R2 Resistance (Bipolar)
(Note 6)
●
●
●
4.5
9
6
10
20
20
kΩ
kΩ
kΩ
REF
R1, R2
, R
(Notes 6, 13)
(Note 6)
14
R
Feedback and Offset Resistances
9
13.5
OFS FB
AC Performance (Note 4)
Output Current Settling Time
(Notes 7, 8)
(Note 12)
(Note 9)
1
1.5
1
µs
nV-s
nV-s
Midscale Glitch Impulse
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
Total Harmonic Distortion
Output Noise Voltage Density
V
= ±10V, 10kHz Sine Wave
1
mV
P-P
REF
THD
(Note 10)
(Note 11)
108
10
dB
nV/√Hz
Analog Outputs (Note 4)
Output Capacitance (Note 4)
C
DAC Register Loaded to All 1s: C
DAC Register Loaded to All 0s: C
●
●
115
70
130
80
pF
pF
OUT
OUT1
OUT1
Digital Inputs
V
V
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Current
●
●
●
●
2.4
V
V
IH
IL
0.8
±1
8
I
0.001
µA
pF
IN
C
Digital Input Capacitance
(Note 4) V = 0V
IN
IN
Timing Characteristics
t
t
t
t
t
t
t
t
Data to WR Setup Time
Data to WR Hold Time
WR Pulse Width
●
●
●
●
●
●
●
●
80
0
20
–12
25
ns
ns
ns
ns
ns
ns
ns
ns
DS
DH
80
0
WR
BWS
BWH
LD
MLBYTE to WR Setup Time
MLBYTE to WR Hold Time
LD Pulse Width
–12
–12
55
0
150
150
0
Clear Pulse Width
50
CLR
LWD
WR to LD Delay Time
Power Supply
V
Supply Voltage
Supply Current
●
●
4.5
5
5.5
10
V
CC
I
Digital Inputs = 0V or V
µA
CC
CC
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 9: V = 0V. DAC register contents changed from all 0s to all 1s or
all 1s to all 0s. LD high, WR and MLBYTE pulsed.
REF
Note 2: ±1LSB = ±0.0015% of full scale = ±15.3ppm of full scale.
Note 3: Using internal feedback resistor.
Note 4: Guaranteed by design, not subject to test.
Note 10: V = 6V
at 1kHz. DAC register loaded with all 1s.
REF
RMS
R = 600Ω. Unipolar mode op amp = LT1468.
L
Note 11: Calculation from e = √4kTRB where: k = Boltzmann constant
(J/°K), R = resistance (Ω), T = temperature (°K), B = bandwidth (Hz).
Note 12: Midscale transition code 0111 1111 1111 1111 to
1000 0000 0000 0000.
n
Note 5: I
with DAC register loaded to all 0s.
(OUT1)
Note 6: Typical temperature coefficient is 100ppm/°C.
Note 7: I load = 100Ω in parallel with 13pF.
OUT1
Note 13: R1 and R2 are measured between R1 and R
, R2 and R
COM
.
COM
Note 8: To 0.0015% for a full-scale change, measured from the falling
edge of LD.
sn1599 1599fs
3
LTC1599
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Unipolar Multiplying Mode
Signal-to-(Noise + Distortion)
vs Frequency
Midscale Glitch Impulse
Full-Scale Settling Waveform
–40
–50
40
30
20
10
V
C
= 5V USING AN LT1468
= 30pF
USING AN LT1468
CC
C
V
= 30pF
FEEDBACK
FEEDBACK
= 10V
REF
R
L
= 600Ω
REFERENCE = 6V
RMS
LD PULSE
5V/DIV
–60
–70
GATED
SETTLING
WAVEFORM
500µV/DIV
0
–80
1.5nV-s TYPICAL
–10
500kHz FILTER
–90
–20
–30
–40
80kHz FILTER
–100
–110
500ns/DIV
1599 G02
USING LT1468 OP AMP
CFEEDBACK = 20pF
0V to 10V STEP
30kHz FILTER
10k 100k
0.2
0.4
TIME (µs)
0.8
10
100
1k
0
1.0
0.6
FREQUENCY (Hz)
1599 G03
1599 G01
Bipolar Multiplying Mode
Signal-to-(Noise + Distortion)
vs Frequency, Code = All Zeros
Bipolar Multiplying Mode
Signal-to-(Noise + Distortion)
vs Frequency, Code = All Ones
Supply Current vs Input Voltage
–40
–50
–40
–50
5
V
C
= 5V USING TWO LT1468s
FEEDBACK
= 600Ω
V
C
= 5V USING TWO LT1468s
FEEDBACK
R = 600Ω
L
V
= 5V
CC
CC
CC
= 15pF
= 15pF
ALL DIGITAL INPUTS
TIED TOGETHER
R
L
4
3
2
1
0
REFERENCE = 6V
REFERENCE = 6V
RMS
RMS
–60
–60
–70
–70
–80
–80
500kHz FILTER
500kHz FILTER
–90
–90
80kHz FILTER
30kHz FILTER
–100
–110
–100
–110
80kHz FILTER
30kHz
FILTER
10
100
1k
10k
100k
10
100
1k
10k
100k
0
1
2
3
4
5
FREQUENCY (Hz)
FREQUENCY (Hz)
INTPUT VOLTAGE (V)
1599 G04
1599 G05
1599 G06
Logic Threshold vs Supply Voltage
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
2
3
4
5
6
7
1
0
32768
49152
0
16384
32768
49152
65535
16384
65535
SUPPLY VOLTAGE (V)
DIGITAL INPUT CODE
DIGITAL INPUT CODE
1599 G07
1599 G08
1598 G09
sn1599 1599fs
4
LTC1599
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity
vs Reference Voltage
in Unipolar Mode
Integral Nonlinearity
vs Reference Voltage
in Bipolar Mode
Differential Nonlinearity
vs Reference Voltage
in Unipolar Mode
1.0
0.8
1.0
0.8
1.0
0.8
0.6
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–10 –8 –6 –4 –2
0
2
4
6
8
10
–10 –8 –6 –4 –2
0
2
4
6
8
10
–10 –8 –6 –4 –2
0
2
4
6
8
10
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
1599 G10
1599 G11
1599 G12
Differential Nonlinearity
vs Reference Voltage
in Bipolar Mode
Integral Nonlinearity vs
Suppy Voltage in Unipolar Mode
1.0
0.8
1.0
0.8
0.6
0.6
0.4
V
V
= 10V
= 10V
0.4
REF
0.2
0.2
V
V
= 2.5V
= 2.5V
REF
0
0
REF
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
REF
2
3
4
5
6
7
–10 –8 –6 –4 –2
0
2
4
6
8
10
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
1599 G14
1599 G13
Integral Nonlinearity vs
Suppy Voltage in Bipolar Mode
Differential Nonlinearity vs
Suppy Voltage in Unipolar Mode
2.0
1.5
1.0
0.8
0.6
1.0
0.4
V
REF
= 10V
= 2.5V
REF
0.5
V
= 10V
REF
0.2
V
V
= 2.5V
REF
0
0
V
= 10V
REF
–0.2
–0.4
–0.6
–0.8
–1.0
V
= 10V
– 0.5
–1.0
–1.5
–2.0
REF
REF
V
= 2.5V
V
REF
= 2.5V
2
3
4
5
6
7
2
3
4
5
6
7
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
1599 G15
1599 G16
sn1599 1599fs
5
LTC1599
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Differential Nonlinearity vs
Unipolar Multiplying Mode Frequency
Response vs Digital Code
Supply Voltage in Bipolar Mode
1.0
0.8
0
ALL BITS ON
D15 ON
D14 ON
D13 ON
D12 ON
D11 ON
D10 ON
D9 ON
D8 ON
D7 ON
D6 ON
D5 ON
–20
–40
0.6
0.4
0.2
V
V
= 10V
= 10V
REF
REF
0
–60
V
V
= 2.5V
= 2.5V
REF
REF
–0.2
–0.4
–0.6
–0.8
–1.0
D4 ON
D3 ON
–80
D2 ON
D1 ON
D0 ON
–100
–120
ALL BITS OFF
2
3
4
5
6
7
100
1k
10k
100k
1M
10M
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
1599 G18
1599 G17
VREF
30pF
4 3 2 1 5 6
LTC1599
7
–
LT1468
VOUT
+
8, 9, 19
Bipolar Multiplying Mode Frequency
Response vs Digital Code
Bipolar Multiplying Mode Frequency
Response vs Digital Code
0
–20
–40
–60
–80
0
ALL BITS ON
ALL BITS OFF
D14 ON
D15 AND D14 ON
D15 AND D13 ON
D15 AND D12 ON
D15 AND D11 ON
D15 AND D10 ON
D15 AND D9 ON
D15 AND D8 ON
D15 AND D7 ON
D15 AND D6 ON
D14 AND D13 ON
D14 TO D12 ON
D14 TO D11 ON
D14 TO D10 ON
D14 TO D9 ON
D14 TO D8 ON
D14 TO D7 ON
D14 TO D6 ON
D14 TO D5 ON
–20
–40
–60
D15 AND D5 ON
D15 AND D4 ON
D15 AND D3 ON
D15 AND D2 ON
CODES FROM
CODES FROM
MIDSCALE
TO ZERO SCALE
D14 TO D4 ON
D14 TO D3 ON
D14 TO D2 ON
D14 TO D1 ON
MIDSCALE
TO FULL SCALE
–80
D15 AND D1 ON
D15 AND D0 ON
D14 TO D0 ON
D15 ON
D15 ON
*
*
–100
–100
10
100
1k
10k
100k 1M
10M
10
100
1k
10k
100k 1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
1599 G19
1599 G20
*DAC ZERO VOLTAGE OUTPUT LIMITED BY BIPOLAR
ZERO ERROR TO –96dB TYPICAL (–78dB MAX, A GRADE)
*DAC ZERO VOLTAGE OUTPUT LIMITED BY BIPOLAR
ZERO ERROR TO –96dB TYPICAL (–78dB MAX, A GRADE)
V
REF
V
REF
+
+
LT1468
–
LT1468
–
V
V
OUT
OUT
12pF
12pF
12pF
12pF
15pF
–
15pF
–
4
3
2 1 5 6
4
3
2 1 5 6
7
7
LTC1599
LT1468
+
LTC1599
LT1468
+
8, 9, 19
8, 9, 19
sn1599 1599fs
6
LTC1599
U
U
U
PIN FUNCTIONS
CLVL (Pin 10): Clear Level. CLVL = 0, selects reset to zero
code. CLVL = 1, selects reset to midscale code. Normally
hardwired to a logic high or a logic low.
REF (Pin 1): Reference Input. Typically ±10V, accepts up
to ±25V. In 2-quadrant mode, this pin is the reference
input. In 4-quadrant mode, this pin is driven by external
inverting reference amplifier.
LD (Pin 11): DAC Digital Input Load Control Input. When
LD is taken to a logic low, data is loaded from the input
register into the DAC register, updating the DAC output.
R2 (Pin 2): 4-Quadrant Resistor R2. Typically ±10V,
accepts up to ±25V. In 2-quadrant operation, connect this
pin to ground. In 4-quadrant mode tie to the REF pin and
to the output of an external amplifier. See Figures 1 and 3.
WR (Pin 12): DAC Digital Write Control Input. When WR
istakentoalogiclow,dataisloadedfromthe8digitalinput
pins into the 16-bit wide input register. The MLBYTE pin
determines whether the MSB or LSB byte is loaded.
RCOM (Pin 3): Center Tap Point of the Two 4-Quadrant
Resistors R1 and R2. Normally tied to the inverting input
ofanexternalamplifierin4-quadrantoperation, otherwise
connect this pin to ground. See Figures 1 and 3. The ab-
solutemaximumvoltagerangeonthispinis–0.3Vto12V.
MLBYTE(Pin13):MSBorLSBByteSelect.WhenMLBYTE
is taken to a logic low and WR is taken to a logic low, data
is loaded from the 8 digital input pins into the first 8 bits
ofthe16-bitwideinputregister. WhenMLBYTEistakento
a logic high and WR is taken to a logic low, data is loaded
fromthe8digitalinputpinsintothe8MSBbitsoftheinput
register.
R1 (Pin 4): 4-Quadrant Resistor R1. Typically ±10V,
accepts up to ±25V. In 2-quadrant operation connect this
pin to ground. In 4-quadrant mode tie to ROFS (Pin 5). See
Figures 1 and 3.
D7 to D3 (Pins 14 to 18): Digital Input Data Bits.
DGND (Pin 19): Digital Ground. Tie to ground.
ROFS (Pin 5): Bipolar Offset Resistor. Typically swings
±10V, accepts up to ±25V. In 2-quadrant operation, tie to
RFB. In 4-quadrant operation tie to R1.
V
CC (Pin20):ThePositiveSupplyInput.4.5V≤VCC ≤5.5V.
RFB (Pin6):FeedbackResistor.Normallytiedtotheoutput
Requires a bypass capacitor to ground.
of the current to voltage converter op amp. Typically
D2 to D0 (Pins 21 to 23): Digital Input Data Bits.
swings ±10V. Swings ±VREF
.
CLR (Pin 24): Digital Clear Control Function for the DAC.
When CLR and CLVL are taken to a logic low, the DAC
output and all internal registers are set to zero code. When
CLRistakentoalogiclowandCLVListakentoalogichigh,
theDACoutputandallinternalregistersaresettomidscale
code.
IOUT1 (Pin 7): DAC Current Output. Tie to the inverting
input of the current to voltage converter op amp.
IOUT2F (Pin 8): Force Complement Current Output. Nor-
mally tied to ground.
IOUT2S (Pin 9): Sense Complement Current Output. Nor-
mally tied to ground.
TRUTH TABLE
Table 1
CONTROL INPUTS
CLR
0
WR
MLBYTE
LD
X
REGISTER OPERATION
X
X
0
1
X
X
X
Reset Input and DAC Registers to Zero Scale When CLVL = 0 and Midscale When CLVL = 1
Load the LSB Byte of the Input Register with All 8 Data Bits
Load the MSB Byte of the Input Register with All 8 Data Bits
Load the DAC Register with the Contents of the Input Register
No Register Operation
1
1
1
1
1
1
1
1
1
1
Flow-Through Mode. The DAC Register and the Selected Input Register Are Transparent. The Unselected Input
Register Retains Its Previous Data Byte. Note Only One Byte Is Transparent at a Time, the Selected Byte Being
Determined By the Logic Value of MLBYTE Prior to WR Being Pulsed Low.
sn1599 1599fs
7
LTC1599
W
BLOCK DIAGRA
48k
48k
REF
R2
R
FB
1
2
6
5
12k
R
48k
96k
12k
48k
48k
48k
48k
48k
48k
96k
96k
96k
R
OFS
12k
12k
R
COM
3
R1
4
7
8
9
I
I
OUT1
V
CC
20
OUT2F
I
OUT2S
DECODER
19 DGND
D15
(MSB)
D14
D13
D12
D11
• • •
D0
(LSB)
LD
LOAD
11
RST
RST
24 CLR
POWER-ON
RESET
LOGIC
DAC REGISTER
10 CLVL
MSB ENABLE
LSB ENABLE
INPUT REGISTER
MSB BYTE
INPUT REGISTER
LSB BYTE
WR
12
13
EN
EN
BYTE
ENABLE
LOGIC
MLBYTE
1599 BD
14
15
18
21
22
D1
23
• • • •
D7
D6
D3
D2
D0
W U
W
TI I G DIAGRA
t
t
BWH
BWH
MLBYTE
t
t
BWS
BWS
WR
D0 TO D7
LD
t
t
WR
WR
t
t
t
t
DH
DS
DH
DS
t
t
LD
LWD
CLR
t
1599 TD
CLR
sn1599 1599fs
8
LTC1599
U
W U U
APPLICATIONS INFORMATION
Description
brought to a logic low level, the existing level of MLBYTE
determines which byte is loaded into the input register. If
the logic level of MLBYTE is changed while WR remains
low, no change will occur. This is because WR is an edge
triggered signal and once it goes low it locks out any
furtherchangesinMLBYTE.WRmustbebroughthighand
then low again to accept the new MLBYTE condition. The
second register (DAC register) is updated with the data
from the input register when the LD pin is brought to a
logiclowlevel. UpdatingtheDACregisterupdatestheDAC
outputwiththenewdata. Thedeglitcherisactivatedonthe
falling edge of the LD pin. The asynchronous clear pin
resets the LTC1599 to zero scale when the CLVL pin is at
a logic low level and to midscale when the CLVL pin is at
a logic high level. CLR resets both the input and DAC
registers. The device also has a power-on reset. Table 1
shows the truth table for the device.
The LTC1599 is a 16-bit multiplying, current output DAC
with a 2-byte (8-bit wide) digital interface. The device
operates from a single 5V supply and provides both
unipolar 0V to –10V or 0V to 10V and bipolar ±10V output
ranges from a 10V or –10V reference input. It has three
additional precision resistors on chip for bipolar opera-
tion. Refer to the Block Diagram regarding the following
description.
The 16-bit DAC consists of a precision R-2R ladder for the
13LSBs. The 3MSBs are decoded into seven segments of
resistor value R (48k typ). Each of these segments and the
R-2R ladder carries an equally weighted current of one
eighth of full scale. The feedback resistor RFB and
4-quadrant resistor ROFS have a value of R/4. 4-quadrant
resistors R1 and R2 have a magnitude of R/4. R1 and R2
together with an external op amp (see Figure 4) inverts the
reference input voltage and applies it to the 16-bit DAC
input REF, in 4-quadrant operation. The REF pin presents
a constant input impedance of R/8 in unipolar mode and
R/12inbipolarmode.Theoutputimpedanceofthecurrent
output pin IOUT1 varies with DAC input code. The IOUT1
capacitance due to the NMOS current steering switches
alsovarieswithinputcodefrom70pFto115pF. IOUT2F and
IOUT2S are normally tied to the system analog ground. An
added feature of the LTC1599 is a proprietary deglitcher
thatreducesglitchimpulseto1.5nV-sovertheDACoutput
voltage range.
Unipolar Mode
(2-Quadrant Multiplying, VOUT = 0V to –VREF
)
The LTC1599 can be used with a single op amp to provide
2-quadrant multiplying operation as shown in Figure 1.
With a fixed –10V reference, the circuit shown gives a
precision unipolar 0V to 10V output swing.
Bipolar Mode
(4-Quadrant Multiplying, VOUT = –VREF to VREF
)
The LTC1599 contains on chip all the 4-quadrant resistors
necessary for bipolar operation. 4-quadrant multiplying
operation can be achieved with a minimum of external
components, a capacitor and a dual op amp, as shown in
Figure 3. With a fixed 10V reference, the circuit shown
gives a precision bipolar –10V to 10V output swing.
Digital Section
TheLTC1599hasabytewide(8-bit),digitalinputdatabus.
The device is double-buffered with two 16-bit registers.
The double-buffered feature permits the update of several
DACs simultaneously. The input register is loaded directly
from an 8-bit (or higher) microprocessor bus in a two step
sequence. The MLBYTE pin selects whether the 8 input
data bits are loaded into the LSB or the MSB byte of the
input register. When MLBYTE is brought to a logic low
level and WR is given a logic low going pulse, the 8 data
bits are loaded into the LSB byte of the input register.
Conversely, when MLBYTE is brought to a logic high level
and WR is given a logic low going pulse, the 8 data bits are
loaded into the MSB byte of the input register. If WR is
Op Amp Selection
Because of the extremely high accuracy of the 16-bit
LTC1599, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Tables 2 and 3 contain equations for evaluating the effects
of op amp parameters on the LTC1599’s accuracy when
sn1599 1599fs
9
LTC1599
U
W U U
APPLICATIONS INFORMATION
configured in unipolar or bipolar modes of operation
(Figures 1 and 3). These are the changes the op amp can
cause to the INL, DNL, unipolar offset, unipolar gain error,
bipolar zero and bipolar gain error. Table 4 contains a
partiallistofLTCprecisionopampsrecommendedforuse
with the LTC1599. The two sets of easy-to-use design
equations simplify the selection of op amps to meet the
system’s specified error budget. Select the amplifier from
Table 4 and insert the specified op amp parameters in
either Table 2 or Table 3. Add up all the errors for each
category to determine the effect the op amp has on the
accuracy of the LTC1599. Arithmetic summation gives an
(unlikely) worst-case effect. RMS summation produces a
more realistic effect.
INLdegradationand0.15LSBDNLdegradationwitha10V
full-scale range (20V range in bipolar). For the LTC1599
configured in the unipolar mode, the same 500µV op amp
offset will cause a 3.3LSB zero-scale error and a 3.45LSB
gain error with a 10V full-scale range.
While not directly addressed by the simple equations in
Tables 2 and 3, temperature effects can be handled just as
easily for unipolar and bipolar applications. First, consult
an op amp’s data sheet to find the worst-case VOS and IB
over temperature. Then, plug these numbers in the VOS
and IB equations from Table 2 or Table 3 and calculate the
temperature induced effects.
For applications where fast settling time is important,
Application Note 74, entitled “Component and Measure-
ment Advances Ensure 16-Bit DAC Settling Time,” offers
a thorough discussion of 16-bit DAC settling time and op
amp selection.
Op amp offset will contribute mostly to output offset and
gain error and has minimal effect on INL and DNL. For the
LTC1599,a500µVopampoffsetwillcauseabout0.55LSB
Table 2. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in Unipolar Applications
OP AMP
(mV)
INL (LSB)
DNL (LSB)
UNIPOLAR OFFSET (LSB)
• 6.6 • (10V/V
UNIPOLAR GAIN ERROR (LSB)
V
V
OS
• 1.2 • (10V/V
)
REF
V
• 0.3 • (10V/V
)
V
)
V
OS
• 6.9 • (10V/V )
REF
OS
OS
REF
OS
REF
I (nA)
B
I • 0.00055 • (10V/V
)
REF
I • 0.00015 • (10V/V
)
I • 0.065 • (10V/V
)
0
B
B
REF
B
REF
A
(V/V)
10k/A
3k/A
0
131k/A
VOL
VOL
VOL
VOL
Table 3. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in Bipolar Applications
OP AMP
(mV)
INL (LSB)
DNL (LSB)
BIPOLAR ZERO ERROR (LSB)
• 9.9 • (10V/V
BIPOLAR GAIN ERROR (LSB)
V
V
• 1.2 • (10V/V
)
V
• 0.3 • (10V/V
)
V
OS1
)
V
OS1
• 6.9 • (10V/V
0
)
REF
OS1
OS1
REF
OS1
REF
REF
I
(nA)
I
• 0.00055 • (10V/V
)
I
• 0.00015 • (10V/V
)
I
• 0.065 • (10V/V
)
REF
B1
B1
REF
B1
REF
B1
A
V
10k/A
3k/A
0
196k/A
VOL1
VOL1
VOL
VOL1
(mV)
0
0
0
0
V
• 6.7 • (10V/V
)
V
• 13.2 • (10V/V
)
REF
OS2
OS2
REF
OS2
I
(nA)
0
0
I
• 0.065 • (10V/V
)
I
• 0.13 • (10V/V
)
REF
B2
B2
REF
B2
A
65k/A
131k/A
VOL2
VOL2
VOL2
Table 4. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC1599, with Relevant Specifications
Amplifier Specifications
VOLTAGE
NOISE
nV/√Hz
CURRENT
NOISE
pA/√Hz
SLEW
RATE
V/µs
GAIN BANDWIDTH
PRODUCT
MHz
t
POWER
DISSIPATION
mW
SETTLING
V
I
nA
A
OL
V/mV
with LTC1599
OS
B
AMPLIFIER
LT1001
µV
25
50
60
70
75
µs
2
800
10
14
14
2.7
5
0.12
0.008
0.008
0.3
0.25
0.2
0.8
0.7
120
120
115
19
46
LT1097
0.35
0.25
20
1000
1500
4000
5000
11
LT1112 (Dual)
LT1124 (Dual)
LT1468
0.16
4.5
0.75
12.5
90
10.5/Op Amp
69/Op Amp
10
0.6
22
2.5
117
sn1599 1599fs
10
LTC1599
U
W U U
APPLICATIONS INFORMATION
5V
0.1µF
V
REF
6
3
4
2
1
20
5
R1
R
COM
V
R
R2 REF
R
CC
OFS
FB
33pF
R
R
OFS
FB
R1
R2
8
I
–
OUT1
2
3
DATA
7
INPUTS
6
V
OUT
LTC1599
16-BIT DAC
LT1001
0V TO –V
REF
I
14 TO 18,
21 TO 23
OUT2F
8
+
I
OUT2S
19
9
13
MLBYTE
MLBYTE
WR LD CLR CLVL
12 11 24
10
DGND
WR
LD
CLR
CLVL
Unipolar Binary Code Table
DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
ANALOG OUTPUT
VOUT
MSB
LSB
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
–VREF (65,535/65,536)
–VREF (32,768/65,536) = –VREF/2
–VREF (1/65,536)
0V
1599 F01
Figure 1. Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to –VREF
5V
5
6
+
0.1µF
7
1/2 LT1112
–
V
REF
4
6
3
2
1
20
5
R1
R
COM
R2 REF
V
CC
R
OFS
R
FB
33pF
R
OFS
R
FB
R1
R2
8
DATA
INPUTS
I
–
OUT1
I
2
3
7
1
V
OUT
16-BIT DAC
LTC1599
1/2 LT1112
+
0V TO V
REF
OUT2F
14 TO 18,
21 TO 23
8
I
OUT2S
9
13
MLBYTE
MLBYTE
WR LD CLR CLVL
12 11 24
10
19
DGND
WR
LD
CLR
CLVL
Unipolar Binary Code Table
DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
ANALOG OUTPUT
VOUT
MSB
LSB
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
VREF (65,535/65,536)
V
V
REF (32,768/65,536) = VREF/2
REF (1/65,536)
1599 F02
0V
Figure 2. Noninverting Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to VREF
sn1599 1599fs
11
LTC1599
APPLICATIONS INFORMATION
U
W U U
V
REF
5V
5
+
0.1µF
7
1/2 LT1112
6
–
6
4
3
2
1
20
5
R1
R
COM
V
CC
R2 REF
R
R
OFS
FB
15pF
R
R
OFS
FB
R1
R2
8
I
–
OUT1
I
2
3
7
DATA
INPUTS
1
V
OUT
–V
16-BIT DAC
LTC1599
1/2 LT1112
+
TO V
REF
REF
OUT2F
14 TO 18,
21 TO 23
8
I
OUT2S
19
9
13
MLBYTE
MLBYTE
WR LD CLR CLVL
12 11 24
10
DGND
WR
LD
CLR
CLVL
Bipolar Offset Binary Code Table
DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
ANALOG OUTPUT
VOUT
MSB
LSB
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
V
V
0V
REF (32,767/32,768)
REF (1/32,768)
–VREF (1/32,768)
–VREF
1599 F03
Figure 3. Bipolar Operation (4-Quadrant Multiplication) VOUT = –VREF to VREF
Precision Voltage Reference Considerations
A reference’s output voltage temperature coefficient af-
fects not only the full-scale error, but can also affect the
circuit’s INL and DNL performance. If a reference is
chosen with a loose output voltage temperature coeffi-
cient, then the DAC output voltage along its transfer
characteristic will be very dependent on ambient condi-
tions. Minimizing the error due to reference temperature
coefficient can be achieved by choosing a precision refer-
ence with a low output voltage temperature coefficient
and/or tightly controlling the ambient temperature of the
circuit to minimize temperature gradients.
Much in the same way selecting an operational amplifier
for use with the LTC1599 is critical to the performance of
the system, selecting a precision voltage reference also
requires due diligence. As shown in the section describing
the basic operation of the LTC1599, the output voltage of
theDACcircuitisdirectlyaffectedbythevoltagereference;
thus, any voltage reference error will appear as a DAC
output voltage error.
There are three primary error sources to consider when
selecting a precision voltage reference for 16-bit applica-
tions: output voltage initial tolerance, output voltage tem-
perature coefficient and output voltage noise.
As precision DAC applications move to 16-bit and higher
performance, reference output voltage noise may contrib-
ute a dominant share of the system’s noise floor. This in
turn can degrade system dynamic range and signal-to-
noise ratio. Care should be exercised in selecting a voltage
reference with as low an output noise voltage as practical
for the system resolution desired. Precision voltage refer-
ences, like the LT1236, produce low output noise in the
Initial reference output voltage tolerance, if uncorrected,
generates a full-scale error term. Choosing a reference
with low output voltage initial tolerance, like the LT1236
(±0.05%), minimizes the gain error caused by the refer-
ence; however, a calibration sequence that corrects for
system zero- and full-scale error is always recommended.
0.1Hz to 10Hz region, well below the 16-bit LSB level in 5V
sn1599 1599fs
12
LTC1599
U
W U U
APPLICATIONS INFORMATION
or 10V full-scale systems. However, as the circuit band-
widths increase, filtering the output of the reference may
be required to minimize output noise.
resistance traces. This preserves the excellent accuracy
(1LSB INL and DNL) of the LTC1599.
A 16-Bit, 4mA to 20mA Current Loop Controller
for Industrial Applications
Table 5. Partial List of LTC Precision References Recommended
for Use with the LTC1599, with Relevant Specifications
INITIAL
TOLERANCE
TEMPERATURE
DRIFT
0.1Hz to 10Hz
NOISE
Modern process control systems must often deal with
legacy 4mA to 20mA analog current loops as a means of
interfacing with actuators and valves located at a distance.
The circuit in Figure 5 provides an output to a current loop
controlled by an LTC1599, a 16-bit current output DAC. A
dual rail-to-rail op amp (U1, LT1366) controls a P-channel
power FET (Q2) to produce a current mirror with a precise
8:1 ratio as defined by a resistor array. The input current
to this mirror circuit is produced by a grounded base
cascode stage using a high gain transistor (Q1). The use
of a bipolar transistor in this location results in an error
term associated with U1B and Q1’s base current (–0.2%
for the device shown). For control applications however,
absolute accuracy of the output to an actuator is usually
not required. If a higher degree of absolute accuracy is
required, Q1 can be replaced with an N-channel JFET;
however, this requires a single amplifier at U1B with the
ability to drive the gate below ground. An enhancement
mode N-channel FET can be used in place of Q1 but
MOSFET leakage current must be considered and gate
overdrive must be avoided.
REFERENCE
LT1019A-5,
LT1019A-10
±0.05%
5ppm
12µV
P-P
LT1236A-5,
LT1236A-10
LT1460A-5,
LT1460A-10
±0.05%
5ppm
3µV
P-P
±0.075%
10ppm
20µV
P-P
Grounding
As with any high resolution converter, clean grounding is
important.Alowimpedanceanaloggroundplaneandstar
groundingshouldbeused. IOUT2F andIOUT2S mustbetied
to the star ground with as low a resistance as possible.
When it is not possible to locate star ground close to
IOUT2F andIOUT2S,separatetracesshouldbeusedtoroute
thesepinstostarground.Thisminimizesthevoltagedrop
from these pins to ground caused by the code dependent
current flowing to ground. When the resistance of these
circuit board traces becomes greater than 1Ω, the circuit
in Figure 4 eliminates voltage drop errors caused by high
5V
2
15V
6
10V
LT1236A-10
4
0.1µF
6
3
4
2
1
20
5
R1
R
V
R
R2 REF
R
COM
R2
FB
CC
OFS
33pF
R
R
OFS
FB
R1
8
DATA
I
–
2
3
OUT1
I
7
INPUTS
6
V
OUT
LTC1599
16-BIT DAC
LT1001
0V TO –10V
14 TO 18,
21 TO 23
OUT2F
8
+
13
MLBYTE
MLBYTE
WR LD CLR CLVL
12 11 24
10
I
DGND
19
OUT2S
3
+
–
9
WR
LD
6
LT1001
2
CLR
CLVL
1599 F04
Figure 4. Driving IOUT2F and IOUT2S with a Force/Sense Amplifier
sn1599 1599fs
13
LTC1599
U
W U U
APPLICATIONS INFORMATION
The output current of the DAC is converted to a voltage via
U3 (LT1112), producing 0V to –2.5V at Pin 1 of U3. The
resulting current in Q1 is determined by two elements of
resistor array, RN1 (3mA max). The emitter of Q1 is
maintained at 0V by the action of U1B.
In the example shown, the use of a dual op amp requires
a zener clamp to protect the gate of the MOS power
transistor. If a separate shunt-regulated supply is pro-
vided for the amplifier replacing U1A, the gate clamp (Z1)
is not required.
In applications that do not require 16-bit resolution and
accuracy, the LTC1599 can be replaced by the 14-bit
parallel LTC1591. Furthermore, the resistor array can be
substituted with discrete resistors, and Q2 could be re-
placed by a high gain bipolar PNP; for example, an FZT600
from Zetex.
As shown, this topology uses the LTC1599’s internal
divider (R1 and R2) to reduce the reference from 5V to
2.5V. If a 2.5V reference is used, it can be connected
directly to REF (Pin 1). Alternatively, if the op amp is
powered such that it has –10V output capability, the
dividerandamplifierpriortotheREFinputarenotrequired
and ROFS can be used for other purposes such as offset
trim. The two RN1 resistors at the emitter of Q1 must be
changed in this case.
Notrimisprovidedashown, asitisexpectedthatsoftware
control is preferable. The output range of 4mA to 20mA is
defined by software, as the full output range is nominally
0mA to 24mA.
Note that the output of the current transmitter shows a
network that is intended to provide a first line of defense
against ESD and prevent oscillation (1000pF and 10Ω)
that could otherwise occur in the power MOSFET if lead
inductance were more than a few inches. C1 should be as
close as possible to Q2. Using MOSFETs that have higher
threshold voltages may require changing Z1 in order to
allow full current output.
U1 is a rail-to-rail amplifier that can operate on suppy
voltages up to 36V. This defines the maximum voltage on
the loop power. If higher loop voltages are required, a
separate low power amplifier at U1A, powered by a zener
regulated supply and referenced to loop power, would
allowvoltagesuptothebreakdownvoltagesofQ1andQ2.
LOOP POWER
24V
3
4
5
6
R3
1k
0.1µF
R
N1
14 13 12 11
2
IF 2.5V REF USED CONNECT
R
R
N1
N1
Z1
6.2V
C2
DIRECTLY TO REF
15
10
2 –
8
12
LT1460-5
4
100pF
R4
1k
R5
Q2
Si9407AEX
6
10Ω
U1A
1
5
6
I
OUT
1/2 LT1366
+
7
3
+
0.1µF
C1
1000pF
7
5V
1/2 LT1112
4
–
0.1µF
5
+
Q1
6
3
4
R1
2
R2
1
REF
20
5
7
U1B
MMBT6429
HFE = 500
R
R
V
R
1/2 LT1366
COM
FB
CC
OFS
C3
6
–
33pF
R6
1k
R
R
OFS
FB
R1
R2
8
I
–
2
3
OUT1
I
DATA
7
INPUTS
R
R
N1
N1
U3
1
1
16
9
8
U2
LTC1599
16-BIT DAC
1/2 LT1112
14 TO 18,
21 TO 23
OUT2F
8
+
I
OUT2S
9
13
R
= 400Ω × 8 RESISTOR ARRAY
N1
MLBYTE
MLBYTE
WR LD CLR CLVL
12 11 24
10
19
DGND
WR
LD
CLR
CLVL
Figure 5. 16-Bit Current Loop Controller for Industrial Applications
sn1599 1599fs
14
LTC1599
U
W U U
APPLICATIONS INFORMATION
A 16-Bit General Purpose Analog Output Circuit
alternative to a resistor divider is the LTC1043 switched
capacitor building block. It can be configured as a high
precision divide-by-2. Please consult the LTC1043 data
sheet for more information.
Industrial applications often use analog signals of 0V to
5V, 0V to 10V, ±5V or ±10V. The topology in Figure 6 uses
anLTC1599toproduceauniversalanalogoutput, capable
of operation over all these ranges, with only software
configuration. High precision analog switches are used to
provideuncompromisingstabilityinallrangesandmatched
resistors internal to the LTC1599 are used, as well as a
configuration that minimizes the effects of channel resis-
tance in the switches. Note that in all cases the analog
switches have minimal current flowing through them. The
use of unbuffered analog switches in series with the
feedback/divider resistors would result in an error be-
cause of temperature coefficient mismatch between the
internalDACresistorsandtheswitchchannelresistances,
as well as the channel resistance variation over the signal
range. Quad analog switch U3 (DG212B) allows configu-
ration of feedback terms and selection of the reference
voltage. Switch C allows the buffered reference voltage to
be injected into the summing node via Pin 5 (ROFS) for
bipolar outputs. When active, switch D places ROFS in
parallel with RFB, producing an output at full scale voltage
equal to the voltage at the REF pin of the LTC1599.
The NOR gate (U4) ensures that switches C and D are not
enabled simultaneously. This eliminates contention be-
tween the reference buffer and the output amplifier.
This topology can be modified to accept a high current
bufferfollowingtheLT1112,ifhigheroutputcurrentlevels
are required or difficult loads need be driven. Adjustment
of CFB’s value may be required for the buffer amplifier
chosen.
Note that the analog switches must handle the full output
swinginthisconfiguration,butthereisavarietyofsuitable
switchesonthemarketincludingtheLTC201.TheDG212B
as shown is a newer generation part with lower leakage,
providing a performance advantage.
The DG333A, a quad single-pole, double-throw switch,
could be used for a 2-channel version similar to this
circuit. Alternatively, a single channel can be created with
the additional switches used as switched capacitor divide-
by-2, as shown on the LTC1043 data sheet. In choosing
analog switches, keep in mind the logic levels and the
signal levels required.
The other switches in U3 (A and B) are used to select the
10VreferenceproducedbytheLT1019,or5Vproducedby
the R3 and R4 divider.
Table 1. Configuration Settings for the Various Output Ranges
V
MODE
REFSEL
BIPOLAR/UNIPOLAR
GAIN
OUT
An inexpensive precision divider can be implemented
using an 8-element resistor array, paralleling four resis-
tors for R3 and four resistors for R4. Symmetry in the
interconnection of these resistors will ensure compensa-
tion for temperature gradient across the resistor array. An
0V to 5V
1
1
1
0
0
0
1
1
0
1
1
1
0V to 10V
–5V to 5V
–10V to 10V
sn1599 1599fs
15
LTC1599
U
W U U
APPLICATIONS INFORMATION
sn1599 1599fs
16
LTC1599
U
W U U
APPLICATIONS INFORMATION
Interfacing to the 68HC11
8-BIT PARALLEL
The circuit in Figure 7 is an example of using the 68HC11
to control the LTC1599. Data is sent to the DAC using two
8-bit parallel transfers from the controller’s Port B. The
WR signal is generated by manipulating the logic output
on Port A’s bit 3, the MLBYTE command is sent to the DAC
using Port A’s bit 4, and the LD command comes from the
SS output on Port D’s bit 5.
LTC1599
PORT B
68HC11
WR LD MLBYTE
PORT A, BIT 3
PORT D, BIT 5
PORT A , BIT 4
1599 F07
Figure 7. Using the 68HC11 to Control the LTC1599
The sample listing 68HC11 assembly code in Listing A is
designed to emulate the Timing Diagram found earlier in
thisdatasheet. Aftervariabledeclaration, themainportion
of the program retrieves the least significant byte from
memory, forces MLBYTE and WR to a logic low, and then
writes the low byte data to Port B. It then sets WR and
MLBYTE high. Next, the most significant byte is copied
from memory and WR is again asserted low. The high byte
is written to Port B and WR is returned high. The transfer
of the 16 bits is completed by cycling the LD input low and
then high using the SS output on Port D.
************************************************************
*
*
*
*
*
*
*
*
*
* This example program uses 8-bit parallel port B, port A and port D
* to transfer 16-bit parallel data to the LTC1599 16-bit current output
* DAC. Port B at $1004 is used for two eight bit transfers. Port A,
* bit 3 is used for the LTC1599’s WR command and bit 4 is used for the
* MLBYTE command. Port D’ SS output is used for the LTC1599’s LD
* command
*
************************************************************
*
*****************************************
* 68HC11 register definitions
*
*****************************************
*
* PIOC EQU
$1002
$1000
$1004
$1008
Parallel I/O control register
*
“STAF,STAI,CWOM,HNDS, OIN, PLS, EGA,INVB”
Port A data register
PORTA EQU
*
“Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0”
Port B data register
“Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0”
Port D data register
PORTB EQU
*
PORTD EQU
*
“ - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD “
Port D data direction register
SPI control register
This memory location holds the LTC1599’s bits 15 - 08
This memory location holds the LTC1599’s bits 07 - 00
DDRD
SPCR
EQU
EQU
$1009
$1028
$00
MBYTE EQU
LBYTE
*
EQU
$01
*****************************************
* Start OUTDATA Routine
*
*****************************************
*
ORG
LDAA
$C000
#$2F
Program start location
INIT1
*
-,-,1,0;1,1,1,1
-, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
PORTD Keeps SS* a logic high when DDRD, Bit5 is set
STAA
LDAA
STAA
#$38
DDRD
-,-,1,1;1,0,0,0
SS* , SCK, MOSI are configured as Outputs
MISO, TxD, RxD are configured as Inputs
*
* DDRD’s Bit5 is a 1 so that port D’s SS* pin is a general output
sn1599 1599fs
17
LTC1599
U
W U U
APPLICATIONS INFORMATION
GETDATA PSHX
PSHY
PSHA
LDY
#$1000 Setup index
*
*****************************************
* Retrieve DAC data from memory and
* send it to the LTC1599
*
*
*****************************************
*
LDAA
BCLR
LBYTE
Retrieve the least significant byte from memory
This sets PORTA, Bit4 output to a logic
PORTA,Y %00010000
*
*
*
low, forcing MLBYTE input to a logic low
This forces a low on the LTC1599’s WR pin
Transfer the least significant byte to the DAC
This forces a high on the LTC1599’s WR pin
This sets PORTA, Bit4 output to a logic
BCLR
STAA
BSET
BSET
PORTA,Y %00001000
PORTB
PORTA,Y %00001000
PORTA,Y %00010000
high, forcing MLBYTE to a logic high
LDAA
BCLR
STAA
BSET
MBYTE
Retrieve the most significant byte from memory
This forces a low on the LTC1599’s WR pin
Transfer the most significant byte to the DAC
This forces a high on the LTC1599’s WR pin
PORTA,Y %00001000
PORTB
PORTA,Y %00001000
*******************************************
* The next two instructions exercise
*
*
* the LD input, latching the data
* that was just loaded
*******************************************
*
*
BCLR
BSET
PORTD,Y %00100000
PORTD,Y %00100000
LD goes low
and returns high
*
*******************************************
* Data transfer routine completed
*******************************************
*
*
PULA
PULY
PULX
RTS
Restore the A register
Restore the Y register
Restore the X register
sn1599 1599fs
18
LTC1599
U
TYPICAL APPLICATION
16-Bit VOUT DAC Programmable Unipolar/Bipolar Configuration
16
15
14
LTC203AC
3
UNIPOLAR/
BIPOLAR
1
2
3
2
+
–
6
LT1468
2
4
15V
LT1236A-10
6
5V
3
2
+
–
0.1µF
6
2
LT1001
4
3
1
20
5
6
R
COM
R1
R2 REF
V
CC
R
OFS
R
FB
15pF
R
OFS
R
FB
R1
R2
I
–
OUT1
7
2
3
8
6
LTC1599
LT1468
V
OUT
16-BIT DAC
DATA
I
OUT2F
+
INPUTS
8
I
14 TO 18,
21 TO 23
OUT2S
9
WR LD CLR CLVL
12 11 24
10
DGND
19
1596 TA02
WR
LD
CLR
CLVL
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTION
G Package
24-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
8.07 – 8.33*
(0.318 – 0.328)
24 23 22 21 20 19 18 17 16 15 14
5.20 – 5.38**
(0.205 – 0.212)
1.73 – 1.99
(0.068 – 0.078)
13
0° – 8°
7.65 – 7.90
(0.301 – 0.311)
0.65
(0.0256)
BSC
0.13 – 0.22
0.55 – 0.95
(0.005 – 0.009)
(0.022 – 0.037)
0.05 – 0.21
(0.002 – 0.008)
0.25 – 0.38
(0.010 – 0.015)
NOTE: DIMENSIONS ARE IN MILLIMETERS
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
G24 SSOP 1098
5
7
8
1
2
3
4
6
9
10 11 12
sn1599 1599fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC1599
TYPICAL APPLICATION
U
17-Bit Sign Magnitude DAC with Bipolar Zero Error of 140µV (0.92LSB at 17 Bits) at 25°C
16
15
14
LTC203AC
3
5V
+
–
3
2
0.1µF
6
2
2
4
LT1468
15pF
15V
1
2
LT1236A-10
6
4
3
6
1
20
5
R
R1
R2
REF
V
R
R
FB
COM
CC
OFS
SIGN
BIT
20pF
R
R
OFS
FB
R1
R2
I
–
2
3
OUT1
7
8
6
16-BIT DAC
LT1468
V
OUT
LTC1599
DATA
I
OUT2F
8
+
INPUTS
I
14 TO 18,
21 TO 23
OUT2S
9
WR LD CLR CLVL
10
DGND
19
1596 TA03
12 11 24
WR
LD
CLR
CLVL
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTION
N Package
24-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.265*
(32.131)
MAX
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
24
23
22
21
20
19
18
17
16
15
10
14
11
13
0.020
(0.508)
MIN
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
0.255 ± 0.015*
(6.477 ± 0.381)
+0.035
–0.015
0.125
(3.175)
MIN
0.325
0.018 ± 0.003
(0.457 ± 0.076)
0.100
(2.54)
BSC
3
4
5
6
7
8
9
12
1
2
+0.889
8.255
N24 1098
(
)
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
RELATED PARTS
PART NUMBER
LT1236
DESCRIPTION
COMMENTS
Precision Reference
16-Bit Accurate Op Amp
0.05% Initial Accuracy, 5ppm Temperature Drift
90MHz Gain Bandwidth, 22V/µs Slew Rate
On-Chip 4-Quadrant Resistors
LT1468
LTC1591/LTC1597 Parallel 14/16-Bit Current Output DACs
LTC1595/LTC1596 Serial 16-Bit Current Output DACs
Low Glitch, ±1LSB Maximum INL, DNL
Low Power, Deglitched, 4-Quadrant Multiplying V
LTC1650
LTC1657
LTC1658
16-Bit Voltage Output DAC
DAC, ±4.5V Output Swing
OUT
16-Bit Parallel Voltage Output DAC
14-Bit Rail-to-Rail Micropower DAC
Low Power, 16-Bit Monotonic Over Temperature, Multiplying Capability
Low Power Multiplying V DAC in MSOP. Output Swings from GND to REF.
OUT
sn1599 1599fs
1599f LT/TP 1199 4K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
©LINEAR TECHNOLOGY CORPORATION 1999
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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