LTC1605IN#PBF [Linear]
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| 型号： | LTC1605IN#PBF |
| 厂家： | 
Linear |
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LTC1605
16-Bit, 100ksps,
Sampling ADC
U
DESCRIPTION
FEATURES
The LTC®1605 is a 100ksps, sampling 16-bit A/D con-
verter that draws only 55mW (typical) from a single 5V
supply. This easy-to-use device includes sample-and-
hold, precision reference, switched capacitor successive
approximation A/D and trimmed internal clock.
■
Sample Rate: 100ksps
■
Single 5V Supply
■
Bipolar Input Range: ±10V
Power Dissipation: 55mW Typ
Integral Nonlinearity: ±2.0LSB Max
Guaranteed No Missing Codes
Signal-to-Noise Ratio: 86dB Typ
Operates with Internal or External Reference
Internal Synchronized Clock
28-Pin 0.3” PDIP, SSOP and SW Packages
Improved 2nd Source to ADS7805 and AD976
■
■
■
■
■
■
■
■
The LTC1605’s input range is an industry standard ±10V.
Maximum DC specs include ±2.0LSB INL and 16-bits no
missing codes over temperature. An external reference
can be used if greater accuracy over temperature is
needed.
The ADC has a microprocessor compatible, 16-bit or two
byte parallel output port. A convert start input and a data
ready signal (BUSY) ease connections to FIFOs, DSPs and
microprocessors.
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APPLICATIONS
■
Industrial Process Control
■
Multiplexed Data Acquisition Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
High Speed Data Acquisition for PCs
■
Digital Signal Processing
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TYPICAL APPLICATION
Typical INL Curve
Low Power, 100kHz, 16-Bit Sampling ADC on 5V Supply
2.0
5V
1.5
1.0
10µF
0.1µF
28
27
V
V
DIG ANA
0.5
6 TO 13
15 TO 22
16-BIT
200Ω
20k
V
IN
1
±10V
INPUT
0
16-BIT
SAMPLING ADC
OR 2 BYTE
PARALLEL
BUS
D15 TO D0
–0.5
–1.0
–1.5
–2.0
33.2k
4k
10k
CAP
REF
4
3
26
25
BUSY
CS
2.2µF
2.2µF
BUFFER
4k
32768
CODE
0
16384
49152
65535
DIGITAL
CONTROL
LOGIC AND
TIMING
CONTROL
SIGNALS
R/C 24
REFERENCE
1605 • TA02
BYTE
23
AGND1 AGND2
DGND
14
1605 • TA01
2
5
1
LTC1605
W W W
U
W
U
ABSOLUTE AXI U RATI GS
/O
PACKAGE RDER I FOR ATIO
(Notes 1, 2)
ORDER PART
TOP VIEW
VANA .......................................................................... 7V
VDIG to VANA ........................................................... 0.3V
NUMBER
V
1
2
3
4
5
6
7
8
9
28
27
V
V
IN
DIG
AGND1
REF
ANA
V
DIG ........................................................................... 7V
LTC1605ACG
LTC1605ACN
LTC1605ACSW
LTC1605AIG
LTC1605AIN
LTC1605AISW
LTC1605CG
LTC1605CN
LTC1605CSW
LTC1605IG
26 BUSY
25 CS
24 R/C
23 BYTE
22 D0
21 D1
20 D2
19 D3
18 D4
17 D5
16 D6
15 D7
Ground Voltage Difference
DGND, AGND1 and AGND2 .............................. ±0.3V
Analog Inputs (Note 3)
CAP
AGND2
D15 (MSB)
D14
VIN ..................................................................... ±25V
CAP ............................VANA + 0.3V to AGND2 – 0.3V
REF....................................Indefinite Short to AGND2
Momentary Short to VANA
D13
D12
D11 10
D10 11
D9 12
Digital Input Voltage (Note 4) ............ VSS – 0.3V to 10V
Digital Output Voltage........ VDGND – 0.3V to VDIG + 0.3V
Power Dissipation.............................................. 500mW
Operating Ambient Temperature Range
LTC1605IN
LTC1605ISW
D8 13
DGND 14
LTC1605C................................................ 0°C to 70°C
LTC1605I............................................ – 40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
G PACKAGE
28-LEAD PLASTIC SSOP
N PACKAGE
28-LEAD PDIP
SW PACKAGE
28-LEAD PLASTIC SO WIDE
TJMAX = 125°C, θJA = 95°C/W (G)
T
JMAX = 125°C, θJA = 130°C/W (N)
TJMAX = 125°C, θJA = 130°C/W (SW)
Consult factory for Military grade parts.
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CONVERTER CHARACTERISTICS With external reference (Notes 5, 6).
LTC1605
LTC1605A
PARAMETER
CONDITIONS
MIN
16
TYP
MAX
MIN
16
TYP
MAX
UNITS
Resolution
●
●
Bits
Bits
No Missing Codes
Transition Noise
15
16
1.0
1.0
LSB
Integral Linearity Error
Bipolar Zero Error
Bipolar Zero Error Drift
Full-Scale Error Drift
Full-Scale Error
(Note 7)
●
●
±3
±2
LSB
Ext. Reference = 2.5V (Note 8)
±10
±10
mV
±2
±7
±2
±5
ppm/°C
ppm/°C
%
Ext. Reference = 2.5V (Notes 12, 13)
Ext. Reference = 2.5V
●
±0.50
±8
±0.25
±8
Full-Scale Error Drift
Power Supply Sensitivity
±2
±2
ppm/°C
V
= V = V
V = 5V ±5% (Note 9)
DD
LSB
ANA
DIG
DD
2
LTC1605
U
U
(Note 5)
ANALOG INPUT
LTC1605/LTC1605A
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
IN
Analog Input Range (Note 9)
4.75V ≤ V
≤ 5.25V, 4.75V ≤ V ≤ 5.25V
●
●
±10
ANA
DIG
I
Analog Input Leakage Current
Analog Input Capacitance
CS = High
±1
µA
IN
C
IN
10
20
pF
R
kΩ
U AnaloW g Input Impedance
IN
(Notes 5, 14)
DYNAMIC ACCURACY
LTC1605/LTC1605A
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
UNITS
S/(N + D) Signal-to-(Noise + Distortion) Ratio
1kHz Input Signal (Note 14)
10kHz Input Signal
20kHz, –60dB Input Signal
87.5
87
30
dB
dB
dB
THD
Total Harmonic Distortion
1kHz Input Signal, First 5 Harmonics
10kHz Input Signal, First 5 Harmonics
– 102
–94
dB
dB
Peak Harmonic or Spurious Noise
1kHz Input Signal
10kHz Input Signal
–102
–94
dB
dB
Full-Power Bandwidth
Aperture Delay
(Note 15)
275
40
kHz
ns
Aperture Jitter
Sufficient to Meet AC Specs
Transient Response
Overvoltage Recovery
Full-Scale Step (Note 9)
(Note 16)
2
µs
150
ns
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INTERNAL REFERENCE CHARACTERISTICS
(Note 5)
LTC1605/LTC1605A
PARAMETER
CONDITIONS
MIN
TYP
2.500
±5
MAX
UNITS
V
V
Output Voltage
Output Tempco
I
I
= 0
= 0
●
●
2.470
2.520
V
REF
REF
OUT
OUT
ppm/°C
Internal Reference Source Current
External Reference Voltage for Specified Linearity
External Reference Current Drain
CAP Output Voltage
1
µA
V
(Notes 9, 10)
2.30
2.50
2.70
100
Ext. Reference = 2.5V (Note 9)
µA
V
I
2.50
OUT
U
= 0U
DIGITAL INPUTS AND DIGITAL OUTPUTS
(Note 5)
LTC1605/LTC1605A
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
V
= 5.25V
= 4.75V
= 0V to V
●
●
●
2.4
V
V
IH
IL
DD
DD
IN
0.8
I
±10
µA
pF
V
IN
DD
C
V
Digital Input Capacitance
High Level Output Voltage
5
IN
V
V
= 4.75V
= 4.75V
I
I
I
I
= –10µA
= –200µA
= 160µA
= 1.6mA
4.5
OH
DD
DD
O
O
O
O
●
●
4.0
V
V
Low Level Output Voltage
0.05
0.10
V
OL
0.4
V
3
LTC1605
DIGITAL INPUTS AND DIGITAL OUTPUTS
U
U
(Note 5)
LTC1605/LTC1605A
TYP
SYMBOL PARAMETER
CONDITIONS
= 0V to V , CS High
MIN
MAX
±10
15
UNITS
µA
I
Hi-Z Output Leakage D15 to D0
Hi-Z Output Capacitance D15 to D0
Output Source Current
V
●
●
OZ
OUT
DD
C
OZ
CS High (Note 9)
pF
I
I
V
V
= 0V
–10
10
mA
mA
SOURCE
SINK
OUT
OUT
Output Sink Current
= V
DD
W U
TIMING CHARACTERISTICS
(Note 5)
LTC1605/LTC1605A
TYP
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNITS
kHz
µs
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Conversion Time
●
●
●
●
●
●
100
SAMPLE(MAX)
8
2
CONV
Acquisition Time
µs
ACQ
1
Convert Pulse Width
(Note 11)
(Note 9)
40
ns
Data Valid Delay After R/C↓
BUSY Delay from R/C↓
BUSY Low
8
65
8
µs
2
C = 50pF
L
ns
3
µs
4
BUSY Delay After End of Conversion
Aperture Delay
220
40
ns
5
ns
6
Bus Relinquish Time
BUSY Delay After Data Valid
Previous Data Valid After R/C↓
R/C to CS Setup Time
Time Between Conversions
●
●
10
50
35
83
83
ns
7
200
7.4
ns
8
µs
9
(Notes 9, 10)
(Notes 9, 10)
10
10
10
ns
10
11
12
µs
Bus Access and Byte DelayW U
ns
POWER REQUIREMENTS (Note 5)
LTC1605/LTC1605A
TYP
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
5.25
16
UNITS
V
V
Positive Supply Voltage
Positive Supply Current
Power Dissipation
(Notes 9, 10)
4.75
DD
I
●
11
55
mA
DD
P
80
mW
DIS
The
●
indicates specifications which apply over the full operating
Note 5: V = 5V, f
specified.
= 100kHz, t = t = 5ns unless otherwise
SAMPLE r f
DD
temperature range; all other limits and typicals T = 25°C.
A
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 6: Linearity, offset and full-scale specifications apply for a V input
with respect to ground.
IN
Note 2: All voltage values are with respect to ground with DGND, AGND1
and AGND2 wired together (unless otherwise noted).
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 3: When these pin voltages are taken below ground or above V
=
ANA
V
= V , they will be clamped by internal diodes. This product can
Note 8: Bipolar offset is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111.
DIG
DD
handle input currents of greater than 100mA below ground or above V
without latch-up.
DD
Note 4: When these pin voltages are taken below ground, they will be
clamped by internal diodes. This product can handle input currents of
90mA below ground without latchup. These pins are not clamped to V
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
.
DD
4
LTC1605
ELECTRICAL CHARACTERISTICS
Note 11: With CS low the falling R/C edge starts a conversion. If R/C
returns high at a critical point during the conversion it can create small
errors. For best results ensure that R/C returns high within 3µs after the
start of the conversion.
voltage (not divided by the full-scale range) and includes the effect of
offset error.
Note 14: All specifications in dB are referred to a full-scale ±10V input.
Note 15: Full-power bandwidth is defined as full-scale input frequency at
which a signal-to-(noise + distortion) degrades to 60dB or 10 bits of
accuracy.
Note 12: As measured with fixed resistors shown in Figure 4. Adjustable to
zero with external potentiometer.
Note 13: Full-scale error is the worst-case of –FS or +FS untrimmed
deviation from ideal first and last code transitions, divided by the transition
Note 16: Recovers to specified performance after (2 • FS) input
overvoltage.
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
Change in CAP Voltage vs
Load Current
Supply Current vs Supply Voltage
Supply Current vs Temperature
0.05
0.04
0.03
0.02
0.01
12.5
12.0
12.0
11.5
11.0
10.5
f
= 100kHz
f
= 100kHz
SAMPLE
SAMPLE
0
11.5
11.0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
–0.09
–0.10
10.5
10.0
9.5
10.0
–80 –70 –60 –50 –40 –30 –20 –10
LOAD CURRENT (mA)
0
10
4.50
4.75
5.00
5.25
5.50
–50 –25
0
25
50
75
100
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
1605 • TPC03
1605 • TPC01
1605 • TPC02
Power Supply Feedthrough vs
Ripple Frequency
Typical INL Curve
Typical DNL Curve
2.0
1.5
–20
–30
–40
–50
–60
–70
2.0
1.5
1.0
1.0
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
32768
CODE
0
16384
49152
65535
32768
CODE
0
16384
49152
65535
1
10
100
1k
10k 100k
1M
RIPPLE FREQUENCY (Hz)
1605 • TPC04
1605 • TPC05
1605 • TPC06
5
LTC1605
W
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TYPICAL PERFORMANCE CHARACTERISTICS
LTC1605 Nonaveraged 4096 Point FFT Plot
0
–10
–20
–30
–40
–50
f
=
100kHz
SAMPLE
IN
f = 1kHz
SINAD = 87.5dB
THD = –101.7dB
–60
–70
–80
–90
–100
–110
–120
–130
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (kHz)
1605 • TPC07
Total Harmonic Distortion vs
Input Frequency
SINAD vs Input Frequency
90
89
88
87
86
85
84
83
82
81
–70
–80
–90
–100
–110
1
10
100
1
10
100
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
1605 • TPC08
1605 • TPC09
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PIN FUNCTIONS
AGND2 (Pin 5): Analog Ground. Tie to analog ground
VIN (Pin 1): Analog Input. Connect through a 200Ω
resistor to the analog input. Full-scale input range is
±10V.
plane.
D15 to D8 (Pins 6 to 13): Three-State Data Outputs.
Hi-Z state when CS is high or when R/C is low.
AGND1 (Pin 2): Analog Ground. Tie to analog ground
plane.
DGND (Pin 14): Digital Ground.
REF (Pin 3): 2.5V Reference Output. Bypass with 2.2µF
tantalum capacitor. Can be driven with an external refer-
ence.
D7 to D0 (Pins 15 to 22): Three-State Data Outputs.
Hi-Z state when CS is high or when R/C is low.
BYTE (Pin 23): Byte Select. With BYTE low, data will be
output with Pin 6 (D15) being the MSB and Pin 22 (D0)
being the LSB. With BYTE high the upper eight bits and
the lower eight bits will be switched. The MSB is output
CAP (Pin 4): Reference Buffer Output. Bypass with 2.2µF
tantalum capacitor.
6
LTC1605
U
U
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PIN FUNCTIONS
on Pin 15 and bit 8 is output on Pin 22. Bit 7 is output on
BUSY (Pin 26): Output Shows Converter Status. It is low
when a conversion is in progress. Data valid on the rising
edge of BUSY. CS or R/C must be high when BUSY rises
or another conversion will start without time for signal
acquisition.
Pin 6 and the LSB is output on Pin 13.
R/C (Pin 24): Read/Convert Input. With CS low, a falling
edge on R/C puts the internal sample-and-hold into the
hold state and starts a conversion. With CS low, a rising
edge on R/C enables the output data bits.
V
ANA (Pin 27): 5V Analog Supply. Bypass to ground with
a 0.1µF ceramic and a 10µF tantalum capacitor.
CS (Pin 25): Chip Select. Internally OR’d with R/C. With
R/C low, a falling edge on CS will initiate a conversion.
With R/C high, a falling edge on CS will enable the output
data.
V
DIG (Pin 28): 5V Digital Supply. Connect directly to Pin
27.
TEST CIRCUITS
Load Circuit for Output Float Delay
Load Circuit for Access Timing
5V
5V
1k
1k
DBN
DBN
DBN
DBN
1k
C
C
L
1k
50pF
50pF
L
LTC1605 • TC02
LTC1605 • TC01
A. HI-Z TO V AND V TO V
B. HI-Z TO V AND V TO V
OL OH
A. V TO HI-Z
OH
B. V TO HI-Z
OL
OH
OL
OH
OL
U
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W
FUNCTIONAL BLOCK DIAGRA
C
SAMPLE
SAMPLE
20k
V
IN
V
V
ANA
DIG
10k
4k
C
ZEROING SWITCHES
4k
REF
2.5V REF
+
REF BUF
COMP
16-BIT CAPACITIVE DAC
–
CAP
(2.5V)
16
D15
D0
SUCCESSIVE APPROXIMATION
REGISTER
•
•
•
OUTPUT LATCHES
AGND1
AGND2
DGND
INTERNAL
CLOCK
CONTROL LOGIC
LTC1605 • BD
CS
R/C
BYTE
BUSY
7
LTC1605
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W U U
APPLICATIONS INFORMATION
Conversion Details
Driving the Analog Inputs
The LTC1605 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 16-bit or two byte parallel output. The
ADC is complete with a precision reference and an internal
clock. The control logic provides easy interface to micro-
processorsand DSPs. (Pleaserefertothe DigitalInterface
section for the data format.)
The nominal input range for the LTC1605 is ±10V or
(±4•VREF)andtheinputisovervoltageprotectedto±25V.
Theinputimpedanceistypically20kΩ,therefore,itshould
be driven with a low impedance source. Wideband noise
coupling into the input can be minimized by placing a
1000pF capacitor at the input as shown in Figure 2. An
NPO-type capacitor gives the lowest distortion. Place the
capacitor as close to the device input pin as possible. If an
amplifier is to be used to drive the input, care should be
takentoselectanamplifierwithadequateaccuracy,linear-
ity and noise for the application. The following list is a
summary of the op amps that are suitable for driving the
LTC1605. More detailed information is available in the
LinearTechnologydatabooksandLinearViewTM CD-ROM.
Conversion start is controlled by the CS and R/C inputs. At
the start of conversion the successive approximation
register(SAR)isreset. Onceaconversioncyclehasbegun
it cannot be restarted.
During the conversion, the internal 16-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, VIN is connected through the resistor divider to
the sample-and-hold capacitor during the acquire phase
andthecomparatoroffsetisnulledbytheautozeroswitches.
In this acquire phase, a minimum delay of 2µs will provide
enough time for the sample-and-hold capacitor to acquire
the analog signal. During the convert phase, the autozero
switches open, putting the comparator into the compare
mode. The input switch switches CSAMPLE to ground,
injecting the analog input charge onto the summing junc-
tion. This input charge is successively compared with the
binary-weighted charges supplied by the capacitive DAC.
Bit decisions are made by the high speed comparator. At
the end of a conversion, the DAC output balances the VIN
input charge. The SAR contents (a 16-bit data word) that
representstheVINareloadedintothe16-bitoutputlatches.
200Ω
A
IN
V
IN
1000pF
33.2k
CAP
1605 • F02
Figure 2. Analog Input Filtering
LT1007 - Low noise precision amplifier. 2.7mA supply
current ±5V to ±15V supplies. Gain bandwidth product
8MHz. DC applications.
LT1097 - Low cost, low power precision amplifier. 300µA
supply current. ±5V to ±15V supplies. Gain bandwidth
product 0.7MHz. DC applications.
LT1227-140MHzvideocurrentfeedbackamplifier. 10mA
supply current. ±5V to ±15V supplies. Low noise and low
distortion.
SAMPLE
SI
C
SAMPLE
R
SAMPLE
HOLD
LT1360 - 37MHz voltage feedback amplifier. 3.8mA sup-
ply current. ±5V to ±15V supplies. Good AC/DC specs.
IN1
V
–
+
IN
R
IN2
LT1363 - 50MHz voltage feedback amplifier. 6.3mA sup-
ply current. Good AC/DC specs.
C
V
DAC
DAC
COMPARATOR
DAC
S
A
R
LT1364/LT1365 - Dual and quad 50MHz voltage feedback
amplifiers. 6.3mA supply current per amplifier. Good AC/
DC specs.
16-BIT
LATCH
1605 • F01
Figure 1. LTC1605 Simplified Equivalent Circuit
LinearView is a trademark of Linear Technology Corporation
8
LTC1605
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APPLICATIONS INFORMATION
applied to VIN and R4 is adjusted until the output code is
changing between 0111 1111 1111 1110 and 0111 1111
1111 1111. Figure 6 shows the bipolar transfer character-
istic of the LTC1605.
Internal Voltage Reference
The LTC1605 has an on-chip, temperature compensated,
curvature corrected, bandgap reference, which is factory
trimmed to 2.50V. The full-scale range of the ADC is equal
to (±4 • VREF) or nominally ±10V. The output of the
reference is connected to the input of a unity-gain buffer
through a4k resistor (seeFigure 3). The inputto the buffer
or the output of the reference is available at REF (Pin 3).
The internal reference can be overdriven with an external
reference if more accuracy is needed. The buffer output
drives the internal DAC and is available at CAP (Pin 4). The
CAP pin can be used to drive a steady DC load of less than
2mA. Driving an AC load is not recommended because it
can cause the performance of the converter to degrade.
1
V
±10V INPUT
IN
2
200Ω
1%
AGND1
2.2µF
+
LTC1605
33.2k
1%
3
4
REF
CAP
+
2.2µF
5
AGND2
1605 • F04
Figure 4. ±10V Input Without Trim
1
V
±10V INPUT
4k
IN
3
REF
(2.5V)
BANDGAP
2
200Ω
AGND1
REFERENCE
1%
2.2µF
V
ANA
2.2µF
+
+
+
–
3
33.2k
1%
REF
5V
LTC1605
576k
R4
50k
4
5
4
CAP
(2.5V)
CAP
R3
50k
2.2µF
INTERNAL
CAPACITOR
DAC
2.2µF
AGND2
1605 • F05
1605 • F03
Figure 5. ±10V Input with Offset and Gain Trim
Figure 3. Internal or External Reference Source
011...111
For minimum code transition noise the REF pin and the
CAP pin should each be decoupled with a capacitor to
filter wideband noise from the reference and the buffer
(2.2µF tantalum).
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
Offset and Gain Adjustments
100...001
100...000
TheLTC1605offsetandfull-scaleerrorshavebeentrimmed
at the factory with the external resistors shown in Figure 4.
This allows for external adjustment of offset and full scale
in applications where absolute accuracy is important. See
Figure 5 for the offset and gain trim circuit. First adjust the
offset to zero by adjusting resistor R3. Apply an input
voltage of –152.6mV (–0.5LSB) and adjust R3 so the code
ischangingbetween1111111111111111and00000000
00000000. Thegainerroristrimmedbyadjusting resistor
R4. An input voltage of 9.999542V (+FS – 1.5LSB) is
FS = 20V
1LSB = FS/65536
–1 0V
1
LSB
–FS/2
FS/2 – 1LSB
LSB
INPUT VOLTAGE (V)
1605 • F06
Figure 6. LTC1605 Bipolar Transfer Characteristics
DC Performance
Onewayofmeasuringthetransitionnoiseassociatedwith
a high resolution ADC is to use a technique where a DC
9
LTC1605
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APPLICATIONS INFORMATION
signal is applied to the input of the ADC and the resulting
output codes are collected over a large number of conver-
sions. For example in Figure 7 the distribution of output
code is shown for a DC input that has been digitized 10000
times. The distribution is Gaussian and the RMS code
transition is about 1LSB.
Timing and Control
Conversion start and data read are controlled by two
digital inputs: CS and R/C. To start a conversion and put
the sample-and-hold into the hold mode bring CS and
R/C low for no less than 40ns. Once initiated it cannot be
restarted until the conversion is complete. Converter
statusisindicatedbytheBUSYoutputandthisislowwhile
the conversion is in progress.
4500
4000
3500
3000
2500
2000
1500
1000
500
Therearetwomodesofoperation.Thefirstmodeisshown
in Figure 8. The digital input R/C is used to control the start
of conversion. CS is tied low. When R/C goes low the
sample-and-hold goes into the hold mode and a conver-
sion is started. BUSY goes low and stays low during the
conversion and will go back high after the conversion has
been completed and the internal output shift registers
havebeenupdated.R/Cshouldremainlowfornolessthan
40ns. During the time R/C is low the digital outputs are in
a Hi-Z state. R/C should be brought back high within 3µs
after the start of the conversion to ensure that no errors
occur in the digitized result. The second mode, shown in
Figure 9, uses the CS signal to control the start of a
conversion and the reading of the digital output. In this
mode the R/C input signal should be brought low no less
than 10ns before the falling edge of CS. The minimum
pulse width for CS is 40ns. When CS falls, BUSY goes low
and will stay low until the end of the conversion. BUSY will
go high after the conversion has been completed. The new
data is valid when CS is brought back low again to initiate
0
–5 –4 –3 –2 –1
0
1
2
3
4
5
CODE
1605 • F07
Figure 7. Histogram for 10000 Conversions
DIGITAL INTERFACE
Internal Clock
The ADC has an internal clock that is trimmed to achieve
a typical conversion time of 7µs. No external adjustments
are required and, with the typical acquisition time of 1µs,
throughput performance of 100ksps is assured.
t
1
R/C
t
11
t
2
t
4
t
3
BUSY
MODE
t
t
6
5
ACQUIRE
CONVERT
ACQUIRE
CONVERT
HI-Z
t
t
ACQ
CONV
t
9
PREVIOUS
DATA VALID
PREVIOUS
DATA VALID
DATA
VALID
DATA
VALID
HI-Z
NOT VALID
DATA MODE
1605 • F08
t
t
7
8
Figure 8. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low)
10
LTC1605
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APPLICATIONS INFORMATION
t
t
t
t
10
10
10
10
R/C
CS
t
t
1
1
t
3
t
4
BUSY
MODE
t
6
ACQUIRE
CONVERT
ACQUIRE
t
CONV
HI-Z
HI-Z
DATA
VALID
DATA BUS
t
t
7
12
1605 • F09
Figure 9. Using CS to Control Conversion and Read Timing
t
t
10
10
R/C
CS
BYTE
HI-Z
HI-Z
HI-Z
HI-Z
PINS 6 TO 13
PINS 15 TO 22
HIGH BYTE
LOW BYTE
LOW BYTE
HIGH BYTE
t
t
t
7
12
12
1605 • F03
Figure 10. Using CS and BYTE to Control Data Bus Read Timing
0
–10
–20
–30
–40
f
=
100kHz
SAMPLE
IN
f = 1kHz
SINAD = 87.5dB
THD = –101.7dB
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (kHz)
1605 • F11
Figure 11. LTC1605 Nonaveraged 4096 Point FFT Plot
11
LTC1605
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APPLICATIONS INFORMATION
band between DC and half the sampling frequency. THD is
expressed as:
a read. Again it is recommended that both R/C and CS
return high within 3µs after the start of the conversion.
2
2
2
2
Output Data
√V2 + V3 + V4 ... + VN
THD = 20log
V1
The output data can be read as a 16-bit word or it can be
read as two 8-bit bytes. The format of the output data is
two’s complement. The digital input pin BYTE is used to
control the two byte read. With the BYTE pin low the first
eight MSBs are output on the D15 to D8 pins and the eight
LSBs are output on the D7 to D0 pins. When the BYTE pin
istakenhightheeightLSBsreplacetheeightMSBs(Figure
10).
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the
second through Nth harmonics.
Board Layout, Power Supplies and Decoupling
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1605, a printed circuit board is
required. Layout for the printed circuit board should
ensure the digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC. The analog input should be screened
by AGND.
Dynamic Performance
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 11 shows a
typical LTC1605 FFT plot which yields a SINAD of 87.5dB
and THD of –102dB.
Figures 12 through 15 show a layout for a suggested
evaluation circuit which will help obtain the best perfor-
mance from the 16-bit ADC. Pay particular attention to the
design of the analog and digital ground planes. The DGND
pin of the LTC1605 can be tied to the analog ground plane.
Placing the bypass capacitor as close as possible to the
power supply, the reference and reference buffer output is
very important. Low impedance common returns for
these bypass capacitors are essential to low noise opera-
tion of the ADC, and the foil width for these tracks should
beaswideaspossible. Also, sinceanypotentialdifference
in grounds between the signal source and ADC appears as
an error voltage in series with the input signal, attention
should be paid to reducing the ground circuit impedance
as much as possible. The digital output latches and the
onboard sampling clock have been placed on the digital
ground plane. The two ground planes are tied together at
the power supply ground connection.
Signal-to-Noise Ratio
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure 11 shows a typical SINAD of 87.5dB
with a 100kHz sampling rate and a 1kHz input.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
12
LTC1605
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APPLICATIONS INFORMATION
Figure 12. Component Side Silkscreen for the Suggested LTC1605 Evaluation Circuit
ANALOG
GROUND PLANE
DIGITAL
GROUND PLANE
ANALOG
GROUND PLANE
Figure 13. Bottom Side Showing Analog Ground Plane
Figure 14. Component Side Showing Separate Analog
and Digital Ground Plane
13
LTC1605
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APPLICATIONS INFORMATION
14
LTC1605
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.397 – 0.407*
(10.07 – 10.33)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
0.301 – 0.311
(7.65 – 7.90)
5
7
8
1
2
3
4
6
9 10 11 12 13 14
0.205 – 0.212**
(5.20 – 5.38)
0.068 – 0.078
(1.73 – 1.99)
0° – 8°
0.0256
(0.65)
BSC
0.005 – 0.009
(0.13 – 0.22)
0.022 – 0.037
(0.55 – 0.95)
0.002 – 0.008
(0.05 – 0.21)
0.010 – 0.015
(0.25 – 0.38)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
G28 SSOP 0694
N Package
28-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.370*
(34.789)
MAX
28 27 26 25 24
23 22 21 20
19 18 17 16 15
0.255 ± 0.015*
(6.477 ± 0.381)
1
2
3
4
5
6
7
8
9
10 11 12 13 14
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.020
(0.508)
MIN
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.125
(3.175)
MIN
0.005
(0.127)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
0.325
–0.015
+0.889
8.255
(
)
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
N28 1197
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC1605
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
SW Package
28-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.697 – 0.712*
(17.70 – 18.08)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.291 – 0.299**
(7.391 – 7.595)
2
3
5
7
8
9
10 11 12 13 14
1
4
6
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029
(0.254 – 0.737)
× 45°
0° – 8° TYP
0.050
(1.270)
TYP
0.004 – 0.012
(0.102 – 0.305)
0.009 – 0.013
NOTE 1
(0.229 – 0.330)
0.014 – 0.019
(0.356 – 0.482)
TYP
0.016 – 0.050
(0.406 – 1.270)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
S28 (WIDE) 0996
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
®
LT 1019-2.5
Precision Bandgap Reference
Low Power 12-Bit, 100ksps ADCs
Single 5V, 12-Bit, 1.25Msps ADC
Low Power 14-Bit, 800ksps ADC
Micropower Precision Series Reference
Micropower 4-/8-Channel 12-Bit ADCs
0.05% Max, 5ppm/°C Max
LTC1274/LTC1277
LTC1415
10mW Power Dissipation, Parallel/Byte Interface
55mW Power Dissipation, 72dB SINAD
LTC1419
True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation
0.075% Max, 10ppm/°C Max, Only 130µA Supply Current
Serial I/O, 3V and 5V Versions
LT1460-2.5
LTC1594/LTC1598
1605fa LT/TP 0598 2K REV A • PRINTED IN THE USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1997
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