LTC1662CN8#TRPBF [Linear]
IC SERIAL INPUT LOADING, 750 us SETTLING TIME, 10-BIT DAC, PDIP8, 0.300 INCH, LEAD FREE, PLASTIC, DIP-8, Digital to Analog Converter;
| 型号： | LTC1662CN8#TRPBF |
| 厂家： | 
Linear |
| 描述： | IC SERIAL INPUT LOADING, 750 us SETTLING TIME, 10-BIT DAC, PDIP8, 0.300 INCH, LEAD FREE, PLASTIC, DIP-8, Digital to Analog Converter 输入元件 光电二极管 转换器 |
| 文件： | 总16页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1662
Ultralow Power, Dual
10-Bit DAC in MSOP
Features
Description
Ultralow Power: 1.5µA (Typ) I per DAC Plus
The LTC®1662 is an ultralow power, fully buffered voltage
output,dual10-bitdigital-to-analogconverter(DAC).Each
DAC channel draws just 1.7µA (typ) total supply-plus-
reference operating current, yet is capable of supplying
DC output currents in excess of 1mA and reliably driving
capacitive loads of up to 1000pF. A programmable sleep
mode further reduces total operating current to 0.05µA.
n
CC
0.05µA Sleep Mode for Extended Battery Life
n
Tiny: Two 10-Bit DACs in an 8-Lead MSOP—
Half the Size of an SO-8
Wide 2.7V to 5.5V Supply Range
n
n
Double Buffered for Simultaneous DAC Updates
n
Rail-to-Rail Voltage Outputs Drive 1000pF
n
Reference Range Includes Supply for Ratiometric
Linear Technology’s proprietary, inherently monotonic
architecture provides excellent linearity and an exception-
ally small external form factor. The double-buffered input
logic provides simultaneous update capability and can be
usedtowritetotheDACswithoutinterruptingsleepmode.
0V to V Output
CC
n
Reference Input Impedance Is Code-Independent
(7.1MΩ Typ)—Eliminates External Buffers
3-Wire Serial Interface with Schmitt Trigger Inputs
Differential Nonlinearity: 0.75LSB Max
n
n
With its tiny operating current and exceptionally small
size, the LTC1662 is ideal for use in the most power-
constrained products. For most designs, there is no
perceptible impact on the power budget; the LTC1662
draws many times less current than even a trimpot,
while providing buffered, low impedance (0.5Ω typical,
applications
n
Mobile Communications
n
Portable Battery-Powered Instruments
n
Remote or Inaccessible Adjustments
V
= 5V) rail-to-rail outputs.
n
CC
Digitally Controlled Amplifiers and Attenuators
Factory or Field Calibration
n
The LTC1662 is pin and software compatible with the
LTC1661 dual, 60µA 10-bit DAC. It is available in 8-pin
MSOP and PDIP packages and is specified over the in-
dustrial temperature range.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Block Diagram
V
GND
7
V
V
OUT A
CC
OUT B
5
Total Supply-Plus-Reference
Operating Current
8
6
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.5V
4.5V
10-BIT
DAC A
10-BIT
DAC B
3.6V
V
= 2.7V
CC
CONTROL
LOGIC
ADDRESS
DECODER
V
= V
CC
REF
CODE = 1023
SHIFT REGISTER
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
1662 TA01b
1662 BD
1
2
3
4
CS/LD
SCK
SDI
REF
1662fa
1
LTC1662
aBsolute maximum ratings
(Note 1)
V
to GND ............................................... –0.3V to 7.5V
Operating Temperature Range
CC
Logic Inputs to GND ................................. –0.3V to 7.5V
, V , REF to GND......... –0.3V to (V + 0.3V)
LTC1662C ............................................... 0°C to 70°C
LTC1662I ............................................ –40°C to 85°C
Lead Temperature (Soldering, 10 sec).................. 300°C
V
OUT A OUT B
CC
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range ..................–65°C to 150°C
pin conFiguration
TOP VIEW
TOP VIEW
CS/LD
SCK
SDI
1
2
3
4
V
OUT A
8
7
6
5
CS/LD
SCK
SDI
1
2
3
4
8 V
OUT A
GND
7 GND
6 V
5 V
CC
V
CC
REF
OUT B
REF
V
OUT B
MS8 PACKAGE
8-LEAD PLASTIC MSOP
N8 PACKAGE
8-LEAD PLASTIC DIP
T
= 125°C, θ = 150°C/W
JA
JMAX
T
JMAX
= 125°C, θ = 100°C/W
JA
orDer inFormation
LEAD FREE FINISH
LTC1662CMS8#PBF
LTC1662IMS8#PBF
LTC1662CN8#PBF
LTC1662IN8#PBF
LEAD BASED FINISH
LTC1662CMS8
TAPE AND REEL
PART MARKING
LTKB
PACKAGE DESCRIPTION
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic DIP
TEMPERATURE RANGE
0°C to 70°C
LTC1662CMS8#TRPBF
LTC1662IMS8#TRPBF
LTC1662CN8#TRPBF
LTC1662IN8#TRPBF
TAPE AND REEL
LTKC
–40°C to 85°C
0°C to 70°C
LTC1662CN8
LTC1662IN8
PART MARKING
LTKB
8-Lead Plastic DIP
–40°C to 85°C
TEMPERATURE RANGE
0°C to 70°C
PACKAGE DESCRIPTION
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic DIP
LTC1662CMS8#TR
LTC1662IMS8#TR
LTC1662CN8#TR
LTC1662IMS8
LTKC
–40°C to 85°C
0°C to 70°C
LTC1662CN8
LTC1662CN8
LTC1662IN8
LTC1662IN8
LTC1662IN8#TR
8-Lead Plastic DIP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
1662fa
2
LTC1662
electrical characteristics The l denotes the specifications which apply over the full operating
temperature range (TA = TMIN to TMAX), otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded
unless otherwise noted.
SYMBOL PARAMETER
Accuracy
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
l
l
Resolution
10
10
Bits
Bits
Monotonicity
(Note 2)
(Note 2)
(Note 2)
DNL
INL
Differential Nonlinearity
0.12
0.8
5
0.75
4
LSB
Integral Nonlinearity
Offset Error
LSB
V
OS
V
OS
V
V
V
= 5V, V = 4.096V, Measured at Code 20
25
mV
CC
REF
TC
V
Temperature Coefficient
15
µV/°C
LSB
OS
l
GE
Gain Error
= 5V, V = 4.096V
1
8
CC
REF
GE TC
PSR
Gain Error Temperature Coefficient
Power Supply Rejection
12
µV/°C
LSB/V
= 2.5V
0.18
REF
Reference Input
Input Voltage Range
l
l
0
V
V
CC
Input Resistance
Active Mode
Sleep Mode
3.9
7.1
2.5
MΩ
GΩ
Input Capacitance
10
pF
Power Supply
l
V
Positive Supply Voltage
Supply Current
For Specified Performance
2.7
5.5
V
CC
I
CC
V
V
V
V
= 3V (Note 3)
= 5V (Note 3)
= 3V (Note 3)
= 5V (Note 3)
3.0
3.5
4.0
4.5
5.0
5.5
µA
µA
µA
µA
CC
CC
CC
CC
l
l
Sleep Mode Operating Current
Supply Plus Reference Current, V = V = 5V (Note 3)
0.05
0.10
0.18
µA
µA
CC
REF
l
DC Performance
Short-Circuit Current Low
Short-Circuit Current High
AC Performance
l
l
V
V
= 0V, V = V = 5V, Code = 1023 (Note 7)
5
3
12
10
70
80
mA
mA
OUT
CC
REF
= V = V = 5V, Code = 0 (Note 7)
OUT
CC
REF
Voltage Output Slew Rate
Voltage Output Settling Time
Capacitive Load Driving
Rising (Notes 4, 5)
Falling (Notes 4, 5)
20
7
V/ms
V/ms
Rising 0.1V to 0.9V
0.5LSB (Notes 4, 5)
0.5LSB (Notes 4, 5)
0.40
0.75
ms
ms
FS
FS
FS
Falling 0.9V to 0.1V
FS
1000
pF
Digital I/O
l
l
V
Digital Input High Voltage
Digital Input Low Voltage
V
V
= 2.7V to 5.5V
= 2.7V to 3.6V
2.4
2.0
V
V
IH
CC
CC
l
l
V
IL
V
V
= 4.5V to 5.5V
= 2.7V to 5.5V
0.8
0.6
V
V
CC
CC
l
I
Digital Input Leakage
V
= GND to V
CC
0.05
1.5
1.0
µA
pF
LK
IN
C
Digital Input Capacitance
IN
1662fa
3
LTC1662
timing characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
16.7
10
UNITS
V
= 4.5V to 5.5V
CC
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
SDI Setup
Relative to SCK Positive Edge
Relative to SCK Positive Edge
(Note 6)
55
0
ns
ns
1
SDI Hold
2
SCK High Time
30
30
100
30
20
0
ns
3
SCK Low Time
(Note 6)
ns
4
CS/LD Pulse Width
LSB SCK High to CS/LD High
CS/LD Low to SCK High
SCK Low to CS/LD Low
CS/LD High to SCK Positive Edge
SCK Frequency
(Note 6)
ns
5
(Note 6)
ns
6
(Note 6)
ns
7
(Note 6)
ns
9
(Note 6)
20
ns
11
Square Wave (Note 6)
MHz
V
= 2.7V to 5.5V
CC
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
SDI Setup
Relative to SCK Positive Edge (Note 6)
75
0
ns
ns
1
SDI Hold
Relative to SCK Positive Edge (Note 6)
2
SCK High Time
(Note 6)
50
50
150
50
30
0
ns
3
SCK Low Time
(Note 6)
ns
4
CS/LD Pulse Width
LSB SCK High to CS/LD High
CS/LD Low to SCK High
SCK Low to CS/LD Low
CS/LD High to SCK Positive Edge
SCK Frequency
(Note 6)
ns
5
(Note 6)
ns
6
(Note 6)
ns
7
(Note 6)
ns
9
(Note 6)
30
ns
11
Square Wave (Note 6)
MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: Digital inputs at 0V or V .
CC
Note 4: Load is 10kΩ in parallel with 100pF.
Note 5: V = V = 5V. DAC switched between 0.1V and 0.9V ;
FS
CC
REF
FS
i.e., codes k = 102 and k = 922.
Note 6: Guaranteed by design, not subject to test.
Note 7: One DAC output loaded.
Note 2: Nonlinearity and monotonicity are defined and tested at V = 5V,
CC
V
REF
= 4.096V, from code 20 to code 1023. See Figure 2.
1662fa
4
LTC1662
typical perFormance characteristics
Total Supply-Plus-Reference
Operating Current
Supply Current
vs Clock Frequency
Supply Current vs Temperature
1000
100
10
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= V
CC
REF
CS/LD = LOGIC LOW
CODE = 1023
CODE = 0
5.5V
4.5V
5.5V
4.5V
V
CC
= 5V
3.6V
V
CC
= 2.7V
V
= 3V
CC
3.6V
V
CC
= 2.7V
V
= V
CC
REF
CODE = 1023
1
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
10 100 1k
10k 100k 1M 10M 100M
FREQUENCY (Hz)
TEMPERATURE (°C)
TEMPERATURE (°C)
1662 G03
1662 G01
1662 G02
Supply Current
vs Logic Input Voltage
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
0.75
0.60
4
3
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 5V
CC
ALL DIGITAL INPUTS
SHORTED TOGETHER
0.40
0.20
0
2
1
0
–1
–2
–3
–4
–0.20
–0.40
–0.60
–0.75
0
256
512
768
1023
0
256
512
768
1023
0
1.5
1
1.5
2
2.5
3
3.5
4
4.5
5
CODE
CODE
LOGIC INPUT VOLTAGE (V)
1662 G05
1662 G06
1662 G04
Integral Nonlinearity (INL)
vs Reference Voltage
Differential Nonlinearity (DNL)
vs Reference Voltage
Offset Voltage vs Temperature
4
0.75
0.50
0.25
0
0
–1
–2
–3
–4
–5
V
V
= 5V
REF
V
CC
= 5.5V
V
CC
= 5.5V
CC
= 4.096V
3
2
1
MAX POS DNL
MAX NEG DNL
MAX POS INL
MAX NEG INL
0
–1
–2
–3
–4
–0.25
–0.50
–0.75
0
1
2
3
4
5
6
0
1
2
3
4
5
6
–55 –35 –15
5
25 45 65 85 105
V
REF
(V)
V
REF
(V)
TEMPERATURE (°C)
1662 G07
1662 G08
1662 G09
1662fa
5
LTC1662
typical perFormance characteristics
Load Regulation vs Output
Current at 5V
Load Regulation vs Output
Current at 3V
Gain Error vs Temperature
1.0
0.8
0
–1
–2
–3
–4
–5
1.0
0.8
V
V
= V = 5V
CC
V
V
= 5V
REF
V
V
= V = 3V
CC
REF
OUT
CC
REF
OUT
= 2.5V
= 4.096V
= 1.5V
CODE = 512
= 25°C
CODE = 512
= 25°C
0.6
0.6
T
T
A
A
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
SOURCE
SINK
SOURCE
SINK
–5 –4 –3 –2 –1
I
0
(mA)
1
2
3
4
5
–55 –35 –15
5
25 45 65 85 105
–1 –0.8–0.6–0.4–0.2
I
0
0.2 0.4 0.6 0.8
1
TEMPERATURE (°C)
(mA)
OUT
OUT
1662 G11
1662 G10
1662 G12
Output Amplifier Current Sourcing
Capability (Mid-Scale)
Output Amplifier Current Sinking
Capability (Mid-Scale)
Max/Min Output Voltage vs Source/
Sink Output Current (VCC = 5V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= V
CC
V
REF
= V
CC
REF
CODE = 512
= 25°C
4.5 CODE = 512
= 25°C
CODE = 1023
T
T
A
A
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
V
V
= 5.5V
= 5V
= 4.5V
V
V
V
= 5.5V
= 5V
= 4.5V
CC
CC
CC
CC
CC
CC
V
A
= V
CC
REF
T
= 25°C
V
V
V
= 3.6V
= 3V
= 2.7V
V
V
V
= 3.6V
= 3V
= 2.7V
CC
CC
CC
CC
CC
CC
CODE = 0
1
10
100
1m
10m
100m
1µ
10µ
100µ
1m
10m
100m
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
OUTPUT SOURCE CURRENT (A)
OUTPUT SINK CURRENT (A)
OUTPUT SOURCE/SINK CURRENT (mA)
1662 G13
1662 G14
1662 G15
Max/Min Output Voltage vs Source/
Sink Output Current (VCC = 3V)
Output Minimum Series
Large-Signal Step Response
Resistance vs Load Capacitance
5
4
3
2
1
0
3.0
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
180
160
140
120
100
80
CODE = 1023
V
A
= V
CC
REF
T
= 25°C
60
40
CODE = 0
V
= V = 5V
CC
REF
20
10% TO 90% STEP
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
100p 1000p 0.01µ 0.1µ
1µ
10µ 100µ
OUTPUT SOURCE/SINK CURRENT (mA)
TIME (0.5ms/DIV)
CAPACITANCE (F)
1662 G16
1662 G17
1662 G18
1662fa
6
LTC1662
pin Functions
CS/LD (Pin 1): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
SDI into the register. When CS/LD is pulled high, SCK is
disabledandtheoperation(s)specifiedinthecontrolcode,
A3-A0, is (are) performed. CMOS and TTL compatible.
REF (Pin 4): Reference Voltage Input. 0V ≤ V ≤ V .
REF CC
V
,V
(Pin8,Pin5):DACAnalogVoltageOutputs.
OUTA OUTB
The output range is
1023
1024
0 ≤ VOUTA,VOUTB ≤ VREF
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
compatible.
V
(Pin 6): Supply Voltage Input. 2.7V ≤ V ≤ 5.5V.
CC
CC
SDI (Pin 3): Serial Interface Data Input. Input word data
on the SDI pin is shifted into the 16-bit register on the
rising edge of SCK. CMOS and TTL compatible.
GND (Pin 7): System Ground.
DeFinitions
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
twoadjacentcodes.TheDNLerrorbetweenanytwocodes
is calculated as follows:
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = V /1024
REF
Resolution (n): Defines the number of DAC output states
DNL = (∆V
– LSB)/LSB
n
OUT
(2 ) that divide the full-scale range. Resolution does not
where ∆V
is the measured voltage difference between
imply linearity.
OUT
two adjacent codes.
Voltage Offset Error (V ): Nominally, the voltage at the
OS
Full-Scale Error (FSE): The deviation of the actual full-
scale voltage from ideal. FSE includes the effects of offset
and gain errors (see Figure 2).
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Figure 2).
Gain Error (GE): The deviation from the slope of the ideal
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
DAC transfer function, expressed in LSBs at full-scale.
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (endpoint INL). Because the output cannot go
below zero, the linearity is measured between full-scale
and the lowest code which guarantees the output will be
greater than zero. The INL error at a given input code is
calculated as follows:
INL = [V
– V – (V – V )(code/1023)]/LSB
OS FS OS
OUT
where V
is the output voltage of the DAC measured at
OUT
the given input code.
1662fa
7
LTC1662
timing Diagram
t
1
t
6
t
2
t
t
4
3
SCK
t
9
t
11
SDI
A3
A2
A1
X1
X0
t
5
t
7
CS/LD
1662 TD
operation
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X1
X0
SDI
CONTROL CODE
INPUT CODE
INPUT WORD W
DON’T CARE
0
(INSTRUCTION
(SCK ENABLED)
CS/LD
1662 F01
EXECUTED)
Figure 1. Register Loading Sequence
1662fa
8
LTC1662
operation
Table 1. DAC Control Functions
CONTROL
INPUT REGISTER
DAC REGISTER
STATUS
POWER-DOWN STATUS
(SLEEP/WAKE)
A3 A2 A1 A0
STATUS
COMMENTS
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
No Change
Load DAC A
Load DAC B
No Change
Load DAC A
No Update
No Change
No Change
No Change
Wake
No Operation. Power-Down Status Unchanged
(Part Stays In Wake or Sleep Mode)
No Update
Load Input Register A with Data. DAC Outputs Unchanged.
Power-Down Status Unchanged
No Update
Load Input Register B with Data. DAC Outputs Unchanged.
Power-Down Status Unchanged
Update Outputs
Update Outputs
Load Both DAC Regs with Existing Contents of Input Regs.
Outputs Update. Part Wakes Up
Wake
Load Input Reg A. Load DAC Regs with New Contents of
Input Reg A and Existing Contents of Reg B. Outputs Update.
Part Wakes Up
1
0
1
0
Load DAC B
Update Outputs
Wake
Load Input Reg B. Load DAC Regs with Existing Contents of
Input Reg A and New Contents of Reg B. Outputs Update.
Part Wakes Up
1
1
1
1
1
1
0
1
1
1
0
1
No Change
No Change
No Update
No Update
Wake
Sleep
Wake
Part Wakes Up. Input and DAC Regs Unchanged.
DAC Outputs Reflect Existing Contents of DAC Regs
Part Goes to Sleep. Input and DAC Regs Unchanged.
DAC Outputs Set to High Impedance State
Load DACs A, B
with Same
10-Bit Code
Update Outputs
Load Both Input Regs. Load Both DAC Regs with New
Contents of Input Regs. Outputs Update. Part Wakes Up
Note: All control codes other than those shown are undefined and not subject to test.
Transfer Function
V
(Pin 6) is in transition. If it is not possible to sequence
CC
the supplies, clamp the voltage at REF by connecting a
SchottkydiodebetweenPin4(anode)andPin6(cathode).
The transfer function for the LTC1662 is:
k
VOUT(IDEAL)
=
V
REF
Serial Interface
1024
See Table 2. The 16-bit input word consists of the 4-bit
controlcode,the10-bitinputcodeandtwodon’t-carebits.
where k is the decimal equivalent of the binary DAC input
code D9-D0 and V is the voltage at REF (Pin 4).
REF
Table 2. LTC1662 Input Word
Power-On Reset
Input Word
The LTC1662 actively clears the outputs to zero-scale
when power is first applied, making system initialization
consistent and repeatable.
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0
Control Code
Input Code
Don’t
Care
Power Supply Sequencing
Aftertheinputwordisloadedintotheregister(seeFigure1),
it is internally converted from serial to parallel format. The
parallel 10-bit-wide input code data path is then buffered
by two latch registers.
The voltage at REF (Pin 4) should be kept within the range
–0.3V ≤ V
≤ V + 0.3V (see the Absolute Maximum
REF
CC
Ratings). Particular care should be taken during power
supplyturn-onandturn-offsequences,whenthevoltageat
1662fa
9
LTC1662
operation
The first of these, the input register, is used for loading
new input codes. The second buffer, the DAC register, is
used for updating the DAC outputs. Each DAC has its own
10-bit input register and 10-bit DAC register.
and 0010 ); then, a single command (1000 ) can be used
b b
both to wake the part and to update the output values.
Alternatively, one DAC may be loaded with a new input
code during sleep; then with just one command, the other
DAC is loaded, the part is awakened and both outputs are
updated.
Byselectingtheappropriate4-bitcontrolcode(seeTable1)
itispossibletoperformsingleoperations, suchasloading
one DAC or changing power-down status (sleep/wake).
In addition, some control codes perform two or more
operations at the same time. For example, one such code
loads DAC A, updates both outputs and Wakes the part
up. The DACs can be loaded separately or together, but
the outputs are always updated together.
For example, control code 0001 is used to load DAC A
b
duringsleep.Thencontrolcode0101 loadsDACB,wakes
b
the part and simultaneously updates both DAC outputs.
Voltage Outputs
Each of the rail-to-rail output amplifiers contained in
the LTC1662 can typically source or sink at least 1mA
Register Loading Sequence
(V = 5V). The outputs swing to within a few millivolts
CC
See Figure 1. With CS/LD held low, data on the SDI input
is shifted into the 16-bit shift register on the positive edge
of SCK. The 4-bit control code, A3-A0, is loaded first, then
the 10-bit input code, D9-D0, ordered MSB to LSB in each
case.Twodon’t-carebits,X1andX0,areloadedlast.When
the full 16-bit input word has been shifted in, CS/LD is
pulled high, causing the system to respond according to
Table 1. The clock is disabled internally when CS/LD is
high. Note: SCK must be low when CS/LD is pulled low.
of either supply when unloaded and have an equivalent
output resistance of 130Ω (typical) when driving a load to
therails.Theoutputamplifiersarestabledrivingcapacitive
loads of up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. Please
see the Output Minimum Resistance vs Load Capacitance
curve in the Typical Performance Characteristics section.
Rail-to-Rail Output Considerations
Sleep Mode
In any rail-to-rail DAC, the output swing is limited to volt-
ages within the supply range.
DAC control code 1110 is reserved for the special sleep
b
instruction (see Table 1). In this mode, static power
consumption is greatly reduced. The reference input and
analog outputs are set in a high impedance state and all
DAC settings are retained in memory so that when sleep
mode is exited, the outputs of DACs not updated by the
Wake command are restored to their last active state.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 2b.
Similarly, limiting can occur near full-scale when the REF
pin is tied to V . If V = V and the DAC full-scale error
CC
REF
CC
(FSE = V + GE) is positive, the output for the highest
OS
Sleep mode is initiated by performing a load sequence
codes limits at V as shown in Figure 2c. No full-scale
CC
using control code 1110 (the DAC input code D9-D0 is
b
limiting can occur if V is less than V – FSE.
REF
CC
ignored).
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
To save instruction cycles, the DACs may be prepared
with new input codes during sleep (control codes 0001
b
1662fa
10
LTC1662
operation
POSITIVE
FSE
V
REF
= V
CC
OUTPUT
VOLTAGE
INPUT CODE
(2c)
V
REF
= V
CC
OUTPUT
VOLTAGE
0
512
1023
INPUT CODE
(2a)
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
1662 F02
(2b)
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero-Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full-Scale When VREF = VCC
1662fa
11
LTC1662
typical applications
Micropower Trim Circuit with Coarse/Fine Adjustment. Total Supply Current Is 9.5µA
3.3V
0.1µF
R2
1.1M
R1
11k
3.3V
6
0.1µF
2
3.3V
8
1
2.5V
0.1µF
LTC1258-2.5
4
REF
V
CC
4
2
3
–
+
R1
COARSE
11k
1
LT1495
4
V
OUT
8
DAC A
V
OUT A
0.1µF
1
3
2
CS/LD
SDI
LTC1662
U1
R2
FINE
1.1M
CODE A R1 CODEB
SCK
VOUT = VREF
+
•
1024
R2 1024
5
DAC B
V
OUT B
CODE A
1024
1
CODEB
100 1024
= 2.5V
+
•
1662 TA02
7
GND
Using the LTC1258 and the LTC1662 in a Portable Application
Powered by a Single Li-Ion Battery. Total Supply Current Is 8.2µA
Li-Ion BATTERY INPUT
V
≥ 4.3V
IN
0.1µF
0.1µF
6
2
V
CC
1
4
3
2
1
8
0V TO 4.096V
(4mV/BIT)
LTC1258-4.1
4
REF
SDI
SCK
V
OUT A
4.096V
LTC1662
5
0V TO 4.096V
(4mV/BIT)
CS/LD
V
OUT B
GND
7
1662 TA03
1662fa
12
LTC1662
package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.52
(.0205)
REF
8
7 6 5
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
0.889 ± 0.127
(.035 ± .005)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
5.23
(.206)
MIN
1
2
3
4
3.20 – 3.45
(.126 – .136)
0.53 ± 0.152
(.021 ± .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.007)
0.65
(.0256)
BSC
0.42 ± 0.038
(.0165 ± .0015)
SEATING
PLANE
TYP
0.22 – 0.38
0.1016 ± 0.0508
RECOMMENDED SOLDER PAD LAYOUT
(.009 – .015)
(.004 ± .002)
0.65
(.0256)
BSC
TYP
NOTE:
MSOP (MS8) 0307 REV F
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
1662fa
13
LTC1662
package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
N Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510 Rev I)
.400*
(10.160)
MAX
8
7
6
5
4
.255 ± .015*
(6.477 ± 0.381)
1
2
3
.130 ± .005
.300 – .325
.045 – .065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
.065
(1.651)
TYP
.008 – .015
(0.203 – 0.381)
.120
.020
(0.508)
MIN
(3.048)
MIN
+.035
.325
–.015
.018 ± .003
(0.457 ± 0.076)
.100
(2.54)
BSC
+0.889
8.255
N8 REV I 0711
(
)
–0.381
NOTE:
INCHES
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
1662fa
14
LTC1662
revision history
REV
DATE
DESCRIPTION
PAGE NUMBER
A
01/12 Removed Typical values in the Timing Characteristics section.
Corrected Related Parts listing for the LTC1659.
4
16
1662fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC1662
typical application
Ultralow Power DAC Optimizes Mixer Performance
3.3V
0.1µF
3.3V
6
0.1µF
2
I
I
P
LO
1
2.5V
LTC1258-2.5
V
4
REF
CC
4
3.9k
3.9k
0.1%
0.1%
560k
3.9k, 0.1%
8
DAC A
V
OUT A
3.9k
0.1%
1
CS/LD
I
I
P
I + Q
MIXER
3
LO
RF
LTC1662
DAC B
SDI
Q
Q
P
2
SCK
3.9k
0.1%
560k
3.9k, 0.1%
5
V
OUT B
3.9k
0.1%
3.9k
0.1%
1662 TA04
7
GND
Q
Q
Q
P
relateD parts
PART NUMBER
LTC1661
DESCRIPTION
COMMENTS
Dual 10-Bit V
DAC in 8-Lead MSOP Package
V
V
V
V
= 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
= 2.7V to 5.5V, Internal Reference, 60µA
OUT
CC
CC
CC
CC
LTC1663
Single 10-Bit V
DAC with 2-Wire Interface in SOT-23 Package
OUT
LTC1664
Quad 10-Bit V
DAC in 16-Pin Narrow SSOP
= 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
= 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
OUT
LTC1665/LTC1660
Octal 8-/10-Bit V
DAC in 16-Pin Narrow SSOP
OUT
LTC1446/LTC1446L Dual 12-Bit V
DACs in SO-8 Package with Internal Reference
DAC in SO-8 Package
LTC1446: V = 4.5V to 5.5V, V
= 0V to 4.095V
OUT
CC
OUT
LTC1446L: V = 2.7V to 5.5V, V
= 0V to 2.5V
OUT
CC
LTC1448
Dual 12-Bit V
V
= 2.7V to 5.5V, External Reference Can Be Tied to V
CC
OUT
OUT
CC
LTC1454/LTC1454L Dual 12-Bit V
DACs in SO-16 Package with Added Functionality LTC1454: V = 4.5V to 5.5V, V
= 0V to 4.095V
= 0V to 2.5V
OUT
CC
OUT
LTC1454L: V = 2.7V to 5.5V, V
CC
LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: V = 4.5V to 5.5V, V
= 0V to 4.095V
CC
OUT
LTC1458L: V = 2.7V to 5.5V, V
= 0V to 2.5V
OUT
CC
LTC1659
Single Rail-to-Rail 12-Bit V
DAC in 8-Lead MSOP Package
V
= 2.7V to 5.5V, Low Power Multiplying V DAC. Output
OUT
OUT
CC
Swings from GND to REF. REF Input Can Be Tied to V
CC
1662fa
LT 0112 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
LINEAR TECHNOLOGY CORPORATION 2000
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LTC1662IMS8#TR
LTC1662 - Ultralow Power, Dual 10-Bit DAC in MSOP; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C
Linear
LTC1662IN8#PBF
LTC1662 - Ultralow Power, Dual 10-Bit DAC in MSOP; Package: PDIP; Pins: 8; Temperature Range: -40°C to 85°C
Linear
LTC1662IN8#TR
IC SERIAL INPUT LOADING, 750 us SETTLING TIME, 10-BIT DAC, PDIP8, 0.300 INCH, PLASTIC, DIP-8, Digital to Analog Converter
Linear
LTC1662IN8#TRPBF
IC SERIAL INPUT LOADING, 750 us SETTLING TIME, 10-BIT DAC, PDIP8, 0.300 INCH, LEAD FREE, PLASTIC, DIP-8, Digital to Analog Converter
Linear
LTC1663-1CS5
LTC1663 - 10-Bit Rail-to-Rail Micropower DAC with 2-Wire Interface; Package: SOT; Pins: 5; Temperature Range: 0°C to 70°C
Linear
©2020 ICPDF网 联系我们和版权申明