LTC1662IN8 [Linear]
Ultralow Power, Dual 10-Bit DAC in MSOP; 超低功耗，双通道10位DAC ，采用MSOP
| 型号： | LTC1662IN8 |
| 厂家： | 
Linear |
| 描述： | Ultralow Power, Dual 10-Bit DAC in MSOP |
| 文件： | 总12页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Final Electrical Specifications
LTC1662
Ultralow Power, Dual
10-Bit DAC in MSOP
March 2000
U
DESCRIPTIO
FEATURES
The LTC®1662 is an ultralow power, fully buffered volt-
ageoutput,dual10-bitdigital-to-analogconverter(DAC).
Each DAC draws just 1.7µA (typ) total supply-plus-
reference operating current, yet is capable of supplying
DC output currents in excess of 1mA and reliably driving
capacitive loads of up to 1000pF. A programmable Sleep
mode further reduces total operating current to a negli-
gible 0.05µA.
■
Ultralow Power: 1.5µA (Typ) ICC per DAC Plus
0.05µA Sleep Mode for Extended Battery Life
■
Tiny: Two 10-Bit DACs in an 8-Lead MSOP—
Half the Size of an SO-8
Wide 2.7V to 5.5V Supply Range
■
■
Double Buffered for Simultaneous DAC Updates
■
Rail-to-Rail Voltage Outputs Drive 1000pF
■
Reference Range Includes Supply for Ratiometric
0V-to-VCC Output
Linear Technology’s proprietary, inherently monotonic
voltage interpolation architecture provides excellent lin-
earity while allowing for an exceptionally small external
form factor. The double-buffered input logic provides
simultaneousupdatecapabilityandcanbeusedtowriteto
either DAC without interrupting Sleep mode.
■
Reference Input Impedance Is Code-Independent
(7.1MΩ Typ)—Eliminates External Buffers
■
3-Wire Serial Interface with
Schmitt Trigger Inputs
■
Differential Nonlinearity: ±0.75LSB Max
U
With its ultralow operating current and exceptionally
small size, the LTC1662 is ideal for use in battery-
powered products.
APPLICATIO S
■
Mobile Communications
■
The LTC1662 is pin- and software-compatible with the
LTC1661 micropower dual 10-bit DAC. It is available in
8-pin MSOP and PDIP packages and is specified over the
Portable Battery-Powered Instruments
■
Remote Industrial Devices
■
Digitally Controlled Amplifiers and Attenuators
■
industrial temperature range.
Automatic Calibration for Manufacturing
, LTC and LT are registered trademarks of Linear Technology Corporation.
W
BLOCK DIAGRA
V
GND
V
V
OUT A
CC
OUT B
5
Total Supply-Plus-Reference
Operating Current
8
7
6
5.5
5.0
4.5
4.0
3.5
3.0
2.5
V
A
= V
CC
REF
T
= 25°C
10-BIT
DAC A
10-BIT
DAC B
CODE = 1023
CODE = 512
CONTROL
LOGIC
ADDRESS
DECODER
CODE = 0
SHIFT REGISTER
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
CC
1662 G01
1
2
3
4
CS/LD
SCK
D
REF
IN
1662 BD
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
1
LTC1662
W W W
U
ABSOLUTE AXI U RATI GS
(Note 1)
VCC to GND .............................................. –0.3V to 7.5V
Logic Inputs to GND ................................ –0.3V to 7.5V
VOUT A, VOUT B, REF to GND ......... –0.3V to (VCC + 0.3V)
Maximum Junction Temperature ......................... 125°C
Storage Temperature Range ................ –65°C to 150°C
Operating Temperature Range
LTC1662C ............................................. 0°C to 70°C
LTC1662I........................................... –40°C to 85°C
Lead Temperature (Soldering, 10 sec)................ 300°C
W
U
/O
PACKAGE RDER I FOR ATIO
ORDER PART
ORDER PART
TOP VIEW
NUMBER
NUMBER
TOP VIEW
CS/LD
SCK
1
2
3
4
V
OUT A
8
7
6
5
CS/LD
SCK
1
2
3
4
8 V
OUT A
GND
LTC1662CMS8
LTC1662IMS8
LTC1662CN8
LTC1662IN8
7 GND
6 V
5 V
D
IN
D
IN
V
CC
CC
REF
OUT B
REF
V
OUT B
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING
N8 PACKAGE
8-LEAD PLASTIC DIP
TJMAX = 125°C, θJA = 150°C/W
LTKB
LTKC
TJMAX = 125°C, θJA = 100°C/W
Consult factory for Military grade parts.
The ● denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range (TA = TMIN to TMAX), otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT Unloaded
unless otherwise noted.
SYMBOL PARAMETER
Accuracy
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
●
●
●
●
●
10
10
Bits
Bits
Monotonicity
(Note 2)
(Note 2)
(Note 2)
DNL
INL
Differential Nonlinearity
±0.12
±0.8
±5
±0.75
±4
LSB
Integral Nonlinearity
Offset Error
LSB
V
V
V
= 5V, V = 4.096V, Measured at Code 20
±25
mV
OS
OS
CC
REF
TC
V
Temperature Coefficient
±15
±1
µV/°C
LSB
OS
GE
Gain Error
V
= 5V, V = 4.096V
●
±8
CC
REF
GE TC
Gain Error Temperature
Coefficient
±12
µV/°C
PSR
Power Supply Rejection
V
= 2.5V
0.18
LSB/V
REF
Reference Input
Input Voltage Range
●
●
0
V
CC
V
Input Resistance
Active Mode
Sleep Mode
3.9
7.1
2.5
MΩ
GΩ
Input Capacitance
10
pF
2
LTC1662
The ● denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range (TA = TMIN to TMAX), otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT Unloaded
unless otherwise noted.
SYMBOL PARAMETER
Power Supply
CONDITIONS
MIN
TYP
MAX
UNITS
V
Positive Supply Voltage
Supply Current
For Specified Performance
●
2.7
5.5
V
CC
I
V
V
V
V
= 3V (Note 3)
= 5V (Note 3)
= 3V (Note 3)
= 5V (Note 3)
3.0
3.5
4.0
4.5
5.0
5.5
µA
µA
µA
µA
CC
CC
CC
CC
CC
●
●
Sleep Mode Operating Current Supply Plus Reference Current, V = V
= 5V, (Note 3)
REF
0.05
0.10
0.18
µA
µA
CC
●
DC Performance
Short-Circuit Current Low
Short-Circuit Current High
AC Performance
Voltage Output Slew Rate
V
V
= 0V, V = V = 5V, Code = 1023 (Note 7)
●
●
5
3
12
10
70
80
mA
mA
OUT
OUT
CC
REF
= V = V
= 5V, Code = 0 (Note 7)
REF
CC
Rising (Notes 4, 5)
Falling (Notes 4, 5)
20
7
V/ms
V/ms
Voltage Output Settling Time 0.1V to 0.9V ±0.5LSB (Notes 4, 5)
0.40
0.75
ms
ms
FS
FS
0.9V to 0.1V ±0.5LSB (Notes 4, 5)
FS
FS
Capacitive Load Driving
1000
pF
Digital I/O
V
Digital Input High Voltage
Digital Input Low Voltage
V
V
= 2.7V to 5.5V
= 2.7V to 3.6V
●
●
2.4
2.0
V
V
IH
CC
CC
V
V
V
= 4.5V to 5.5V
= 2.7V to 5.5V
●
●
0.8
0.6
V
V
IL
CC
CC
I
Digital Input Leakage
V
= GND to V
CC
●
±0.05
±1.0
µA
LK
IN
C
Digital Input Capacitance
(Note 6)
1.5
pF
IN W U
The ● denotes the specifications which apply over the full operating temperature
TI I G CHARACTERISTICS
range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
= 4.5V to 5.5V
CC
t
t
t
t
t
t
t
t
t
D
D
Valid to SCK Setup
Valid to SCK Hold
●
●
●
●
●
●
●
●
●
●
55
0
15
–10
14
14
27
2
ns
ns
1
IN
IN
2
SCK High Time
(Note 6)
30
30
100
30
20
0
ns
3
SCK Low Time
(Note 6)
ns
4
CS/LD Pulse Width
(Note 6)
ns
5
LSB SCK High to CS/LD High
CS/LD Low to SCK High
SCK Low to CS/LD Low
CS/LD High to SCK Positive Edge
SCK Frequency
(Note 6)
ns
6
(Note 6)
–21
–5
0
ns
7
(Note 6)
ns
9
(Note 6)
20
ns
11
Square Wave (Note 6)
16.7
MHz
V
= 2.7V to 5.5V
CC
t
t
t
t
D
Valid to SCK Setup
(Note 6)
(Note 6)
(Note 6)
(Note 6)
●
●
●
●
75
0
20
–10
15
ns
ns
ns
ns
1
IN
IN
D
Valid to SCK Hold
2
3
4
SCK High Time
SCK Low Time
50
50
15
3
LTC1662
W U
The ● denotes the specifications which apply over the full operating temperature
TI I G CHARACTERISTICS
range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
(Note 6)
MIN
150
50
TYP
30
3
MAX
UNITS
ns
t
t
t
t
t
CS/LD Pulse Width
●
●
●
●
●
●
5
LSB SCK High to CS/LD High
CS/LD Low to SCK High
SCK Low to CS/LD Low
CS/LD High to SCK Positive Edge
SCK Frequency
(Note 6)
ns
6
(Note 6)
30
–14
–5
0
ns
7
(Note 6)
0
ns
9
(Note 6)
30
ns
11
Square Wave (Note 6)
10
MHz
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 4: Load is 10kΩ in parallel with 100pF.
Note 5: V = V = 5V. DAC switched between 0.1V and 0.9V ; i.e.,
CC
REF
FS
FS
Note 2: Nonlinearity and monotonicity are defined and tested at V = 5V,
codes k = 102 and k = 922.
CC
V
= 4.096V, from code 20 to code 1023. See Figure 2.
REF
Note 6: Guaranteed by design, not subject to test.
Note 7: One DAC output loaded.
Note 3: Digital inputs at 0V or V
.
CC
W U
W
TI I G DIAGRA
t
1
t
t
t
t
4
6
2
3
SCK
t
t
11
9
D
IN
A1
X1
A3
A2
X0
t
t
7
5
CS/LD
1662 TD
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
0.75
0.60
4
3
0.40
0.20
2
1
0
0
–0.20
–0.40
–0.60
–0.80
–1
–2
–3
–4
0
256
512
768
1023
0
256
512
768
1023
CODE
CODE
1662 G03
1662 G02
4
LTC1662
U
OPERATIO
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X1
X0
D
IN
CONTROL CODE
INPUT CODE
INPUT WORD W
DON’T CARE
0
(INSTRUCTION
(SCK ENABLED)
CS/LD
1662 F01
EXECUTED)
Figure 1. Register Loading Sequence
Table 1. DAC Control Functions
CONTROL
INPUT REGISTER
DAC REGISTER
STATUS
POWER-DOWN STATUS
(SLEEP/WAKE)
A3 A2 A1 A0
STATUS
COMMENTS
0
0
0
0
0
0
0
0
1
0
1
0
No Change
No Update
No Update
No Update
No Change
No Change
No Change
No Operation. Power-Down Status Unchanged
(Part Stays In Wake or Sleep Mode)
Load DAC A
Load DAC B
Load Input Register A with Data. DAC Outputs
Unchanged. Power-Down Status Unchanged
Load Input Register B with Data. DAC Outputs
Unchanged. Power-Down Status Unchanged
0
0
0
0
0
1
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
No Change
Load DAC A
Update Outputs
Wake
Wake
Load Both DAC Regs with Existing Contents of Input
Regs. Outputs Update. Part Wakes Up
1
1
0
0
0
1
1
0
Update Outputs
Update Outputs
Load Input Reg A. Load DAC Regs with New Contents
of Input Reg A and Existing Contents of Reg B. Outputs
Update. Part Wakes Up
Load DAC B
Wake
Load Input Reg B. Load DAC Regs with Existing Contents
of Input Reg A and New Contents of Reg B. Outputs
Update. Part Wakes Up
1
1
1
0
1
1
1
0
0
1
0
1
Reserved
Reserved
No Change
No Change
No Update
Wake
Sleep
Wake
Part Wakes Up. Input and DAC Regs Unchanged. DAC
Outputs Reflect Existing Contents of DAC Regs
1
1
1
1
1
1
0
1
No Update
Part Goes to Sleep. Input and DAC Regs Unchanged. DAC
Outputs Set to High Impedance State
Load DACs A, B
with Same
Update Outputs
Load Both Input Regs. Load Both DAC Regs with New
Contents of Input Regs. Outputs Update. Part Wakes Up
10-Bit Code
5
LTC1662
U
U
U
PI FU CTIO S
CS/LD (Pin 1): Serial Interface Chip Select/Load Input.
WhenCS/LDislow, SCKisenabledforshiftingdataonDIN
into the register. When CS/LD is pulled high, SCK is
disabled and the operation(s) specified in the Control
code, A3-A0, is (are) performed. CMOS and TTL compat-
ible.
REF (Pin 4): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
V
OUT A, VOUT B (Pins 8,5): DAC Analog Voltage Outputs.
The output range is
1023
1024
0 ≤ VOUTA,VOUTB ≤ VREF
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
VCC (Pin 6): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
GND (Pin 7): System Ground.
compatible.
DIN (Pin 3): Serial Interface Data Input. Input word data on
the DIN pin is shifted into the 16-bit register on the rising
edge of SCK. CMOS and TTL compatible.
U
U
DEFI ITIO S
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
twoadjacentcodes.TheDNLerrorbetweenanytwocodes
is calculated as follows:
INL = [VOUT – VOS – (VFS – VOS)(code/1023)]/LSB
where VOUT is the output voltage of the DAC measured at
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
DNL = (∆VOUT – LSB)/LSB
where ∆VOUT is the measured voltage difference between
two adjacent codes.
LSB = VREF/1024
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Full-Scale Error (FSE): The deviation of the actual full-
scale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
Gain Error (GE): The deviation from the slope of the ideal
DAC transfer function, expressed in LSBs at full scale.
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve(EndpointINL).Becausetheoutputcannotgobelow
zero, the linearity is measured between full scale and the
lowest code which guarantees the output will be greater
than zero. The INL error at a given input code is calculated
as follows:
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
6
LTC1662
U
OPERATIO
Transfer Function
In addition, some Control codes perform two or more
operations at the same time. For example, one such code
loads DAC A, updates both outputs and Wakes the part up.
The DACs can be loaded separately or together, but the
outputs are always updated together.
The transfer function for the LTC1662 is:
k
VOUT(IDEAL)
=
VREF
1024
Register Loading Sequence
where k is the decimal equivalent of the binary DAC input
code D9-D0 and VREF is the voltage at REF (Pin 6).
See Figure 1. With CS/LD held low, data on the DIN input
isshiftedintothe16-bitShiftRegisteronthepositiveedge
of SCK. The 4-bit Control code, A3-A0, is loaded first, then
the10-bitInputcode,D9-D0,orderedMSB-to-LSBineach
case. Two don’t-care bits, X1 and X0, are loaded last.
When the full 16-bit Input word has been shifted in, CS/LD
ispulledhigh, causingthesystemtorespondaccordingto
Table 2. The clock is disabled internally when CS/LD is
high. Note: SCK must be low when CS/LD is pulled low.
Power-On Reset
The LTC1662 positively clears the outputs to zero scale
when power is first applied, making system initialization
consistent and repeatable.
Power Supply Sequencing
The voltage at REF (Pin 4) should be kept within the range
–0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum
Ratings). Particular care should be taken during power
supply turn-on and turn-off sequences, when the voltage
at VCC (Pin 6) is in transition.
Sleep Mode
DAC control code 1110b is reserved for the special Sleep
instruction (see Table 2). In this mode, the digital circuits
remainactivewhiletheanalogsectionsaredisabled;static
power consumption is greatly reduced. The reference
input and analog outputs are set in a high impedance state
and all DAC settings are retained in memory so that when
Sleep mode is exited, the outputs of DACs not updated by
the Wake command are restored to their last active state.
Serial Interface
See Table 1. The 16-bit Input word consists of the 4-bit
Controlcode,the10-bitInputcodeandtwodon’t-carebits.
Table 1. LTC1662 Input Word
Input Word
Sleep mode is initiated by performing a load sequence
using control code 1110b (the DAC input code D9-D0 is
ignored).
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0
Control Code
Input Code
Don’t
Care
Tosaveinstructioncycles, theDACsmaybepreparedwith
new input codes during Sleep (control codes 0001b and
0010b); then, a single command (1000b) can be used both
to wake the part and to update the output values.
AftertheInputwordisloadedintotheregister(seeFigure 1),
it is internally converted from serial to parallel format. The
parallel 10-bit-wide Input code data path is then buffered
by two latch registers.
Alternatively, one DAC may be loaded with a new input
code during Sleep; then with just one command, the other
DAC is loaded, the part is awakened and both outputs are
updated.
Thefirstofthese,theInputRegister,isusedforloadingnew
input codes. The second buffer, the DAC Register, is used
forupdatingtheDACoutputs. EachDAChasitsown10-bit
Input Register and 10-bit DAC Register.
For example, control code 0001b is used to load DAC A
during Sleep. Then Control code 0101b loads DAC B,
wakes the part and simultaneously updates both DAC
outputs.
Byselectingtheappropriate4-bitControlcode(seeTable 2)
itispossibletoperformsingleoperations, suchasloading
one DAC or changing Power-Down status (Sleep/Wake).
7
LTC1662
U
OPERATIO
Voltage Outputs
Rail-to-Rail Output Considerations
Each of the rail-to-rail output amplifiers contained in the
LTC1662 can typically source or sink up to 1mA
(VCC = 5V). The outputs swing to within a few millivolts
of either supply when unloaded and have an equivalent
output resistance of 85Ω (typical) when driving a load to
the rails. The output amplifiers are stable driving capaci-
tive loads up to 1000pF.
In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 2b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale error
(FSE = VOS + GE) is positive, the output for the highest
codes limits at VCC as shown in Figure 2c. No full-scale
limiting can occur if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
POSITIVE
FSE
V
= V
CC
REF
OUTPUT
VOLTAGE
INPUT CODE
(c)
V
REF
= V
CC
OUTPUT
VOLTAGE
0
512
1023
INPUT CODE
(a)
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
1662 F02
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
8
LTC1662
U
TYPICAL APPLICATIO
Using the LTC1258 and the LTC1662 In a Portable Application
Powered by a Single Li-Ion Battery. Total Supply Current Is 8.2µA
Li-ION BATTERY INPUT
V
≥ 4.3V
IN
0.1µF
0.1µF
6
2
V
CC
1
4
3
2
1
8
0V TO 4.096V
(4mV/BIT)
LTC1258-4.1
4
REF
V
OUT A
4.096V
D
IN
LTC1662
SCK
5
0V TO 4.096V
(4mV/BIT)
CS/LD
V
OUT B
GND
7
1662 F03
9
LTC1662
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
8
7
6
5
0.118 ± 0.004**
(3.00 ± 0.102)
0.193 ± 0.006
(4.90 ± 0.15)
1
0.040 ± 0.006
2
3
4
0.034 ± 0.004
(0.86 ± 0.102)
(1.02 ± 0.15)
0.007
(0.18)
0° – 6° TYP
SEATING
PLANE
0.012
(0.30)
REF
0.021 ± 0.006
(0.53 ± 0.015)
0.006 ± 0.004
(0.15 ± 0.102)
0.0256
(0.65)
BSC
MSOP (MS8) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
10
LTC1662
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
8
7
6
5
4
0.255 ± 0.015*
(6.477 ± 0.381)
1
2
3
0.130 ± 0.005
0.300 – 0.325
0.045 – 0.065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
0.125
0.020
(0.508)
MIN
(3.175)
MIN
+0.035
0.325
–0.015
0.018 ± 0.003
(0.457 ± 0.076)
0.100
(2.54)
BSC
+0.889
8.255
(
)
N8 1098
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
11
LTC1662
U
TYPICAL APPLICATIO
Micropower Trim Circuit with Coarse/Fine Adjustment. Total Supply Current Is 9.5µA
3.3V
0.1µF
R2
1.1M
R1
11k
3.3V
6
0.1µF
2
3.3V
8
1
2.5V
0.1µF
LTC1258-2.5
4
4
REF
V
CC
2
3
–
+
R1
COARSE
11k
1
LT1495
4
V
OUT
8
DAC A
V
OUT A
0.1µF
1
3
2
CS/LD
LTC1662
U1
D
IN
CODE A R1 CODE B
R2
FINE
1.1M
V
= V
+
SCK
•
OUT
REF
(
)
)
1024
R2
1024
5
DAC B
V
OUT B
CODE A
1024
1
CODE B
= 2.5V
+
•
(
100 1024
7
GND
1662 F04
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1661
Dual 10-Bit V
DAC in 8-Lead MSOP Package
V
V
V
V
= 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
= 2.7V to 5.5V, Internal Reference, 60µA
OUT
CC
CC
CC
CC
LTC1663
Single 10-Bit V
DAC with 2-Wire Interface in SOT-23 Package
OUT
LTC1664
Quad 10-Bit V
DAC in 16-Pin Narrow SSOP
= 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
= 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
OUT
LTC1665/LTC1660
LTC1446/LTC1446L
Octal 8/10-Bit V
DAC in 16-Pin Narrow SSOP
OUT
Dual 12-Bit V
DACs in SO-8 Package with Internal Reference
DAC in SO-8 Package
LTC1446: V = 4.5V to 5.5V, V
LTC1446L: V = 2.7V to 5.5V, V
= 0V to 4.095V
OUT
CC
OUT
= 0V to 2.5V
CC
OUT
LTC1448
Dual 12-Bit V
Dual 12-Bit V
V
= 2.7V to 5.5V, External Reference Can Be Tied to V
OUT
CC CC
LTC1454/LTC1454L
DACs in SO-16 Package with Added Functionality LTC1454: V = 4.5V to 5.5V, V
= 0V to 4.095V
OUT
CC
OUT
LTC1454L: V = 2.7V to 5.5V, V
= 0V to 2.5V
CC
OUT
LTC1458/LTC1458L
LTC1659
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
Single Rail-to-Rail 12-Bit V DAC in 8-Lead MSOP Package
LTC1458: V = 4.5V to 5.5V, V
= 0V to 4.095V
CC
OUT
LTC1458L: V = 2.7V to 5.5V, V
= 0V to 2.5V
CC
OUT
Low Power Multiplying V
DAC. Output Swings from
OUT
OUT
V
: 2.7V to 5.5V
CC
GND to REF. REF Input Can Be Tied to V
CC
1662i LT/TP 0300 4K • PRINTED IN THE USA
LINEAR TECHNOLOGY CORPORATION 2000
12 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
相关型号：
LTC1662IN8#PBF
LTC1662 - Ultralow Power, Dual 10-Bit DAC in MSOP; Package: PDIP; Pins: 8; Temperature Range: -40°C to 85°C
Linear
LTC1662IN8#TR
IC SERIAL INPUT LOADING, 750 us SETTLING TIME, 10-BIT DAC, PDIP8, 0.300 INCH, PLASTIC, DIP-8, Digital to Analog Converter
Linear
LTC1662IN8#TRPBF
IC SERIAL INPUT LOADING, 750 us SETTLING TIME, 10-BIT DAC, PDIP8, 0.300 INCH, LEAD FREE, PLASTIC, DIP-8, Digital to Analog Converter
Linear
LTC1663-1CS5
LTC1663 - 10-Bit Rail-to-Rail Micropower DAC with 2-Wire Interface; Package: SOT; Pins: 5; Temperature Range: 0°C to 70°C
Linear
LTC1663-1CS5#PBF
LTC1663 - 10-Bit Rail-to-Rail Micropower DAC with 2-Wire Interface; Package: SOT; Pins: 5; Temperature Range: 0°C to 70°C
Linear
LTC1663-1CS5#TR
LTC1663 - 10-Bit Rail-to-Rail Micropower DAC with 2-Wire Interface; Package: SOT; Pins: 5; Temperature Range: 0°C to 70°C
Linear
LTC1663-1CS5#TRM
LTC1663 - 10-Bit Rail-to-Rail Micropower DAC with 2-Wire Interface; Package: SOT; Pins: 5; Temperature Range: 0°C to 70°C
Linear
LTC1663-1CS5#TRMPBF
LTC1663 - 10-Bit Rail-to-Rail Micropower DAC with 2-Wire Interface; Package: SOT; Pins: 5; Temperature Range: 0°C to 70°C
Linear
LTC1663-1CS5#TRPBF
LTC1663 - 10-Bit Rail-to-Rail Micropower DAC with 2-Wire Interface; Package: SOT; Pins: 5; Temperature Range: 0°C to 70°C
Linear
©2020 ICPDF网 联系我们和版权申明