LTC1669CMS8#PBF_技术文档

LTC1669

10-Bit Rail-to-Rail

Micropower DAC with

2

I C Interface

FEATURES

DESCRIPTION

The LTC^®1669 is a 10-bit voltage output DAC with true

buffered rail-to-rail output voltage capability. It operates

from a single supply with a range of 2.7V to 5.5V. The

reference for the DAC is selectable between the supply

voltage or an internal bandgap reference. Selecting the

internal bandgap reference will set the full-scale output

voltagerangeto2.5V.Selectingthesupplyasthereference

sets the output voltage range to the supply voltage.

n

Micropower 10-Bit DAC in SOT-23

Low Operating Current: 60μA

Ultralow Power Shutdown Mode: 12μA

n

2-Wire Serial Interface Compatible

2

with I C™

n

Selectable Internal Reference or Ratiometric to

V

CC

n

Maximum DNL Error: 0.75LSB

8 User Selectable Addresses (MSOP Package)

Single 2.7V to 5.5V Operation

Buffered True Rail-to-Rail Voltage Output

Power-On Reset

The part features a simple 2-wire serial interface compat-

ible with I C that allows communication between many

devices. The internal data registers are double buffered to

allow for simultaneous update of several devices at once.

The DAC can be put in low current power-down mode for

use in power conscious systems.

2

1.5V V and 2.1V V for SDA and SCL

Small 5-Lead TSOT-23 and 8-Lead MSOP Packages

IL

IH

Power-on reset ensures the DAC output is at 0V when

power is initially applied, and all internal registers are

cleared. The LTC1669 is pin-for-pin compatible with the

LTC1663.

APPLICATIONS

n

Digital Calibration

Offset/Gain Adjustment

Industrial Process Control

Automatic Test Equipment

n

For SMBus-compatible designs, please refer to the

LTC1663.

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

n

Arbitrary Function Generators

n

Battery-Powered Data Conversion Products

BLOCK DIAGRAM

4 (5)

V

CC

Differential Nonlinearity (DNL)

BANDGAP

1.25V

1.0

REFERENCE

V

A

= V = 5V

CC

REF

0.8

0.6

T

= 25°C

REFERENCE

SELECT

0.4

0.2

0

10-BIT

–0.2

–0.4

–0.6

–0.8

–1.0

DAC LATCH

V

3 (8)

OUT

10-BIT BUFFERED V

DAC

OUT

COMMAND

LATCH

INPUT

LATCH

MSOP

PACKAGE

ONLY

640 1024

768 896

0

512

CODE

28 156 384

(6)

(2)

(3)

AD0

AD1

AD2

1669 G02

2-WIRE INTERFACE

SDA

SCL

5 (4)

GND

2 (7)

1669 BD

1 (1)

NOTE: PIN NUMBERS IN PARENTHESES REFER TO THE MSOP PACKAGE

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1

LTC1669

(Note 1)

ABSOLUTE MAXIMUM RATINGS

V

to GND .............................................. –0.3V to 7.5V

Operating Temperature Range

CC

SDA, SCL ................................................. –0.3V to 7.5V

AD0, AD1, AD2 (MSOP Only)........–0.3V to (V + 0.3V)

LTC1669C ............................................... 0°C to 70°C

LTC1669I............................................. –40°C to 85°C

Storage Temperature Range.................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ................. 300°C

CC

V

.............................................–0.3V to (V + 0.3V)

OUT

CC

PIN CONFIGURATION

TOP VIEW

SDA

AD1

AD2

SCL

1

2

3

4

8 V

OUT

7 GND

6 AD0

SDA 1

GND 2

5 SCL

5 V

V

3

4 V

CC

OUT

MS8 PACKAGE

8-LEAD PLASTIC MSOP

S5 PACKAGE

5-LEAD PLASTIC SOT-23

= 125°C, θ = 250°C/W

T

= 125°C, θ = 150°C/W

JA

JMAX

T

JMAX

JA

ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING

LTAHV

PACKAGE DESCRIPTION

8-Lead Plastic MSOP

PACKAGE DESCRIPTION

5-Lead Plastic TSOT-23

TEMPERATURE RANGE

0°C to 70°C

LTC1669CMS8#PBF

LTC1669IMS8#PBF

LTC1669CMS8#TRPBF

LTC1669IMS8#TRPBF

LTAHX

–40°C to 85°C

0°C to 70°C

LTC1669-8CMS8#PBF

LTC1669-8IMS8#PBF

TAPE AND REEL (MINI)

LTC1669CS5#TRMPBF

LTC1669-1CS5#TRMPBF

TRM = 500 pieces.

LTC1669-8CMS8#TRPBF LTAHT

LTC1669-8IMS8#TRPBF

TAPE AND REEL

LTAHU

–40°C to 85°C

TEMPERATURE RANGE

0°C to 70°C

PART MARKING

LTAHW

LTC1669CS5#TRPBF

LTC1669-1CS5#TRPBF

LTAHR

0°C to 70°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

1669fa

2

LTC1669

ELECTRICAL CHARACTERISTICS ^The● denotes speciﬁcations which apply over the full operating tempera-

ture range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 2.7V to 5.5V, V_CCset as reference, V_OUTunloaded, unless otherwise noted.

SYMBOL

DAC

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

Resolution

10

Bits

Monotonicity

(Note 2)

DNL

INL

Differential Nonlinearity

Integral Nonlinearity

Offset Error

Guaranteed Monotonic (Note 2)

(Note 2)

0.2

0.5

10

0.75

2.5

30

LSB

mV

V

Measured at Code 20

OS

Offset Error Temperature Coefﬁcient

Full-Scale Error

15

μV/°C

OSTC

l

FSE

Reference Set to V

Reference Set to Internal Bandgap

3

15

LSB

CC

V

OUT

DAC Output Span

Reference Set to V

0 to V

CC

0 to 2.5

V

CC

Reference Set to Internal Bandgap

V

FSTC

Full-Scale Voltage Temperature

Coefﬁcient

Reference Set to V

30

50

μV/°C

CC

Reference Set to Internal Bandgap

PSRR

Power Supply Rejection Ratio

Reference Set to Internal Bandgap,

Code = 1023

0.4

LSB/V

Power Supply

l

V

Positive Supply Voltage

Supply Current

2.7

5.5

V

CC

l

I

V

= 3V (Note 3)

= 5V (Note 3)

60

75

100

125

μA

CC

l

I

SD

Supply Current in Shutdown Mode

(Note 3)

12

24

μA

Op Amp DC Performance

Short-Circuit Current (Sourcing)

l

V

Shorted to GND, Input Code = 1023

25

30

100

120

mA

OUT

Short-Circuit Current (Sinking)

Output Impedance to GND

Shorted to V , Input Code = 0

CC

OUT

Ω

kΩ

Input Code = 0, V = 5V

65

150

500

CC

Input Code = 0, V = 5V

In Shutdown Mode

Ω

Output Impedance to V

Input Code = 1023, V = 5V

80

120

CC

Input Code = 1023, V = 5V

CC

AC Performance

Voltage Output Slew Rate

Rising (Notes 4, 5)

Falling (Notes 4, 5)

0.75

0.25

V/μs

Voltage Output Settling Time

Digital Feedthrough

To 0.5LSB (Notes 4, 5)

30

0.75

70

μs

nV•s

Digital-to-Analog Glitch Impulse

1LSB Change Around Major Carry

Digital Inputs SCL, SDAs

l

V

High Level Input Voltage

Low Level Input Voltage

Logic Threshold Voltage

Digital Input Leakage

2.1

V

IH

1.5

IL

1.8

V

LTH

LEAK

l

I

V

= 5.5V and 0V, V = GND to V

CC

1

μA

pF

CC

IN

C

Digital Input Capacitance

(Note 7)

10

IN

Digital Output SDA

Digital Output Low Voltage

l

V

I

= 3mA

0.4

V

OL

PULLUP

1669fa

3

LTC1669

ELECTRICAL CHARACTERISTICS

The ● denotes speciﬁcations which apply over the full operating tempera-

ture range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 2.7V to 5.5V, V_CCset as reference, V_OUTunloaded, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

1.5

UNITS

Address Inputs AD0, AD1, AD2 (MSOP Only)

l

I

Address Pin Pull-Up Current

High Level Input Voltage

Low Level Input Voltage

V

IN

= 0V

0.5

μA

V

UP

V

– 0.3

CC

IH

0.8

V

IL

The ● denotes speciﬁcations which apply over the full operating temperature

TIMING CHARACTERISTICS

range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 2.7V to 5.5V, V_CCset as reference, V_OUTunloaded, unless otherwise noted.

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

Timing Characteristics (Notes 6, 7)

f

t

Clock Operating Frequency

Bus Free Time Between Stop and Start Condition

Hold Time After (Repeated) Start Condition

Repeated Start Condition Setup Time

Stop Condition Setup Time

Data Hold Time (Input)

●

100

kHz

SCL

4.7

4

μs

ns

μs

ns

BUF

HD, STA

SU, STA

SU, STO

HD, DAT (IN)

HD, DAT (OUT)

SU, DAT

LOW

4.7

4

0

Data Hold Time (Output)

225

250

4.7

4

500

3450

Data Setup Time

Clock Low Period

Clock High Period

HIGH

Clock, Data Fall Time

20

300

f

Clock, Data Rise Time

1000

r

Note 3: Digital inputs at 0V or V

.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Nonlinearity and monotonicity are deﬁned from code 20 to code

1003 (full scale). See Applications Information.

CC

Note 4: Load is 10kΩ in parallel with 100pF.

Note 5: V = V = 5V. DAC switched between 0.1V and 0.9V ,

FS

CC

REF

FS

i.e., codes k = 102 and k = 922.

Note 6: All values are referenced to V and V levels.

Note 7: Guaranteed by design and not subject to test.

IH

IL

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LTC1669

TYPICAL PERFORMANCE CHARACTERISTICS

Source and Sink Current

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Capability with V_CC= 5V

1.0

0.8

1.0

0.8

5.0

4.5

T = 25°C

A

V

T

= V = 5V

CC

V

T

= V = 5V

CC

REF

A

REF

A

= 25°C

DAC CODE = 1023

0.6

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

DAC CODE = 0

0

28 156 384

512

640 1024

768 896

0

1

2

3

4

5

6

7

8

9

10

0

28 156 384

512

640 1024

768 896

CODE

OUTPUT CURRENT SOURCE/SINK (mA)

1669 G02

1669 G03

1669 G01

Large-Signal Step Response

Midscale Glitch

Load Regulation vs Output Current

1.0

0.8

V

= V

= 5V

REF

CC

5

= 2.5V

SDA

(VOLTS)

5V

OUT

CODE = 512

SDA

0

5

4

3

2

1

0

0.6

T

= 25°C

0V

A

0.4

CODE = 512 TO 511

CODE = 990

0.2

0

V

R

C

= 5V

CC

L

= 4.7k

= 100pF

= 25°C

V

OUT

–0.2

–0.4

–0.6

–0.8

–1.0

V

OUT

10mV/DIV

(VOLTS)

SOURCE

SINK

T

A

V

= 5V

CC

L

R

= 4.7k

CODE = 32

C

= 100pF

= 25°C

T

A

1669 G05

1669 G04

2μs/DIV

–4 –3 –2 –1

I

0

2

3

5μs/DIV

1

4

1669 G06

(mA)

OUT

Offset Error Voltage vs

Temperature

Full-Scale Output Voltage vs

Temperature

Load Regulation vs Output Current

1.0

0.8

5

4

2.510

2.508

2.506

2.504

2.502

2.500

2.498

2.496

2.494

2.492

2.490

V

= V

= 3V

REF

CC

REFERENCE SET TO

INTERNAL BANDGAP

= 1.5V

OUT

CODE = 512

0.6

3

T

= 25°C

A

2

0.4

0.2

1

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1

–2

–3

–4

–5

SOURCE

SINK

–1.0

0.8 1.0

–60

80

–60

80

–0.8–0.6–0.4–0.2

0

0.2 0.4 0.6

–40 –20

0

20 40 60

100

–40 –20

0

20 40 60

100

I

(mA)

TEMPERATURE (°C)

OUT

1669 G07

1669 G08

1669 G09

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5

LTC1669

PIN FUNCTIONS

SDA (Pin 1, Pin 1 on SOT-23): Serial Data Bidirectional

Pin. Data is shifted into the SDA pin and acknowledged

by the SDA pin. High impedance pin while data is shifted

in. Open-drainN-channeloutputduringacknowledgment.

SCL (Pin 4, Pin 5 on SOT-23): Serial Clock Input Pin.

Data is shifted into the SDA pin at the rising edges of the

clock. This high impedance pin requires a pull-up resistor

or current source to V .

CC

Requires a pull-up resistor or current source to V .

CC

V

(Pin 5, Pin 4 on SOT-23): Power Supply. 2.7V ≤ V

CC

AD1 (Pin 2): Slave Address Select Bit 1. Tie this pin to

≤ 5.5V. Also used as the reference voltage input when the

either V or GND to modify the corresponding bit of the

part is programmed to use V as the reference.

CC

LTC1669’s slave address.

AD0 (Pin 6): Slave Address Select Bit 0. Tie this pin to

AD2 (Pin 3): Slave Address Select Bit 2. Tie this pin to

either V or GND to modify the corresponding bit of the

CC

either V or GND to modify the corresponding bit of the

LTC1669’s slave address.

CC

LTC1669’s slave address.

GND (Pin 7, Pin 2 on SOT-23): System Ground.

V

(Pin 8, Pin 3 on SOT-23): Voltage Output. Buffered

OUT

rail-to-rail DAC output.

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6

LTC1669

DEFINITIONS

Differential Nonlinearity (DNL): The difference between

the measured change and the ideal 1LSB change for any

twoadjacentcodes. TheDNLerrorbetweenanytwocodes

is calculated as follows:

greater than zero. The INL error at a given input code is

calculated as follows:

INL = [V_OUT– V_OS– (V_FS– V_OS)(code/1023)]/LSB

Where V_OUTis the output voltage of the DAC measured

at the given input code.

DNL = (ΔV

– LSB)/LSB

OUT

Where ΔV

is the measured voltage difference between

OUT

Least Signiﬁcant Bit (LSB): The ideal voltage difference

between two successive codes.

two adjacent codes.

Digital Feedthrough: The glitch that appears at the ana-

log output caused by AC coupling from the digital inputs

when they change state. The area of the glitch is speciﬁed

in (nV)(sec).

LSB = V /1024

REF

Resolution (n): Deﬁnes the number of DAC output states

n

(2 ) that divide the full-scale range. Resolution does not

imply linearity.

Full-ScaleError(FSE):Thedeviationoftheactualfull-scale

voltage from ideal. FSE includes the effects of offset and

gain errors (see Applications Information).

Voltage Offset Error (V ): Nominally, the voltage at the

OS

output when the DAC is loaded with all zeros. A single

supply DAC can have a true negative offset, but the output

cannot go below zero (see Applications Information).

Integral Nonlinearity (INL): The deviation from a straight

line passing through the endpoints of the DAC transfer

curve (Endpoint INL). Because the output cannot go

below zero, the linearity is measured between full scale

and the lowest code that guarantees the output will be

For this reason, single supply DAC offset is measured at

the lowest code that guarantees the output will be greater

than zero.

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LTC1669

TIMING DIAGRAM

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LTC1669

APPLICATIONS INFORMATION

Write Word Protocol Used by the LTC1669

1

7

1

8

1

8

1

8

1

S

Slave Address Wr

A

Command Byte

A

LSData Byte

A

MSData Byte

A

P

1669 TA03

S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition

Serial Digital Interface

Write Word Protocol

The LTC1669 communicates with a host (master) using

the standard 2-wire interface. The Timing Diagram shows

the timing relationship of the signals on the bus. The two

bus lines, SDA and SCL, must be high when the bus is

not in use. External pull-up resistors or current sources,

ThemasterinitiatescommunicationwiththeLTC1669with

aSTARTconditionanda7-bitaddressfollowedbytheWrite

Bit (Wr) = 0. The LTC1669 acknowledges and the master

delivers the command byte. The LTC1669 acknowledges

and latches the command byte into the command byte

inputregister.Themasterthendeliverstheleastsigniﬁcant

data byte. Again the LTC1669 acknowledges and the data

is latched into the least signiﬁcant data byte input register.

The master then delivers the most signiﬁcant data byte.

The LTC1669 acknowledges once more and latches the

data into the most signiﬁcant data byte input register.

Lastly, the master terminates the communication with a

STOP condition. On the reception of the STOP condition,

the LTC1669 transfers the input register information to

output registers and the DAC output is updated.

2

such as the LTC1694 SMBus/I C Accelerator, are required

on these lines.

The LTC1669 is a receive-only (slave) device. The master

can communicate with the LTC1669 using the Quick Com-

mand, Send Byte or Write Word protocols as explained

later.

The START and STOP Conditions

When the bus is not in use, both SCL and SDA must be

high. A bus master signals the beginning of a communica-

tion to a slave device by transmitting a START condition.

A START condition is generated by transitioning SDA

from high to low while SCL is high.

Slave Address (MSOP Package Only)

The LTC1669 can respond to one of eight 7-bit addresses.

The ﬁrst 4 bits (MSBs) have been factory programmed to

0100. The ﬁrst 4 bits of the LTC1669-8 have been factory

programmed to 0011. The three address bits, AD2, AD1

and AD0 are programmed by the user and determine the

LSBs of the slave address, as shown in the table below:

When the master has ﬁnished communicating with the

slave, it issues a STOP condition. A STOP condition is

generated by transitioning SDA from low to high while

SCL is high. The bus is then free for communication with

2

another I C device.

LTC1669

0100 xxx

0100 000

0100 001

0100 010

0100 011

0100 100

0100 101

0100 110

0100 111

LTC-1669-8

0011 xxx

0011 000

0011 001

0011 010

0011 011

0011 100

0011 101

0011 110

0011 111

AD2

L

AD1

L

AD0

L

Acknowledge

The Acknowledge signal is used for handshaking between

the master and the slave. An Acknowledge (active LOW)

generated by the slave lets the master know that the latest

byteofinformationwasreceived.TheAcknowledgerelated

clockpulseisgeneratedbythemaster.Themasterreleases

the SDA line (HIGH) during the Acknowledge clock pulse.

The slave-receiver must pull down the SDA line during the

Acknowledge clock pulse so that it remains a stable LOW

during the HIGH period of this clock pulse.

L

H

L

H

L

H

L

H

L

H

L

H

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9

LTC1669

APPLICATIONS INFORMATION

Slave Address (SOT-23 Package)

The Bandgap (BG) bit when set to “0” selects the DAC

supply voltage as its voltage reference. The full-scale

output of the DAC with this setting is equal to the supply

voltage. When the BG bit is set to “1,” the internal bandgap

reference(≈1.25V)isselectedastheDAC’sreference. The

full-scale output voltage for this setting is 2.5V.

The slave address for the SOT-23 package has been

factory programmed to be “0100 000” (LTC1669) and

“0100 001” (LTC1669-1). If another address is required,

please consult the factory.

Command Byte

Data Bytes

7

6

5

4

3

2

1

0

Least Signiﬁcant Data Byte

X

BG

SD

SY

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

SY

SD

1

0

Allows update on Acknowledge of SYNC Address only

Update on Stop condition only (Power-On Default)

1

0

Puts the device in power-down mode

Puts the device in standard operating mode

(Power-On Default)

Most Signiﬁcant Data Byte

7

6

5

4

3

2

1

0

BG

X

1

0

Selects the internal bandgap reference

Selects the supply as the reference (Power-On Default)

X

D9

D8

X = Don’t care

X

Don’t Care

Send Byte Protocol

The stop condition normally initiates the update of the

DAC’s output latches. Simultaneous update of more than

one DAC or other devices on the bus can be achieved by

reissuing new start bit, address, command and data bytes

before issuing a ﬁnal stop condition (which will update

all the devices). An alternate way to achieve simultaneous

LTC1669 updates is to override the stop condition update

by setting the “SY” bit of the command byte. Setting this

bit sets the device to update the DAC output latches only

at the reception of a SYNC address quick command. The

actual update occurs on the rising edge of SCL during the

Acknowledge. In this way, all devices can update on the

reception of the SYNC address quick command instead

of the STOP condition.

The Send Byte protocol used on the LTC1669 is actually a

subset of the Write Word protocol described previously.

The Send Byte protocol can only be used to send the

command byte information to the LTC1669.

1

7

1

8

1

S

Slave Address Wr

A

Command Byte

A

P

S = Start Condition, Wr = Write Bit, A = Acknowledge, P = Stop Condition

1669 TA04

The Send Byte protocol is also used whenever the Write

Word protocol is interrupted for any reason. Reception of

a START or STOP condition after the Acknowledge of the

command byte, but before the Acknowledge of the last

data byte, will cause both data bytes to be ignored and

the command byte to be accepted.

A Shutdown (SD) bit = HIGH will put the device in a low

powerstatebutretainalldatalatchinformation.Shutdown

will occur at the reception of a STOP condition. This way

shutdown could be synchronized to other devices. The

output impedance of the DAC will go to a high impedance

state (≈500kΩ to GND).

Reception of a START or STOP condition before the Ac-

knowledgeofthecommandbytewillcausetheinterrupted

command byte to be ignored.

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10

LTC1669

APPLICATIONS INFORMATION

SYNC Address/Quick Command

Rail-to-Rail Output Considerations

As in any rail-to-rail device, the output is limited to volt-

ages within the supply range.

Inadditiontotheslaveaddress,theLTC1669hasanaddress

that can be shared by other devices so that they may be

updatedsynchronously. TheaddressiscalledtotheSYNC

address and uses the quick command protocol.

If the DAC offset is negative, the output for the lowest

codes limits at 0V as shown in Figure 1b.

The SYNC Address is 1111 110

Similarly, limiting can occur near full scale when V is

CC

1

7

1

used as the reference. If V = V and the DAC full-scale

REF

CC

Start 1111 110

SYNC Address

SY/CLR

Ack

Stop

1669 TA05

error (FSE) is positive, the output for the highest codes

limits at V as shown in Figure 1c. No full-scale limiting

CC

can occur if the internal reference is used.

SY/CLR

1

0

Update output latches on rising edge of SCL during

Acknowledge of SYNC Address

Clear all internal latches on rising edge of SCL during

Acknowledge of SYNC Address

Offset and linearity are deﬁned and tested over the region

of the DAC transfer function where no output limiting can

occur.

The SY/CLR bit set high only has meaning when the “SY”

bit of the command byte was previously set HIGH. On

the otherhand, the SY/CLR bit set LOW will always clear

the part, independent of the state of the “SY” bit in the

command byte.

Internal Reference

In applications where a predictable output is required

that is independent of supply voltage, the LTC1669 has a

user-selectable internal reference. Selecting the internal

reference will set the full-scale output voltage to 2.5V. This

can be useful in applications where the supply voltage is

poorly regulated.

Voltage Output

The output ampliﬁer contained in the LTC1669 can source

or sink up to 5mA. The output stage swings to within a

few millivolts of either supply rail when unloaded and

has an equivalent output resistance of 85Ω when driving

a load to the rails. The output ampliﬁer is stable driving

capacitive loads up to 1000pF.

Using the LT^®1460 Micropower Series Reference as a

Power Supply for the LTC1669

In applications where the advantages of using the internal

reference are required but the full-scale range needs to

be greater than 2.5V, an external series reference can be

used. The LT1460 is ideal for use as a power supply for

the LTC1669 and can provide 3V, 3.3V and 5V full-scale

outputvoltageranges.TheLT1460providesaccuracy,noise

immunityandextendedsupplyrangetotheLTC1669when

A small resistor placed in series with the output can be

used to achieve stability for any load capacitance greater

than 1000pF. For example, a 0.1μF load can be driven

by the LTC1669 if a 110Ω series resistance is used. The

phase margin of the resulting circuit is 45° and increases

monotonicallyfromthispointiflargervaluesofresistance,

capacitance or both are substituted for the values given.

the LTC1669 is operated ratiometric to V . Since both

CC

partsareavailableinSOT-23packages,thePCboardspace

for this application is extremely small. See Figure 2.

1669fa

11

LTC1669

APPLICATIONS INFORMATION

POSITIVE

FSE

V

= V

CC

REF

OUTPUT

VOLTAGE

INPUT CODE

(c)

V

= V

CC

REF

OUTPUT

VOLTAGE

0

512

1023

INPUT CODE

(a)

OUTPUT

VOLTAGE

0V

NEGATIVE

OFFSET

INPUT CODE

(b)

1669 F01

Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative

Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V_REF= V_CC

1669fa

12

LTC1669

APPLICATIONS INFORMATION

LT1460S3-3

IN OUT

3V

1

2

3.9V TO 20V

+

GND

3

0.1μF

0.01μF

4 (5)

V

CC

5 (4)

SCL

SDA

3 (8)

TO

μP

LTC1669

OUT

0V ≤ V

≤ 3V

OUT

1 (1)

GND

LTC1669 PIN NUMBERS IN PARENTHESES

REFER TO MSOP PACKAGE

2 (7)

1669 F02

Figure 2. LT1460 As Power Supply for the LTC1669

1669fa

13

LTC1669

PACKAGE DESCRIPTION

S5 Package

5-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1635)

0.62

MAX

0.95

REF

2.90 BSC

(NOTE 4)

1.22 REF

1.50 – 1.75

(NOTE 4)

2.80 BSC

1.4 MIN

3.85 MAX 2.62 REF

PIN ONE

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

0.30 – 0.45 TYP

5 PLCS (NOTE 3)

0.95 BSC

0.80 – 0.90

0.20 BSC

DATUM ‘A’

0.01 – 0.10

1.00 MAX

0.30 – 0.50 REF

1.90 BSC

0.09 – 0.20

(NOTE 3)

NOTE:

S5 TSOT-23 0302

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

1669fa

14

LTC1669

PACKAGE DESCRIPTION

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1660)

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

0.889 ± 0.127

(.035 ± .005)

0.52

(.0205)

REF

8

7 6

5

5.23

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

3.20 – 3.45

(.206)

4.90 ± 0.152

(.193 ± .006)

(.126 – .136)

MIN

DETAIL “A”

0.254

(.010)

0° – 6° TYP

GAUGE PLANE

0.65

(.0256)

BSC

0.42 ± 0.038

(.0165 ± .0015)

TYP

1

2

3

4

0.53 ± 0.152

(.021 ± .006)

1.10

(.043)

MAX

0.86

(.034)

REF

RECOMMENDED SOLDER PAD LAYOUT

DETAIL “A”

0.18

(.007)

SEATING

PLANE

NOTE:

0.22 – 0.38

(.009 – .015)

TYP

0.127 ± 0.076

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

(.005 ± .003)

0.65

(.0256)

BSC

MSOP (MS8) 0603

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

1669fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

15

LTC1669

TYPICAL APPLICATION

Program Up to 16 Control Outputs Per BUS and Place Them Where They Are Needed

V

= 2.7V TO 5.5V

CC

1

V

CC

SMBus 1

5

4

+

LTC1694

0.1μF

SMBus 2

GND

2

+

5

0.1μF

4

1

SCL

SDA

V

CC

8

LTC1669CMS8

CONTROL

OUTPUT 0

0V ≤ V

6

2

3

V

OUT

AD0

AD1

AD2

< V

CC

SCL

μP

SDA

OUT0

GND

7

+

5

0.1μF

4

1

SCL

SDA

V

CC

8

LTC1669CMS8

CONTROL

OUTPUT 1

0V ≤ V

6

2

3

V

OUT

AD0

AD1

AD2

< V

CC

OUT1

GND

7

+

5

0.1μF

4

1

SCL

SDA

V

CC

8

LTC1669-8CMS8

CONTROL

OUTPUT 15

0V ≤ V

6

2

3

V

OUT

AD0

AD1

AD2

< V

OUT15

CC

GND

7

2

TO OTHER I

DEVICES

C

1669 TA06

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

2

LTC1694

SMBus/I C Accelerator

Dual SMBus Accelerator with Active AC and DC Pull-Up Current Sources

Dual SMBus Accelerator with Active AC Pull-Up Current Only

2

LTC1694-1

DACs

SMBus/I C Accelerator

Single Rail-to-Rail 12-Bit V

DAC in 8-Lead MSOP Low Power Multiplying V

DAC. Output Swings from GND to REF. REF

OUT

LTC1659

Package. V = 2.7V to 5.5V

Input Can Be Tied to V . 3-Wire Interface.

CC

LTC1660/LTC1664

LTC1661

Octal/Quad 10-Bit V

DACs in 16-Pin Narrow SSOP

V

CC

V

CC

= 2.7V to 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface.

OUT

Dual 10-Bit V

in 8-Lead MSOP Package

OUT

LTC1663

10-Bit V

in SOT-23, SMBUS Interface

Pin Compatible with LTC1669

OUT

ADCs

LTC1285/LTC1288

LTC1286/LTC1298

8-Pin SO, 3V Micropower ADCs

8-Pin SO, 5V Micropower ADCs

1- or 2-Channel, Autoshutdown

1669fa

LT 1007 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

16

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1669CMS8#PBF
厂家：	Linear
描述：	LTC1669 - 10-Bit Rail-to-Rail Micropower DAC with I<sup>2</sup>C Interface; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C 光电二极管转换器
文件：	总16页 (文件大小：157K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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