LTC1669IMS8 [Linear]
10-Bit Rail-to-Rail Micropower DAC with I2C Interface; 10位轨至轨微DAC,具有I2C接口型号: | LTC1669IMS8 |
厂家: | Linear |
描述: | 10-Bit Rail-to-Rail Micropower DAC with I2C Interface |
文件: | 总12页 (文件大小:186K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC1669
10-Bit Rail-to-Rail
Micropower DAC with I2C Interface
U
DESCRIPTIO
FEATURES
The LTC®1669 is a 10-bit voltage output DAC with true
buffered rail-to-rail output voltage capability. It operates
from a single supply with a range of 2.7V to 5.5V. The
reference for the DAC is selectable between the supply
voltage or an internal bandgap reference. Selecting the
internal bandgap reference will set the full-scale output
voltage range to 2.5V. Selecting the supply as the refer-
ence sets the output voltage range to the supply voltage.
■
Micropower 10-Bit DAC in SOT-23
■
Low Operating Current: 60µA
■
Ultralow Power Shutdown Mode: 12µA
■
2-Wire Serial Interface Compatible
with I2CTM
■
Selectable Internal Reference or Ratiometric to VCC
Maximum DNL Error: 0.75LSB
8 User Selectable Addresses (MSOP Package)
Single 2.7V to 5.5V Operation
Buffered True Rail-to-Rail Voltage Output
Power-On Reset
1.5V VIL and 2.1V VIH for SDA and SCL
■
■
■
■
■
■
■
The part features a simple 2-wire serial interface compat-
ible with I2C that allows communication between many
devices. The internal data registers are double buffered to
allow for simultaneous update of several devices at once.
The DAC can be put in low current power-down mode for
use in power conscious systems.
Small 5-Lead SOUT-23 and 8-Lead MSOP Packages
APPLICATIO S
Power-on reset ensures the DAC output is at 0V when
power is initially applied, and all internal registers are
cleared. The LTC1669 is pin-for-pin compatible with the
LTC1663.
■
Digital Calibration
■
Offset/Gain Adjustment
■
Industrial Process Control
■
Automatic Test Equipment
, LTC and LT are registered trademarks of Linear Technology Corporation.
I2C is a trademark of Philips Electronics N.V.
■
Arbitrary Function Generators
■
Battery-Powered Data Conversion Products
W
BLOCK DIAGRA
4 (5)
V
CC
BANDGAP
1.25V
Differential Nonlinearity (DNL)
REFERENCE
1.0
V
REF
= V = 5V
CC
0.8
0.6
REFERENCE
SELECT
T
A
= 25°C
0.4
0.2
10-BIT
DAC LATCH
0
–0.2
–0.4
–0.6
–0.8
–1.0
V
3 (8)
OUT
10-BIT BUFFERED V
DAC
OUT
COMMAND
LATCH
INPUT
LATCH
MSOP
PACKAGE
ONLY
(6)
(2)
(3)
AD0
AD1
AD2
0
768 896
1024
28 156 384 512 640
CODE
2-WIRE INTERFACE
1669 G02
SDA
SCL
GND
2 (7)
1669 BD
1 (1)
5 (4)
NOTE: PIN NUMBERS IN PARENTHESES REFER TO THE MSOP PACKAGE
1669f
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LTC1669
W W W
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ABSOLUTE AXI U RATI GS (Note 1)
VCC to GND .............................................. –0.3V to 7.5V
SDA, SCL ..................................................–0.3V to 7.5V
AD0, AD1, AD2 (MSOP Only) ...... –0.3V to (VCC + 0.3V)
VOUT ............................................ –0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC1669C .............................................. 0°C to 70°C
LTC1669I........................................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
W
U
/O
PACKAGE RDER I FOR ATIO
ORDER PART
ORDER PART
NUMBER
NUMBER
TOP VIEW
TOP VIEW
LTC1669CMS8 LTC1669-8CMS8
LTC1669IMS8 LTC1669-8IMS8
LTC1669CS5
LTC1669-1CS5
SDA
AD1
AD2
SCL
1
2
3
4
8 V
OUT
7 GND
6 AD0
SDA 1
GND 2
5 SCL
5 V
V
3
4 V
CC
CC
OUT
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING
S5 PART MARKING
S5 PACKAGE
5-LEAD PLASTIC SOT-23
LTAHV
LTAHX
LTAHT
LTAHU
LTAHW
LTAHR
TJMAX = 125°C, θJA = 150°C/W
TJMAX = 125°C, θJA = 250°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded,
unless otherwise noted.
SYMBOL PARAMETER
DAC
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
●
●
●
●
●
10
10
Bits
Bits
Monotonicity
(Note 2)
DNL
INL
Differential Nonlinearity
Guaranteed Monotonic (Note 2)
(Note 2)
±0.2
±0.5
±10
±15
±0.75
±2.5
±30
LSB
LSB
mV
Integral Nonlinearity
Offset Error
V
V
Measured at Code 20
OS
Offset Error Temperature Coefficient
Full-Scale Error
µV/°C
OSTC
FSE
Reference Set to V
Reference Set to Internal Bandgap
●
●
±3
±3
±15
±15
LSB
LSB
CC
V
V
DAC Output Span
Reference Set to V
0 to V
CC
V
V
OUT
CC
Reference Set to Internal Bandgap
0 to 2.5
Full-Scale Voltage Temperature Coefficient
Power Supply Rejection Ratio
Reference Set to V
±30
±50
µV/°C
µV/°C
FSTC
CC
Reference Set to Internal Bandgap
PSRR
Reference Set to Internal Bandgap,
Code = 1023
±0.4
LSB/V
Power Supply
V
Positive Supply Voltage
Supply Current
●
2.7
5.5
V
CC
I
V
V
= 3V (Note 3)
= 5V (Note 3)
●
●
60
75
100
125
µA
µA
CC
CC
CC
I
Supply Current in Shutdown Mode
(Note 3)
●
12
24
µA
SD
Op Amp DC Performance
Short-Circuit Current (Sourcing)
Short-Circuit Current (Sinking)
V
V
Shorted to GND, Input Code = 1023
●
●
25
30
100
120
mA
OUT
OUT
Shorted to V , Input Code = 0
mA
CC
1669f
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LTC1669
The ● denotes specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
unless otherwise noted.
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded,
SYMBOL PARAMETER
Output Impedance to GND
CONDITIONS
MIN
TYP
MAX
UNITS
Input Code = 0, V = 5V
65
150
500
Ω
Ω
kΩ
CC
CC
Input Code = 0, V = 3V
In Shutdown Mode
Output Impedance to V
Input Code = 1023, V = 5V
80
120
Ω
Ω
CC
CC
Input Code = 1023, V = 3V
CC
AC Performance
Voltage Output Slew Rate
Rising (Notes 4, 5)
Falling (Notes 4, 5)
0.75
0.25
V/µs
V/µs
Voltage Output Settling Time
Digital Feedthrough
To ±0.5LSB (Notes 4, 5)
30
0.75
70
µs
nV • s
nV • s
Digital-to-Analog Glitch Impulse
1LSB Change Around Major Carry
Digital Inputs SCL, SDA
V
V
V
High Level Input Voltage
Low Level Input Voltage
Logic Threshold Voltage
Digital Input Leakage
●
●
2.1
V
V
IH
1.5
IL
1.8
0.5
V
LTH
LEAK
I
V
= 5.5V and 0V, V = GND to V
CC
●
●
±1
µA
pF
CC
IN
C
Digital Input Capacitance
(Note 7)
10
IN
Digital Output SDA
Digital Output Low Voltage
Address Inputs AD0, AD1, AD2 (MSOP Only)
V
I
= 3mA
●
0.4
1.5
0.8
V
OL
PULLUP
I
Address Pin Pull-Up Current
High Level Input Voltage
Low Level Input Voltage
V
= 0V
IN
●
●
●
µA
V
UP
V
V
V
– 0.3
CC
IH
V
IL W U
The ● denotes specifications which apply over the full operating temperature
TI I G CHARACTERISTICS
range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded, unless otherwise noted.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
Timing Characteristics (Notes 6, 7)
f
t
t
t
t
t
t
t
t
t
t
t
Clock Operating Frequency
Bus Free Time Between Stop and Start Condition
Hold Time After (Repeated) Start Condition
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time (Input)
●
●
●
●
●
●
●
●
●
●
●
●
100
kHz
µs
µs
µs
µs
ns
ns
ns
µs
µs
ns
ns
SCL
4.7
4
BUF
HD, STA
SU, STA
SU, STO
HD, DAT (IN)
HD, DAT (OUT)
SU, DAT
LOW
4.7
4
0
Data Hold Time (Output)
225
250
4.7
4
500
3450
Data Setup Time
Clock Low Period
Clock High Period
HIGH
Clock, Data Fall Time
20
20
300
f
Clock, Data Rise Time
1000
r
Note 1: Absolute maximum ratings are those values beyond which the life
Note 4: Load is 10kΩ in parallel with 100pF.
Note 5: V = V = 5V. DAC switched between 0.1V and 0.9V ,
FS
of a device may be impaired.
CC
REF
FS
Note 2: Nonlinearity and monotonicity are defined from code 20 to code
1003 (full scale). See Applications Information.
i.e., codes k = 102 and k = 922.
Note 6: All values are referenced to V and V levels.
IH
IL
Note 3: Digital inputs at 0V or V
.
CC
Note 7: Guaranteed by design and not subject to test.
1669f
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LTC1669
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Source and Sink Current
Capability with VCC = 5V
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
0.8
1.0
0.8
5.0
4.5
T
= 25°C
V
T
= V = 5V
CC
V
T
= V = 5V
CC
A
REF
A
REF
A
= 25°C
= 25°C
DAC CODE = 1023
0.6
0.6
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
DAC CODE = 0
0
512
768 896
0
28 156 384
640
1024
28 156 384
512
640 1024
768 896
0
1
2
3
4
5
6
7
8
9
10
CODE
CODE
OUTPUT CURRENT SOURCE/SINK (mA)
1669 G01
1669 G02
1669 G03
Large-Signal Step Response
Midscale Glitch
Load Regulation vs Output Current
1.0
0.8
V
V
= V
= 5V
CC
REF
5
0
5
4
3
2
1
0
= 2.5V
SDA
OUT
5V
CODE = 512
(VOLTS)
SDA
0.6
T
= 25°C
A
0V
0.4
CODE = 512 TO 511
0.2
0
V
OUT
–0.2
–0.4
–0.6
–0.8
–1.0
V
(VOLTS)
SOURCE
SINK
OUT
10mV/DIV
1669 G04
1669 G05
–4
0
2
3
–3 –2 –1
I
1
4
5µs/DIV
2µs/DIV
(mA)
OUT
1669 G06
Offset Error Voltage vs
Temperature
Full-Scale Output Voltage vs
Temperature
Load Regulation vs Output Current
1.0
0.8
5
4
2.510
2.508
2.506
2.504
2.502
2.500
2.498
2.496
2.494
2.492
2.490
V
V
= V
= 3V
CC
REF
REFERENCE SET TO
INTERNAL BANDGAP
= 1.5V
OUT
CODE = 512
0.6
3
T
= 25°C
A
2
0.4
0.2
1
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1
–2
–3
–4
–5
SOURCE
SINK
0.8 1.0
–60
80
80
–1.0
20
TEMPERATURE (°C)
60
–0.8–0.6–0.4–0.2
0
0.2 0.4 0.6
–40 –20
0
40
100
–60 –40
0
20
60
100
–20
40
I
(mA)
TEMPERATURE (°C)
OUT
1669 G07
1669 G08
1669 G09
1669f
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LTC1669
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PIN FUNCTIONS
SDA (Pin 1, Pin 1 on SOT-23): Serial Data Bidirectional
Pin. Data is shifted into the SDA pin and acknowledged by
the SDA pin. High impedance pin while data is shifted in.
Open-drain N-channel output during acknowledgment.
Requires a pull-up resistor or current source to VCC.
VCC (Pin 5, Pin 4 on SOT-23): Power Supply. 2.7V ≤ VCC
≤ 5.5V. Also used as the reference voltage input when the
part is programmed to use VCC as the reference.
AD0 (Pin 6): Slave Address Select Bit 0. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1669’s slave address.
AD1 (Pin 2): Slave Address Select Bit 1. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1669’s slave address.
GND (Pin 7, Pin 2 on SOT-23): System Ground.
V
OUT (Pin 8, Pin 3 on SOT-23): Voltage Output. Buffered
AD2 (Pin 3): Slave Address Select Bit 2. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1669’s slave address.
rail-to-rail DAC output.
SCL (Pin 4, Pin 5 on SOT-23): Serial Clock Input Pin. Data
is shifted into the SDA pin at the rising edges of the clock.
This high impedance pin requires a pull-up resistor or
current source to VCC.
U
U
DEFINITIONS
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
twoadjacentcodes.TheDNLerrorbetweenanytwocodes
is calculated as follows:
zero. The INL error at a given input code is calculated as
follows:
INL = [VOUT – VOS – (VFS – VOS)(code/1023)]/LSB
Where VOUT is the output voltage of the DAC measured at
the given input code.
DNL = (∆VOUT – LSB)/LSB
Where ∆VOUT is the measured voltage difference between
two adjacent codes.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
DigitalFeedthrough: Theglitchthatappearsattheanalog
outputcausedbyACcouplingfromthedigitalinputswhen
they change state. The area of the glitch is specified in
(nV)(sec).
LSB = VREF/1024
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Full-Scale Error (FSE): The deviation of the actual full-
scale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve(EndpointINL).Becausetheoutputcannotgobelow
zero, the linearity is measured between full scale and the
lowestcodethatguaranteestheoutputwillbegreaterthan
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
1669f
5
LTC1669
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TI I G DIAGRA
1669f
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LTC1669
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APPLICATIONS INFORMATION
Write Word Protocol Used by the LTC1669
1
7
1
1
8
1
8
1
8
1
1
S
Slave Address Wr
A
Command Byte
A
LSData Byte
A
MSData Byte
A
P
1669 TA03
S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition
Serial Digital Interface
Write Word Protocol
The LTC1669 communicates with a host (master) using
the standard 2-wire interface. The Timing Diagram shows
the timing relationship of the signals on the bus. The two
bus lines, SDA and SCL, must be high when the bus is not
in use. External pull-up resistors or current sources, such
as the LTC1694 SMBus/I2C Accelerator, are required on
these lines.
The master initiates communication with the LTC1669
withaSTARTconditionanda7-bitaddressfollowedbythe
Write Bit (Wr) = 0. The LTC1669 acknowledges and the
master delivers the command byte. The LTC1669 ac-
knowledges and latches the command byte into the com-
mand byte input register. The master then delivers the
least significant data byte. Again the LTC1669 acknowl-
edges and the data is latched into the least significant data
byte input register. The master then delivers the most
significant data byte. The LTC1669 acknowledges once
more and latches the data into the most significant data
byte input register. Lastly, the master terminates the
communication with a STOP condition. On the reception
of the STOP condition, the LTC1669 transfers the input
register information to output registers and the DAC
output is updated.
The LTC1669 is a receive-only (slave) device. The master
can communicate with the LTC1669 using the Quick
Command, Send Byte or Write Word protocols as ex-
plained later.
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA
from high to low while SCL is high.
Slave Address (MSOP Package Only)
The LTC1669 can respond to one of eight 7-bit addresses.
The first 4 bits (MSBs) have been factory programmed to
0100. The first 4 bits of the LTC1669-8 have been factory
programmed to 0011. The three address bits, AD2, AD1
and AD0 are programmed by the user and determine the
LSBs of the slave address, as shown in the table below:
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generatedbytransitioningSDAfromlowtohighwhileSCL
is high. The bus is then free for communication with
another SMBus device.
LTC1669
0100 xxx
0100 000
0100 001
0100 010
0100 011
0100 100
0100 101
0100 110
0100 111
LTC-1669-8
0011 xxx
0011 000
0011 001
0011 010
0011 011
0011 100
0011 101
0011 110
0011 111
Acknowledge
AD2
L
AD1
L
AD0
L
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge re-
lated clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
line during the Acknowledge clock pulse so that it remains
a stable LOW during the HIGH period of this clock pulse.
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
H
H
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LTC1669
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APPLICATIONS INFORMATION
Slave Address (SOT-23 Package)
The Bandgap (BG) bit when set to “0” selects the DAC
supply voltage as its voltage reference. The full-scale
output of the DAC with this setting is equal to the supply
voltage. When the BG bit is set to “1,” the internal bandgap
reference(≈1.25V)isselectedastheDAC’sreference. The
full-scale output voltage for this setting is 2.5V.
The slave address for the SOT-23 package has been
factory programmed to be “0100 000” (LTC1669) and
“0100 001” (LTC1669-1). If another address is required,
please consult the factory.
Command Byte
Data Bytes
7
6
5
4
3
2
1
0
Least Significant Data Byte
X
X
X
X
X
BG
SD
SY
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
SY
1
0
Allows update on Acknowledge of SYNC Address only
Update on Stop condition only (Power-On Default)
Most Significant Data Byte
SD
1
0
Puts the device in power-down mode
Puts the device in standard operating mode
(Power-On Default)
7
6
5
4
3
2
1
0
X
X
X
X
X
X
D9
D8
X = Don’t care
BG
X
1
0
Selects the internal bandgap reference
Selects the supply as the reference (Power-On Default)
Send Byte Protocol
X
Don’t Care
The Send Byte protocol used on the LTC1669 is actually a
subset of the Write Word protocol described previously.
The Send Byte protocol can only be used to send the
command byte information to the LTC1669.
The stop condition normally initiates the update of the
DAC’s output latches. Simultaneous update of more than
one DAC or other devices on the bus can be achieved by
reissuing new start bit, address, command and data bytes
before issuing a final stop condition (which will update all
the devices). An alternate way to achieve simultaneous
LTC1669 updates is to override the stop condition update
by setting the “SY” bit of the command byte. Setting this
bit sets the device to update the DAC output latches only
at the reception of a SYNC address quick command. The
actual update occurs on the rising edge of SCL during the
Acknowledge. In this way, all devices can update on the
reception of the SYNC address quick command instead of
the STOP condition.
1
7
1
1
8
1
1
S
Slave Address Wr
A
Command Byte
A
P
S = Start Condition, Wr = Write Bit, A = Acknowledge, P = Stop Condition
1669 TA04
The Send Byte protocol is also used whenever the Write
Word protocol is interrupted for any reason. Reception of
a START or STOP condition after the Acknowledge of the
command byte, but before the Acknowledge of the last
data byte, will cause both data bytes to be ignored and the
command byte to be accepted.
Reception of a START or STOP condition before the
Acknowledge of the command byte will cause the inter-
rupted command byte to be ignored.
A Shutdown (SD) bit = HIGH will put the device in a low
powerstatebutretainalldatalatchinformation.Shutdown
will occur at the reception of a STOP condition. This way
shutdown could be synchronized to other devices. The
output impedance of the DAC will go to a high impedance
state (≈500kΩ to GND).
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LTC1669
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APPLICATIONS INFORMATION
SYNC Address/Quick Command
Rail-to-Rail Output Considerations
As in any rail-to-rail device, the output is limited to
voltages within the supply range.
In addition to the slave address, the LTC1669 has an
address that can be shared by other devices so that they
may be updated synchronously. The address is called to
the SYNC address and uses the quick command protocol.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.
The SYNC Address is 1111 110
Similarly, limiting can occur near full scale when VCC is
used as the reference. If VREF = VCC and the DAC full-scale
error (FSE) is positive, the output for the highest codes
limits at VCC as shown in Figure 1c. No full-scale limiting
can occur if the internal reference is used.
1
7
1
1
1
Start 1111 110
SYNC Address
SY/CLR
Ack
Stop
1669 TA05
SY/CLR
1
0
Update output latches on rising edge of SCL during
Acknowledge of SYNC Address
Clear all internal latches on rising edge of SCL during
Acknowledge of SYNC Address
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
Internal Reference
The SY/CLR bit set high only has meaning when the “SY”
bit of the command byte was previously set HIGH. On the
otherhand, the SY/CLR bit set LOW will always clear the
part, independent of the state of the “SY” bit in the
command byte.
In applications where a predictable output is required that
is independent of supply voltage, the LTC1669 has a user-
selectable internal reference. Selecting the internal refer-
ence will set the full-scale output voltage to 2.5V. This can
be useful in applications where the supply voltage is
poorly regulated.
Voltage Output
The output amplifier contained in the LTC1669 can source
or sink up to 5mA. The output stage swings to within a few
millivolts of either supply rail when unloaded and has an
equivalentoutputresistanceof85Ωwhendrivingaloadto
the rails. The output amplifier is stable driving capacitive
loads up to 1000pF.
Using the LT®1460 Micropower Series Reference as a
Power Supply for the LTC1669
In applications where the advantages of using the internal
reference are required but the full-scale range needs to be
greater than 2.5V, an external series reference can be
used. The LT1460 is ideal for use as a power supply for the
LTC1669 and can provide 3V, 3.3V and 5V full-scale
output voltage ranges. The LT1460 provides accuracy,
noiseimmunityandextendedsupplyrangetotheLTC1669
when the LTC1669 is operated ratiometric to VCC. Since
both parts are available in SOT-23 packages, the PC board
space for this application is extremely small. See Figure 2.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance greater
than 1000pF. For example, a 0.1µF load can be driven by
theLTC1669ifa110Ωseriesresistanceisused.Thephase
margin of the resulting circuit is 45° and increases mono-
tonically from this point if larger values of resistance, ca-
pacitance or both are substituted for the values given.
1669f
9
LTC1669
U
W U U
APPLICATIONS INFORMATION
POSITIVE
FSE
V
= V
CC
REF
OUTPUT
VOLTAGE
INPUT CODE
(c)
V
= V
CC
REF
OUTPUT
VOLTAGE
0
512
1023
INPUT CODE
(a)
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
1669 F01
Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
LT1460S3-3
3V
1
2
3.9V TO 20V
IN
OUT
+
GND
3
0.1µF
0.01µF
4 (5)
V
CC
5 (4)
SCL
SDA
3 (8)
TO
µP
LTC1669
OUT
0V ≤ V
≤ 3V
OUT
1 (1)
GND
LTC1669 PIN NUMBERS IN PARENTHESES
REFER TO MSOP PACKAGE
2 (7)
1669 F02
Figure 2. LT1460 As Power Supply for the LTC1669
1669f
10
LTC1669
U
PACKAGE DESCRIPTION
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
0.62
MAX
0.95
REF
2.90 BSC
(NOTE 4)
1.22 REF
1.50 – 1.75
(NOTE 4)
2.80 BSC
1.4 MIN
3.85 MAX 2.62 REF
PIN ONE
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
NOTE:
S5 TSOT-23 0302
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
0.52
(.0205)
REF
8
7 6
5
5.23
(.206)
MIN
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
3.20 – 3.45
(.126 – .136)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
0.65
(.0256)
BSC
0.42 ± 0.038
1
2
3
4
(.0165 ± .0015)
0.53 ± 0.152
(.021 ± .006)
TYP
1.10
(.043)
MAX
0.86
(.034)
REF
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.18
(.007)
SEATING
PLANE
NOTE:
0.22 – 0.38
(.009 – .015)
TYP
0.127 ± 0.076
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
(.005 ± .003)
0.65
(.0256)
BSC
MSOP (MS8) 0603
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
1669f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LTC1669
U
TYPICAL APPLICATION
Program Up to 16 Control Outputs Per BUS and Place Them Where They Are Needed
V
CC
= 2.7V TO 5.5V
1
V
CC
SMBus 1
5
4
+
LTC1694
0.1µF
SMBus 2
GND
2
+
5
0.1µF
4
1
V
SCL
SDA
CC
8
LTC1669CMS8
CONTROL
OUTPUT 0
0V ≤ V
6
2
3
V
OUT
AD0
AD1
AD2
< V
CC
SCL
µP
SDA
OUT0
GND
7
+
5
0.1µF
4
1
V
SCL
SDA
CC
8
LTC1669CMS8
CONTROL
OUTPUT 1
0V ≤ V
6
2
3
V
OUT
AD0
AD1
AD2
< V
CC
OUT1
GND
7
+
5
0.1µF
4
1
V
SCL
SDA
CC
8
LTC1669-8CMS8
CONTROL
OUTPUT 15
0V ≤ V
6
2
3
V
OUT
AD0
AD1
AD2
< V
CC
OUT15
GND
7
2
TO OTHER I
DEVICES
C
1669 TA06
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
2
LTC1694
SMBus/I C Accelerator
Dual SMBus Accelerator with Active AC and DC Pull-Up Current Sources
Dual SMBus Accelerator with Active AC Pull-Up Current Only
2
LTC1694-1
DACs
SMBus/I C Accelerator
LTC1659
Single Rail-to-Rail 12-Bit V
DAC in
Low Power Multiplying V
GND to REF. REF Input Can Be Tied to V . 3-Wire Interface.
DAC. Output Swings from
OUT
OUT
8-Lead MSOP Package. V = 2.7V to 5.5V
CC
CC
LTC1660/LTC1664
LTC1661
Octal/Quad 10-Bit V
DACs in 16-Pin Narrow SSOP
V
V
= 2.7V to 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface.
= 2.7V to 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface.
OUT
CC
CC
Dual 10-Bit V
in 8-Lead MSOP Package
OUT
LTC1663
10-Bit V
in SOT-23, SMBUS Interface
Pin-for-Pin Compatible with LTC1669
OUT
ADCs
LTC1285/LTC1288
LTC1286/LTC1298
8-Pin SO, 3V Micropower ADCs
8-Pin SO, 5V Micropower ADCs
1- or 2-Channel, Autoshutdown
1- or 2-Channel, Autoshutdown
1669f
LT/TP 1103 1K • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
12
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003
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