LTC1709EG#PBF_技术文档

LTC1709

2-Phase, 5-Bit Adjustable,

High Efficiency, Synchronous Step-Down

Switching Regulator

U

DESCRIPTIO

FEATURES

The LTC^®1709 is a 2-phase, VID programmable, synchro-

nous step-down switching regulator controller that drives

all N-channel external power MOSFET stages in a fixed

frequency architecture. The 2-phase controller drives its

two output stages out of phase at frequencies up to

300kHz to minimize the RMS ripple currents in both input

and output capacitors. The 2-phase technique effectively

multiplies the fundamental frequency by two, improving

transient response while operating each channel at a

optimum frequency for efficiency. Thermal design is also

simplified.

■

Two Ouput Stages Operate Antiphase Reducing

Input Capacitance and Power Supply Noise

5-Bit VID Control (VRM 8.4 Compliant)

V_OUT: 1.3V to 3.5V in 50mV/100mV Steps

Current Mode Control Ensures Current Sharing

True Remote Sensing Differential Amplifier

OPTI-LOOP^TMCompensation Minimizes C_OUT

Programmable Fixed Frequency: 150kHz to

300kHz—Effective 300kHz to 600kHz Switching

Frequency

■

±1% Output Voltage Accuracy

Wide V_INRange: 4V to 36V Operation

Adjustable Soft-Start Current Ramping

Internal Current Foldback

An internal differential amplifier provides true remote

sensing of the regulated supply’s positive and negative

output terminals as required in high current applications.

Short-Circuit Shutdown Timer with Defeat Option

Overvoltage Soft-Latch Eliminates Nuisance Trips

Low Shutdown Current: 20µA

The RUN/SS pin provides soft-start and optional timed,

short-circuit shutdown. Current foldback limits MOSFET

dissipatonduringshort-circuitconditionswhenovercurrent

latchoff is disabled. OPTI-LOOP compensation allows the

transient response to be optimized for a wide range of

output capacitors and ESR values.

Small 36-Lead Narrow (0.209") SSOP Package

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APPLICATIO S

■

Desktop Computers

■

Internet/Network Servers

■

Large Memory Arrays

■

DC Power Distribution Systems

, LTC and LT are registered trademarks of Linear Technology Corporation.

OPTI-LOOP is a trademark of Linear Technology Corporation.

■

Battery Chargers

U

TYPICAL APPLICATIO

V

IN

5V TO 28V

Efficiency Curve

10µF ×4

35V

0.1µF

100

90

Q1

Q2

V

TG1

BOOST 1

SW1

V

= 5V

OUT

= 200kHz

IN

RUN/SS

S

IN

0.002Ω

V

= 1.6V

0.47µF

f

S

1µH

S

LTC1709

1.2nF

BG1

15k

I

PGND

TH

SGND

80

+

S

SENSE1

–

5 VID BITS VID0–VID4

Q3

Q4

TG2

BOOST2

SW2

70

60

50

S

0.002Ω

EAIN

V

OUT

0.47µF

1.3V TO 3.5V

40A

1µH

FBOUT

SENSEIN

S

BG2

V

INTV

DIFFOUT

CC

+

C

10µF

OUT

+

–

SENSE 2

1000µF

4V

OS

0

5

10 15 20 25 30 35 40 45

LOAD CURRENTS (A)

+

–

OS

×2

1709 TA01a

Q1–Q4 2× FAIRCHILD FDS7760A OR SILICONIX Si4874

1709 TA01

Figure 1. High Current 2-Phase Step-Down Converter

1

LTC1709

W W

U W

U

W

U

ABSOLUTE AXI U RATI GS

(Note 1)

PACKAGE/ORDER I FOR ATIO

TOP VIEW

ORDER PART

NUMBER

Input Supply Voltage (V_IN).........................36V to –0.3V

Topside Driver Voltages (BOOST 1, 2).......42V to –0.3V

Switch Voltage (SW1, 2) .............................36V to –5 V

SENSE 1⁺, SENSE 2⁺, SENSE 1^–,

1

2

NC

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

RUNN/SS

+

TG1

SENSE 1

–

LTC1709EG

3

SW1

BOOST 1

SENSE 1

4

EAIN

PLLFLTR

PLLIN

SENSE 2^–Voltages....................... (1.1)INTV_CCto –0.3V

EAIN, V_OS⁺, V_OS^–, EXTV_CC, INTV_CC, RUN/SS,

AMPMD, V_BIAS, ATTENIN, ATTENOUT,

5

V

IN

6

BG1

7

EXTV

CC

NC

VID0–VID4, Voltages ...................................7V to –0.3V

Boosted Driver Voltage (BOOST-SW) ..........7V to –0.3V

PLLFLTR, PLLIN, V_DIFFOUTVoltages .... INTV_CCto –0.3V

8

INTV

CC

I

TH

9

PGND

BG2

SGND

10

11

12

13

14

15

16

17

18

V

DIFFOUT

BOOST 2

SW2

V

–

I_THVoltage................................................2.7V to –0.3V

OS

+

–

Peak Output Current <1µs(TGL1, 2; BG1, 2).............. 3A

INTV_CCRMS Output Current................................ 50mA

Operating Ambient Temperature Range

OS

TG2

SENSE 2

+

AMPMD

V

BIAS

ATTENOUT

ATTENIN

VID0

(Note 2) .................................................. –40°C to 85°C

Junction Temperature (Note 3)............................. 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

VID4

VID3

VID2

VID1

G PACKAGE

36-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 85°C/W

Consult factory for Industrial and Military grade parts.

ELECTRICAL CHARACTERISTICS ^The● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V, V_RUN/SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loop

V

Regulated Feedback Voltage

Maximum Current Sense Threshold

Feedback Current

(Note 4); I Voltage = 1.2V

●

0.792

62

0.800

75

0.808

88

V

mV

nA

EAIN

TH

–

V

= 5V

SENSEMAX

INEAIN

SENSE

I

(Note 4)

–5

–50

V

Output Voltage Load Regulation

LOADREG

Measured in Servo Loop; ∆I Voltage: 1.2V to 0.7V

●

0.1

–0.1

0.5

–0.5

%

TH

Measured in Servo Loop; ∆I Voltage: 1.2V to 2V

TH

V

Reference Voltage Line Regulation

Output Overvoltage Threshold

Undervoltage Lockout

V

= 3.6V to 30V (Note 4)

IN

0.002

0.86

3.5

0.02

0.88

4

%/V

V

REFLNREG

OVL

Measured at V

●

0.84

3

EAIN

UVLO

V

Ramping Down

V

IN

TH

g

Transconductance Amplifier g

I

= 1.2V; Sink/Source 5µA; (Note 4)

3

mmho

V/mV

m

Transconductance Amplifier Gain

= 1.2V; (g xZ ; No Ext Load); (Note 4)

1.5

mOL

m

L

I

Input DC Supply Current

Normal Mode

Shutdown

(Note 5)

Q

EXTV Tied to V ; V

= 5V

470

20

µA

CC

OUT OUT

V

= 0V

40

RUN/SS

I

Soft-Start Charge Current

RUN/SS Pin ON Arming

= 1.9V

Rising

–0.5

1.0

–1.2

1.5

µA

RUN/SS

V

1.9

V

RUN/SS

2

LTC1709

The ● denotes the specifications which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V, V_RUN/SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

Rising from 3V

MIN

TYP

4.1

2

MAX

4.5

4

UNITS

V

RUN/SS Pin Latchoff Arming

RUN/SS Discharge Current

V

RUN/SS

RUN/SSLO

SCL

I

Soft Short Condition V

= 0.5V;

0.5

µA

EAIN

V

= 4.5V

RUN/SS

I

Shutdown Latch Disable Current

Total Sense Pins Source Current

Maximum Duty Factor

V

= 0.5V

EAIN

1.6

–60

99.5

5

µA

%

SDLHO

SENSE

Each Channel: V

In Dropout

(Note 6)

C

–

– = V + + = 0V

SENSE1 , 2

–85

98

SENSE1 , 2

DF

MAX

Top Gate Transition Time:

Rise Time

Fall Time

TG1, 2 t

= 3300pF

30

40

90

ns

r

f

LOAD

Bottom Gate Transition Time:

Rise Time

Fall Time

(Note 6)

BG1, 2 t

C

= 3300pF

30

20

90

ns

r

f

LOAD

TG/BG t

Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

(Note 6)

= 3300pF Each Driver

1D

C

90

ns

LOAD

BG/TG t

Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

(Note 6)

= 3300pF Each Driver

2D

C

90

ns

LOAD

t

Minimum On-Time

Tested with a Square Wave (Note 7)

180

200

ON(MIN)

Internal V Regulator

CC

V

Internal V Voltage

6V < V < 30V; V = 4V

EXTVCC

4.8

4.5

5.0

0.2

120

4.7

0.2

5.2

1.0

240

V

%

INTVCC

CC

IN

INT

INTV Load Regulation

I

= 0 to 20mA; V

= 4V

EXTVCC

LDO

CC

EXT

EXTV Voltage Drop

= 20mA; V

= 5V

mV

V

CC

EXTVCC

EXTV Switchover Voltage

= 20mA, EXTV Ramping Positive

●

EXTVCC

LDOHYS

CC

EXTV Switchover Hysteresis

= 20mA, EXTV Ramping Negative

V

CC

VID Parameters

R

ATTEN

Resistance Between ATTENIN and

ATTENOUT Pins

20

kΩ

ATTEN

Resistive Divider Worst-Case Error

Programmed from 1.3V to 2.05V (VID4 = 0)

Programmed from 2.1V to 3.5V (VID4 = 1)

●

–0.25

–0.35

+0.25

%

ERR

R

VID0–VID4 Pull-Up Resistance

VID0–VID4 Logic Threshold Low

VID0–VID4 Logic Threshold High

VID0–VID4 Leakage

(Note 8)

40

kΩ

V

PULLUP

VID

0.4

1

THLOW

THHIGH

LEAK

1.6

V

< VID0–VID4 < 7V

µA

BIAS

Oscillator and Phase-Locked Loop

f

Nominal Frequency

Lowest Frequency

Highest Frequency

PLLIN Input Resistance

V

= 1.2V

= 0V

190

120

280

220

140

310

50

250

160

360

kHz

kΩ

NOM

LOW

HIGH

PLLFLTR

≥ 2.4V

R

PLLIN

I

Phase Detector Output Current

Sinking Capability

Sourcing Capability

PLLFLTR

f

< f

> f

–15

15

µA

PLLIN

OSC

R

Controller 2-Controller 1 Phase

180

Deg

RELPHS

Differential Amplifier/Op Amp Gain Block (Note 9)

A

Gain

Differential Amp Mode

Differential Amp Mode; 0V < V < 5V

0.995

46

1

1.005

V/V

dB

DA

CMRR

Common Mode Rejection Ratio

55

DA

CM

3

LTC1709

The ● denotes the specifications which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V, V_RUN/SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

Differential Amp Mode; Measured at V + Input

MIN

TYP

MAX

UNITS

kΩ

R

IN

Input Resistance

Input Offset Voltage

80

OS

V

Op Amp Mode; V = 2.5V; V = 5V;

DIFFOUT

6

mV

OS

CM

I

= 1mA

DIFFOUT

I

Input Bias Current

Op Amp Mode

30

200

nA

V/mV

V

B

A

V

Open Loop DC Gain

Op Amp Mode; 0.7V ≤ V

Op Amp Mode

< 10V

DIFFOUT

5000

OL

Common Mode Input Voltage Range

Common Mode Rejection Ratio

Power Supply Rejection Ratio

Maximum Output Current

Maximum Output Voltage

Gain-Bandwidth Product

Slew Rate

0

3

CM

CMRR

Op Amp Mode; 0V < V < 3V

70

10

90

35

11

2

dB

OA

CM

PSRR

Op Amp Mode; 6V < V < 30V

dB

OA

IN

I

Op Amp Mode; V

= 0V

mA

V

CL

DIFFOUT

V

Op Amp Mode; I

= 1mA

O(MAX)

GBW

SR

MHz

V/µs

Op Amp Mode; R = 2k

5

L

Note 1: Absolute Maximum Ratings are those values beyond which the

life of a device may be impaired.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 2: The LTC1709EG is guaranteed to meet performance specifications

from 0°C to 70°C. Specifications over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls.

Note 7: The minimum on-time condition corresponds to the on inductor

peak-to-peak ripple current ≥40% I

(see Minimum On-Time

MAX

Considerations in the Applications Information section).

Note 8: Each built-in pull-up resistor attached to the VID inputs also has a

Note 3: T is calculated from the ambient temperature T and power

series diode to allow input voltages higher than the VIDV supply without

damage or clamping (see the Applications Information section).

J

A

CC

dissipation P according to the following formulas:

D

LTC1709EG: T = T + (P • 85°C/W)

Note 4: The LTC1709 is tested in a feedback loop that servos V to a

specified voltage and measures the resultant V

Note 5: Dynamic supply current is higher due to the gate charge being

Note 9: When the AMPMD pin is high, the IC pins are connected directly to

the internal op amp inputs. When the AMPMD pin is low, internal MOSFET

switches connect four 40k resistors around the op amp to create a

standard unity-gain differential amp.

J

A

D

ITH

.

EAIN

delivered at the switching frequency. See Applications Information.

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TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Output Current

(Figure 12)

Efficiency vs Output Current

(Figure 12)

Efficiency vs Input Voltage

(Figure 12)

100

80

60

40

20

0

100

90

100

80

60

40

20

0

V

OUT

= 3.3V

= 5V

= 20A

V

= 2V

OUT

EXTVCC

OUT

IN

= 12V

I

f = 200kHz

V

= 5V

IN

= 8V

= 12V

= 20V

V

= 5V

= 0V

EXTVCC

80

V

= 2V

OUT

EXTVCC

INTERNAL LDO VS EXTERNALLY

APPLIED 5V OVERALL EFFICIENCY

(FIGURE 12)

= 0V

f = 200kHz

70

0.1

1

10

100

0.1

1

10

100

5

10

15

20

OUTPUT CURRENT (A)

V

IN

(V)

OUTPUT CURRENT (A)

1709 G01

1709 G02

1709 G03

4

LTC1709

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Supply Current vs Input Voltage

and Mode

INTV_CCand EXTV_CCSwitch

Voltage vs Temperature

EXTV_CCVoltage Drop

1000

800

600

400

200

0

250

200

150

100

50

5.05

5.00

4.95

4.90

4.85

4.80

4.75

4.70

INTV VOLTAGE

CC

ON

EXTV SWITCHOVER THRESHOLD

CC

SHUTDOWN

10 15

INPUT VOLTAGE (V)

0

5

20

25

30

35

0

10

20

30

40

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

CURRENT (mA)

1709 G04

1709 G05

1709 G06

Maximum Current Sense Threshold

vs Percent of Nominal Output

Voltage (Foldback)

Maximum Current Sense Threshold

vs Duty Factor

Internal 5V LDO Line Reg

75

5.1

5.0

80

70

60

50

40

30

20

10

0

I

= 1mA

LOAD

4.9

4.8

4.7

4.6

4.5

50

25

0

4.4

0

20

40

60

80

100

20

10

INPUT VOLTAGE (V)

30

35

0

25

50

75

100

0

5

15

25

DUTY FACTOR (%)

PERCENT ON NOMINAL OUTPUT VOLTAGE (%)

1709 G08

1709 G07

1709 G09

Current Sense Threshold

vs I_THVoltage

Maximum Current Sense Threshold

vs V_RUN/SS(Soft-Start)

Maximum Current Sense Threshold

vs Sense Common Mode Voltage

80

90

80

60

40

20

V

= 1.6V

SENSE(CM)

70

76

72

68

64

60

50

40

30

20

10

0

–10

–20

–30

0

1

2

3

4

5

0

1

2

3

4

5

6

0

0.5

1

1.5

(V)

2

2.5

V

(V)

COMMON MODE VOLTAGE (V)

V

RUN/SS

ITH

1709 G11

1709 G10

1709 G12

5

LTC1709

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Load Regulation

V_ITHvs V_RUN/SS

SENSE Pins Total Source Current

0.0

–0.1

–0.2

–0.3

–0.4

2.5

2.0

1.5

1.0

100

50

FCB = 0V

= 15V

V

= 0.7V

OSENSE

V

IN

FIGURE 1

0

–50

–100

0.5

0

1

2

3

4

5

0

2

3

4

5

6

0

2

4

6

1

V

(V)

LOAD CURRENT (A)

V

COMMON MODE VOLTAGE (V)

RUN/SS

SENSE

1709 G13

1709 G14

1709 G15

Maximum Current Sense

Threshold vs Temperature

Soft-Start Up (Figure 12)

RUN/SS Current vs Temperature

80

78

76

74

72

70

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

V_ITH

1V/DIV

V_OUT

2V/DIV

V_RUNSS

2V/DIV

100ms/DIV

1629 G19

0

–50 –25

0

25

50

75 100 125

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

1709 G17

1709 G18

Load Step Response Using Active

Voltage Positioning (Figure 12)

Current Sense Pin Input Current

vs Temperature

EXTV_CCSwitch Resistance

vs Temperature

35

33

31

29

27

25

10

8

EXTV = 5V

CC

V_OUT

50mV/DIV

6

20A

I_OUT

10A/DIV

4

0A

2

20µs/DIV

1709 G20

0

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

1709 G21

1709 G22

6

LTC1709

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Oscillator Frequency

vs Temperature

Undervoltage Lockout

vs Temperature

V_RUN/SSShutdown Latch

Thresholds vs Temperature

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

350

300

3.50

3.45

3.40

3.35

V

= 5V

FREQSET

LATCH ARMING

250

200

150

100

50

LATCHOFF

THRESHOLD

V

= OPEN

= 0V

FREQSET

V

FREQSET

3.30

3.25

3.20

0

50

100 125

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

TEMPERATURE (°C)

125

–50 –25

0

25

75

–50 –25

0

25

75

50

75 100

TEMPERATURE (°C)

1709 G23

1709 G24

1709 G25

U

PI FU CTIO S

RUN/SS (Pin 1): Combination of Soft-Start, Run Control

Input and Short-Circuit Detection Timer. A capacitor to

groundatthispinsetstheramptimetofullcurrentoutput.

Forcing this pin below 0.8V causes the IC to shut down all

internal circuitry. All functions are disabled in shutdown.

SENSE 1⁺, SENSE 2⁺(Pins 2,14): The (+) Input to Each

Differential Current Comparator. The I_THpin voltage and

built-in offsets between SENSE^–and SENSE⁺pins in

conjunction with R_SENSEset the current trip threshold.

NC (Pins 7, 36): Do not connect.

_TH(Pin 8): Error Amplifier Output and Switching Regula-

torCompensationPoint.Bothcurrentcomparator’sthresh-

oldsincreasewiththiscontrolvoltage. Thenormalvoltage

range of this pin is from 0V to 2.4V

I

SGND (Pin 9): Signal Ground, common to both control-

lers. Route separately to the PGND pin.

V_DIFFOUT(Pin 10): Output of a Differential Amplifier that

provides true remote output voltage sensing. This pin

normally drives an external resistive divider that sets the

output voltage.

SENSE 1^–, SENSE 2^–(Pins 3, 13): The (–) Input to the

Differential Current Comparators.

EAIN (Pin 4): Input to the Error Amplifier that compares

thefeedbackvoltagetotheinternal0.8Vreferencevoltage.

This pin is normally connected to a resistive divider from

the output of the differential amplifier (DIFFOUT).

V_OS^–, V_OS⁺(Pins 11, 12): Inputs to an Operational Ampli-

fier. Internal precision resistors capable of being elec-

tronically switched in or out can configure it as a differen-

tial amplifier or an uncommitted Op Amp.

PLLFLTR (Pin 5): The Phase-Locked Loop’s Low Pass

Filter is tied to this pin. Alternatively, this pin can be driven

with an AC or DC voltage source to vary the frequency of

the internal oscillator.

ATTENOUT (Pin 15): Voltage Feedback Signal Resistively

Divided According to the VID Programming Code.

ATTENIN (Pin 16): The Input to the VID Controlled Resis-

tive Divider.

PLLIN (Pin 6): External Synchronization Input to Phase

Detector. This pin is internally terminated to SGND with

50kΩ. The phase-locked loop will force the rising top gate

signal of controller 1 to be synchronized with the rising

edge of the PLLIN signal.

VID0–VID4 (Pins 17,18, 19, 20, 21): VID Control Logic

Input Pins.

V

_BIAS(Pin 22): Supply Pin for the VID Control Circuit.

7

LTC1709

U

PI FU CTIO S

AMPMD (Pin 23): This Logic Input pin controls the

connections of internal precision resistors that configure

the operational amplifier as a unity-gain differential

amplifier.

PGND (Pin 28): Driver Power Ground, connect to sources

of bottom N-channel MOSFETS and the (–) terminals of

C_IN.

INTV_CC(Pin 29): Output of the Internal 5V Linear Low

Dropout Regulator and the EXTV_CCSwitch. The driver and

control circuits are powered from this voltage source.

Decouple to power ground with a 1µF ceramic capacitor

placed directly adjacent to the IC and minimum of 4.7µF

additional tantalum or other low ESR capacitor.

TG2, TG1 (Pins 24, 35): High Current Gate Drives for Top

N-Channel MOSFETS. These are the outputs of floating

drivers with a voltage swing equal to INTV_CCsuperim-

posed on the switch node voltage SW.

SW2, SW1 (Pins 25, 34): Switch Node Connections to

Inductors. Voltage swing at these pins is from a Schottky

diode (external) voltage drop below ground to V_IN.

EXTV_CC(Pin 30): External Power Input to an Internal

Switch . This switch closes and supplies INTV_CC,bypass-

ing the internallow dropout regulator whenever EXTV_CCis

higher than 4.7V. See EXTV_CCConnection in the Applica-

tions Information section. Do not exceed 7V on this pin

and ensure V_EXTVCC≤ V_IN.

BOOST 2, BOOST 1 (Pins 26, 33): Bootstrapped Supplies

to the Topside Floating Drivers. External capacitors are

connectedbetweentheBoostandSwitchpins,andSchottky

diodes are connected between the Boost and INTV_CCpins.

V_IN(Pin32):MainSupplyPin.Shouldbecloselydecoupled

to the IC’s signal ground pin.

BG2, BG1 (Pins 27, 31): High Current Gate Drives for

Bottom N-Channel MOSFETS. Voltage swing at these pins

is from ground to INTV_CC.

8

LTC1709

U

U W

FU CTIO AL DIAGRA

PLLIN

INTV

CC

V

IN

PHASE DET

F

IN

50k

PLLFLTR

D

C

DUPLICATE FOR

SECOND CHANNEL

B

BOOST

TG

R

C

LP

B

DROP

OUT

DET

+

CLK1

CLK2

TOP

BOT

C

LP

IN

OSCILLATOR

BOT

FORCE BOT

SW

S

R

Q

TO

SWITCH

LOGIC

INTV

CC

SECOND

BG

CHANNEL

PGND*

–

+

V

OS

SHDN

A1

–

+

INTV

CC

I1

–

L

–

+

SENSE

30k

4(V

)

FB

–

C

OUT

R

SENSE

AMPMD

DIFFOUT

SLOPE

COMP

0V POSITION

45k

2.4V

V

OUT

EAIN

V

0.8V

REF

FB

V

IN

–

EA

V

IN

+

0.80V

0.86V

+

–

4.7V

OV

5V

LDO

REG

+

–

EXTV

CC

V

IN

C

I

TH

1.2µA

INTV

CC

5V

+

SHDN

RST

RUN

R

C

SOFT-

4(V

FB

)

START

INTERNAL

SUPPLY

SGND

6V

RUN/SS

R2

20k

C

SS

ATTENIN

5-BIT VID DECODER

ATTENOUT

TYPICAL ALL

VID PINS

40k

R1

R1 VARIABLE

VID0

VID1

VID2

VID3

VID4

V

BIAS

1709 FBD

9

LTC1709

U

(Refer to Functional Diagram)

OPERATIO

Main Control Loop

Low Current Operation

The LTC1709 uses a constant frequency, current mode

step-down architecture with inherent current sharing.

During normal operation, the top MOSFET is turned on

each cycle when the oscillator sets the RS latch, and

turned off when the main current comparator, I1, resets

the RS latch. The peak inductor current at which I1 resets

the RS latch is controlled by the voltage on the I_THpin,

which is the output of the error amplifier EA. The differen-

tialamplifier,A1,producesasignalequaltothedifferential

voltage sensed across the output capacitor but re-refer-

ences it to the internal signal ground (SGND) reference.

The EAIN pin receives a portion of this voltage feedback

signal at the DIFFOUT as determined by VID logic input

pins (VID0 to VID4) and is compared to the internal

reference voltage by the EA. When the load current in-

creases, it causes a slight decrease in the EAIN pin voltage

relative to the 0.8V reference, which in turn causes the I_TH

voltage to increase until the average inductor current

matches the new load current. After the top MOSFET has

turned off, the bottom MOSFET is turned on for the rest of

the period.

The LTC1709 operates in a continuous, PWM control

mode. The resulting operation at low output currents

optimizes transient response at the expense of substantial

negative inductor current during the latter part of the

period. The level of ripple current is determined by the

inductor value, input voltage, output voltage, and fre-

quency of operation.

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be

synchronized to an external source via the PLLIN pin. The

output of the phase detector at the PLLFLTR pin is also the

DC frequency control input of the oscillator that operates

over a 140kHz to 310kHz range corresponding to a DC

voltageinputfrom0Vto2.4V.Whenlocked,thePLLaligns

the turn on of the top MOSFET to the rising edge of the

synchronizingsignal.WhenPLLINisleftopen,thePLLFLTR

pingoeslow,forcingtheoscillatortominimumfrequency.

InputcapacitanceESRrequirementsandefficiencylosses

are substantially reduced because the peak current drawn

from the input capacitor is effectively divided by two and

power loss is proportional to the RMS current squared. A

two stage, single output voltage implementation can re-

duce input path power loss by 75% and radically reduce

the required RMS current rating of the input capacitor(s).

The top MOSFET drivers are biased from floating boot-

strap capacitor C_B, which normally is recharged during

each off cycle through an external Schottky diode. When

V_INdecreasestoavoltageclosetoV_OUT,however,theloop

may enter dropout and attempt to turn on the top MOSFET

continuously. A dropout detector detects this condition

and forces the top MOSFET to turn off for about 400ns

every 10th cycle to recharge the bootstrap capacitor, C_B.

INTV_CC/EXTV_CCPower

Power for the top and bottom MOSFET drivers and most

of the IC circuitry is derived from INTV_CC. When the

EXTV_CCpin is left open, an internal 5V low dropout

regulator supplies INTV_CCpower. If the EXTV_CCpin is

taken above 4.7V, the 5V regulator is turned off and an

internalswitchisturnedonconnectingEXTV_CCtoINTV_CC.

This allows the INTV_CCpower to be derived from a high

efficiency external source such as the output of the regu-

lator itself or a secondary winding, as described in the

Applications Information section. An external Schottky

diode can be used to minimize the voltage drop from

EXTV_CCto INTV_CCin applications requiring greater than

the specified INTV_CCcurrent. Voltages up to 7V can be

applied to EXTV_CCfor additional gate drive capability.

The main control loop is shut down by pulling Pin 1 (RUN/

SS) low. Releasing RUN/SS allows an internal 1.2µA

current source to charge soft-start capacitor C_SS. When

C_SSreaches1.5V,themaincontrolloopisenabledwiththe

I_THvoltageclampedatapproximately30%ofitsmaximum

value. As C_SScontinues to charge, I_THis gradually re-

leased allowing normal operation to resume. When the

RUN/SS pin is low, all LTC1709 functions are shut down.

IfV_OUThasnotreached70%ofitsnominalvaluewhenC_SS

has charged to 4.1V, an overcurrent latchoff can be

invoked as described in the Applications Information

section.

10

LTC1709

U

(Refer to Functional Diagram)

OPERATIO

Differential Amplifier

Short-Circuit Detection

This amplifier provides true differential output voltage

sensing. Sensing both V_OUT⁺and V_OUT^–benefits regula-

tion in high current applications and/or applications hav-

ing electrical interconnection losses. The AMPMD pin

allows selection of internal, precision feedback resistors

for high common mode rejection differencing applica-

tions, or direct access to the actual amplifier inputs

withouttheseinternalfeedbackresistorsforotherapplica-

tions. The AMPMD pin is grounded to connect the internal

precisionresistorsinaunity-gaindifferencingapplication,

or tied to the INTV_CCpin to bypass the internal resistors

and make the amplifier inputs directly available. The

amplifier is a unity-gain stable, 2MHz gain-bandwidth,

>120dB open-loop gain design. The amplifier has an

output slew rate of 5V/µs and is capable of driving capaci-

tive loads with an output RMS current typically up to

35mA. The amplifier is not capable of sinking current and

therefore must be resistively loaded to do so.

The RUN/SS capacitor is used initially to limit the inrush

current from the input power source. Once the controllers

have been given time, as determined by the capacitor on

the RUN/SS pin, to charge up the output capacitors and

provide full-load current, the RUN/SS capacitor is then

usedasashort-circuittimeoutcircuit.Iftheoutputvoltage

falls to less than 70% of its nominal output voltage the

RUN/SS capacitor begins discharging assuming that the

output is in a severe overcurrent and/or short-circuit

condition. If the condition lasts for a long enough period

as determined by the size of the RUN/SS capacitor, the

controller will be shut down until the RUN/SS pin voltage

is recycled. This built-in latchoff can be overidden by

providing a current >5µA at a compliance of 5V to the

RUN/SS pin. This current shortens the soft-start period

but also prevents net discharge of the RUN/SS capacitor

during a severe overcurrent and/or short-circuit condi-

tion.Foldbackcurrentlimitingisactivatedwhentheoutput

voltage falls below 70% of its nominal level whether or not

the short-circuit latchoff circuit is enabled.

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APPLICATIO S I FOR ATIO

ThebasicLTC1709applicationcircuitisshowninFigure 1

on the first page. External component selection begins

with the selection of the inductor(s) based on ripple

current requirements and continues with the R_{SENSE1, 2}

resistor selection using the calculated peak inductor cur-

rent and/or maximum current limit. Next, the power

MOSFETs and D1 and D2 are selected. The operating

frequency and the inductor are chosen based mainly on

the amount of ripple current. Finally, C_INis selected for its

ability to handle the input ripple current (that PolyPhase^TM

operationminimizes)andC_OUTischosenwithlowenough

ESR to meet the output ripple voltage and load step

specifications (also minimized with PolyPhase). Current

mode architecture provides inherent current sharing be-

tween output stages. The circuit shown in Figure 1 can be

configured for operation up to an input voltage of 28V

(limited by the external MOSFETs).

current. The LTC1709 current comparator has a maxi-

mum threshold of 75mV/R_SENSEand an input common

mode range of SGND to 1.1( INTV_CC). The current com-

parator threshold sets the peak inductor current, yielding

a maximum average output current I_MAXequal to the peak

value less half the peak-to-peak ripple current, ∆I_L.

Allowing a margin for variations in the LTC1709 and

external component values yields:

R

_SENSE= 2(50mV/I_MAX

)

Operating Frequency

The LTC1709 uses a constant frequency, phase-lockable

architecture with the frequency determined by an internal

capacitor. This capacitor is charged by a fixed current plus

an additional current which is proportional to the voltage

applied to the PLLFLTR pin. Refer to Phase-Locked Loop

and Frequency Synchronization in the Applications Infor-

mation section for additional information.

R_SENSESelection For Output Current

R_{SENSE1, 2}are chosen based on the required peak output

PolyPhase is a registered trademark of Linear Technology Corporation.

11

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A graph for the voltage applied to the PLLFLTR pin vs

frequency is given in Figure 2. As the operating frequency

isincreasedthegatechargelosseswillbehigher,reducing

efficiency (see Efficiency Considerations). The maximum

switching frequency is approximately 310kHz.

In a 2-phase converter, the net ripple current seen by the

output capacitor is much smaller than the individual

inductor ripple currents due to ripple cancellation. The

details on how to calculate the net output ripple current

can be found in Application Note 77.

Figure 3 shows the net ripple current seen by the output

capacitors for the 1- and 2- phase configurations. The

outputripplecurrentisplottedforafixedoutputvoltageas

the duty factor is varied between 10% and 90% on the

x-axis. The output ripple current is normalized against the

inductor ripple current at zero duty factor. The graph can

be used in place of tedious calculations, simplifying the

design process.

2.5

2.0

1.5

1.0

0.5

0

Accepting larger values of ∆I_Lallows the use of low

inductances, butcanresultinhigheroutputvoltageripple.

A reasonable starting point for setting ripple current is ∆I_L

=0.4(I_OUT)/2,whereI_OUTisthetotalloadcurrent.Remem-

ber, the maximum ∆I_Loccurs at the maximum input

voltage. The individual inductor ripple currents are deter-

mined by the inductor, input and output voltages.

1.0

120

170

220

270

320

OPERATING FREQUENCY (kHz)

1709 F02

Figure 2. Operating Frequency vs V_PLLFLTR

Inductor Value Calculation and Output Ripple Current

1-PHASE

2-PHASE

0.9

0.8

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because

MOSFET gate charge and transition losses increase di-

rectly with frequency. In addition to this basic tradeoff, the

effect of inductor value on ripple current and low current

operation must also be considered. The PolyPhase ap-

proach reduces both input and output ripple currents

while optimizing individual output stages to run at a lower

fundamental frequency, enhancing efficiency.

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

1709 F03

Figure 3. Normalized Output Ripple Current vs

Duty Factor [I_RMS≈ 0.3 (∆I_O(P–P))]

Theinductorvaluehasadirecteffectonripplecurrent.The

inductor ripple current ∆I_Lper individual section, N,

decreases with higher inductance or frequency and in-

Inductor Core Selection

Once the values for L1 and L2 are known, the type of

inductor must be selected. High efficiency converters

generally cannot afford the core loss found in low cost

powdered iron cores, forcing the use of more expensive

ferrite, molypermalloy, or Kool Mµ^®cores. Actual core

loss is independent of core size for a fixed inductor value,

creases with higher V_INor V_OUT

:

V_OUT

fL

V_OUT

V

IN

∆I_L=

1−

where f is the individual output stage operating frequency.

Kool Mµ is a registered trademark of Magnetics, Inc.

12

LTC1709

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APPLICATIO S I FOR ATIO

but it is very dependent on inductance selected. As induc-

tance increases, core losses go down. Unfortunately,

increased inductance requires more turns of wire and

therefore copper losses will increase.

V_OUT

V

IN

Main SwitchDuty Cycle =

V – V_OUT

IN

Synchronous SwitchDuty Cycle =

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

V

IN

The MOSFET power dissipations at maximum output

current are given by:

2

V_OUTI_MAX

P_MAIN

=

1+ δ R_DS(ON)

+

(

)

V

IN

2

Molypermalloy (from Magnetics, Inc.) is a very good, low

losscorematerialfortoroids,butitismoreexpensivethan

ferrite. A reasonable compromise from the same manu-

facturer is Kool Mµ. Toroids are very space efficient,

especially when you can use several layers of wire. Be-

cause they lack a bobbin, mounting is more difficult.

However, designs for surface mount are available which

do not increase the height significantly.

2

)

I_MAX

2

k V

C_RSS

f

(

IN

(

)( )

2

V – V_OUTI_MAX

IN

P_SYNC

=

1+ δ R_DS(ON)

(

)

V

IN

2

where δ is the temperature dependency of R_DS(ON)and k

is a constant inversely related to the gate drive current.

Power MOSFET, D1 and D2 Selection

Both MOSFETs have I²R losses but the topside N-channel

equation includes an additional term for transition losses,

which peak at the highest input voltage. For V_IN< 20V the

high current efficiency generally improves with larger

MOSFETs, while for V_IN> 20V the transition losses rapidly

increasetothepointthattheuseofahigherR_DS(ON)device

with lower C_RSSactual provides higher efficiency. The

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during a

short-circuit when the synchronous switch is on close to

100% of the period.

Two external power MOSFETs must be selected for each

output stage for the LTC1709: One N-channel MOSFET for

the top (main) switch, and one N-channel MOSFET for the

bottom (synchronous) switch.

The peak-to-peak drive levels are set by the INTV_CCvolt-

age. This voltage is typically 5V during start-up (see

EXTV_CCPinConnection).Consequently,logic-levelthresh-

old MOSFETs must be used in most applications. The only

exception is if low input voltage is expected (V_IN< 5V);

then, sublogic-level threshold MOSFETs (V_GS(TH)< 1V)

should be used. Pay close attention to the BV_DSSspecifi-

cation for the MOSFETs as well; most of the logic-level

MOSFETs are limited to 30V or less.

The term (1 + δ) is generally given for a MOSFET in the

form of a normalized R_DS(ON)vs. Temperature curve, but

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs. C_RSSis usually specified in the MOS-

FET characteristics. The constant k = 1.7 can be used to

estimate the contributions of the two terms in the main

switch dissipation equation.

SelectioncriteriaforthepowerMOSFETsincludethe“ON”

resistance R_DS(ON), reverse transfer capacitance C_RSS

,

input voltage, and maximum output current. When the

LTC1709isoperatingincontinuousmodethedutyfactors

for the top and bottom MOSFETs of each output stage are

given by:

TheSchottkydiodes,D1andD2showninFigure1conduct

during the dead-time between the conduction of the two

large power MOSFETs. This helps prevent the body diode

13

LTC1709

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APPLICATIO S I FOR ATIO

of the bottom MOSFET from turning on, storing charge

during the dead-time, and requiring a reverse recovery

period which would reduce efficiency. A 1A to 3A Schottky

(depending on output current) diode is generally a good

compromise for both regions of operation due to the

relatively small average current. Larger diodes result in

additional transition losses due to their larger junction

capacitance.

These worst-case conditions are commonly used for

design because even significant deviations do not offer

much relief. Note that capacitor manufacturer’s ripple

current ratings are often based on only 2000 hours of life.

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may also be paralleled to

meet size or height requirements in the design. Always

consult the capacitor manufacturer if there is any

question.

C_INand C_OUTSelection

In continuous mode, the source current of each top

It is important to note that the efficiency loss is propor-

tional to the input RMS current squared and therefore a

2-phase implementation results in 75% less power loss

when compared to a single phase design. Battery/input

protection fuse resistance (if used), PC board trace and

connector resistance losses are also reduced by the re-

ductionoftheinputripplecurrentina2-phasesystem.The

requiredamountofinputcapacitanceisfurtherreducedby

the factor, 2, due to the effective increase in the frequency

of the current pulses.

N-channel MOSFET is a square wave of duty cycle V_OUT

/

V_IN. A low ESR input capacitor sized for the maximum

RMS current must be used. The details of a closed form

equation can be found in Application Note 77. Figure 4

shows the input capacitor ripple current for a 2-phase

configuration with the output voltage fixed and input

voltage varied. The input ripple current is normalized

against the DC output current. The graph can be used in

place of tedious calculations. The minimum input ripple

currentcanbeachievedwhentheinputvoltageistwicethe

output voltage

The selection of C_OUTis driven by the required effective

series resistance (ESR). Typically once the ESR require-

ment has been met, the RMS current rating generally far

exceeds the I_RIPPLE(P-P)requirements. The steady state

output ripple (∆V_OUT) is determined by:

In the graph of Figure 4, the 2-phase local maximum input

RMS capacitor currents are reached when:

V_OUT2k − 1

=

1

V

IN

4

∆V_OUT≈ ∆I_RIPPLEESR +

16fC_OUT

where k = 1, 2.

Where f = operating frequency of each stage, C_OUT

=

0.6

output capacitance and ∆I_RIPPLE= combined inductor

ripple currents.

0.5

0.4

0.3

0.2

0.1

0

The output ripple varies with input voltage since ∆I_Lis a

functionofinputvoltage.Theoutputripplewillbelessthan

50mV at max V_INwith ∆I_L= 0.4I_OUT(MAX)/2 assuming:

1-PHASE

2-PHASE

C_OUTrequired ESR < 4(R_SENSE) and

C_OUT> 1/(16f)(R_SENSE

)

The emergence of very low ESR capacitors in small,

surface mount packages makes very physically small

implementations possible. The ability to externally com-

pensatetheswitchingregulatorloopusingtheI_THpin(OPTI-

LOOP compensation) allows a much wider selection of

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

1709 F04

Figure 4. Normalized RMS Input Ripple Current vs

Duty Factor for 1 and 2 Output Stages

14

LTC1709

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output capacitor types. OPTI-LOOP compensation effec-

tively removes constraints on output capacitor ESR. The

impedance characteristics of each capacitor type are sig-

nificantly different than an ideal capacitor and therefore

require accurate modeling or bench evaluation during

design.

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC1709 to be

exceeded. The supply current is dominated by the gate

charge supply current, in addition to the current drawn

from the differential amplifier output. The gate charge is

dependent on operating frequency as discussed in the

Efficiency Considerations section. The supply current can

either be supplied by the internal 5V regulator or via the

EXTV_CCpin. When the voltage applied to the EXTV_CCpin

is less than 4.7V, all of the INTV_CCload current is supplied

by the internal 5V linear regulator. Power dissipation for

the IC is higher in this case by (I_IN)(V_IN– INTV_CC) and

efficiency is lowered. The junction temperature can be

estimated by using the equations given in Note 1 of the

Electrical Characteristics. For example, the LTC1709 V_IN

current is limited to less than 24mA from a 24V supply:

Manufacturers such as Nichicon, United Chemicon and

Sanyoshouldbeconsideredforhighperformancethrough-

hole capacitors. The OS-CON semiconductor dielectric

capacitor available from Sanyo and the Panasonic SP

surface mount types have the lowest (ESR)(size) product

of any aluminum electrolytic at a somewhat higher price.

An additional ceramic capacitor in parallel with OS-CON

type capacitors is recommended to reduce the inductance

effects.

In surface mount applications, multiple capacitors may

have to be paralleled to meet the ESR or RMS current

handling requirements of the application. Aluminum elec-

trolytic and dry tantalum capacitors are both available in

surface mount configurations. New special polymer sur-

face mount capacitors offer very low ESR also but have

muchlowercapacitivedensityperunitvolume. Inthecase

oftantalum,itiscriticalthatthecapacitorsaresurgetested

for use in switching power supplies. Several excellent

choices are the AVX TPS, AVX TPSV or the KEMET T510

seriesofsurfacemounttantalums,availableincaseheights

ranging from 2mm to 4mm. Other capacitor types include

Sanyo OS-CON, Nichicon PL series and Sprague 595D

series. Consultthemanufacturerforotherspecificrecom-

mendations. A combination of capacitors will often result

in maximizing performance and minimizing overall cost

and size.

T_J= 70°C + (24mA)(24V)(85°C/W) = 119°C

Use of the EXTV_CCpin reduces the junction temperature

to:

T_J= 70°C + (24mA)(5V)(85°C/W) = 80.2°C

The input supply current should be measured while the

controller is operating in continuous mode at maximum

V_INand the power dissipation calculated in order to pre-

vent the maximum junction temperature from being ex-

ceeded.

EXTV_CCConnection

The LTC1709 contains an internal P-channel MOSFET

switch connected between the EXTV_CCand INTV_CCpins.

When the voltage applied to EXTV_CCrises above 4.7V, the

internal regulator is turned off and an internal switch

closes, connecting the EXTV_CCpin to the INTV_CCpin

therebysupplyinginternalandMOSFETgatedrivingpower

to the IC. The switch remains closed as long as the voltage

applied to EXTV_CCremains above 4.5V. This allows the

MOSFET driver and control power to be derived from the

output during normal operation (4.7V < V_EXTVCC< 7V) and

from the internal regulator when the output is out of

regulation (start-up, short-circuit). Do not apply greater

than 7V to the EXTV_CCpin and ensure that EXTV_CC< V_IN+

0.3V when using the application circuits shown. If an

INTV_CCRegulator

An internal P-channel low dropout regulator produces 5V

at the INTV_CCpin from the V_INsupply pin. The INTV_CC

regulator powers the drivers and internal circuitry of the

LTC1709.TheINTV_CCpinregulatorcansupplyupto50mA

peak and must be bypassed to power ground with a

minimum of 4.7µF tantalum or electrolytic capacitor. An

additional 1µF ceramic capacitor placed very close to the

IC is recommended due to the extremely high instanta-

neous currents required by the MOSFET gate drivers.

15

LTC1709

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external voltage source is applied to the EXTV_CCpin when

the V_INsupply is not present, a diode can be placed in

series with the LTC1709’s V_INpin and a Schottky diode

between the EXTV_CCand the V_INpin, to prevent current

from backfeeding V_IN.

4.7V but less than 7V. This can be done with either the

inductive boost winding as shown in Figure 5a or the

capacitive charge pump shown in Figure 5b. The charge

pump has the advantage of simple magnetics.

Topside MOSFET Driver Supply (C_B,D_B) (Refer to

Functional Diagram)

Significant efficiency gains can be realized by powering

INTV_CCfrom the output, since the V_INcurrent resulting

from the driver and control currents will be scaled by the

ratio: (Duty Factor)/(Efficiency). For 5V regulators this

means connecting the EXTV_CCpin directly to V_OUT. How-

ever, for 3.3V and other lower voltage regulators, addi-

tionalcircuitryisrequiredtoderiveINTV_CCpowerfromthe

output.

External bootstrap capacitors C_B1and C_B2connected to

the BOOST 1 and BOOST 2 pins supply the gate drive

voltages for the topside MOSFETs. Capacitor C_Bin the

Functional Diagram is charged though diode D_Bfrom

INTV_CCwhentheSWpinislow.WhenthetopsideMOSFET

turns on, the driver places the C_Bvoltage across the gate-

sourceofthedesiredMOSFET.ThisenhancestheMOSFET

and turns on the topside switch. The switch node voltage,

The following list summarizes the four possible connec-

tions for EXTV_CC:

SW, rises to V_INand the BOOST pin rises to V_IN+ V_INTVCC

.

1. EXTV_CCleft open (or grounded). This will cause INTV_CC

to be powered from the internal 5V regulator resulting in

a significant efficiency penalty at high input voltages.

The value of the boost capacitor C_Bneeds to be 30 to 100

times that of the total input capacitance of the topside

MOSFET(s). ThereversebreakdownofD_Bmustbegreater

than V_IN(MAX).

2. EXTV_CCconnected directly to V_OUT. This is the normal

connection for a 5V regulator and provides the highest

efficiency.

The final arbiter when defining the best gate drive ampli-

tude level will be the input supply current. If a change is

made that decreases input current, the efficiency has

improved. If the input current does not change then the

efficiency has not changed either.

3. EXTV_CCconnected to an external supply. If an external

supply is available in the 5V to 7V range, it may be used to

powerEXTV_CCprovidingitiscompatiblewiththeMOSFET

gate drive requirements.

Output Voltage

4. EXTV_CCconnected to an output-derived boost network.

For 3.3V and other low voltage regulators, efficiency gains

can still be realized by connecting EXTV_CCto an output-

derived voltage which has been boosted to greater than

The LTC1709 has a true remote voltage sense capablity.

Thesensingconnectionsshouldbereturnedfromtheload

back to the differential amplifier’s inputs through a com-

+

OPTIONAL EXTV CONNECTION

CC

V

IN

+

5V < V

< 7V

V

SEC

+

C

IN

C

IN

V

IN

BAT85

0.22µF

BAT85

V

LTC1709

IN

1N4148

V

TG1

SEC

TG1

+

LTC1709

N-CH

VN2222LL

R

1µF

EXTV

CC

N-CH

EXTV

CC

R

SENSE

V

OUT

V

SW1

BG1

SW1

BG1

OUT

L1

T1

+

C

OUT

N-CH

PGND

1709 F05b

1709 F05a

Figure 5a. Secondary Output Loop with EXTV_CCConnection

Figure 5b. Capacitive Charge Pump for EXTV_CC

16

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mon, tightly coupled pair of PC traces. The differential

amplifier corrects for DC drops in both the power and

ground paths. The differential amplifier output signal is

divided down and compared with the internal precision

0.8V voltage reference by the error amplifier.

Table 1. VID Output Voltage Programming

VID4

1

0

VID3

0

1

0

1

VID2

0

1

0

1

0

1

0

1

VID1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

V

(V)

OUT

3.50V

3.40V

3.30V

3.20V

3.10V

3.00V

2.90V

2.80V

2.70V

2.60V

2.50V

2.40V

2.30V

2.20V

2.10V

*

The differential amplifier can be used in either of two

configurations according to the voltage applied to the

AMPMD pin. The first configuration with the connections

illustrated in the Functional Diagram, utilizes a set of

internal, precision resistors to enable precision instru-

mentation-type measurement of the output voltage. This

configuration is activated when the AMPMD pin is tied to

ground. When the AMPMD pin is tied to INTV_CC, the

resistors are disconnected and the amplifier inputs are

made directly available. It can be used for general uses if

the amplifier is not required for true remote sensing. The

amplifier has a 0V to 3V common mode input range

limitation due to the internal switching of its inputs. The

output uses an NPN emitter follower without any internal

pull-down current. A DC resistive load to ground is re-

quired in order to sink current. The output will swing from

0V to 10V (V_IN≥ V_DIFFOUT+ 2V).

2.05V

2.00V

1.95V

1.90V

1.85V

1.80V

1.75V

1.70V

1.65V

1.60V

1.55V

1.50V

1.45V

1.40V

1.35V

1.30V

Output Voltage Programming

The output voltage is digitally set to levels between 1.3V

and3.5Vusingthevoltageidentification(VID)logicinputs

VID0 to VID4. The internal 5-bit DAC configured as a

precision resistive voltage divider sets the output voltage

in 100mV or 50mV increments according to Table 1.

The VID codes are engineered to be compatible with Intel

Pentium^®II and Pentium III processor specifications for

output voltages from 1.3V to 3.5V.

The LSB (VID0) represents 50mV or 100mV increments

depending on the MSB. The MSB is VID4.

Between the ATTENOUT pin and ground is a variable

resistor,R1,whosevalueiscontrolledbythefiveVIDinput

pins (VID0 to VID4). Another resistor, R2, between the

ATTENIN and the ATTENOUT pins completes the resistive

divider. The output voltage is thus set by the ratio of

(R1 + R2) to R1.

* Represents codes without a defined output voltage as specified in Intel

specifications. The LTC1709 interprets these codes as a valid input and

produces an output voltage as follows: (11111) = 2V

Each VID digital input is pulled up by a 40k resistor in

series with a diode from V_BIAS. Therefore, it must be

grounded to get a digital low input, and can be either

Pentium is a registered trademark of Intel Corporation.

17

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floatedorconnectedtoV_BIAStogetadigitalhighinput.The

series diode is used to prevent the digital inputs from

being damaged or clamped if they are driven higher than

Diode D1 in Figure 6 reduces the start delay but allows C_SS

to ramp up slowly providing the soft-start function. The

RUN/SS pin has an internal 6V zener clamp (see Func-

tional Diagram).

V

_BIAS. The digital inputs accept CMOS voltage levels.

V_BIASis the supply voltage for the VID section. It is

normally connected to INTV_CCbut can be driven from

other sources. If it is driven from another source, that

source MUST be in the range of 2.7V to 5.5V and MUST be

alive prior to enabling the LTC1709.

V

INTV

IN

CC

R

3.3V OR 5V

RUN/SS

*

R

*

SS

D1

RUN/SS

D1*

C

SS

C

SS

Soft-Start/Run Function

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

1709 F06

The RUN/SS pin provides three functions: 1) Run/Shut-

down,2)soft-startand3)adefeatableshort-circuitlatchoff

timer. Soft-start reduces the input power sources’ surge

currents by gradually increasing the controller’s current

limit I_TH(MAX). The latchoff timer prevents very short,

extreme load transients from tripping the overcurrent

latch. A small pull-up current (>5µA) supplied to the RUN/

SS pin will prevent the overcurrent latch from operating.

The following explanation describes how the functions

operate.

Figure 6. RUN/SS Pin Interfacing

Fault Conditions: Overcurrent Latchoff

The RUN/SS pin also provides the ability to latch off the

controllerswhenanovercurrentconditionisdetected.The

RUN/SS capacitor, C_SS, is used initially to limit the inrush

current of both controllers. After the controllers have been

started and been given adequate time to charge up the

output capacitors and provide full load current, the RUN/

SS capacitor is used for a short-circuit timer. If the output

voltagefallstolessthan70%ofitsnominalvalueafterC_SS

reaches 4.1V, C_SSbegins discharging on the assumption

that the output is in an overcurrent condition. If the

condition lasts for a long enough period as determined by

the size of C_SS, the controller will be shut down until the

RUN/SS pin voltage is recycled. If the overload occurs

during start-up, the time can be approximated by:

An internal 1.2µA current source charges up the soft-start

capacitor, C_SS. When the voltage on RUN/SS reaches

1.5V, the controller is permitted to start operating. As the

voltage on RUN/SS increases from 1.5V to 3.0V, the

internal current limit is increased from 25mV/R_SENSEto

75mV/R_SENSE. The output current limit ramps up slowly,

taking an additional 1.25s/µF to reach full current. The

outputcurrentthusrampsupslowly,reducingthestarting

surge current required from the input power supply. If

RUN/SS has been pulled all the way to ground there is a

delay before starting of approximately:

t

_LO1≈ (C_SS• 0.6V)/(1.2µA) = 5 • 10⁵(C_SS)

Iftheoverloadoccursafterstart-up,thevoltageonC_SSwill

continue charging and will provide additional time before

latching off:

1.5V

1.2µA

t_DELAY

=

C_SS= 1.25s / µF C

SS

(

)

t

_LO2≈ (C_SS• 3V)/(1.2µA) = 2.5 • 10⁶(C_SS)

The time for the output current to ramp up is then:

This built-in overcurrent latchoff can be overridden by

providing a pull-up resistor, R_SS, to the RUN/SS pin as

shown in Figure 6. This resistance shortens the soft-start

period and prevents the discharge of the RUN/SS capaci-

tor during a severe overcurrent and/or short-circuit con-

dition. When deriving the 5µA current from V_INas in the

figure, current latchoff is always defeated. Diode connect-

ing this pull-up resistor to INTV_CC, as in

3V − 1.5V

1.2µA

t_RAMP

=

C_SS= 1.25s / µF C

SS

(

)

By pulling the RUN/SS pin below 0.8V the LTC1709 is put

into low current shutdown (I_Q< 40µA). The RUN/SS pins

can be driven directly from logic as shown in Figure 6.

18

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Figure 6, eliminates any extra supply current during shut-

down while eliminating the INTV_CCloading from prevent-

ing controller start-up.

The output of the phase detector is a complementary pair

of current sources charging or discharging the external

filter network on the PLLFLTR pin. A simplified block

diagram is shown in Figure 7.

Why should you defeat current latchoff? During the

prototypingstageofadesign,theremaybeaproblemwith

noise pickup or poor layout causing the protection circuit

to latch off the controller. Defeating this feature allows

troubleshooting of the circuit and PC layout. The internal

short-circuit and foldback current limiting still remains

active, thereby protecting the power supply system from

failure. A decision can be made after the design is com-

plete whether to rely solely on foldback current limiting or

to enable the latchoff feature by removing the pull-up

resistor.

If the external frequency (f_PLLIN) is greater than the oscil-

lator frequency f_0SC, current is sourced continuously,

pulling up the PLLFLTR pin. When the external frequency

is less than f_0SC, current is sunk continuously, pulling

down the PLLFLTR pin. If the external and internal fre-

quencies are the same but exhibit a phase difference, the

currentsourcesturnonforanamountoftimecorrespond-

ing to the phase difference. Thus the voltage on the

PLLFLTR pin is adjusted until the phase and frequency of

the external and internal oscillators are identical. At this

stable operating point the phase comparator output is

open and the filter capacitor C_LPholds the voltage. The

LTC1709 PLLIN pin must be driven from a low impedance

source such as a logic gate located close to the pin.

The value of the soft-start capacitor C_SSmay need to be

scaled with output voltage, output capacitance and load

current characteristics. The minimum soft-start capaci-

tance is given by:

The loop filter components (C_LP, R_LP) smooth out the

current pulses from the phase detector and provide a

stable input to the voltage controlled oscillator. The filter

components C_LPand R_LPdetermine how fast the loop

acquires lock. Typically R_LP=10kΩ and C_LPis 0.01µF to

0.1µF.

C_SS> (C_OUT)(V_OUT)(10^-4)(R_SENSE

)

The minimum recommended soft-start capacitor of C_SS

0.1µF will be sufficient for most applications.

=

Phase-Locked Loop and Frequency Synchronization

The LTC1709 has a phase-locked loop comprised of an

internal voltage controlled oscillator and phase detector.

This allows the top MOSFET turn-on to be locked to the

rising edge of an external source. The frequency range of

the voltage controlled oscillator is ±50% around the

center frequency f_O. A voltage applied to the PLLFLTR pin

of 1.2V corresponds to a frequency of approximately

220kHz. The nominal operating frequency range of the

LTC1709 is 140kHz to 310kHz.

2.4V

R

LP

10k

PHASE

DETECTOR

C

LP

EXTERNAL

OSC

PLLFLTR

PLLIN

DIGITAL

PHASE/

FREQUENCY

DETECTOR

OSC

50k

The phase detector used is an edge sensitive digital type

which provides zero degrees phase shift between the

external and internal oscillators. This type of phase detec-

tor will not lock up on input frequencies close to the

harmonics of the VCO center frequency. The PLL hold-in

range, ∆f_H, is equal to the capture range, ∆f_C:

1709 F07

Figure 7. Phase-Locked Loop Block Diagram

Minimum On-Time Considerations

Minimum on-time t_ON(MIN)is the smallest time duration

thattheLTC1709iscapableofturningonthetopMOSFET.

It is determined by internal timing delays and the gate

chargerequiredtoturnonthetopMOSFET.Lowdutycycle

∆f_H= ∆f_C= ±0.5 f_O

(150kHz-300kHz)

19

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INTV

CC

applications may approach this minimum on-time limit

and care should be taken to ensure that:

R

T2

T1

I

TH

LTC1709

V_OUT

R

C

t_{ON MIN}

<

(

)

C

V f

^IN( )

1709 F08

Ifthedutycyclefallsbelowwhatcanbeaccommodatedby

the minimum on-time, the LTC1709 will begin to skip

cycles resulting in variable frequency operation. The out-

put voltage will continue to be regulated, but the ripple

current and ripple voltage will increase.

Figure 8. Active Voltage Positioning Applied to the LTC1709

tion is included in Design Solutions 10 or the LTC1736

data sheet. (See www.linear-tech.com)

Efficiency Considerations

The minimum on-time for the LTC1709 is generally less

than 200ns. However, as the peak sense voltage de-

creases,theminimumon-timegraduallyincreases.Thisis

of particular concern in forced continuous applications

withlowripplecurrentatlightloads.Ifthedutycycledrops

below the minimum on-time limit in this situation, a

significant amount of cycle skipping can occur with corre-

spondingly larger ripple current and voltage ripple.

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can be

expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

If an application can operate close to the minimum on-

time limit, an inductor must be chosen that has a low

enough inductance to provide sufficient ripple amplitude

to meet the minimum on-time requirement. As a general

rule, keep the inductor ripple current of each phase equal

whereL1, L2, etc. aretheindividuallossesasapercentage

of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC1709 circuits: 1) I²R losses, 2) Topside

MOSFET transition losses, 3) INTV_CCregulator current

and 4) LTC1709 V_INcurrent (including loading on the

differential amplifier output).

to or greater than 15% of I_OUT(MAX)at V_IN(MAX)

.

Voltage Positioning

Voltage positioning can be used to minimize peak-to-peak

outputvoltageexcursionunderworst-casetransientload-

ing conditions. The open-loop DC gain of the control loop

is reduced depending upon the maximum load step speci-

fication. Voltage positioning can easily be added to the

LTC1709 by loading the I_THpin with a resistive divider

having a Thevenin equivalent voltage source equal to the

midpoint operating voltage of the error amplifier, or 1.2V

(see Figure 8).

1) I²R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resistor,

and input and output capacitor ESR. In continuous mode

the average output current flows through L and R_SENSE

,

but is “chopped” between the topside MOSFET and the

synchronous MOSFET. If the two MOSFETs have approxi-

mately the same R_DS(ON), then the resistance of one

MOSFET can simply be summed with the resistances of L,

R_SENSEand ESR to obtain I²R losses. For example, if each

R_DS(ON)=10mΩ, R_L=10mΩ, and R_SENSE=5mΩ, then the

total resistance is 25mΩ. This results in losses ranging

from 2% to 8% as the output current increases from 3A to

15A per output stage for a 5V output, or a 3% to 12% loss

per output stage for a 3.3V output. Efficiency varies as the

inverse square of V_OUTfor the same external components

The resistive load reduces the DC loop gain while main-

taining the linear control range of the error amplifier. The

worst-case peak-to-peak output voltage deviation due to

transient loading can theoretically be reduced to half or

alternatively the amount of output capacitance can be

reduced for a particular application. A complete explana-

20

LTC1709

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and output power level. The combined effects of increas-

ingly lower output voltages and higher currents required

by high performance digital systems is not doubling but

quadrupling the importance of loss terms in the switching

regulator system!

minimum of 200µF to 300µF of output capacitance having

a maximum of 10mΩ to 20mΩ of ESR. The LTC1709

2-phase architecture typically halves the input and output

capacitance requirement over competing solutions. Other

lossesincludingSchottkyconductionlossesduringdead-

time and inductor core losses generally account for less

than 2% total additional loss.

2) Transition losses apply only to the topside MOSFET(s),

and are significant only when operating at high input

voltages (typically 12V or greater). Transition losses can

be estimated from:

Checking Transient Response

The regulator loop response can be checked by looking at

the load transient response. Switching regulators take

several cycles to respond to a step in DC (resistive) load

current. When a load step occurs, V_OUTshifts by an

amount equal to ∆I_LOAD(ESR), where ESR is the effective

series resistance of C_OUT• (∆I_LOAD) also begins to charge

or discharge C_OUTgenerating the feedback error signal

thatforcestheregulatortoadapttothecurrentchangeand

return V_OUTto its steady-state value. During this recovery

time V_OUTcan be monitored for excessive overshoot or

ringing, which would indicate a stability problem. The

availability of the I_THpin not only allows optimization of

control loop behavior but also provides a DC coupled and

AC filtered closed loop response test point. The DC step,

rise time, and settling at this test point truly reflects the

closed loop response. Assuming a predominantly second

order system, phase margin and/or damping factor can be

estimated using the percentage of overshoot seen at this

pin. The bandwidth can also be estimated by examining

the rise time at the pin. The I_THexternal components

shown in the Figure 1 circuit will provide an adequate

starting point for most applications.

2

Transition Loss = (1.7) V_INI_O(MAX)C_RSS

f

3) INTV_CCcurrent is the sum of the MOSFET driver and

control currents. The MOSFET driver current results from

switching the gate capacitance of the power MOSFETs.

Each time a MOSFET gate is switched from low to high to

low again, a packet of charge dQ moves from INTV_CCto

ground. The resulting dQ/dt is a current out of INTV_CCthat

is typically much larger than the control circuit current. In

continuous mode, I_GATECHG= (Q_T+ Q_B), where Q_Tand Q_B

are the gate charges of the topside and bottom side

MOSFETs.

SupplyingINTV_CCpowerthroughtheEXTV_CCswitchinput

from an output-derived source will scale the V_INcurrent

required for the driver and control circuits by the ratio

(Duty Factor)/(Efficiency). For example, in a 20V to 5V

application, 10mA of INTV_CCcurrent results in approxi-

mately 3mA of V_INcurrent. This reduces the mid-current

loss from 10% or more (if the driver was powered directly

from V_IN) to only a few percent.

4) The V_INcurrent has two components: the first is the

DC supply current given in the Electrical Characteristics

table, which excludes MOSFET driver and control cur-

rents; the second is the current drawn from the differential

amplifier output. V_INcurrent typically results in a small

(<0.1%) loss.

The I_THseries R_C-C_Cfilter sets the dominant pole-zero

loop compensation. The values can be modified slightly

(from 0.2 to 5 times their suggested values) to optimize

transient response once the final PC layout is done and the

particular output capacitor type and value have been

determined. The output capacitors need to be decided

upon because the various types and values determine the

loop gain and phase. An output current pulse of 20% to

80% of full-load current having a rise time of <2µs will

produce output voltage and I_THpin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop. The initial output voltage step resulting

from the step change in output current may not be within

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efficiency degradation in portable systems. It is very

important to include these “system” level losses in the

design of a system. The internal battery and input fuse

resistance losses can be minimized by making sure that

C_INhas adequate charge storage and a very low ESR at the

switching frequency. A 50W supply will typically require a

21

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50A I RATING

PK

the bandwidth of the feedback loop, so this signal cannot

be used to determine phase margin. This is why it is better

to look at the Ith pin signal which is in the feedback loop

and is the filtered and compensated control loop re-

sponse. The gain of the loop will be increased by increas-

ing R_Cand the bandwidth of the loop will be increased by

decreasing C_C. If R_Cis increased by the same factor that

C_Cis decreased, the zero frequency will be kept the same,

thereby keeping the phase the same in the most critical

frequency range of the feedback loop. The output voltage

settling behavior is related to the stability of the closed-

loopsystemandwilldemonstratetheactualoverallsupply

performance.

V

IN

12V

LTC1709

TRANSIENT VOLTAGE

SUPPRESSOR

GENERAL INSTRUMENT

1.5KA24A

1709 F09

Figure 9. Automotive Application Protection

Design Example

Asadesignexample,assumeV_IN=5V(nominal),V_IN= 5.5V

(max), V_OUT=1.8V, I_MAX=20A, T_A=70°Candf = 300kHz.

Theinductancevalueischosenfirstbasedona30%ripple

current assumption. The highest value of ripple current

occursatthemaximuminputvoltage. TiethePLLFLTRpin

to the INTV_CCpin for 300kHz operation. The minimum

inductance for 30% ripple current is:

Automotive Considerations: Plugging into the

Cigarette Lighter

As battery-powered devices go mobile, there is a natural

interest in plugging into the cigarette lighter in order to

conserveorevenrechargebatterypacksduringoperation.

But before you connect, be advised: you are plugging into

the supply from hell. The main battery line in an automo-

bileisthesourceofanumberofnastypotentialtransients,

including load-dump, reverse-battery, and double-bat-

tery.

V_OUT

f ∆I

( )

V_OUT

V

IN

L ≥

1−

1.8V

5.5V

≥

1−

300kHz 30% 10A

(

)( )(

)

≥ 1.35µH

Load-dump is the result of a loose battery cable. When the

cablebreaksconnection,thefieldcollapseinthealternator

can cause a positive spike as high as 60V which takes

several hundred milliseconds to decay. Reverse-battery is

just what it says, while double-battery is a consequence of

tow truck operators finding that a 24V jump start cranks

cold engines faster than 12V.

A 1.5µH inductor will produce 27% ripple current. The

peak inductor current will be the maximum DC value plus

one half the ripple current, or 11.4A. The minimum on-

time occurs at maximum V_IN:

V_OUT

V f

IN

1.8V

)(

t_{ON MIN}

=

= 1.1µs

(

)

ThenetworkshowninFigure9isthemoststraightforward

approach to protect a DC/DC converter from the ravages

of an automotive power line. The series diode prevents

current from flowing during reverse-battery, while the

transient suppressor clamps the input voltage during

load-dump. Note that the transient suppressor should not

conduct during double-battery operation, but must still

clamptheinputvoltagebelowbreakdownoftheconverter.

AlthoughtheLT1709hasamaximuminputvoltageof36V,

most applications will be limited to 30V by the MOSFET

5.5V 300kHz

(

)

The R_SENSEresistors value can be calculated by using the

maximum current sense voltage specification with some

accomodation for tolerances:

50mV

11.4A

R_SENSE

=

≈ 0.004Ω

BV_DSS

.

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The power dissipation on the topside MOSFET can be

easily estimated. Using a Siliconix Si4420DY for example;

R_DS(ON)= 0.013Ω, C_RSS= 300pF. At maximum input

voltage with T_j(estimated) = 110°C at an elevated ambient

temperature:

The duty factor for this application is:

V_O1.8V

D.F. =

=

= 0.36

V

IN

5V

Using Figure 4, the RMS ripple current will be:

I_INRMS= (20A)(0.23) = 4.6A_RMS

1.8V

5.5V

P_MAIN

=

10 ²1+ 0.005 110°C − 25°C

( ) )(

(

)

]

[

An input capacitor(s) with a 4.6A_RMSripple current rating

is required.

2

0.013Ω + 1.7 5.5V 10A 300pF

(

) (

)(

)

300kHz = 0.65W

(

)

The output capacitor ripple current is calculated by using

the inductor ripple already calculated for each inductor

andmultiplyingbythefactorobtainedfromFigure 3along

with the calculated duty factor. The output ripple in con-

tinuous mode will be highest at the maximum input

voltage since the duty factor is <50%. The maximum

output current ripple is:

The worst-case power disipated by the synchronous

MOSFET under normal operating conditions at elevated

ambient temperature and estimated 50°C junction tem-

perature rise is:

2

) (

5.5V − 1.8V

5.5V

= 1.29W

P_SYNC

=

10A 1.48 0.013Ω

(

)(

)

V_OUT

∆I_COUT

=

0.3 at 33%D. F.

(

)

fL

1.8V

Ashort-circuittogroundwillresultinafoldedbackcurrent

of about:

∆I_COUTMAX

=

0.3

300kHz 1.5µH

)(

= 1.2A_RMS

(

)

200ns 5.5V

25mV

1

2

(

)

V_OUTRIPPLE= 20mΩ 1.2A

= 24mV

RMS

(

)

I_SC

=

+

= 7A

RMS

0.004Ω

1.5µH

The worst-case power disipated by the synchronous

MOSFET under short-circuit conditions at elevated ambi-

ent temperature and estimated 50°C junction temperature

rise is:

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1709. These items are also illustrated graphically in

the layout diagram of Figure 11. Check the following in

your layout:

5.5V − 1.8V

2

P

SYNC

=

7A 1.48 0.013Ω

(

) (

)(

)

5.5V

1) Are the signal and power grounds segregated? The

LTC1709 signal ground pin should return to the (–) plate

of C_OUTseparately. The power ground returns to the

sources of the bottom N-channel MOSFETs, anodes of the

Schottky diodes, and (–) plates of C_IN, which should have

as short lead lengths as possible.

= 630mW

which is less than half of the normal, full-load conditions.

Incidentally, since the load no longer dissipates power in

the shorted condition, total system power dissipation is

decreased by over 99%.

+

2) Does the LTC1709 V_OSpin connect to the point of

–

load? Does the LTC1709 V_OSpin connect to the load

return?

23

LTC1709

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APPLICATIO S I FOR ATIO

3)AretheSENSE^–andSENSE⁺leadsroutedtogetherwith

minimum PC trace spacing? The filter capacitors between

SENSE⁺and SENSE^–pin pairs should be as close as

possible to the LTC1709. Ensure accurate current sensing

with Kelvin connections at the current sense resistor.

finite impedances during the total period of the switching

regulator.ExternalOPTI-LOOPcompensationallowsover-

compensation for PC layouts which are not optimized but

this is not the recommended design procedure.

Simplified Visual Explanation of How a 2-Phase

Controller Reduces Both Input and Output RMS Ripple

Current

4) Does the (+) plate of C_INconnect to the drains of the

topside MOSFETs and the (–) plate of C_INto the sources of

the bottom MOSFETS as closely as possible? This capaci-

tor provides the AC current to the MOSFETs. Keep the

input current path formed by the input capacitor, top and

bottom MOSFETs, and the Schottky diode on the same

side of the PC board in a tight loop to minimize conducted

and radiated EMI.

A multiphase power supply significantly reduces the

amount of ripple current in both the input and output

capacitors. Theeffectiveinputandoutputripplefrequency

is multiplied up by the number of phases used. Figure 11

graphically illustrates the principle.

The worst-case RMS ripple current for a single stage

design peaks at an input voltage of twice the output

voltage.Theworst-caseRMSripplecurrentforatwostage

design results in peak outputs of 1/4 and 3/4 of input

voltage. When the RMS current is calculated, higher

effective duty factor results and the peak current levels are

divided as long as the currents in each stage are balanced.

Refer to Application Note 77 for a detailed description of

howtocalculateRMScurrentforthemultiphaseswitching

regulator. Figures 3 and 4 help to illustrate how the input

and output currents are reduced by using an additional

phase. The input current peaks drop in half and the

frequency is doubled for this 2-phase converter. The input

capacity requirement is thus reduced theoretically by a

factor of four! Ceramic input capacitors with their

unbeatably low ESR characteristics can be used.

5) Is the INTV_CC1µF ceramic decoupling capacitor con-

nected closely between INTV_CCand the PGND pin? This

capacitor carries the MOSFET driver peak currents. A

small value is recommended to allow placement immedi-

ately adjacent to the IC.

6) Keep the switching nodes, SW1 (SW2), away from

sensitive small-signal nodes. Ideally the switch nodes

should be placed at the furthest point from the LTC1709.

7)Usealowimpedancesourcesuchasalogicgatetodrive

the PLLIN pin and keep the lead as short as possible.

The diagram in Figure 10 illustrates all branch currents in

a 2-phase switching regulator. It becomes very clear after

studying the current waveforms why it is critical to keep

the high-switching-current paths to a small physical size.

High electric and magnetic fields will radiate from these

“loops” just as radio stations transmit signals. The output

capacitor ground should return to the negative terminal of

the input capacitor and not share a common ground path

with any switched current paths. The left half of the circuit

gives rise to the “noise” generated by a switching regula-

tor. The ground terminations of the sychronous MOSFETs

and Schottky diodes should return to the negative plate(s)

of the input capacitor(s) with a short isolated PC trace

since very high switched currents are present. A separate

isolated path from the negative plate(s) of the input

capacitor(s) should be used to tie in the IC power ground

pin (PGND) and the signal ground pin (SGND). This

technique keeps inherent signals generated by high cur-

rent pulses from taking alternate current paths that have

Figure 4 illustrates the RMS input current drawn from the

input capacitance vs the duty cycle as determined by the

ratio of input and output voltage. The peak input RMS

currentlevelofthesinglephasesystemisreducedby50%

in a 2-phase solution due to the current splitting between

the two stages.

An interesting result of the 2-phase solution is that the V_IN

which produces worst-case ripple current for the input

capacitor, V_OUT= V_IN/2, in the single phase design pro-

duces zero input current ripple in the 2-phase design.

24

LTC1709

U

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APPLICATIO S I FOR ATIO

The output ripple current is reduced significantly when

compared to the single phase solution using the same

inductance value because the V_OUT/L discharge current

term from the stage that has its bottom MOSFET on

subtracts current from the (V_IN- V_OUT)/L charging current

resultingfromthestagewhichhasitstopMOSFETon. The

output ripple current is:

The input and output ripple frequency is increased by the

number of stages used, reducing the output capacity

requirements.WhenV_INisapproximatelyequalto2(V_OUT

)

as illustrated in Figures 3 and 4, very low input and output

ripple currents result.

1− 2D 1−D

(

)

2V_OUT

fL

∆I_RIPPLE

=

1− 2D +1

where D is duty factor.

SW1

L1

R

SENSE1

D1

V

OUT

IN

R

IN

C

OUT

+

C

R

L

IN

SW2

L2

R

SENSE2

D2

BOLD LINES INDICATE

HIGH, SWITCHING

CURRENT LINES.

KEEP LINES TO A

MINIMUM LENGTH.

1709 F10

Figure 10. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator

25

LTC1709

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APPLICATIO S I FOR ATIO

SINGLE PHASE

DUAL PHASE

SW V

SW1 V

SW2 V

I

CIN

I

L1

L2

I

COUT

I

CIN

I

COUT

RIPPLE

1709 F11

Figure 11. Single and 2-Phase Current Waveforms

26

LTC1709

U

PACKAGE DESCRIPTIO

Dimensions in inches (millimeters) unless otherwise noted.

G Package

36-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

12.67 – 12.93*

(0.499 – 0.509)

36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19

7.65 – 7.90

(0.301 – 0.311)

5

7

8

1

2

3

4

6

9 10 11 12 13 14 15 16 17 18

5.20 – 5.38**

(0.205 – 0.212)

1.73 – 1.99

(0.068 – 0.078)

0° – 8°

0.65

(0.0256)

BSC

0.13 – 0.22

0.55 – 0.95

(0.005 – 0.009)

(0.022 – 0.037)

0.05 – 0.21

(0.002 – 0.008)

0.25 – 0.38

(0.010 – 0.015)

NOTE: DIMENSIONS ARE IN MILLIMETERS

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.152mm (0.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

G36 SSOP 1098

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

27

LTC1709

U

TYPICAL APPLICATIO

L1

LTC1709

+

1

2

36

35

34

33

32

31

30

29

28

27

26

25

24

23

1.5µH

1000pF

0.004Ω

RUN/SS

NC

TG1

0.1µF

SENSE 1

EAIN

0.22µF

D3

M1

M2

3

–

D1

SW1

10k

INTV

CC

4

MBRM

140T3

BOOST 1

10Ω

5

2.7k

51k

PLLFLTR

PLLIN

NC

V

IN

BG1

100pF

6

C

OUT

0.1µF

7

GND

4×180µF

4V

3.3nF

EXTV

CC

47k

15k

47µF×2

35V

8

1µF,25V

I

INTV

TH

SGND

CC

4.7µF

6.3V

9

V

IN

5V TO 28V

PGND

BG2

10

11

12

13

14

V

DIFFOUT

–

BOOST 2

SW2

OS

D2

MBRM

140T3

D4

+

10Ω

OS

–

+

SENSE 2

TG2

0.22µF

M3

M4

AMPMD

0.004Ω

1000pF

V

OUT

15

16

17

18

22

21

20

19

1.3V TO 3.5V

L2

1.5µH

ATTENOUT

ATTENIN

VID0

V

BIAS

VID4

VID3

VID2

0.1µF

470pF

VID1

VID INPUTS

SWITCHING FREQUENCY = 310kHz

MI – M4: FAIRCHILD FDS7760A

L1 – L2: SUMIDA CEP125-1R5M

C

OUTPUT CAPACITORS: PANASONIC EEFUE0G181R

OUT

D3, D4: CENTRAL CMDSH-3TR

1709 TA02

Figure 12. 5V Input, 1.8V/20A Power Supply with Active Voltage Positioning

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Current Mode Ensures Accurate Current Sharing,

3.5V ≤ V ≤ 36V

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with 5-Bit VID and Power Good Indication

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≤ 3.5V, Current Mode Ensures

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IN

OUT

Adaptive Power and Burst Mode are trademarks of Linear Technology Corporation.

1709f LT/TP 0500 4K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

LINEAR TECHNOLOGY CORPORATION 1999

●

(408)432-1900 FAX:(408)434-0507 www.linear-tech.com


型号：	LTC1709EG#PBF
厂家：	Linear
描述：	LTC1709 - 2-Phase, 5-Bit Adjustable,High Efficiency, Synchronous Step-Down Switching Regulator; Package: SSOP; Pins: 36; Temperature Range: -40°C to 85°C 开关光电二极管
文件：	总28页 (文件大小：296K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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