LTC1735CS_技术文档

LTC1735

High Efficiency

Synchronous Step-Down

Switching Regulator

U

FEATURES

DESCRIPTIO

The LTC^®1735 is a synchronous step-down switching

regulator controller that drives external N-channel power

MOSFETs using a fixed frequency architecture. Burst

Mode^TMoperation provides high efficiency at low load

currents. The precision 0.8V reference is compatible with

future microprocessor generations. OPTI-LOOP compen-

sation allows the transient response to be optimized over

a wide range of output capacitance and ESR values.

■

Dual N-Channel MOSFET Synchronous Drive

■

Synchronizable/Programmable Fixed Frequency

■

Wide V_INRange: 3.5V to 36V Operation

■

V_OUTRange: 0.8V to 6V

OPTI-LOOP^TMCompensation Minimizes C_OUT

■

±

1% Output Voltage Accuracy

■

Internal Current Foldback

Output Overvoltage Crowbar Protection

Latched Short-Circuit Shutdown Timer

with Defeat Option

The operating frequency (synchronizable up to 500kHz) is

set by an external capacitor allowing maximum flexibility

in optimizing efficiency. A forced continuous control pin

reduces noise and RF interference and can assist second-

ary winding regulation by disabling Burst Mode operation

when the main output is lightly loaded.

■

Very Low Dropout Operation: 99% Duty Cycle

Forced Continuous Control Pin

Optional Programmable Soft-Start

Remote Output Voltage Sense

Logic Controlled Micropower Shutdown: I_Q< 25µA

LTC1435 Pin Compatible with

Minor Component Changes

Protection features include internal foldback current lim-

iting, output overvoltage crowbar and optional short-

circuit shutdown. Soft-start is provided by an external

capacitor that can be used to properly sequence supplies.

The operating current level is user-programmable via an

external current sense resistor. Wide input supply range

allows operation from 3.5V to 30V (36V maximum).

■

^{Available in 16-L}U^{ead Narrow SSOP and SO Packages}

APPLICATIO S

■

Notebook and Palmtop Computers, PDAs

■

Cellular Telephones and Wireless Modems

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode and OPTI-LOOP are trademarks of Linear Technology Corporation.

■

DC Power Distribution Systems

U

TYPICAL APPLICATIO

V

IN

5V TO 24V

C

OSC

IN

22µF

M1

FDS6680A

C

OSC

47pF

TG

BOOST

SW

50V

C

B

0.22µF

RUN/SS

C

: PANASONIC EEFUEOG181R

C

OUT

SS

0.1µF

: MARCON THCR70E1H226ZT

IN

I

TH

L1: PANASONIC ETQP6FZR0HFA

R

: IRC LRF2010-01-R005J

SENSE

C

330pF

LTC1735

L1

2µH

C

R

C2

100pF

SENSE

R

C

D

B

CMDSH-3

V

1.6V

9A

0.005Ω

OUT

33k

V

IN

SGND

100pF

INTV

R1

20k

1%

CC

+

C

V

4.7µF

OUT

OSENSE

180µF

4V

+

M2

FDS6680A

D1

MBRS340T3

BG

–

×4

SP

R2

20k

1%

SENSE

1000pF

PGND

+

SENSE

1735 F01

Figure 1. High Efficiency Step-Down Converter

1

LTC1735

W W U W

U

W

U

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

Input Supply Voltage (V_IN).........................36V to –0.3V

TOP VIEW

ORDER PART

Topside Driver Supply Voltage (BOOST)....42V to –0.3V

Switch Voltage (SW) ....................................36V to –5V

EXTV_CCVoltage ...........................................7V to –0.3V

Boosted Driver Voltage (BOOST – SW) .......7V to –0.3V

SENSE⁺, SENSE^–Voltages .......... 1.1 (INTV_CC) to –0.3V

FCB Voltage ............................(INTV_CC+ 0.3V) to –0.3V

I_TH, V_OSENSEVoltages ...............................2.7V to –0.3V

RUN/SS Voltages.........................................7V to –0.3V

Peak Driver Output Current <10µs (TG, BG) .............. 3A

INTV_CCOutput Current ......................................... 50mA

Operating Ambient Temperature Range

NUMBER

C

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

TG

OSC

RUN/SS

BOOST

SW

LTC1735CGN

LTC1735CS

LTC1735IGN

LTC1735IS

I

TH

FCB

V

IN

SGND

INTV

CC

V

BG

OSENSE

–

SENSE

PGND

+

GN PART MARKING

SENSE

EXTV

CC

GN PACKAGE

16-LEAD NARROW

PLASTIC SSOP

S PACKAGE

16-LEAD PLASTIC SO

1735

1735I

T_JMAX= 125°C, θ_JA= 130°C/W (GN)

T_JMAX= 125°C, θ_JA= 110°C/W (S)

LTC1735C ............................................... 0°C to 85°C

LTC1735I............................................ –40°C to 85°C

Junction Temperature (Note 2)............................. 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

Consult factory for Military grade parts.

ELECTRICAL CHARACTERISTICS ^The● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V, V_RUN/SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loop

I

Feedback Current

(Note 3)

–4

0.8

–25

0.808

0.02

nA

V

VOSENSE

V

Feedback Voltage

●

0.792

OSENSE

∆V

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

= 3.6V to 30V (Note 3)

IN

0.001

%/V

LINEREG

(Note 3)

Measured in Servo Loop; V = 0.7V

Measured in Servo Loop; V = 2V

LOADREG

●

0.1

–0.1

0.3

–0.3

%

ITH

DF Max

Maximum Duty Factor

In Dropout

98

99.4

1.3

%

mmho

V

g

Transconductance Amplifier g

Forced Continuous Threshold

Forced Continuous Current

m

V

●

0.76

0.84

0.8

0.84

–0.3

0.88

FCB

I

V

= 0.85V

– 0.17

0.86

µA

FCB

V

Feedback Overvoltage Lockout

V

OVL

I

Input DC Supply Current

Normal Mode

(Note 4)

Q

450

15

µA

Shutdown

V

= 0V

25

1.9

4.5

RUN/SS

V

Run Pin Start Threshold

, Ramping Positive

= 0V

1.0

1.5

4.1

–1.2

2

V

RUN/SS

SCL

Run Pin Begin Latchoff Threshold

Soft-Start Charge Current

RUN/SS Discharge Current

I

–0.7

0.5

µA

Soft Short Condition, V

= 0.5V,

4

OSENSE

V

= 4.5V

RUN/SS

UVLO

∆V

Undervoltage Lockout

Measured at V Pin (V Ramping Down)

●

3.5

75

3.9

85

V

IN

Maximum Current Sense Threshold

V

= 0.7V

OSENSE

60

mV

SENSE(MAX)

2

LTC1735

ELECTRICAL CHARACTERISTICS ^The● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V, V_RUN/SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

60

MAX

80

UNITS

µA

–

+

I

t

Sense Pins Total Source Current

Minimum On-Time

V

= V

= 0V

SENSE

Tested with a Square Wave (Note 6)

(Note 7)

160

200

ns

ON(MIN)

TG Transition Time:

Rise Time

Fall Time

TG t

C

= 3300pF

50

90

ns

r

f

LOAD

BG Transition Time:

Rise Time

Fall Time

(Note 7)

BG t

C

= 3300pF

50

40

90

80

ns

r

f

LOAD

TG/BG t

Top Gate Off to Synchronous

Gate On Delay Time

C

= 3300pF Each Driver

100

ns

1D

2D

LOAD

TG/BG t

Synchronous Gate Off to Top

Gate On Delay Time

C

= 3300pF Each Driver

70

ns

LOAD

Internal V Regulator

CC

V

Internal V Voltage

6V < V < 30V, V = 4V

EXTVCC

5.0

4.5

5.2

0.2

130

4.7

0.2

5.4

1

V

%

INTVCC

CC

IN

Internal V Load Regulation

I

= 0 to 20mA, V

= 4V

LDO(INT)

LDO(EXT)

EXTVCC

CC

EXTVCC

EXTV Drop Voltage

= 20mA, V

= 5V

200

mV

V

CC

EXTVCC

EXTV Switchover Voltage

= 20mA, EXTV Ramping Positive

●

CC

EXTV Hysteresis

V

EXTVCC(HYS)

CC

Oscillator

f

Oscillator Frequency

C

= 43pF (Note 5)

OSC

265

0.9

300

1.3

1.2

335

kHz

V

OSC

f /f

Maximum Sync Frequency Ratio

FCB Pin Threshold For Sync

H

OSC

f

Ramping Negative

FCB(SYNC)

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 5: Oscillator frequency is tested by measuring the C

charge

OSC

current (I ) and applying the formula:

OSC

Note 2: T is calculated from the ambient temperature T and power

J

A

–1

11

dissipation P according to the following formulas:

8.477(10 )

1

I

DIS

D

f

=

+

OSC

LTC1735CS, LTC1735IS: T = T + (P • 110 °C/W)

C

(pF)+ 11

I

J

A

D

OSC

CHG

LTC1735CGN, LTC1735IGN: T = T + (P • 130°C/W)

Note 3: The LTC1735 is tested in a feedback loop that servos V

J

A

D

Note 6: The minimum on-time condition corresponds to an inductor peak-

to-peak ripple current ≥40% of I (see Minimum On-Time

Considerations in the Applications Information section).

Note 7: Rise and fall times are measured using 10% and 90% levels.

Delay times are measured using 50% levels.

to

OSENSE

MAX

the balance point for the error amplifier (V = 1.2V).

ITH

Note 4: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

3

LTC1735

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Load Current

(3 Operating Modes)

Efficiency vs Load Current

Efficiency vs Input Voltage

100

90

80

70

60

50

40

100

95

90

85

80

75

70

100

90

80

70

60

50

40

30

20

EXTV = 5V

CC

EXTV OPEN

CC

EXTV = 5V

CC

OUT

FIGURE 1

V

= 15V

FIGURE 1

V

= 1.6V

IN

V

IN

= 5V

BURST

SYNC

I

= 5A

OUT

V

IN

= 24V

CONT

I

= 0.5A

OUT

V

= 10V

IN

OUT

S

= 3.3V

R

= 0.01Ω

= 300kHz

f

O

0.1

0.01

LOAD CURRENT (A)

0.001

1

10

0.01

0.1

1

10

0

10

15

20

25

30

5

LOAD CURRENT (A)

INPUT VOLTAGE (V)

1735 G01

1735 G02

1735 G03

V_IN– V_OUTDropout Voltage

vs Load Current

Efficiency vs Input Voltage

Load Regulation

500

400

300

200

100

0

100

95

90

85

80

75

70

0

–0.1

–0.2

–0.3

–0.4

R

V

= 0.005Ω

FCB = 0V

= 15V

EXTV OPEN

SENSE

= 5V – 5% DROP

CC

V

= 1.6V

OUT

IN

OUT

FIGURE 1

I

= 5A

OUT

I

= 0.5A

OUT

0

2

4

6

8

10

0

10

15

20

25

30

0

2

4

6

8

10

5

LOAD CURRENT (A)

INPUT VOLTAGE (V)

LOAD CURRENT (A)

1735 G06

1735 G04

1735 G05

Input and Shutdown Currents

vs Input Voltage

EXTV_CCSwitch Drop

vs INTV_CCLoad Current

INTV_CCLine Regulation

500

400

300

200

100

0

100

80

60

40

20

0

6

5

4

3

500

400

300

200

100

0

1mA LOAD

EXTV OPEN

CC

2

1

0

SHUTDOWN

EXTV = 5V

CC

0

5

10

15

20

25

30

35

0

15

20

25

30

35

5

10

0

10

20

30

40

50

INPUT VOLTAGE (V)

INTV LOAD CURRENT (mA)

CC

1735 G07

1735 G08

1735 G09

4

LTC1735

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Maximum Current Sense Threshold

vs Normalized Output Voltage

(Foldback)

Maximum Current Sense Threshold

vs V_RUN/SS

Maximum Current Sense Threshold

vs Sense Common Mode Voltage

80

60

40

20

80

76

72

68

64

60

80

70

60

50

40

30

20

10

0

V

= 1.6V

SENSE(CM)

0

1

2

3

4

5

6

50

NORMALIZED OUTPUT VOLTAGE (%)

1

3

0

25

75

100

0

2

4

5

V

(V)

RUN/SS

COMMON MODE VOLTAGE (V)

1735 G11

1735 G10

1735 G12

Maximum Current Sense Threshold

vs I_THVoltage

Maximum Current Sense Threshold

vs Temperature

V_ITHvs V_RUN/SS

90

80

2.5

2.0

1.5

1.0

80

V

= 0.7V

V

= 1.6V

OSENSE

SENSE(CM)

70

60

75

70

65

50

40

30

20

10

0

0.5

0

–10

–20

–30

60

0

0.5

1

1.5

(V)

2

2.5

0

2

3

4

5

6

–40 –15 10

35

60

85 110 135

1

TEMPERATURE (°C)

V

(V)

V

RUN/SS

ITH

1735 G13

1735 G15

1735 G18

SENSE Pins Total Source Current

I_THVoltage vs Load Current

Output Current vs Duty Cycle

2.5

2.0

1.5

1.0

100

80

100

50

V

= 10V

IN

OUT

I

/I

(SYNC)

OUT MAX

= 3.3V

= 0.01Ω

I

/I

OUT MAX

R

SENSE

(FREE RUN)

f

= 300kHz

O

CONTINUOUS

MODE

60

0

SYNCHRONIZED f = f

O

40

Burst Mode

OPERATION

–50

–100

0.5

0

20

0

f

= f

O

SYNC

0

2

3

4

5

6

1

2

4

0

20

40

60

80

100

0

6

LOAD CURRENT (A)

DUTY CYCLE (%)

V

COMMON MODE VOLTAGE (V)

SENSE

1735 G17

1735 G14

1735 G16

5

LTC1735

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Oscillator Frequency

vs Temperature

RUN/SS Pin Current

vs Temperature

FCB Pin Current vs Temperature

300

290

280

270

260

250

0

–1

–2

–3

–4

–5

0

–0.2

–0.4

–0.6

–0.8

–1.0

C

OSC

= 47pF

V

= 0V

V

FCB

= 0.85V

RUN/SS

–40 –15 10

35

60

85 110 135

–40 –15 10

35

60

85 110 135

–40 –15 10

35

60

85 110 135

TEMPERATURE (°C)

1735 G19

1735 G20

1735 G21

V_OUT(RIPPLE)

(Burst Mode Operation)

Start-Up

V_OUT(RIPPLE)(Synchronized)

I_LOAD= 10mA

FIGURE 1

I_LOAD= 50mA

FIGURE 1

V_OUT

1V/DIV

V_OUT

10mV/DIV

V_OUT

20mV/DIV

V_RUN/SS

5V/DIV

I_L

5A/DIV

I_L

5A/DIV

1735 G22

1735 G23

1735 G24

FCB = 5V

V_IN= 15V

50µs/DIV

V_IN= 15V

5ms/DIV

EXT SYNC f = f_O

10µs/DIV

V

_OUT= 1.6V

V_IN= 15V

V

_OUT= 1.6V

R_LOAD= 0.16Ω

V_OUT= 1.6V

V_OUT(RIPPLE)

(Burst Mode Operation)

Load Step (Burst Mode Operation)

Load Step (Continuous Mode)

I_LOAD= 1.5A

FIGURE 1

V_OUT

20mV/DIV

V_OUT

50mV/DIV

V_OUT

50mV/DIV

I_L

5A/DIV

I_L

5A/DIV

1735 G27

1735 G26

1735 G25

FCB = 5V

_IN= 15V

V_OUT= 1.6V

5µs/DIV

10mA TO

9A LOAD STEP

FCB = 5V

V_IN= 15V

V_OUT= 1.6V

10µs/DIV

0A TO

9A LOAD STEP

FCB = 0V

V_IN= 15V

V_OUT= 1.6V

10µs/DIV

V

6

LTC1735

U

PI FU CTIO S

C_OSC(Pin 1): External capacitor C_OSCfrom this pin to

ground sets the operating frequency.

EXTV_CC(Pin 9): Input to the Internal Switch Connected to

INTV_CC. This switch closes and supplies V_CCpower when-

ever EXTV_CCis higher than 4.7V. See EXTV_CCconnection

in the Applications Information section. Do not exceed 7V

on this pin and ensure EXTV_CC≤ V_IN.

RUN/SS (Pin 2): Combination of Soft-Start and Run

Control Inputs. A capacitor to ground at this pin sets the

ramptimetofulloutputcurrent. Thetimeisapproximately

1.25s/µF. Forcing this pin below 1.5V causes the device to

be shutdown. In shutdown all functions are disabled.

Latchoff overcurrent protection is also invoked via this pin

as described in the Applications Information section.

PGND (Pin 10): Driver Power Ground. Connects to the

source of bottom N-channel MOSFET, the anode of the

Schottky diode, and the (–) terminal of C_IN.

BG (Pin 11): High Current Gate Drive for Bottom

N-Channel MOSFET. Voltage swing at this pin is from

ground to INTV_CC.

I_TH(Pin 3): Error Amplifier Compensation Point. The

current comparator threshold increases with this control

voltage. Nominal voltage range for this pin is 0V to 2.4V.

INTV_CC(Pin12):OutputoftheInternal5.2VRegulatorand

EXTV_CCSwitch. The driver and control circuits are pow-

ered from this voltage. Decouple to power ground with a

1µF ceramic capacitor placed directly adjacent to the IC

together with a minimum of 4.7µF tantalum or other low

ESR capacitor.

FCB (Pin 4): Forced Continuous/Synchronization Input.

Tie this pin to ground for continuous synchronous opera-

tion, to a resistive divider from the secondary output when

using a secondary winding or to INTV_CCto enable Burst

Modeoperationatlowloadcurrents.Clockingthispinwith

a signal above 1.5V_P–Pdisables Burst Mode operation but

allows cycle-skipping at low load currents and synchro-

nizes the internal oscillator with the external clock.

V_IN(Pin 13): Main Supply Pin. Must be closely decoupled

to power ground.

SW (Pin 14): Switch Node Connection to Inductor and

Bootstrap Capacitor. Voltage swing at this pin is from a

Schottky diode (external) voltage drop below ground to

V_IN.

SGND (Pin 5): Small-Signal Ground. All small-signal

components such as C_OSC, C_SS, the feedback divider plus

the loop compensation resistors and capacitor(s) should

single-pointtietothispin.Thispinshould,inturn,connect

to PGND.

BOOST (Pin 15): Supply to Topside Floating Driver. The

bootstrap capacitor is returned to this pin. Voltage swing

V_OSENSE(Pin 6): Receives the feedback voltage from an

external resistive divider across the output.

SENSE^–(Pin 7): The (–) Input to the Current Comparator.

SENSE⁺(Pin 8): The (+) Input to the Current Comparator.

Built-in offsets between SENSE^–and SENSE⁺pins in

conjunction with R_SENSEset the current trip threshold.

at this pin is from a diode drop below INTV_CCto (V_IN

INTV_CC).

+

TG (Pin 16): High Current Gate Drive for Top N-Channel

MOSFET. This is the output of a floating driver with a

voltage swing equal to INTV_CCsuperimposed on the

switch node voltage SW.

7

LTC1735

U

U W

FU CTIO AL DIAGRA

V

IN

+

V

13

IN

UVL

C

IN

C

OSC

C

0.8V

REF

INTV

CC

SGND

FCB

4

1

5

0.17µA

OSC

FC

D

B

C

BOOST

15

F

–

+

SYNC

OSC

V

SEC

+

1.2V

0.8V

C

B

TG

16

FORCE BOT

TOP

DROP

OUT

+

SW

14

C

SEC

DET

BOT

SWITCH

LOGIC

OV

S

R

D

TOP ON

0.55V

+

–

1

Q

B

+

–

0.86V

2.4V

SD

IREV

2k

45k

–

V

OUT

V

OSENSE

6

Ω

V

FB

0.8V

gm =1.3m

SD

ICMP

–

BOT

+

–

+

I

2

–

+

–

1

EA

C

OUT

+

INTV

12

CC

0.86V

R1

R2

V

3mV

IN

BURST

DISABLE

FC

+

C

INTVCC

5.2V

LDO

REG

INTV

RUN

SOFT-

START

+

OVER-

CURRENT

LATCHOFF

CC

1.2µA

A

4(V

FB

)

BUFFERED

TH

I

BG

11

4.7V

+

–

30k

6V

SLOPE COMP

PGND

10

R

C

+

–

2

3

8

7

9

RUN/SS

I

SENSE

EXTV

CC

TH

C

SS

R

SENSE

1735 FD

8

LTC1735

U

(Refer to Functional Diagram)

OPERATIO

Main Control Loop

conditions that may overvoltage the output. In this case,

the top MOSFET is turned off and the bottom MOSFET is

turned on until the overvoltage condition is cleared.

The LTC1735 uses a constant frequency, current mode

step-down architecture. During normal operation, the top

MOSFET is turned on each cycle when the oscillator sets

the RS latch and turned off when the main current com-

parator I₁resets the RS latch. The peak inductor current at

which I₁resets the RS latch is controlled by the voltage on

Pin 3 (I_TH), which is the output of error amplifier EA. Pin 6

(V_OSENSE), described in the pin functions, allows EA to

receive an output feedback voltage V_FBfrom an external

resistive divider. When the load current increases, it

causes a slight decrease in V_FBrelative to the 0.8V refer-

ence, which in turn causes the I_THvoltage to increase until

the average inductor current matches the new load cur-

rent. While the top MOSFET is off, the bottom MOSFET is

turnedonuntileithertheinductorcurrentstartstoreverse,

as indicated by current comparator I₂, or the beginning of

the next cycle.

Foldback current limiting for an output shorted to ground

is provided by amplifier A. As V_OSENSEdrops below 0.6V,

the buffered I_THinput to the current comparator is gradu-

ally pulled down to a 0.86V clamp. This reduces peak

inductor current to about 1/4 of its maximum value.

Low Current Operation

The LTC1735 has three low current modes controlled by

the FCB pin. Burst Mode operation is selected when the

FCB pin is above 0.8V (typically tied to INTV_CC). In Burst

Modeoperation,iftheerroramplifierdrivestheI_THvoltage

below 0.86V, the buffered I_THinput to the current com-

parator will be clamped at 0.86V. The inductor current

peak is then held at approximately 20mV/R_SENSE(about

1/4 of maximum output current). If I_THthen drops below

0.5V, the Burst Mode comparator B will turn off both

MOSFETs to maximize efficiency. The load current will be

supplied solely by the output capacitor until I_THrises

above the 60mV hysteresis of the comparator and switch-

ing is resumed. Burst Mode operation is disabled by

comparator F when the FCB pin is brought below 0.8V.

This forces continuous operation and can assist second-

ary winding regulation.

The top MOSFET driver is powered from a floating boot-

strap capacitor C_B. This capacitor is normally recharged

from INTV_CCthrough an external diode when the top

MOSFET is turned off. As V_INdecreases towards V_OUT, the

converter will attempt to turn on the top MOSFET continu-

ously (“dropout’’). A dropout counter detects this condi-

tionandforcesthetopMOSFETtoturnoffforabout500ns

every tenth cycle to recharge the bootstrap capacitor.

When the FCB pin is driven by an external oscillator, a low

noise cycle-skipping mode is invoked and the internal

oscillator is synchronized to the external clock by com-

parator C. In this mode the 25% minimum inductor

current clamp is removed, providing constant frequency

discontinuous operation over the widest possible output

current range. This constant frequency operation is not

quite as efficient as Burst Mode operation, but provides a

lower noise, constant frequency spectrum.

The main control loop is shut down by pulling Pin 2

(RUN/SS)low.ReleasingRUN/SSallowsaninternal1.2µA

current source to charge soft-start capacitor C_SS. When

C_SSreaches1.5V,themaincontrolloopisenabledwiththe

I_THvoltageclampedatapproximately30%ofitsmaximum

value. As C_SScontinues to charge, I_THis gradually re-

leased allowing normal operation to resume. If V_OUThas

not reached 70% of its final value when C_SShas charged

to 4.1V, latchoff can be invoked as described in the

Applications Information section.

The FCB pin is tied to ground when forced continuous

operation is desired. This is the least efficient mode, but is

desirable in certain applications. The output can source or

sink current in this mode. When sinking current while in

forced continuous operation, current will be forced back

into the main power supply potentially boosting the input

supply to dangerous voltage levels—BEWARE.

The internal oscillator can be synchronized to an external

clock applied to the FCB pin and can lock to a frequency

between 90% and 130% of its nominal rate set by capaci-

tor C_OSC

.

Anovervoltagecomparator, OV, guardsagainsttransient

overshoots (>7.5%) as well as other more serious

9

LTC1735

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(Refer to Functional Diagram)

OPERATIO

Foldback Current, Short-Circuit Detection and

Short-Circuit Latchoff

outputvoltagefallsbelow70%ofitsnominallevelwhether

or not the short-circuit latchoff circuit is enabled.

The RUN/SS capacitor, C_SS, is used initially to limit the

inrush current of the switching regulator. After the con-

troller has been started and been given adequate time to

charge up the output capacitors and provide full load cur-

rent, C_SSis used as a short-circuit time-out circuit. If the

output voltage falls to less than 70% of its nominal output

voltage, C_SSbegins discharging on the assumption that

the output is in an overcurrent and/or short-circuit condi-

tion. If the condition lasts for a long enough period as

determined by the size of C_SS, the controller will be shut

down until the RUN/SS pin voltage is recycled. This built-

in latchoff can be overridden by providing a current >5µA

at a compliance of 5V to the RUN/SS pin. This current

shortens the soft-start period but also prevents net dis-

charge of C_SSduring an overcurrent and/or short-circuit

condition. Foldback current limiting is activated when the

INTV_CC/EXTV_CCPOWER

Power for the top and bottom MOSFET drivers and most

of the internal circuitry of the LTC1735 is derived from the

INTV_CCpin. When the EXTV_CCpin is left open, an internal

5.2V low dropout regulator supplies the INTV_CCpower

from V_IN. If EXTV_CCis raised above 4.7V, the internal

regulator is turned off and an internal switch connects

EXTV_CCto INTV_CC. This allows a high efficiency source,

suchastheprimaryorasecondaryoutputoftheconverter

itself, to provide the INTV_CCpower. Voltages up to 7V can

be applied to EXTV_CCfor additional gate drive capability.

To provide clean start-up and to protect the MOSFETs,

undervoltage lockout is used to keep both MOSFETs off

until the input voltage is above 3.5V.

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ThebasicLTC1735applicationcircuitisshowninFigure 1

on the first page. External component selection is driven

by the load requirement and begins with the selection of

R_SENSE. OnceR_SENSEisknown, C_OSCandLcanbechosen.

Next, the power MOSFETs and D1 are selected. The

operating frequency and the inductor are chosen based

largelyonthedesiredamountofripplecurrent. Finally, C_IN

is selected for its ability to handle the large RMS current

into the converter and C_OUTis chosen with low enough

ESR to meet the output voltage ripple and transient speci-

fications. The circuit shown in Figure 1 can be configured

for operation up to an input voltage of 28V (limited by the

external MOSFETs).

Allowing a margin for variations in the LTC1735 and

external component values yields:

50mV

R

=

SENSE

I

MAX

C_OSCSelection for Operating Frequency and

Synchronization

The choice of operating frequency and inductor value is a

trade-off between efficiency and component size. Low

frequency operation improves efficiency by reducing

MOSFET switching losses, both gate charge loss and

transition loss. However, lower frequency operation re-

quires more inductance for a given amount of ripple

current.

R_SENSESelection for Output Current

R_SENSEis chosen based on the required output current.

The LTC1735 current comparator has a maximum thresh-

old of 75mV/R_SENSEand an input common mode range of

SGND to 1.1(INTV_CC). The current comparator threshold

sets the peak of the inductor current, yielding a maximum

average output current I_MAXequal to the peak value less

half the peak-to-peak ripple current, ∆I_L.

The LTC1735 uses a constant frequency architecture with

the frequency determined by an external oscillator capaci-

tor C_OSC. Each time the topside MOSFET turns on, the

voltage on C_OSCis reset to ground. During the on-time,

C_OSCischargedbyafixedcurrent.Whenthevoltageonthe

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capacitor reaches 1.19V, C_OSCis reset to ground. The

process then repeats.

allowed to reverse. The 25% minimum inductor current

clamp present in Burst Mode operation is removed,

providing constant frequency discontinuous operation

over the widest possible output current range. In this

mode the synchronous MOSFET is forced on once every

10 clock cycles to recharge the bootstrap capacitor. This

minimizes audible noise while maintaining reasonably

high efficiency.

The value of C_OSCis calculated from the desired operating

frequency assuming no external clock input on the FCB

pin:

7

1.61(10 )

Frequency

C

(pF) =

– 11

OSC

Inductor Value Calculation

A graph for selecting C_OSCversus frequency is shown in

Figure 2. The maximum recommended switching fre-

quency is 550kHz .

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because of

MOSFET gate charge losses. In addition to this basic trade

off, the effect of inductor value on ripple current and low

current operation must also be considered.

The internal oscillator runs at its nominal frequency (f_O)

when the FCB pin is pulled high to INTV_CCor connected to

ground. Clocking the FCB pin above and below 0.8V will

cause the internal oscillator to injection lock to an external

clock signal applied to the FCB pin with a frequency

between 0.9f_Oand 1.3f_O. The clock high level must exceed

1.3V for at least 0.3µs and the clock low level must be less

than 0.3V for at least 0.3µs. The top MOSFET turn-on will

synchronize with the rising edge of the clock.

Theinductorvaluehasadirecteffectonripplecurrent.The

inductor ripple current ∆I_Ldecreases with higher induc-

tance or frequency and increases with higher V_INor V_OUT

:

Attempting to synchronize to too high an external fre-

quency (above 1.3f_O) can result in inadequate slope com-

pensation and possible loop instability. If this condition

existssimplylowerthevalueofC_OSCsof_EXT=f_Oaccording

to Figure 2.

1

V

OUT

V

IN

∆I =

V

1–

L

OUT

(f)(L)

Accepting larger values of ∆I_Lallows the use of low

inductances, but results in higher output voltage ripple

and greater core losses. A reasonable starting point for

setting ripple current is∆I_L= 0.3 to 0.4(I_MAX). Remember,

the maximum ∆I_Loccurs at the maximum input voltage.

When synchronized to an external clock, Burst Mode

operation is disabled but the inductor current is not

100.0

87.5

75.0

62.5

50.0

37.5

25.0

12.5

0

The inductor value also has an effect on low current

operation. The transition to low current operation begins

when the inductor current reaches zero while the bottom

MOSFET is on. Burst Mode operation begins when the

averageinductorcurrentrequiredresultsinapeakcurrent

below 25% of the current limit determined by R_SENSE

.

Lower inductor values (higher ∆I_L) will cause this to occur

at higher load currents, which can cause a dip in efficiency

in the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to decrease.

0

100

200

300

400

500

600

OPERATING FREQUENCY (kHZ)

1735 F02

Figure 2. Timing Capacitor Value

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Inductor Core Selection

SelectioncriteriaforthepowerMOSFETsincludethe“ON”

resistance R_DS(ON), reverse transfer capacitance C_RSS

input voltage and maximum output current. When the

LTC1735 is operating in continuous mode the duty cycles

for the top and bottom MOSFETs are given by:

,

Once the value for L is known, the type of inductor must be

selected. High efficiency converters generally cannot af-

ford the core loss found in low cost powdered iron cores,

forcing the use of more expensive ferrite, molypermalloy

or Kool Mµ^®cores. Actual core loss is independent of

coresizeforafixedinductorvalue, butitisverydependent

on inductance selected. As inductance increases, core

losses go down. Unfortunately, increased inductance re-

quires more turns of wire and therefore copper losses will

increase.

V

OUT

Main SwitchDuty Cycle =

IN

V – V

IN

OUT

Synchronous SwitchDuty Cycle =

V

IN

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

The MOSFET power dissipations at maximum output

current are given by:

2

) (

V

OUT

P

=

I

1+δ R

+

(

)

MAIN

MAX

DS(ON)

IN

2

k V

I

C

f

(

) (

)(

)( )

IN

MAX RSS

Molypermalloy (from Magnetics, Inc.) is a very good, low

losscorematerialfortoroids,butitismoreexpensivethan

ferrite. A reasonable compromise from the same manu-

facturer is Kool Mµ. Toroids are very space efficient,

especially when you can use several layers of wire. Be-

cause they generally lack a bobbin, mounting is more

difficult. However, designsforsurfacemountareavailable

that do not increase the height significantly.

2

) (

V – V

IN

OUT

P

=

I

(

1+δ R

)

SYNC

MAX

DS(ON)

V

IN

where δ is the temperature dependency of R_DS(ON)and k

is a constant inversely related to the gate drive current.

Both MOSFETs have I²R losses while the topside

N-channel equation includes an additional term for transi-

tion losses, which are highest at high input voltages. For

V_IN< 20V the high current efficiency generally improves

with larger MOSFETs, while for V_IN> 20V the transition

losses rapidly increase to the point that the use of a higher

R_DS(ON)device with lower C_RSSactually provides higher

efficiency. The synchronous MOSFET losses are greatest

at high input voltage or during a short-circuit when the

duty cycle in this switch is nearly 100%.

Power MOSFET and D1 Selection

Two external power MOSFETs must be selected for use

with the LTC1735: An N-channel MOSFET for the top

(main) switch and an N-channel MOSFET for the bottom

(synchronous) switch.

The peak-to-peak gate drive levels are set by the INTV_CC

voltage. This voltage is typically 5.2V during start-up (see

EXTV_CCpinconnection).Consequently,logic-levelthresh-

old MOSFETs must be used in most LTC1735 applica-

tions. The only exception is when low input voltage is

expected (V_IN< 5V); then, sub-logic level threshold

MOSFETs (V_GS(TH)< 3V) should be used. Pay close

attention to the BV_DSSspecification for the MOSFETs as

well; many of the logic level MOSFETs are limited to 30V

or less.

The term (1 + δ) is generally given for a MOSFET in the

form of a normalized R_DS(ON)vs Temperature curve, but

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs. C_RSSis usually specified in the

MOSFET characteristics. The constant k = 1.7 can be

used to estimate the contributions of the two terms in the

main switch dissipation equation.

Kool Mµ is a registered trademark of Magnetics, Inc.

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TheSchottkydiodeD1showninFigure1conductsduringthe

dead-timebetweentheconductionofthetwopowerMOSFETs.

This prevents the body diode of the bottom MOSFET from

turning on and storing charge during the dead-time, which

could cost as much as 1% in efficiency. A 3A Schottky is

generally a good size for 10A to 12A regulators due to the

relatively small average current. Larger diodes can result in

additionaltransitionlossesduetotheirlargerjunctioncapaci-

tance. The diode may be omitted if the efficiency loss can be

tolerated.

increases with input voltage. Typically, once the ESR

requirement for C_OUThas been met, the RMS current

ratinggenerallyfarexceedstheI_{RIPPLE(P–P)}requirement.

With∆I_L=0.3I_OUT(MAX)andallowing2/3oftherippledue

toESRtheoutputripplewillbelessthan50mVatmaxV_IN

assuming:

C_OUTrequired ESR < 2.2 R_SENSE

C_OUT> 1/(8fR_SENSE

)

ThefirstconditionrelatestotheripplecurrentintotheESR

of the output capacitance while the second term guaran-

tees that the output capacitance does not significantly

discharge during the operating frequency period due to

ripple current. The choice of using smaller output capaci-

tance increases the ripple voltage due to the discharging

term but can be compensated for by using capacitors of

very low ESR to maintain the ripple voltage at or below

50mV. The I_THpin OPTI-LOOP compensation compo-

nents can be optimized to provide stable, high perfor-

mancetransientresponseregardlessoftheoutputcapaci-

tors selected.

C_INSelection

In continuous mode, the source current of the top

N-channel MOSFET is a square wave of duty cycle V_OUT

/

V_IN. To prevent large voltage transients, a low ESR input

capacitor sized for the maximum RMS current must be

used. The maximum RMS capacitor current is given by:

1/2

V

IN

V

OUT

I

– 1

RMS O(MAX)

IN

This formula has a maximum at V_IN= 2V_OUT, where

I_RMS= I_O(MAX)/2. This simple worst case condition is com-

monlyusedfordesignbecauseevensignificantdeviationsdo

not offer much relief. Note that capacitor manufacturers’

ripple current ratings are often based on only 2000 hours of

life. This makes it advisable to further derate the capacitor or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may also be paralleled to meet

size or height requirements in the design. Always consult the

manufacturer if there is any question.

The selection of output capacitors for CPU or other appli-

cations with large load current transients is primarily

determined by the voltage tolerance specifications of the

load. The resistive component of the capacitor, ESR,

multiplied by the load current change plus any output

voltage ripple must be within the voltage tolerance of the

load (CPU).

The required ESR due to a load current step is:

R_ESR< ∆V/∆I

where∆Iisthechangeincurrentfromfullloadtozeroload

(orminimumload)and∆Vistheallowedvoltagedeviation

(not including any droop due to finite capacitance).

C_OUTSelection

The selection of C_OUTis primarily determined by the

effective series resistance (ESR) to minimize voltage

ripple. The output ripple (∆V_OUT) in continuous mode is

determined by:

The amount of capacitance needed is determined by the

maximum energy stored in the inductor. The capacitance

mustbesufficienttoabsorbthechangeininductorcurrent

when a high current to low current transition occurs. The

oppositeloadcurrenttransitionisgenerallydeterminedby

the control loop OPTI-LOOP components, so make sure

not to over compensate and slow down the response. The

minimum capacitance to assure the inductors’ energy is

adequately absorbed is:

1

∆V_OUT≈ ∆I_LESR +

8fC_OUT

Where f = operating frequency, C_OUT= output capaci-

tance and ∆I_L= ripple current in the inductor. The output

ripple is highest at maximum input voltage since ∆I_L

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L(∆I)²

2(∆V)V_OUT

as close as possible to the power pins of the load. Any

inductance present in the circuit board traces negates

their usefulness.

C_OUT

>

where ∆I is the change in load current.

INTV_CCRegulator

Manufacturers such as Nichicon, United Chemicon and

Sanyo can be considered for high performance through-

hole capacitors. The OS-CON semiconductor dielectric

capacitor available from Sanyo has the lowest (ESR)(size)

product of any aluminum electrolytic at a somewhat

higher price. An additional ceramic capacitor in parallel

with OS-CON capacitors is recommended to reduce the

inductance effects.

An internal P-channel low dropout regulator produces the

5.2V supply that powers the drivers and internal circuitry

within the LTC1735. The INTV_CCpin can supply a maxi-

mum RMS current of 50mA and must be bypassed to

ground with a minimum of 4.7µF tantalum, 10µF special

polymer or low ESR type electrolytic capacitor. A 1µF

ceramic capacitor placed directly adjacent to the INTV_CC

and PGND IC pins is highly recommended. Good bypass-

ing is required to supply the high transient currents

required by the MOSFET gate drivers.

In surface mount applications multiple capacitors may

need to be used in parallel to meet the ESR, RMS current

handling and load step requirements of the application.

Aluminum electrolytic, dry tantalum and special polymer

capacitors are available in surface mount packages. Spe-

cial polymer surface mount capacitors offer very low ESR

but have much lower capacitive density per unit volume

than other capacitor types. These capacitors offer a very

cost-effective output capacitor solution and are an ideal

choice when combined with a controller having high loop

bandwidth. Tantalum capacitors offer the highest capaci-

tance density and are often used as output capacitors for

switching regulators having controlled soft-start. Several

excellent surge-tested choices are the AVX TPS, AVX

TPSV or the KEMET T510 series of surface mount

tantalums, available in case heights ranging from 2mm to

4mm. Aluminum electrolytic capacitors can be used in

cost-driven applications providing that consideration is

given to ripple current ratings, temperature and long-term

reliability.Atypicalapplicationwillrequireseveraltomany

aluminum electrolytic capacitors in parallel. A combina-

tion of the above mentioned capacitors will often result in

maximizing performance and minimizing overall cost.

Other capacitor types include Nichicon PL series, NEC

Neocap, Panasonic SP and Sprague 595D series. Consult

manufacturers for other specific recommendations.

Higher input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC1735 to be

exceeded. The system supply current is normally domi-

nated by the gate charge current. Additional loading of

INTV_CCalso needs to be taken into account for the power

dissipation calculations. The total INTV_CCcurrent can be

supplied by either the 5.2V internal linear regulator or by

the EXTV_CCinput pin. When the voltage applied to the

EXTV_CCpin is less than 4.7V, all of the INTV_CCcurrent is

supplied by the internal 5.2V linear regulator. Power

dissipation for the IC in this case is highest: (V_IN)(I_INTVCC

)

and overall efficiency is lowered. The gate charge is

dependent on operating frequency as discussed in the

Efficiency Considerations section. The junction tempera-

ture can be estimated by using the equations given in

Note 2 of the Electrical Characteristics. For example, the

LTC1735CS is limited to less than 17mA from a 30V

supply when not using the EXTV_CCpin as follows:

T_J= 70°C + (17mA)(30V)(110°C/W) = 126°C

UseoftheEXTV_CCinputpinreducesthejunctiontempera-

ture to:

T_J= 70°C + (17mA)(5V)(110°C/W) = 79°C

Like all components, capacitors are not ideal. Each ca-

pacitor has its own benefits and limitations. Combina-

tions of different capacitor types have proven to be a very

cost effective solution. Remember also to include high

frequency decoupling capacitors. They should be placed

To prevent maximum junction temperature from being

exceeded, the input supply current must be checked

operating in continuous mode at maximum V_IN.

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EXTV_CCConnection

MOSFET gate drive requirements. This is the typical case

asthe5Vpowerisalmostalwayspresentandisderivedby

another high efficiency regulator.

The LTC1735 contains an internal P-channel MOSFET

switch connected between the EXTV_CCand INTV_CCpins.

Whenever the EXTV_CCpin is above 4.7V the internal 5.2V

regulator shuts off, the switch closes and INTV_CCpower is

supplied via EXTV_CCuntil EXTV_CCdrops below 4.5V. This

allows the MOSFET gate drive and control power to be

derived from the output or other external source during

normal operation. When the output is out of regulation

(start-up,shortcircuit)powerissuppliedfromtheinternal

regulator. Do not apply greater than 7V to the EXTV_CCpin

and ensure that EXTV_CC≤ V_IN.

V

IN

OPTIONAL EXTV

CONNECTION

CC

5V ≤ V

≤ 7V

+

SEC

C

IN

1N4148

V

SEC

V

IN

+

LTC1735

6.8V

1µF

N-CH

TG

SW

BG

R

SENSE

V

OUT

L1

1:N

EXTV

CC

R4

R3

+

C

OUT

Significant efficiency gains can be realized by powering

INTV_CCfrom the output, since the V_INcurrent resulting

from the driver and control currents will be scaled by a

factor of (Duty Cycle)/(Efficiency). For 5V regulators this

FCB

SGND

PGND

1735 F03a

simply means connecting the EXTV_CCpin directly to V_OUT

.

Figure 3a. Secondary Output Loop and EXTV_CCConnection

However, for 3.3V and other lower voltage regulators,

additional circuitry is required to derive INTV_CCpower

from the output.

+

V

IN

1µF

+

The following list summarizes the four possible connec-

tions for EXTV_CC:

C

IN

0.22µF

BAT85

V

IN

1. EXTV_CCleft open (or grounded). This will cause INTV_CC

to be powered from the internal 5.2V regulator resulting in

an efficiency penalty of up to 10% at high input voltages.

LTC1735

VN2222LL

N-CH

TG

SW

BG

R

SENSE

V

OUT

L1

EXTV

CC

2. EXTV_CCconnected directly to V_OUT. This is the normal

connection for a 5V output regulator and provides the

highest efficiency. For output voltages higher than 5V,

EXTV_CCis required to connect to V_OUTso the SENSE pins’

absolute maximum ratings are not exceeded.

+

C

OUT

N-CH

PGND

1735 F03b

3. EXTV_CCconnected to an output-derived boost network.

For 3.3V and other low voltage regulators, efficiency gains

can still be realized by connecting EXTV_CCto an output-

derived voltage that has been boosted to greater than

4.7V. This can be done with either the inductive boost

winding as shown in Figure 3a or the capacitive charge

pump shown in Figure 3b. The charge pump has the

advantage of simple magnetics.

Figure 3b. Capacitive Charge Pump for EXTV_CC

Output Voltage Programming

The output voltage is set by an external resistive divider

according to the following formula:

R2

R1

V

= 0.8V 1+

OUT

4. EXTV_CCconnected to an external supply. If an external

supply is available in the 5V to 7V range (EXTV_CC≤ V_IN),

such as notebook main 5V system power, it may be used

to power EXTV_CCproviding it is compatible with the

The resistive divider is connected to the output as shown

in Figure 4 allowing remote voltage sensing.

15

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V

OUT

V_OUTresistive divider. The maximum current flowing out

of the sense pins is:

R2

V

I_SENSE⁺+ I_SENSE^–= (2.4V – V_OUT)/24k

OSENSE

47pF

R1

LTC1735

SGND

SinceV_OSENSEisservoedtothe0.8Vreferencevoltage, we

can choose R1 in Figure 4 to have a maximum value to

absorb this current:

1735 F04

Figure 4. Setting the LTC1735 Output Voltage

0.8V

R1

= 24k

(MAX)

Topside MOSFET Driver Supply (C_B, D_B)

2.4V – V

OUT

An external bootstrap capacitor C_Bconnected to the

BOOST pin supplies the gate drive voltage for the topside

MOSFET.CapacitorC_BintheFunctionalDiagramischarged

though external diode D_Bfrom INTV_CCwhen the SW pin

is low. Note that the voltage across C_Bis about a diode

drop below INTV_CC. When the topside MOSFET is to be

turned on, the driver places the C_Bvoltage across the

gate-source of the MOSFET. This enhances the MOSFET

and turns on the topside switch. The switch node voltage

SW rises to V_INand the BOOST pin rises to V_IN+ INTV_CC.

The value of the boost capacitor C_Bneeds to be 100 times

greater than the total input capacitance of the topside

MOSFET. In most applications 0.1µF to 0.33µF is ad-

equate. The reverse breakdown on D_Bmust be greater

Regulating an output voltage of 1.8V, the maximum value

of R1 should be 32k. Note that at output voltages above

2.4V no maximum value of R1 is necessary to absorb the

sense pin currents; however, R1 is still bounded by the

V_OSENSEfeedback current.

Soft-Start/Run Function

The RUN/SS pin is a multipurpose pin that provides a soft-

start function and a means to shut down the LTC1735.

Soft-start reduces surge currents from V_INby gradually

increasing the controller’s current limit I_TH(MAX). This pin

can also be used for power supply sequencing.

Pulling the RUN/SS pin below 1.5V puts the LTC1735 into

alowquiescentcurrentshutdown(I_Q<25µA).Thispincan

be driven directly from logic as shown in Figure 5. Releas-

ing the RUN/SS pin allows an internal 1.2µA current

source to charge up the external soft-start capacitor C_SS.

If RUN/SS has been pulled all the way to ground there is

a delay before starting of approximately:

than V_IN(MAX)

.

When adjusting the gate drive level, the final arbiter is the

total input current for the regulator. If you make a change

and the input current decreases, then you improved the

efficiency. If there is no change in input current, then there

is no change in efficiency.

1.5V

1.2µA

SENSE⁺/SENSE^–Pins

t_DELAY

=

C_SS= 1.25s/µF C

SS

(

)

The common mode input range of the current comparator

is from 0V to 1.1(INTV_CC). Continuous linear operation in

step-down applications is guaranteed throughout this

range allowing output voltages anywhere from 0.8V to 7V.

A differential NPN input stage is used and is biased with

internal resistors from an internal 2.4V source as shown

in the Functional Diagram. This causes current to either be

sourced or sunk by the sense pins depending on the

output voltage. If the output voltage is below 2.4V current

will flow out of both sense pins to the main output. This

forces a minimum load current that can be fulfilled by the

When the voltage on RUN/SS reaches 1.5V the LTC1735

begins operating with a current limit at approximately

25mV/R_SENSE.AsthevoltageontheRUN/SSpinincreases

from 1.5V to 3.0V, the internal current limit is increased

from 25mV/R_SENSEto 75mV/R_SENSE. The output current

limit ramps up slowly, taking an additional 1.25s/µF to

reach full current. The output current thus ramps up

slowly, reducing the starting surge current required from

the input power supply.

16

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Diode D1 in Figure 5 reduces the start delay while allowing

C_SSto charge up slowly for the soft-start function. This

diode and C_SScan be deleted if soft-start is not needed.

The RUN/SS pin has an internal 6V zener clamp (See

Functional Diagram).

capacitor during a severe overcurrent and/or short-circuit

condition. When deriving the 5µA current from V_INas in

Figure 6a, current latchoff is always defeated. Diode con-

necting this pull-up resistor to INTV_CC, as in Figure 6b,

eliminatesanyextrasupplycurrentduringcontrollershut-

down while eliminating the INTV_CCloading from prevent-

ing controller start-up. If the voltage on C_SSdoes not

exceed 4.1V the overcurrent latch is not armed and the

function is disabled.

3.3V OR 5V

RUN/SS

D1

C

SS

C

SS

Why should you defeat overcurrent latchoff? During the

prototypingstageofadesign,theremaybeaproblemwith

noise pickup or poor layout causing the protection circuit

to latch off. Defeating this feature will easily allow trouble-

shooting of the circuit and PC layout. The internal short-

circuit and foldback current limiting still remains active,

thereby protecting the power supply system from failure.

After the design is complete, a decision can be made

whether to enable the latchoff feature.

1735 F05

Figure 5. RUN/SS Pin Interfacing

Fault Conditions: Overcurrent Latchoff

The RUN/SS pin also provides the ability to shut off the

controller and latch off when an overcurrent condition is

detected. The RUN/SS capacitor, C_SS, is used initially to

turn on and limit the inrush current of the controller. After

the controller has been started and given adequate time to

charge up the output capacitor and provide full load

current, C_SSis used as a short-circuit timer. If the output

voltagefallstolessthan70%ofit’snominaloutputvoltage

after C_SSreaches 4.1V, the assumption is made that the

output is in a severe overcurrent and/or short-circuit

condition and C_SSbegins discharging. If the condition

lasts for a long enough period as determined by the size of

C_SS, the controller will be shut down until the RUN/SS pin

voltage is recycled.

The value of the soft-start capacitor C_SSwill need to be

scaled with output current, output capacitance and load

current characteristics. The minimum soft-start capaci-

tance is given by:

C_SS> (C_OUT)(V_OUT)(10^–4)(R_SENSE

)

The minimum recommended soft-start capacitor of

C_SS= 0.1µF will be sufficient for most applications.

Fault Conditions: Current Limit and Current Foldback

The LTC1735 current comparator has a maximum sense

voltage of 75mV resulting in a maximum MOSFET current

This built-in latchoff can be overridden by providing a

current >5µA at a compliance of 5V to the RUN/SS pin as

shown in Figure 6. This current shortens the soft-start

period but also prevents net discharge of the RUN/SS

of 75mV/R_SENSE

.

The LTC1735 includes current foldback to help further

limit load current when the output is shorted to ground.

The foldback circuit is active even when the overload

shutdown latch described above is defeated. If the output

falls by more than half, then the maximum sense voltage

is progressively lowered from 75mV to 30mV. Under

short-circuit conditions with very low duty cycle, the

LTC1735 will begin cycle skipping in order to limit the

short-circuit current. In this situation the bottom MOSFET

will be conducting the peak current. The short-circuit

ripple current is determined by the minimum on-time

V

INTV

IN

CC

3.3V OR 5V

RUN/SS

R

SS

D1

RUN/SS

D1

C

SS

C

SS

1735 F06

(a)

(b)

Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated

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t_ON(MIN)of the LTC1735 (approximately 200ns), the input

the gate charge required to turn on the top MOSFET. Low

duty cycle applications may approach this minimum on-

time limit and care should be taken to ensure that:

voltage and inductor value:

∆I_L(SC)= t_ON(MIN)V_IN/L

The resulting short-circuit current is:

V

OUT

t

<

ON(MIN)

V (f)

IN

30mV

1

2

I

=

+ ∆I

SC

L(SC)

Ifthedutycyclefallsbelowwhatcanbeaccommodatedby

the minimum on-time, the LTC1735 will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple current and voltage will increase.

R

SENSE

The current foldback function is always active and is not

effected by the current latchoff function.

The minimum on-time for the LTC1735 in a properly

configured application is generally less than 200ns. How-

ever, as the peak sense voltage decreases, the minimum

on-time gradually increases as shown in Figure 7. This is

of particular concern in forced continuous applications

withlowripplecurrentatlightloads.Ifthedutycycledrops

below the minimum on-time limit in this situation, a

significant amount of cycle skipping can occur with corre-

spondingly larger current and voltage ripple.

Fault Conditions: Output Overvoltage Protection

(Crowbar)

The output overvoltage crowbar is designed to blow a

system fuse in the input lead when the output of the

regulator rises much higher than nominal levels. This

conditioncauseshugecurrentstoflow,muchgreaterthan

in normal operation. This feature is designed to protect

against a shorted top MOSFET; it does not protect against

a failure of the controller itself.

If an application can operate close to the minimum on-

time limit, an inductor must be chosen that is low enough

to provide sufficient ripple amplitude to meet the mini-

mum on-time requirement. As a general rule keep the

inductor ripple current equal or greater than 30% of

The comparator (OV in the Functional Diagram) detects

overvoltage faults greater than 7.5% above the nominal

output voltage. When this condition is sensed the top

MOSFET is turned off and the bottom MOSFET is forced

on. The bottom MOSFET remains on continuously for as

long as the 0V condition persists; if V_OUTreturns to a safe

level, normal operation automatically resumes.

I_OUT(MAX)at V_IN(MAX)

.

250

200

150

100

50

Note that dynamically changing the output voltage may

cause overvoltage protection to be momentarily activated

during programmed output voltage decreases. This will

notcausepermanentlatchoffnorwillitdisruptthedesired

voltage change. With soft-latch overvoltage protection,

dynamically changing the output voltage is allowed and

the overvoltage protection tracks the newly programmed

output voltage, always protecting the load.

0

Minimum On-Time Considerations

0

10

20

30

40

∆I /I

(%)

L

OUT(MAX)

Minimum on-time t_ON(MIN)is the smallest amount of time

that the LTC1735 is capable of turning the top MOSFET on

andoffagain.Itisdeterminedbyinternaltimingdelaysand

1735 F07

Figure 7. Minimum On-Time vs ∆I_L

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FCB Pin Operation

internal current source pulling the pin high. Remember to

include this current when choosing resistor values R3 and

R4.

WhentheFCBpindropsbelowits0.8Vthreshold,continu-

ous mode operation is forced. In this case, the top and

bottom MOSFETs continue to be driven synchronously

regardless of the load on the main output. Burst Mode

operation is disabled and current reversal is allowed in the

inductor.

The internal LTC1735 oscillator can be synchronized to an

external oscillator by applying and clocking the FCB pin

with a signal above 1.5V_P–P. When synchronized to an

external frequency, Burst Mode operation is disabled but

cycleskippingisallowedatlowloadcurrentssincecurrent

reversal is inhibited. The bottom gate will come on every

10 clock cycles to assure the bootstrap cap is kept re-

freshed. The rising edge of an external clock applied to the

FCB pin starts a new cycle.

In addition to providing a logic input to force continuous

synchronous operation and external synchronization, the

FCB pin provides a means to regulate a flyback winding

output. During continuous mode, current flows continu-

ouslyinthetransformerprimary.Thesecondarywinding(s)

draw current only when the bottom, synchronous switch

is on. When primary load currents are low and/or the V_IN/

V_OUTratio is low, the synchronous switch may not be on

for a sufficient amount of time to transfer power from the

outputcapacitortothesecondaryload.Forcedcontinuous

operationwillsupportsecondarywindingsprovidingthere

is sufficient synchronous switch duty factor. Thus, the

FCB input pin removes the requirement that power must

be drawn from the inductor primary in order to extract

power from the auxiliary windings. With the loop in

continuous mode, the auxiliary outputs may nominally be

loaded without regard to the primary output load.

The range of synchronization is from 0.9f_Oto 1.3f_O, with

f_Oset by C_OSC. Attempting to synchronize to a higher

frequency than 1.3f_Ocan result in inadequate slope com-

pensation and cause loop instability with high duty cycles

(duty cycle > 50%). If loop instability is observed while

synchronized, additional slope compensation can be ob-

tained by simply decreasing C_OSC

.

The following table summarizes the possible states avail-

able on the FCB pin:

Table 1

FCB Pin

Condition

DC Voltage: 0V to 0.7V

Burst Disabled/Forced Continuous

Current Reversal Enabled

The secondary output voltage V_SECis normally set as

shown in Figure 3a by the turns ratio N of the transformer:

DC Voltage: ≥ 0.9V

Burst Mode Operation,

No Current Reversal

V_SEC(N + 1)V_OUT

Feedback Resistors

Regulating a Secondary Winding

However, if the controller goes into Burst Mode operation

and halts switching due to a light primary load current,

then V_SECwill droop. An external resistive divider from

Ext Clock: (0V to V

)

Burst Mode Operation Disabled

No Current Reversal

FCBSYNC

(V

FCBSYNC

> 1.5V)

Efficiency Considerations

V_SECto the FCB pin sets a minimum voltage V_SEC(MIN)

:

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can be

expressed as:

R4

R3

V

≈ 0.8V 1+

SEC(MIN)

If V_SECdrops below this level, the FCB voltage forces

continuous switching operation until V_SECis again above

its minimum.

%Efficiency = 100% – (L1 + L2 + L3 + …)

In order to prevent erratic operation if no external connec-

tions are made to the FCB pin, the FCB pin has a 0.17µA

whereL1, L2, etc. aretheindividuallossesasapercentage

of input power.

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Although all dissipative elements in the circuit produce

losses, 4 main sources usually account for most of the

losses in LTC1735 circuits: 1) LTC1735 V_INcurrent,

2) INTV_CCcurrent, 3) I²R losses, 4) Topside MOSFET

transition losses.

4) Transition losses apply only to the topside MOSFET(s)

and only become significant when operating at high input

voltages (typically 12V or greater). Transition losses can

be estimated from:

2

Transition Loss = (1.7) V_INI_O(MAX)C_RSS

f

1) The V_INcurrent is the DC supply current given in the

electrical characteristics which excludes MOSFET driver

andcontrolcurrents.V_INcurrentresultsinasmall(<0.1%)

loss that increases with V_IN.

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efficiency degradation in portable systems. It is very

important to include these “system” level losses in the

design of a system. The internal battery and fuse resis-

tancelossescanbeminimizedbymakingsurethatC_INhas

adequate charge storage and very low ESR at the switch-

ing frequency. A 25W supply will typically require a

minimum of 20µF to 40µF of capacitance having a maxi-

mum of 0.01Ω to 0.02Ω of ESR. Other losses including

Schottky conduction losses during dead-time and induc-

tor core losses generally account for less than 2% total

additional loss.

2) INTV_CCcurrent is the sum of the MOSFET driver and

control currents. The MOSFET driver current results from

switching the gate capacitance of the power MOSFETs.

Each time a MOSFET gate is switched from low to high to

low again, a packet of charge dQ moves from INTV_CCto

ground. The resulting dQ/dt is a current out of INTV_CCthat

is typically much larger than the control circuit current. In

continuous mode, I_GATECHG= f(Q_T+Q_B), where Q_Tand Q_B

are the gate charges of the topside and bottom-side

MOSFETs.

Checking Transient Response

SupplyingINTV_CCpowerthroughtheEXTV_CCswitchinput

fromanoutput-derivedorotherhighefficiencysourcewill

scale the V_INcurrent required for the driver and control

circuits by a factor of (Duty Cycle)/(Efficiency). For ex-

ample, in a 20V to 5V application, 10mA of INTV_CCcurrent

results in approximately 3mA of V_INcurrent. This reduces

the mid-current loss from 10% or more (if the driver was

powered directly from V_IN) to only a few percent.

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in load current.

When a load step occurs, V_OUTshifts by an amount equal

to ∆I_LOAD(ESR), where ESR is the effective series resis-

tance of C_OUT. ∆I_LOADalso begins to charge or discharge

C_OUTgenerating the feedback error signal that forces the

regulator to adapt to the current change and return V_OUT

to its steady-state value. During this recovery time V_OUT

can be monitored for excessive overshoot or ringing,

which would indicate a stability problem. OPTI-LOOP

compensation allows the transient response to be opti-

mized over a wide range of output capacitance and ESR

values. The availability of the I_THpin not only allows

optimization of control loop behavior but also provides a

DC coupled and AC filtered closed loop response test

point. The DC step, rise time and settling at this test point

truly reflects the closed loop response. Assuming a pre-

dominantly second order system, phase margin and/or

damping factor can be estimated using the percentage of

overshoot seen at this pin. The bandwidth can also be

estimated by examining the rise time at the pin. The I_TH

external components shown in the Figure 1 circuit will

provide an adequate starting point for most applications.

3) I²R losses are predicted from the DC resistances of the

MOSFET, inductor and current shunt. In continuous mode

the average output current flows through L and R_SENSE

,

but is “chopped” between the topside main MOSFET and

the synchronous MOSFET. If the two MOSFETs have

approximately the same R_DS(ON), then the resistance of

one MOSFET can simply be summed with the resistances

of L and R_SENSEto obtain I²R losses. For example, if each

R_DS(ON)= 0.03Ω, R_L= 0.05Ω and R_SENSE= 0.01Ω, then

thetotalresistanceis0.09Ω.Thisresultsinlossesranging

from 2% to 9% as the output current increases from 1A to

5A for a 5V output, or a 3% to 14% loss for a 3.3V output.

Effeciency varies as the inverse square of V_OUTfor the

same external components and output power level. I²R

lossescausetheefficiencytodropathighoutputcurrents.

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The I_THseries R_C–C_Cfilter sets the dominant pole-zero

loop compensation. The values can be modified slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the final PC layout is done and the

particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

feedbackfactorgainandphase. Anoutputcurrentpulseof

20% to 100% of full load current having a rise time of 1µs

to10µswillproduceoutputvoltageandI_THpinwaveforms

that will give a sense of the overall loop stability without

breaking the feedback loop. The initial output voltage step

may not be within the bandwidth of the feedback loop, so

the standard second-order overshoot/DC ratio cannot be

used to determine phase margin. The gain of the loop will

be increased by increasing R_Cand the bandwidth of the

loop will be increased by decreasing C_C. If R_Cis increased

bythesamefactorthatC_Cisdecreased,thezerofrequency

will be kept the same, thereby keeping the phase the same

in the most critical frequency range of the feedback loop.

The output voltage settling behavior is related to the

stability of the closed-loop system and will demonstrate

the actual overall supply performance. For a detailed

explanation of optimizing the compensation components,

including a review of control loop theory, refer to Applica-

tion Note 76.

Active voltage positioning improves transient response

and reduces the output capacitance required to power a

microprocessorwhereatypicalloadstepcanbefrom0.2A

to 15A in 100ns or 15A to 0.2A in 100ns. The voltage at the

microprocessor must be held to about ±0.1V of nominal

in spite of these load current steps. Since the control loop

cannot respond this fast, the output capacitors must

supply the load current until the control loop can respond.

Capacitor ESR and ESL primarily determine the amount of

droop or overshoot in the output voltage. Normally, sev-

eral capacitors in parallel are required to meet micropro-

cessor transient requirements.

Active voltage positioning is a form of deregulation. It sets

the output voltage high for light loads and low for heavy

loads. When load current suddenly increases, the output

voltage starts from a level higher than nominal so the

output voltage can droop more and stay within the speci-

fied voltage range. When load current suddenly decreases

the output voltage starts at a level lower than nominal so

the output voltage can have more overshoot and stay

within the specified voltage range. Less output capaci-

tance is required when voltage positioning is used be-

cause more voltage variation is allowed on the output

capacitors.

Active voltage positioning can be implemented using the

OPTI-LOOParchitectureoftheLTC1735andtworesistors

connected to the I_THpin. An input voltage offset is intro-

ducedwhentheerroramplifierhastodrivearesistiveload.

This offset is limited to ±30mV at the input of the error

amplifier. The resulting change in output voltage is the

product of input offset and the feedback voltage divider

ratio.

A second, more severe transient is caused by switching in

loads with large (>1µF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C_OUT, causing a rapid drop in V_OUT. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

C_LOADto C_OUTis greater than1:50, the switch rise time

should be controlled so that the load rise time is limited to

approximately (25)(C_LOAD). Thus a 10µF capacitor would

require a 250µs rise time, limiting the charging current to

about 200mA.

Figure 8 shows a CPU-core-voltage regulator with active

voltage positioning. Resistors R1 and R4 force the input

voltage offset that adjusts the output voltage according to

the load current level. To select values for R1 and R4, first

determinetheamountofoutputderegulationallowed. The

actual specification for a typical microprocessor allows

the output to vary ±0.112V. The LTC1735 reference accu-

racy is ±1%. Using 1% tolerance resistors, the total

feedback divider accuracy is about 1% because both

feedback resistors are close to the same value. The result-

ing setpoint accuracy is ±2% so the output transient

Improve Transient Response and Reduce Output

Capacitance with Active Voltage Positioning

Fast load transient response, limited board space and low

cost are requirements of microprocessor power supplies.

21

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R3

680k

V

IN

7.5V TO

24V

C12 TO C14

10µF

R1

R4

C7

27k

100k

0.1µF

35V

C9, C19: TAIYO YUDEN JMK107BJ105

C10: KEMET T494A475M010AS

C12 TO C14: TAIYO YUDEN GMK325F106

C15 TO C18: PANASONIC EEFUE0G181R

D1: CENTRAL SEMI CMDSH-3

C1

GND

39pF

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

M1

C

TG

BOOST

SW

OSC

FDS6680A

C2

0.1µF

D2: MOTOROLA MBRS340

L1: PANASONIC ETQP6F1R0SA

M1 TO M3: FAIRCHILD FDS6680A

R5: IRC LRF2512-01-R003-J

RUN/SS

C3

100pF

C8

0.22µF

R2

100k

U1: LINEAR TECHNOLOGY LTC1735CS

I

TH

C4

U1

LTC1735

100pF

L1

1µH

R5

0.003Ω

D1

V

1.5V

15A

OUT

FCB

SGND

V

IN

CMDSH-3

C11

330pF

D2

C19

1µF

INTV

CC

MBRS340

C5

47pF

R6

10k

M2, M3

FDS6680A

×2

C15 TO

+

BG

OSENSE

C18

180µF

4V

C10

4.7µF

10V

+

R7

C9

1µF

11.5k

–

GND

SENSE

PGND

C6

1000pF

+

SENSE

EXTV

5V (OPTIONAL)

CC

1735 F08

Figure 8. CPU-Core-Voltage Regulator with Active Voltage Positioning

voltage cannot exceed ±0.082V. At V_OUT= 1.5V, the

maximum output voltage change controlled by the I_THpin

would be:

required for a given load current. V_ITHcontrols the peak

sense resistor voltage, which represents the DC output

current plus one half of the peak-to-peak inductor current.

The no load to full load V_ITHrange is from 0.3V to 2.4V,

which controls the sense resistor voltage from 0V to the

∆V_SENSE(MAX)voltage of 75mV. The calculated V_ITHscale

factor with a 0.003Ω sense resistor is:

Input Offset • V_OUT

∆V_OSENSE

=

V_REF

±0.03V •1.5

0.8V

= ±56mV

V

_ITHRange • SenseResistor Value

V_ITHScaleFactor =

∆V_SENSE(MAX)

With the optimum resistor values at the I_THpin, the output

voltage will swing from 1.55V at minimum load to 1.44V

at full load. At this output voltage, active voltage position-

ing provides an additional ±56mV to the allowable tran-

sient voltage on the output capacitors, a 68% improve-

ment over the ±82mV allowed without active voltage

positioning.

(2.4V – 0.3V)• 0.003

=

= 0.084V/A

0.075V

V_ITHat any load current is:

∆I_L

2

V_ITH= I_OUTDC

+

• V_ITHScaleFactor

The next step is to calculate the I_THpin voltage, V_ITH, scale

factor. The V_ITHscale factor reflects the I_THpin voltage

+V_ITHOffset

22

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At full load current:

The Thevenin equivalent of the gain limiting resistance

value of 17.54k is made up of a resistor R4 that sources

current into the I_THpin and resistor R1 that sinks current

to SGND.

5A_P−P

V

=

15A +

• 0.084V/A + 0.3V

ITH(MAX)

2

To calculate the resistor values, first determine the ratio

between them:

= 1.77V

At minimum load current:

V

_INTVCC– V

5.2V – 1.085V

1.085V

ITH(NOM)

k =

=

= 3.79

2A_P−P

2

V

ITH(NOM)

V

=

0.2A +

• 0.084V/A + 0.3V

ITH(MIN)

V_INTVCCis equal to V_EXTVCCor 5.2V if EXTV_CCis not used.

Resistor R4 is:

= 0.40V

In this circuit, V_ITHchanges from 0.40V at light load to

1.77V at full load, a 1.37V change. Notice that ∆I_L, the

peak-to-peak inductor current, changes from light load to

full load. Increasing the DC inductor current decreases the

permeability of the inductor core material, which de-

creases the inductance and increases ∆I_L. The amount of

inductance change is a function of the inductor design.

R4 = (k +1)•R_ITH= (3.79 +1)•17.54 = 84.0k

Resistor R1 is:

(k + 1)•R_ITH(3.79 + 1)•17.54k

R1=

=

= 22.17k

k

3.79

Unfortunately,PCBnoisecanaddtothevoltagedeveloped

across the sense resistor, R5, causing the I_THpin voltage

to be slightly higher than calculated for a given output

current. The amount of noise is proportional to the output

current level. This PCB noise does not present a serious

problem but it does change the effective value of R5 so the

calculated values of R1 and R4 may need to be adjusted to

achieve the required results. Since PCB noise is a function

ofthelayout,itwillbethesameonallboardswiththesame

layout.

To create the ±30mV input offset, the gain of the error

amplifier must be limited. The desired gain is:

∆V

1.37V

ITH

A_V=

=

= 22.8

Input Offset Error 2(0.03V)

Connectingaresistortotheoutputofthetransconductance

error amplifier will limit the voltage gain. The value of this

resistor is:

A_V

22.8

R_ITH

=

= 17.54k

Figures 9 and 10 show the transient response before and

after active voltage positioning is implemented. Notice

that active voltage positioning reduced the transient re-

Error Amplifier g_m1.3ms

To center the output voltage variation, V_ITHmust be

centered so that no I_THpin current flows when the output

voltage is nominal. V_ITH(NOM)is the average voltage be-

tween V_ITHat maximum output current and minimum

output current:

sponse from almost 200mV_P-Pto a little over 100mV_P-P

.

Refer to Design Solutions 10 for more information about

active voltage positioning.

V

_ITH(MAX)– V

ITH(MIN)

V

=

+ V

ITH(MIN)

ITH(NOM)

2

1.77V – 0.40V

+ 0.40V = 1.085V

2

23

LTC1735

U

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APPLICATIO S I FOR ATIO

The network shown in Figure 11 is the most straight

forward approach to protect a DC/DC converter from the

ravages of an automotive power line. The series diode

prevents current from flowing during reverse-battery,

while the transient suppressor clamps the input voltage

during load-dump. Note that the transient suppressor

should not conduct during double-battery operation, but

must still clamp the input voltage below breakdown of the

converter. Although the LTC1735 has a maximum input

voltage of 36V, most applications will be limited to 30V by

V_IN= 12V

_OUT= 1.5V

FIGURE 8 CIRCUIT

OUTPUT

V

VOLTAGE

1.5V

100mV/DIV

15A

10A/DIV

0A

LOAD

CURRENT

50µs/DIV

1735 F09

the MOSFET BV_DSS

.

Figure 9. Normal Transient Response (Without R1, R4)

50A I RATING

PK

FIGURE 8 CIRCUIT

V_IN= 12V

_OUT= 1.5V

V

IN

V

12V

1.582V

1.5V

OUTPUT

VOLTAGE

LTC1735

TRANSIENT VOLTAGE

SUPPRESSOR

GENERAL INSTRUMENT

1.5KA24A

100mV/DIV

1.418V

15A

1735 F11

LOAD

CURRENT

10A/DIV

Figure 11. Plugging into the Cigarette Lighter

0A

50µs/DIV

1735 F10

Design Example

As a design example, assume V_IN= 12V(nominal),

V_IN= 22V(max), V_OUT= 1.8V, I_MAX= 5A and f = 300kHz.

R_SENSEand C_OSCcan immediately be calculated:

Figure 10. Transient Response with Active Voltage Positioning

Automotive Considerations: Plugging into the

Cigarette Lighter

R_SENSE= 50mV/5A = 0.01Ω

C_OSC= 1.61(10⁷)/(300kHz) – 11pF = 43pF

As battery-powered devices go mobile, there is a natural

interest in plugging into the cigarette lighter in order to

conserveorevenrechargebatterypacksduringoperation.

But before you connect, be advised: you are plugging

into the supply from hell. The main power line in an

automobile is the source of a number of nasty potential

transients, including load-dump, reverse-battery and

double-battery.

Assume a 3.3µH inductor and check the actual value of the

ripple current. The following equation is used:

V

(f)(L)

V

OUT

V

IN

OUT

∆I =

1–

L

The highest value of the ripple current occurs at the

maximum input voltage:

Load-dump is the result of a loose battery cable. When the

cablebreaksconnection,thefieldcollapseinthealternator

can cause a positive spike as high as 60V which takes

several hundred milliseconds to decay. Reverse-battery is

just what it says, while double-battery is a consequence of

tow-truck operators finding that a 24V jump start cranks

cold engines faster than 12V.

1.8V

300kHz(3.3µH)

1.8V

22V

∆I =

1–

= 2.3A

L

The maximum ripple current is 33% of maximum output

current, which is about right.

24

LTC1735

U

W

U U

APPLICATIO S I FOR ATIO

Next verify the minimum on-time of 200ns is not violated.

The minimum on-time occurs at maximum V_IN:

C_INis chosen for an RMS current rating of at least 2.5A at

temperature. C_OUTis chosen with an ESR of 0.02Ωfor low

outputripple. Theoutputrippleincontinuousmodewillbe

highest at the maximum input voltage. The worst-case

output voltage ripple due to ESR is approximately:

V

1.8V

OUT

t

=

= 273ns

ON(MIN)

V

f

22V(300kHz)

IN(MAX)

V

= R (∆I ) = 0.02Ω(2.3A) = 46mV

ESR L P−P

ORIPPLE

Since the output voltage is below 2.4V the output resistive

divider will need to be sized to not only set the output

voltage but also to absorb the sense pin current.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1735. These items are also illustrated graphically in

the layout diagram of Figure 12. Check the following in

your layout:

0.8V

R1

= 24k

= 24K

(MAX)

2.4V – V

OUT

0.8V

2.4V – 1.8V

= 32k

1) Are the signal and power grounds segregated? The

LTC1735 PGND pin should tie to the ground plane close to

the input capacitor(s). The SGND pin should then connect

toPGNDandallcomponentsthatconnecttoSGNDshould

make a single point tie to the SGND pin. The synchronous

MOSFET source pins should connect to the input

capacitor(s) ground.

Choosing 1% resistors; R1 = 25.5k and R2 = 32.4k yields

an output voltage of 1.816V.

The power dissipation on the topside MOSFET can be

easilyestimated. ChoosingaSiliconixSi4412DYresultsin

R_DS(ON)= 0.042Ω, C_RSS= 100pF. At maximum input

voltage with T(estimated) = 50°C:

2) Does the V_OSENSEpin connect directly to the feedback

resistors? The resistive divider R1, R2 must be connected

between the (+) plate of C_OUTand signal ground. The 47pF

to 100pF capacitor should be as close as possible to the

LTC1735.Becarefullocatingthefeedbackresistorstoofar

away from the LTC1735. The V_OSENSEline should not be

routed close to any other nodes with high slew rates.

3) AretheSENSE^–andSENSE⁺leadsroutedtogetherwith

minimum PC trace spacing? The filter capacitor between

SENSE⁺andSENSE^–shouldbeascloseaspossibletothe

LTC1735. Ensure accurate current sensing with Kelvin

connections as shown in Figure 13. Series resistance can

be added to the SENSE lines to increase noise rejection.

2

( )

1.8V

22V

P

=

5 1+(0.005)(50°C – 25°C) 0.042Ω

(

]

)

MAIN

[

2

+1.7 22V 5A 100pF 300kHz

(

) ( )(

)(

)

= 220mW

Because the duty cycle of the bottom MOSFET is much

greaterthanthetop,alargerMOSFET,SiliconixSi4410DY,

(R_DS(ON)= 0.02Ω) is chosen. The power dissipation in the

bottom MOSFET, again assuming T_A= 50°C, is:

2

22V – 1.8V

P

=

5A 1.1 0.02Ω

( ) ( )(

4) Does the (+) terminal of C_INconnect to the drain of the

topside MOSFET(s) as closely as possible? This capacitor

provides the AC current to the MOSFET(s).

)

SYNC

22V

= 500mW

Thanks to current foldback, the bottom MOSFET dissipa-

tion in short-circuit will be less than under full load

conditions.

5) Is the INTV_CCdecoupling capacitor connected closely

betweenINTV_CCand the power ground pin? This capaci-

tor carries the MOSFET driver peak currents. An addi-

tional 1µF ceramic capacitor placed immediately next to

25

LTC1735

U

W

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APPLICATIO S I FOR ATIO

the INTV_CCand PGND pins can help improve noise

performance.

feedback pins. All of these nodes have very large and fast

moving signals and therefore should be kept on the

“output side” (Pin 9 to Pin 16) of the LTC1735 and occupy

minimum PC trace area.

6) Keep the switching node (SW), top gate node (TG) and

boost node (BOOST) away from sensitive small-signal

nodes, especially from the voltage and current sensing

+

C

M1

OSC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

C

TG

BOOST

SW

OSC

C

SS

C

IN

RUN/SS

C

R

C

I

TH

V

IN

LTC1735

C2

FCB

V

IN

C

D

B

D1

SGND

INTV

CC

47pF

+

4.7µF

V

BG

OSENSE

M2

–

SENSE

PGND

1000pF

+

SENSE

EXTV

CC

L1

–

R1

C

OUT

V

OUT

+

R2

R

SENSE

1735 F12

Figure 12. LTC1735 Layout Diagram

HIGH CURRENT PATH

1735 F13

CURRENT SENSE

RESISTOR

(R

SENSE

)

+

–

SENSE SENSE

Figure 13. Kelvin Sensing R_SENSE

26

LTC1735

U

TYPICAL APPLICATIO S

1.8V/5A Converter from Design Example with Burst Mode Operation Disabled

V

IN

4.5V TO 22V

C

IN

OSC

22µF

50V

43pF

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

M1

C

TG

BOOST

SW

OSC

CER

Si4412DY

C

B

SS

0.1µF

RUN/SS

C

R

C

470pF

33k

I

TH

C

C2

LTC1735

220pF

L1

3.3µH

R

SENSE

D

B

V

1.8V

5A

0.01Ω

OUT

FCB

V

IN

CMDSH-3

R2

32.4k

1%

C

SGND

INTV

OUT

CC

+

150µF

47pF

4.7µF

6.3V

×2

M2

Si4410DY

R1

V

BG

OSENSE

25.5k

1%

PANASONIC SP

MBRS140T3

–

SENSE

PGND

SGND

1000pF

OPTIONAL:

+

SENSE

EXTV

CC

C

: PANASONIC EEFUEOG151R

OUT

IN

CONNECT TO 5V

: MARCON THCR70LE1H226ZT

L1: PANASONIC ETQP6F3R3HFA

: IRC LR 2010-01-R010F

R

SENSE

1735 TA02

CPU Core Voltage Regulator for 2-Step Applications (V_IN= 5V)

V

IN

5V

100k*

C

IN

C

39pF

150µF

6.3V

×2

OSC

1

16

15

14

13

12

11

10

9

M1

C

TG

BOOST

SW

OSC

FDS6680A

C

B

SS

0.22µF

0.1µF

2

3

4

5

6

7

8

RUN/SS

C

R

C

220pF

20k

I

TH

C

C2

LTC1735

220pF

L1

0.78µH

R

SENSE

D

B

V

1.5V

12A

0.004Ω

OUT

FCB

V

IN

MBR0530

R2

32.4k

1%

SGND

INTV

CC

100pF

C

OUT

C

+

O

180µF

4V

47pF

4.7µF

47µF

M2, M3

FDS6680A

×2

10V

R1

25.5k

1%

V

BG

×3

OSENSE

1µF

MBRD835L

–

SENSE

PGND

SGND

1000pF

C

: PANASONIC EEFUEOG181R

OUT

IN

+

V

SENSE

EXTV

IN

CC

: PANASONIC EEFUEOJ151R

C : TAIYO YUDEN LMK550BJ476MM-B

O

L1: COILCRAFT 1705022P-781HC

R

: IRC LRF 2512-01-R004-J

SENSE

1735 TA03

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

27

LTC1735

U

TYPICAL APPLICATIO S

Selectable Output Voltage Converter with Burst Mode Operation Disabled for CPU Power

V

IN

4.5V TO 24V

0.1µF

4.7Ω

C

IN

C

+

OSC

22µF

×2

43pF

1

2

3

4

5

6

7

8

16

M1

CER

C

TG

OSC

FDS6680A

C

B

SS

0.1µF

0.22µF

15

14

13

12

11

10

9

C

: MARCON THCR70EIH226ZT

: KEMET T510X447M006AS

IN

OUT

RUN/SS

BOOST

C

R

C

L1: PANASONIC ETQP6F1R2HFA

330pF

33k

R

: IRC LRF2512-01-R004F

SENSE

I

TH

SW

C

C2

47pF

LTC1735

L1

1.2µH

R

SENSE

0.004Ω

D

B

V

OUT

FCB

V

IN

CMDSH-3

1.35V/1.60V

12A

R2

47pF

10k

1%

C

SGND

INTV

CC

OUT

+

470µF

6.3V

47pF

4.7µF

M2

FDS6680A

×2

R3

33.2k

1%

R1

14.3k

1%

×3

KEMET

V

BG

OSENSE

47pF

1µF

CER

MBRS340T3

–

SENSE

PGND

VN2222

10k

ON: V

OUT

= 1.60V

= 1.35V

1000pF

OFF: V

OUT

OPTIONAL:

+

SENSE

EXTV

CC

CONNECT TO 5V

10Ω

SGND

1735 TA05

4V to 40V Input to 12V Flyback Converter

V

IN

4V TO 40V

CMDSH-3

FMMT625

V

OUT

C

V

12V

3A

IN

OUT

10k

6.2V

T1

10

22µF

50V

×2

6

7

R2

113k

1%

C

3

OUT

470µF

16V

+

1M

C

OSC

150pF

R1

8.06k

1%

47Ω

×4

1

16

15

14

13

12

11

10

9

M1

IR2910

M2

Si4450DY

MBRS1100

C

TG

BOOST

SW

OSC

C

SS

0.1µF

1nF

100V

22Ω

2

RUN/SS

C

R

C

2200pF

3.3k

1nF

100V

3

R

SENSE

0.004Ω

I

TH

C

C2

100pF

LTC1735

4

5

6

7

8

FCB

V

IN

SGND

INTV

CC

0.1µF

47pF

+

V

BG

OSENSE

4.7µF

–

SENSE

PGND

3300pF

C

: MARCON THCR70EIH226ZT

IN

+

: AVX TPSV227M016R0150

OUT

SENSE

EXTV

CC

T1: COILTRONICS VP5-0155

100Ω

R

: IRC LRF2512-01-R004F

SENSE

1735 TA07

28

LTC1735

U

TYPICAL APPLICATIO S

5V/3.5A Converter with 12V/200mA Auxiliary Output

V

IN

5.5V TO 28V

C

IN

OSC

51pF

+

22µF

30V

OS-CON

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

M1

C

TG

BOOST

SW

OSC

IRF7803

C

B

SS

0.1µF

1000pF

22Ω

0.1µF

RUN/SS

C

MBRS1100T3

R

C

470pF

33k

C

I

SEC

TH

+

C

C2

220pF

22µF

35V

LTC1735

R

SENSE

0.012Ω

D

B

AVX

V

OUT

FCB

V

IN

CMDSH-3

5V

T1

3.5A

R2

105k

1%

1:1.8

C

OUT

SGND

INTV

CC

10µH

100µF

10V

+

100pF

4.7µF

M2

IRF7803

×3

AVX

R1

20k

1%

V

BG

OSENSE

MBRS140T3

–

SENSE

PGND

SGND

1000pF

+

SENSE

EXTV

CC

C

: SANYO OS-CON 305C22M

IN

100Ω

: AVX TPSD107M010R0068

OUT

100Ω

T1: 1:8 DALE LPE6562-A262

V

OUT2

10k

90.9k

12V

120mA

UNREG

1735 TA04

Dual Output 15W 3.3V/5V Power Supply

V

IN

4.5V TO 28V

C

OSC

47pF

+

C

IN

22µF

T1C

V

OUT2

•

5V

1

16

15

14

13

12

11

10

9

M1

50V

C

3

6

TG

BOOST

SW

OSC

1.5A

Si4412DY

0.01µF

C

SS

B

C

OUT2

+

0.1µF

M3

100µF

10V

2

3

4

5

6

7

8

Si4412DY

RUN/SS

C

470pF

×2

4.7k

CMDSH-3

MBRS140T3

I

TH

R

C

LTC1735

33k

R

SENSE

0.01Ω

D

B

T1A

T1B

V

3.3V

2.5A

FCB

SGND

V

OUT1

V

IN

•

CMDSH-3

C

1

8 2

7

C2

R2

100pF

62.6k

INTV

CC

C

OUT1

1%

+

100µF

10V

100pF

4.7µF

M2

Si4412DY

R1

20k

1%

BG

OSENSE

×2

MBRS140T3

–

SENSE

PGND

1000pF

SGND

+

V

OUT2

SENSE

EXTV

CC

C

: MARCON THCR70EIH226ZT

IN

: AVX TPSD107M010R0065

OUT1, 2

T1: BI TECHNOLOGIES HM00-93839

R

: IRC LRF2512-01-R010 F

1735 TA08

SENSE

29

LTC1735

U

PACKAGE DESCRIPTION

Dimensions in inches (millimeters) unless otherwise noted.

GN Package

16-Lead Plastic SSOP (Narrow 0.150)

(LTC DWG # 05-08-1641)

0.189 – 0.196*

(4.801 – 4.978)

0.009

(0.229)

REF

16 15 14 13 12 11 10 9

0.229 – 0.244

(5.817 – 6.198)

0.150 – 0.157**

(3.810 – 3.988)

1

2

3

4

5

6

7

8

0.015 ± 0.004

(0.38 ± 0.10)

× 45°

0.053 – 0.068

(1.351 – 1.727)

0.004 – 0.0098

(0.102 – 0.249)

0.007 – 0.0098

(0.178 – 0.249)

0° – 8° TYP

0.016 – 0.050

(0.406 – 1.270)

0.0250

(0.635)

BSC

0.008 – 0.012

(0.203 – 0.305)

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

GN16 (SSOP) 1098

30

LTC1735

U

PACKAGE DESCRIPTION

Dimensions in inches (millimeters) unless otherwise noted.

S Package

16-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.386 – 0.394*

(9.804 – 10.008)

16

15

14

13

12

11

10

9

0.150 – 0.157**

(3.810 – 3.988)

0.228 – 0.244

(5.791 – 6.197)

5

7

8

1

2

3

4

6

0.010 – 0.020

(0.254 – 0.508)

× 45°

0.053 – 0.069

(1.346 – 1.752)

0.004 – 0.010

(0.101 – 0.254)

0.008 – 0.010

(0.203 – 0.254)

0° – 8° TYP

0.050

(1.270)

BSC

0.014 – 0.019

(0.355 – 0.483)

TYP

0.016 – 0.050

(0.406 – 1.270)

S16 1098

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

31

LTC1735

U

TYPICAL APPLICATIO

3.3V to 2.5V/5A Converter with External Clock Synchronization Operating at 500kHz

V

IN

3.3V

5V

0.1µF

C

IN

OSC

20pF

+

100µF

10V

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

M1

Si4410DY

C

TG

BOOST

SW

OSC

OS-CON

C

B

SS

0.1µF

C

: SANYO OS-CON 10SL100M

: AVX TPSD107M010R0065

IN

OUT

RUN/SS

C

330pF

L1: COILCRAFT DO3316P-152

R

: IRC LR2010-01-R010-F

SENSE

I

TH

R

C

LTC1735

L1

1.5µH

33k

R

SENSE

D

B

0.01Ω

V

2.5V

5A

FCB

OUT

V

EXT

CLOCK

500kHz

IN

CMDSH-3

C

51pF

C2

R2

43.2k

1%

47pF

C

SGND

INTV

OUT

CC

+

100µF

10V

47pF

4.7µF

M2

Si4410DY

AVX

×3

R1

20k

1%

V

BG

OSENSE

MBRS140T3

–

SENSE

PGND

SGND

1000pF

+

SENSE

EXTV

CC

1735 TA06

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550kHz Dual Output Synchronous Step-Down Controller

High Efficiency Step-Down Controller with Power Good

High Efficiency Step-Down Controller with VID Control

SOT-23 Step-Down Controller

100% DC*, 2.6V to 8.5V V , SO-8

IN

LTC1628

Antiphase Drive for Reduced Input Capacitance

Antiphase Drive, 24-Pin SSOP

LTC1702

LTC1735-1

LTC1736

Output Fault Protection, 16-Pin SO/SSOP

Output Fault Protection, 24-Pin SSOP

LTC1772

100% DC*, Up to 4A, 2.2V to 9.8V V

IN

No R

is trademark of Linear Technology Corporation. *DC = Duty Cycle

SENSE

1735f LT/TP 1199 4K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

LINEAR TECHNOLOGY CORPORATION 1998

●

(408)432-1900 FAX:(408)434-0507 www.linear-tech.com


型号：	LTC1735CS
厂家：	Linear
描述：	High Efficiency Synchronous Step-Down Switching Regulator 高效率同步降压型开关稳压器稳压器开关光电二极管
文件：	总32页 (文件大小：375K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1735CS [Linear]

相关型号：

LTC1735CS#TR

LTC1735CS-1

LTC1735CS-1#PBF

LTC1735CS-1#TR

LTC1735CS-1#TRPBF

LTC1735EGN

LTC1735EGN#PBF

LTC1735EGN#TR

LTC1735EGN#TRPBF

LTC1735I

LTC1735I-1

LTC1735IF