LTC1735IS-1#PBF [Linear]
LTC1735-1 - High Efficiency Synchronous Step-Down Switching Regulator; Package: SO; Pins: 16; Temperature Range: -40°C to 85°C;型号: | LTC1735IS-1#PBF |
厂家: | Linear |
描述: | LTC1735-1 - High Efficiency Synchronous Step-Down Switching Regulator; Package: SO; Pins: 16; Temperature Range: -40°C to 85°C 稳压器 开关 |
文件: | 总28页 (文件大小:335K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC1735-1
High Efficiency
Synchronous Step-Down
Switching Regulator
U
FEATURES
DESCRIPTIO
The LTC®1735-1 is a synchronous step-down switching
regulatorcontrolleroptimizedforCPUpower. OPTI-LOOP
compensation allows the transient response to be opti-
mized over a wide range of output capacitance and ESR
values.
■
Dual N-Channel MOSFET Synchronous Drive
■
Programmable/Synchronizable Fixed Frequency
■
VOUT Range: 0.8V to 7V
Wide VIN Range: 3.5V to 36V Operation
■
■
Very Low Dropout Operation: 99% Duty Cycle
OPTI-LOOPTM Compensation Minimizes COUT
■
The operating frequency (synchronizable up to 500kHz) is
set by an external capacitor allowing maximum flexibility
in optimizing efficiency. The output voltage is monitored
by a power good window comparator that indicates when
the output is within 7.5% of its programmed value, con-
forming to Intel Mobile CPU Specifications.
■
±
1% Output Voltage Accuracy
■
■
■
■
Power Good Output Voltage Monitor
Internal Current Foldback
Output Overvoltage Crowbar Protection
Latched Short-Circuit Shutdown Timer
with Defeat Option
Optional Programmable Soft-Start
Remote Output Voltage Sense
Logic Controlled Micropower Shutdown: IQ < 25µA
■
■
■
■
Protection features include internal foldback current lim-
iting, output overvoltage crowbar and optional short-
circuit shutdown. Soft-start is provided by an external
capacitor that can be used to properly sequence supplies.
The operating current level is user-programmable via an
external current sense resistor. Wide input supply range
allows operation from 3.5V to 30V (36V maximum).
Pin defeatable Burst ModeTM operation provides high
efficiency at low load currents while 99% duty cycle
provides low dropout operation.
Available in 16-LUead Narrow SSOP and SO Packages
APPLICATIO S
■
Notebook and Palmtop Computers, PDAs
Power Supply for Mobile Pentium® III Processor with
■
SpeedStepTM Technology
■
Cellular Telephones and Wireless Modems
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode and OPTI-LOOP are trademarks of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corporation. SpeedStep is a trademark of Intel
Corporation.
U
TYPICAL APPLICATIO
PGOOD
V
IN
4.5V TO 24V
C
C
: MARCON THCR70E1H226ZT
: PANASONIC EEFUE06181R
C
22µF
50V
CERAMIC
×2
IN
OUT
IN
L1: PANASONIC ETQP6RZ1R20HFA
C
47pF
1
2
3
4
5
6
7
8
OSC
16
15
14
13
12
11
10
9
Q1
FDS6680A
C
TG
R
: IRC CRF2010-01-R004J
OSC
SENSE
C
0.22µF
C
0.1µF
B
SS
RUN/SS
BOOST
L1
R
33k
R
C1
SENSE
0.004Ω
C
330pF
C2
1.2µH
V
OUT
I
LTC1735-1 SW
TH
C
C1
47pF
1.35V TO 1.60V
12A
D1
PGOOD
V
IN
CMDSH-3
D2
R1
–
SENSE
SENSE
INTV
CC
MBRS340T3
10k
0.5%
+
47pF
47pF
1000pF
C
OUT
+
Q2, Q3
FDS6680A
×2
47pF
BG
4.7µF
+
180µF
R3
33.2k
1%
4V
V
PGND
OSENSE
PANASONIC SP
5V
(OPTIONAL)
SGND
EXTV
CC
×4
Q4
2N7002
V
V
= 1: V
= 0: V
= 1.60V
= 1.35V
SEL
SEL
OUT
OUT
10Ω
10Ω
R2
14.3k
0.5%
GND
1735-1 F01
Figure 1. CPU Core DC/DC Converter with Dynamic Voltage Selection from SpeedStep Enabled Processors
1
LTC1735-1
W W
U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
Input Supply Voltage (VIN)........................ 36V to –0.3V
Topside Driver Supply Voltage (BOOST)... 42V to –0.3V
Switch Voltage (SW) ................................... 36V to –5V
INTVCC, EXTVCC (BOOST, SW) Voltages..... 7V to –0.3V
SENSE+, SENSE–,
PGOOD Voltages................ 1.1(INTVCC + 0.3V) to –0.3V
ITH, VOSENSE, COSC Voltages .....................2.7V to –0.3V
RUN/SS Voltage ....................(INTVCC + 0.3V) to –0.3V
Peak Driver Output Current <10µs (TG, BG) .............. 3A
INTVCC Output Current ......................................... 50mA
Operating Ambient Temperature Range
LTC1735C-1 ............................................ 0°C to 85°C
LTC1735I-1 ........................................ –40°C to 85°C
Junction Temperature (Note 2)............................. 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TG
NUMBER
OSC
RUN/SS
BOOST
SW
LTC1735CGN-1
LTC1735CS-1
LTC1735IGN-1
LTC1735IS-1
I
TH
PGOOD
V
IN
–
SENSE
INTV
BG
CC
+
SENSE
V
PGND
EXTV
OSENSE
SGND
CC
GN PACKAGE
S PACKAGE
16-LEAD PLASTIC SSOP 16-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 130°C/W (GN)
JMAX = 125°C, θJA = 110°C/W (S)
T
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
I
Feedback Current
(Note 3)
(Note 3)
–4
0.8
–25
0.808
0.02
nA
V
VOSENSE
V
Feedback Voltage
●
0.792
OSENSE
∆V
∆V
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
= 3.6V to 30V (Note 3)
IN
0.001
%/V
LINEREG
(Note 3)
Measured in Servo Loop; V = 0.7V
Measured in Servo Loop; V = 2V
LOADREG
●
●
0.1
–0.1
0.3
–0.3
%
%
ITH
ITH
DF Max
Maximum Duty Factor
In Dropout
98
99.4
1.3
%
mmho
V
g
Transconductance Amplifier g
m
m
V
Feedback Overvoltage Lockout
●
0.84
0.86
0.88
OVL
I
Input DC Supply Current
Normal Mode
(Note 5)
3.6V < V < 30V
Q
450
15
µA
µA
IN
= 0V
Shutdown
V
V
V
V
25
1.9
4.5
RUN/SS
RUN/SS
RUN/SS
RUN/SS
V
Run Pin Start Threshold
, Ramping Positive
, Ramping Positive
= 0V
1.0
1.5
4.1
–1.2
2
V
V
RUN/SS
Run Pin Begin Latchoff Threshold
Soft-Start Charge Current
RUN/SS Discharge Current
I
I
–0.7
0.5
µA
µA
RUN/SS
SCL
Soft Short Condition, V
= 0.5V,
4
OSENSE
V
= 4.5V
RUN/SS
UVLO
∆V
Undervoltage Lockout
Measured at V Pin (Ramping Negative)
●
●
3.5
75
3.9
85
V
mV
µA
IN
Maximum Current Sense Threshold
SENSE Pins Total Source Current
Minimum On-Time
V
V
= 0.7V
60
SENSE(MAX)
OSENSE
–
+
I
t
= V = 0V
SENSE
60
80
SENSE
ON(MIN)
SENSE
Tested with a Square Wave (Note 4)
160
200
ns
2
LTC1735-1
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TG Transition Time:
Rise Time
Fall Time
(Note 7)
TG t
TG t
C
C
= 3300pF
= 3300pF
50
50
90
90
ns
ns
r
f
LOAD
LOAD
BG Transition Time:
Rise Time
Fall Time
(Note 7)
BG t
BG t
C
= 3300pF
= 3300pF
50
40
90
80
ns
ns
r
f
LOAD
LOAD
C
TG/BG T1D
Top Gate Off to Synchronous
Gate-On Delay Time
C
C
= 3300pF Each Driver
= 3300pF Each Driver
100
ns
LOAD
TG/BG T2D
Synchronous Gate Off to Top
Gate-On Delay Time
70
ns
LOAD
Internal V Regulator
CC
V
V
V
V
V
Internal V Voltage
6V < V < 30V, V = 4V
EXTVCC
5.0
4.5
265
5.2
0.2
130
4.7
0.2
5.4
1
V
%
INTVCC
CC
IN
INTV Load Regulation
I
I
I
= 0mA to 20mA, V
= 4V
EXTVCC
LDO(INT)
LDO(EXT)
EXTVCC
CC
CC
CC
CC
EXTV Drop Voltage
= 20mA, V
= 5V
200
mV
V
CC
EXTVCC
EXTV Switchover Voltage
= 20mA, EXTV Ramping Positive
●
CC
CC
EXTV Hysteresis
V
EXTVCC(HYS)
CC
Oscillator
f
Oscillator Frequency
(Note 6), C
= 43pF
OSC
300
1.3
335
kHz
OSC
f /f
H
Maximum Sync Frequency Ratio
OSC
PGOOD Pin
V
V
V
PGOOD Threshold for Sync
PGOOD Threshold for Force Cont.
PGOOD Voltage Low
Ramping Negative
0.9
1.2
0.8
V
V
PG(SYNC)
PG(FC)
PGL
0.76
0.84
200
I
= 2mA
110
mV
µA
PGOOD
I
PGOOD Pull-Up Current
PGOOD Trip Level
V
V
= 0.85V
–0.17
PGOOD
PGOOD
V
With Respect to Set Output Voltage
PG
OSENSE
V
V
Ramping Negative
Ramping Positive
–6.0
6.0
–7.5
7.5
–9.5
9.5
%
%
OSENSE
OSENSE
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 2: T is calculated from the ambient temperature T and power
Note 6: Oscillator frequency is tested by measuring the C
charge
J
A
OSC
dissipation P according to the following formulas:
current (I ) and applying the formula:
D
OSC
LTC1735CS-1, LTC1735IS-1: T = T + (P • 110 °C/W)
J
A
D
–1
8.477(108)
COSC(pF)+ 11 ICHG IDIS
1
1
LTC1735CGN-1, LTC1735IGN-1: T = T + (P • 130°C/W)
fOSC(kHz) =
+
J
A
D
Note 3: The LTC1735-1 is tested in a feedback loop that servos V
OSENSE
to the balance point for the error amplifier (V = 1.2V).
ITH
Note 7: Rise and fall times are measured using 10% to 90% levels.
Note 4: The minimum on-time condition corresponds to an inductor
peak-to-peak ripple current >40% of I (see Minimum On-Time
Delay times are measured using 50% levels.
MAX
Considerations in the Applications Information section).
3
LTC1735-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current
(3 Operating Modes)
Efficiency vs Load Current
Efficiency vs Input Voltage
100
95
90
85
80
75
70
100
90
80
70
60
50
40
100
90
80
70
60
50
40
30
20
EXTV = 5V
CC
OUT
EXTV OPEN
CC
EXTV = 5V
CC
OUT
FIGURE 1
V
= 1.6V
V
= 1.6V
BURST
SYNC
V
IN
= 5V
I
= 5A
OUT
V
IN
= 15V
CONT
V
IN
= 24V
I
= 0.5A
OUT
V
V
= 10V
IN
OUT
S
= 3.3V
R
= 0.01Ω
= 300kHz
f
O
0.1
0.01
LOAD CURRENT (A)
10mA
100mA
1A
10A
0
10
15
20
25
30
0.001
1
10
5
LOAD CURRENT (A)
INPUT VOLTAGE (V)
1735-1 G01
1735-1 G02
1735-1 G03
VIN – VOUT Dropout Voltage
vs Load Current
Efficiency vs Input Voltage
Load Regulation
500
400
300
200
100
0
100
95
90
85
80
75
70
0
–0.1
–0.2
–0.3
–0.4
R
V
= 0.005Ω
EXTV OPEN
CC
FCB = 0V
V = 15V
IN
SENSE
= 5V – 5% DROP
V
= 1.6V
OUT
OUT
FIGURE 1
FIGURE 1
I
= 5A
OUT
I
= 0.5A
OUT
0
2
4
6
8
10
0
10
15
20
25
30
0
2
4
6
8
10
5
LOAD CURRENT (A)
INPUT VOLTAGE (V)
LOAD CURRENT (A)
1735-1 G06
1735-1 G04
1735-1 G05
Input and Shutdown Currents
vs Input Voltage
EXTVCC Switch Drop
INTVCC Line Regulation
vs INTVCC Load Current
500
400
300
200
100
0
100
80
60
40
20
0
6
5
4
3
500
400
300
200
100
0
1mA LOAD
EXTV OPEN
CC
2
1
0
SHUTDOWN
EXTV = 5V
CC
0
5
10
15
20
25
30
35
0
15
20
25
30
35
0
10
20
30
40
50
5
10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INTV LOAD CURRENT (mA)
CC
1735-1 G07
1735-1 G09
1735-1 G08
4
LTC1735-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Current Sense Threshold
vs Normalized Output Voltage
(Foldback)
Maximum Current Sense Threshold
vs Sense Common Mode Voltage
Maximum Current Sense Threshold
vs VRUN/SS
80
76
72
68
64
60
80
70
60
50
40
30
20
10
0
80
60
40
20
V
= 1.6V
SENSE(CM)
0
50
NORMALIZED OUTPUT VOLTAGE (%)
0
1
2
3
4
5
6
1
3
0
25
75
100
0
2
4
5
V
(V)
COMMON MODE VOLTAGE (V)
RUN/SS
1735-1 G10
1735-1 G11
1735-1 G12
Maximum Current Sense Threshold
vs Temperature
Maximum Current Sense Voltage
vs ITH Voltage
VITH vs VRUN/SS
90
80
2.5
2.0
1.5
1.0
80
75
70
65
V
= 0.7V
V
= 1.6V
OSENSE
SENSE(CM)
70
60
50
40
30
20
10
0
0.5
0
–10
–20
–30
60
0
0.5
1
1.5
(V)
2
2.5
–40 –15 10
35
60
85 110 135
0
2
3
4
5
6
1
TEMPERATURE (°C)
V
(V)
V
RUN/SS
ITH
1735-1 G18
1735-1 G13
1735-1 G15
Output Current vs Duty Cycle
SENSE Pins Total Source Current
ITH Voltage vs Load Current
2.5
2.0
1.5
1.0
100
80
100
50
V
V
= 10V
I
/I
IN
OUT
OUT MAX
= 3.3V
= 0.01Ω
(SYNCHRONIZED)
R
SENSE
I
/I
OUT MAX
f
= 300kHz
O
(FREE RUN)
CONTINUOUS
MODE
60
0
SYNCHRONIZED f = f
O
40
Burst Mode
OPERATION
–50
–100
0.5
0
20
0
f
= f
O
SYNC
2
4
0
2
3
4
5
6
0
40
60
80
100
0
6
20
1
LOAD CURRENT (A)
DUTY CYCLE (%)
V
COMMON MODE VOLTAGE (V)
SENSE
1735-1 G16
1735-1 G17
1735-1 G14
5
LTC1735-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Oscillator Frequency
vs Temperature
RUN/SS Pin Current
vs Temperature
PGOOD Pin Current
vs Temperature
300
290
280
270
260
250
0
–1
–2
–3
–4
–5
0
–0.2
–0.4
–0.6
–0.8
–1.0
C
OSC
= 47pF
V
= 0V
V
= 0.85V
RUN/SS
PGOOD
–40 –15 10
35
60
85 110 135
–40 –15 10
35
60
85 110 135
–40 –15 10
35
60
85 110 135
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1735-1 G19
1735-1 G20
1735-1 G21
VOUT(RIPPLE)
(Burst Mode Operation)
Start-Up
VOUT(RIPPLE) (Synchronized)
ILOAD = 10mA
FIGURE 1
ILOAD = 50mA
VOUT
1V/DIV
VOUT
10mV/DIV
VOUT
20mV/DIV
VRUN/SS
5V/DIV
IL
IL
5A/DIV
5A/DIV
IL
5A/DIV
VIN = 15V
VOUT = 1.6V
50µs/DIV
1735-1 G24
V
IN = 15V
VOUT = 1.6V
LOAD = 0.16Ω
5ms/DIV
1735-1 G22
EXT SYNC f = fO
VIN = 15V
VOUT = 1.6V
10µs/DIV
1735-1 G23
R
Load Step
(Burst Mode Operation)
VOUT(RIPPLE)
(Burst Mode Operation)
Load Step (Continuous Mode)
ILOAD = 1.5A
FIGURE 1
FIGURE 1
FIGURE 1
VOUT
20mV/DIV
VOUT
50mV/DIV
VOUT
50mV/DIV
IL
IL
IL
5A/DIV
5A/DIV
5A/DIV
0A TO
10µs/DIV
1735-1 G27
VIN = 15V
VOUT = 1.6V
5µs/DIV
1735-1 G25
10mA TO
10µs/DIV
1735-1 G26
11A LOAD STEP
PGOOD = 0V
VIN = 15V
11A LOAD STEP
V
IN = 15V
VOUT = 1.6V
VOUT = 1.6V
6
LTC1735-1
U
U
U
PI FU CTIO S
COSC (Pin 1): External capacitor COSC from this pin to
ground sets the operating frequency.
SGND (Pin 8): Small-Signal Ground. All small-signal
components such as COSC, CSS, the feedback divider plus
the loop compensation resistors and capacitor(s) should
single-pointtietothispin.Thispinshould,inturn,connect
to PGND.
RUN/SS (Pin 2): Combination of Soft-Start and Run
Control Inputs. A capacitor to ground at this pin sets the
ramptimetofullcurrentoutput. Thetimeisapproximately
1.25s/µF. Forcing this pin below 1.5V causes the device to
be shut down. In shutdown all functions are disabled.
Latchoff overcurrent protection is also invoked via this pin
as described in the Applications Information section.
EXTVCC (Pin 9): Input to the Internal Switch Connected to
INTVCC. This switch closes and supplies VCC power when-
ever EXTVCC is higher than 4.7V. See EXTVCC connection
in Applications Information section. Do not exceed 7V on
this pin and ensure EXTVCC is ≤ VIN.
ITH (Pin 3): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 2.4V.
PGND (Pin 10): Driver Power Ground. This pin connects
to the source of the bottom N-channel MOSFET, the anode
of the Schottky diode and the (–) terminal of CIN.
PGOOD (Pin 4): Open-Drain Logic Output and Forced
Continuous/Synchronization Input. The PGOOD pin is
pulled to ground when the voltage on the VOSENSE pin is
not within ±7.5% of its nominal set point. If power good
indication is not needed, this pin can be tied to ground to
force continuous synchronous operation. Clocking this
pin with a signal above 1.5VP-P synchronizes the internal
oscillator to the external clock. Synchronization only
occurswhilethemainoutputisinregulation(PGOODnot
internally pulled low). When synchronized, Burst Mode
operation is disabled but cycle skipping is allowed at low
load currents. This pin requires a pull-up resistor for
powergoodindication. Donotconnectthispindirectlyto
an external source (or INTVCC). Do not exceed INTVCC on
this pin.
BG (Pin 11): High Current Gate Drive for the Bottom
N-Channel MOSFET. Voltage swing at this pin is from
ground to INTVCC
.
INTVCC (Pin 12): Output of the Internal 5.2V Low Dropout
Regulator and EXTVCC Switch. The driver and control
circuits are powered from this voltage. Decouple to power
ground with a 1µF ceramic capacitor placed directly adja-
cent to the IC together with a minimum of 4.7µF tantalum
or other low ESR capacitor.
VIN (Pin 13): Main Supply Pin. This pin must be closely
decoupled to power ground.
SW (Pin 14): Switch Node Connection to Inductor and
Bootstrap Capacitor. Voltage swing at this pin is from a
Schottky diode (external) voltage drop below ground to
VIN.
SENSE– (Pin 5): The (–) Input to the Current Comparator.
SENSE+ (Pin 6): The (+) Input to the Current Comparator.
Built-in offsets between SENSE+ and SENSE– pins in
conjunction with RSENSE set the inductor current trip
threshold.
BOOST (Pin 15): Supply to Topside Floating Driver. The
bootstrap capacitor is returned to this pin. Voltage swing
at this pin is from a diode drop below INTVCC to VIN
INTVCC.
+
VOSENSE (Pin 7): Receives the feedback voltage from an
external resistive divider across the output.
TG (Pin 16): High Current Gate Drive for Top N-Channel
MOSFET. This is the output of a floating driver with a
voltage swing equal to INTVCC superimposed on the
switch node voltage SW.
7
LTC1735-1
U
U W
FU CTIO AL DIAGRA
V
IN
+
V
IN
13
C
IN
INTV
CC
C
OSC
UVL
0.8V
REF
INTV
CC
100k
INTV
CC
PGOOD
C
SGND
0.17µA
4
1
8
OSC
FC
D
B
C
BOOST
15
F
–
+
–
+
SYNC
OSC
1.2V
FORCE BOT
DROP
0.8V
C
B
TG
16
TOP
OUT
DET
SW
14
–
BOT
SWITCH
LOGIC
+
0.74V
OV
S
R
D
1
TOP ON
0.55V
+
R
SENSE
L
Q
V
B
OUT
–
+
–
0.86V
+
C
OUT
2.4V
SD
IREV
2k
45k
45k
–
V
OSENSE
7
Ω
V
FB
g
m
=1.3m
ICMP
–
BOT
–
+
I
I
2
–
+
+
–
1
EA
+
+
INTV
12
CC
0.8V
0.86V
R1
R2
V
IN
3mV
BURST
DISABLE
FC
SD
+
C
INTVCC
5.2V
LDO
REG
INTV
RUN
CC
1.2µA
SOFT-
A
4(V
FB
)
BUFFERED
START
+
OVER-
CURRENT
LATCHOFF
I
BG
11
TH
4.8V
+
–
30k
30k
6V
SLOPE COMP
PGND
10
R
C
+
–
2
3
6
5
9
RUN/SS
I
TH
SENSE
SENSE
EXTV
CC
C
SS
C
C
1735-1 FD
U
OPERATIO
(Refer to Functional Diagram)
Main Control Loop:
the average inductor current matches the new load cur-
rent. While the top MOSFET is off, the bottom MOSFET is
turnedonuntileithertheinductorcurrentstartstoreverse,
as indicated by current comparator I2, or the beginning of
the next cycle.
The LTC1735-1 uses a constant frequency, current mode
step-down architecture. During normal operation, the top
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the main current
comparator I1 resets the RS latch. The peak inductor
current at which I1 resets the RS latch is controlled by the
voltage on Pin ITH, which is the output of error amplifier
EA. Pin VOSENSE, described in the Pin Functions, allows EA
toreceiveanoutputfeedbackvoltageVFB fromtheexternal
resistive divider. When the load current increases, it
causes a slight decrease in VFB relative to the 0.8V refer-
ence, which in turn causes the ITH voltage to increase until
The top MOSFET driver is powered from a floating boot-
strap capacitor CB. This capacitor is normally recharged
from INTVCC through an external Schottky diode when the
topMOSFETisturnedoff. AsVIN decreasestowardsVOUT
,
the converter will attempt to turn on the top MOSFET con-
tinuously(“dropout’’).Adropoutcounterdetectsthiscon-
ditionandforcesthetopMOSFETtoturnoffforabout500ns
every tenth cycle to recharge the bootstrap capacitor.
8
LTC1735-1
U
(Refer to Functional Diagram)
OPERATIO
The main control loop is shut down by pulling Pin 2 (RUN/
SS) low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor CSS. When
CSS reaches1.5V,themaincontrolloopisenabledwiththe
continuous operation and assists in controlling voltage
regulation. If the output voltage is not within 7.5% of its
nominal value the PGOOD open-drain output will be
pulled low and Burst Mode operation will be disabled.
ITH voltageclampedatapproximately30%ofitsmaximum
Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff
value. As CSS continues to charge, ITH is gradually re-
leased allowing normal operation to resume. If VOUT has
not reached 70% of its final value when CSS has charged
to 4.1V, latchoff can be invoked as described in the
Applications Information section.
The RUN/SS capacitor, CSS, is used initially to limit the
inrush current of the switching regulator. After the con-
troller has been started and been given adequate time to
charge up the output capacitors and provide full load
current, CSS is used as a short-circuit time-out circuit. If
the output voltage falls to less than 70% of its nominal
outputvoltage, CSS beginsdischargingontheassumption
that the output is in an overcurrent and/or short-circuit
condition. If the condition lasts for a long enough period
as determined by the size of the CSS, the controller will be
shut down until the RUN/SS pin voltage is recycled. This
built-in latchoff can be overridden by providing a current
>5µA at a compliance of 5V to the RUN/SS pin. This
currentshortensthesoft-startperiodbutalsopreventsnet
discharge of CSS during an overcurrent and/or short-
circuit condition. Foldback current limiting is activated
when the output voltage falls below 70% of its nominal
level whether or not the short-circuit latchoff circuit is
enabled.
The internal oscillator can be synchronized to an external
clock applied though a series resistor to the PGOOD pin
and can lock to a frequency between 90% and 130% of its
nominal rate set by capacitor COSC
.
An overvoltage comparator OV guards against transient
overshoots (>7.5%) as well as other more serious
conditions that may overvoltage the output. In this case,
the top MOSFET is turned off and the bottom MOSFET is
turned on until the overvoltage condition is cleared.
Foldback current limiting for an output shorted to ground
is provided by amplifier A. As VOSENSE drops below 0.6V,
thebufferedITHinputtothecurrentcomparatorisgradually
pulled down to a 0.86V clamp. This reduces peak inductor
current to about 1/4 of its maximum value.
Low Current Operation
INTVCC/EXTVCC Power
The LTC1735-1 has three low current modes controlled
bythePGOODpin.BurstModeoperationisselectedwhen
the PGOOD pin is above 0.8V (typically tied through a
resistor to INTVCC). During Burst Mode operation, if the
error amplifier drives the ITH voltage below 0.86V, the
buffered ITH input to the current comparator will be
clamped at 0.86V. The inductor current peak is then held
at approximately 20mV/RSENSE (about 1/4 of maximum
output current). If ITH then drops below 0.5V, the Burst
Mode comparator B will turn off both MOSFETs to maxi-
mizeefficiency. Theloadcurrentwillbesuppliedsolelyby
the output capacitor until ITH rises above the 60mV
hysteresis of the comparator and switching is resumed.
Burst Mode operation is disabled by comparator F when
the PGOOD pin is brought below 0.8V. This forces
Power for the top and bottom MOSFET drivers and most
of the internal circuitry of the LTC1735-1 is derived from
the INTVCC pin. When the EXTVCC pin is left open, an
internal 5.2V low dropout regulator supplies the INTVCC
power from VIN. If EXTVCC is raised above 4.7V, the
internal regulator is turned off and an internal switch
connects EXTVCC to INTVCC. This allows a high efficiency
source, such as the primary or a secondary output of the
converter itself, to provide the INTVCC power. Voltages up
to 7V can be applied to EXTVCC for additional gate drive
capability.
To provide clean start-up and to protect the MOSFETs,
undervoltage lockout is used to keep both MOSFETs off
until the input voltage is above 3.5V.
9
LTC1735-1
U
(Refer to Functional Diagram)
OPERATIO
POWER GOOD
over the widest possible output current range. This con-
stant frequency operation is not quite as efficient as Burst
Mode operation, but does provide a lower noise, constant
frequency operation. When the power good window com-
parator indicates the output is not in regulation, the
PGOOD pin is pulled to ground and synchronization is
inhibited. Obviously when driving the PGOOD pin with an
external clock the power good indication is not available
unless additional circuitry is added.
A window comparator monitors the output voltage and its
open-drain output is pulled low when the divided down
output voltage (appearing at the VOSENSE pin) is not within
±7.5% of the reference voltage of 0.8V.
During a programmed output voltage transition (i.e., a
transition from 1.55V to 1.3V) the PGOOD open-drain
output will be pulled low and Burst Mode operation will be
disableduntiltheoutputvoltageiswithin7.5%ofitsnewly
programmed value.
If the PGOOD pin is tied to ground, continuous operation
is forced. This operation is the least efficient mode, but is
desirable in certain applications. The output can source
or sink current in this mode. When forcing continuous
operationandsinkingcurrent, currentwillbeforcedback
into the main power supply potentially boosting the input
supply to dangerous voltage levels—BEWARE.
When the PGOOD pin is driven by an external oscillator
through a series resistor, cycle-skipping operation is
invoked and the internal oscillator is synchronized to the
external clock by comparator C. In this mode, the 25%
minimum inductor current clamp is removed, providing
low noise, constant frequency discontinuous operation
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The basic LTC1735-1 application circuit is shown in
Figure 1 on the first page of this data sheet. External
component selection is driven by the load requirement
and begins with the selection of RSENSE. Once RSENSE
is known, COSC and L can be chosen. Next, the power
MOSFETs and D1 are selected. The operating frequency
and the inductor are chosen based largely on the desired
amount of ripple current. Finally, CIN is selected for its
ability to handle the large RMS current into the converter
and COUT is chosen with low enough ESR to meet the
output voltage ripple and transient specifications. The
circuit shown in Figure 1 can be configured for operation
up to an input voltage of 28V (limited by the external
MOSFETs).
Allowing a margin for variations in the LTC1735-1 and
external component values yields:
50mV
IMAX
RSENSE
=
COSC Selection for Operating Frequency
and Synchronization
The choice of operating frequency and inductor value is
a trade-off between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET switching losses, both gate charge loss and
transition loss. However, lower frequency operation
requires more inductance for a given amount of ripple
current.
RSENSE Selection For Output Current
The LTC1735-1 uses a constant frequency architecture
with the frequency determined by an external oscillator
capacitor COSC. Each time the topside MOSFET turns on,
thevoltageonCOSC isresettoground. Duringtheon-time,
COSC ischargedbyafixedcurrent.Whenthevoltageonthe
capacitor reaches 1.19V, COSC is reset to ground. The
process then repeats.
RSENSE is chosen based on the required output current.
The LTC1735-1 current comparator has a maximum
threshold of 75mV/RSENSE and an input common mode
range of SGND to 1.1(INTVCC). The current comparator
threshold sets the peak of the inductor current, yielding a
maximum average output current IMAX equal to the peak
value less half the peak-to-peak ripple current, ∆IL.
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The value of COSC is calculated from the desired operating
frequencyassumingnoexternalclockinputonthePGOOD
pin:
clamp present in Burst Mode operation is removed,
providing constant frequency discontinuous operation
over the widest possible output current range. In this
mode the synchronous MOSFET is forced on once every
10 clock cycles to recharge the bootstrap capacitor. This
minimizes audible noise while maintaining reasonably
high efficiency.
1.61(107)
Frequency
COSC(pF) =
– 11
A graph for selecting COSC versus frequency is given in
Figure 2. The maximum recommended switching fre-
quency is 550kHz .
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge losses. In addition to this basic trade
off, the effect of inductor value on ripple current and low
current operation must also be considered.
The internal oscillator runs at its nominal frequency (fO)
when the PGOOD pin is pulled high (to INTVCC) though a
series resistor or connected to ground. Clocking the
PGOOD pin above and below 1.2V will cause the internal
oscillator to injection-lock to an external clock signal
applied to the PGOOD pin with a frequency between 0.9fO
and 1.3fO. The clock high level must exceed 1.3V for at
least 0.3µs, and the clock low level must be less than 0.3V
for at least 0.3µs. The top MOSFET turn-on will synchro-
nize with the rising edge of the external clock.
Theinductorvaluehasadirecteffectonripplecurrent.The
inductor ripple current ∆IL decreases with higher induc-
Attempting to synchronize to too high of an external
frequency (above 1.3fO) can result in inadequate slope
compensation and possible loop instability at high duty
cycles. If this condition exists, simply lower the value of
COSC so (fEXT = fO) according to Figure 2.
tance or frequency and increases with higher VIN or VOUT
:
1
VOUT
V
IN
∆IL =
VOUT 1–
(f)(L)
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is∆IL = 0.3 to 0.4(IMAX). Remember,
the maximum ∆IL occurs at the maximum input voltage.
100.0
87.5
75.0
62.5
50.0
37.5
25.0
12.5
0
The inductor value also has an effect on low current
operation. The transition to low current operation begins
when the inductor current reaches zero while the bottom
MOSFET is on. Burst Mode operation begins when the
averageinductorcurrentrequiredresultsinapeakcurrent
below 25% of the current limit determined by RSENSE
.
0
100
200
300
400
500
600
OPERATING FREQUENCY (kHZ)
Lower inductor values (higher ∆IL) will cause this to occur
at higher load currents, which can cause a dip in efficiency
in the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
1735-1 F02
Figure 2. Timing Capacitor Value
When synchronized to an external clock, Burst Mode
operation is disabled but the inductor current is not
allowed to reverse. The 25% minimum inductor current
11
LTC1735-1
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SelectioncriteriaforthepowerMOSFETsincludethe“ON”
resistance RDS(ON), reverse transfer capacitance CRSS
input voltage and maximum output current. When the
LTC1735-1 is operating in continuous mode the duty
cycles for the top and bottom MOSFETs are given by:
Inductor Core Selection
,
Once the value for L is known, the type of inductor must be
selected.Highefficiencyconvertersgenerallycannotafford
the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool Mµ® cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
moreturnsofwireandthereforecopperlosseswillincrease.
VOUT
Main SwitchDuty Cycle =
V
IN
V – VOUT
IN
Synchronous SwitchDuty Cycle =
V
IN
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductancecollapsesabruptlywhenthepeakdesigncurrent
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
The MOSFET power dissipations at maximum output
current are given by:
VOUT
2
PMAIN
=
I
1+ δ R
+
(
MAX) (
)
DS(ON)
V
IN
2
k V
I
C
f
(
IN) ( MAX)( RSS)( )
V – VOUT
2
IN
P
=
I
(
1+ δ R
MAX) (
)
SYNC
DS(ON)
Molypermalloy (from Magnetics, Inc.) is a very good, low
losscorematerialfortoroids,butitismoreexpensivethan
ferrite. A reasonable compromise from the same
manufacturer is Kool Mµ. Toroids are very space efficient,
especiallywhenyoucanuseseverallayersofwire.Because
they generally lack a bobbin, mounting is more difficult.
However, designs for surface mount are available that do
not increase the height significantly.
V
IN
where δ is the temperature dependency of RDS(ON) and k
is a constant inversely related to the gate drive current.
Both MOSFETs have I2R losses while the topside
N-channel equation includes an additional term for transi-
tion losses, which are highest at high input voltages. For
VIN < 20V the high current efficiency generally improves
with larger MOSFETs, while for VIN > 20V the transition
losses rapidly increase to the point that the use of a higher
RDS(ON) device with lower CRSS actually provides higher
efficiency. The synchronous MOSFET losses are greatest
athighinputvoltageorduringashortcircuitwhentheduty
cycle in this switch is nearly 100%.
Power MOSFET and D1 Selection
Two external power MOSFETs must be selected for use
with the LTC1735-1: an N-channel MOSFET for the top
(main) switch, and an N-channel MOSFET for the bottom
(synchronous) switch.
The peak-to-peak gate drive levels are set by the INTVCC
voltage. This voltage is typically 5.2V during start-up (see
EXTVCC Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most LTC1735-1
applications. The only exception is when low input voltage
is expected (VIN < 5V); then, sub-logic level threshold
MOSFETs (VGS(TH) < 3V) should be used. Pay close
attention to the BVDSS specification for the MOSFETs as
well; most of the logic level MOSFETs are limited to 30V or
less.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. CRSS is usually specified in the
MOSFETcharacteristics. Theconstantk=1.7canbeused
to estimate the contributions of the two terms in the main
switch dissipation equation.
The Schottky diode D1 shown in Figure 1 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
Kool Mµ is a registered trademark of Magnetics, Inc.
12
LTC1735-1
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MOSFET from turning on and storing charge during the
dead-time, which could cost as much as 1% in efficiency.
A3ASchottkyisgenerallyagoodsizefor10Ato12Aregu-
lators due to the relatively small average current. Larger
diodes result in additional transition losses due to their
largerjunctioncapacitance.Thediodemaybeomittedifthe
efficiency loss can be tolerated.
the output ripple will be less than 50mV at max VIN
assuming:
COUT required ESR < 2.2 RSENSE
COUT > 1/(8fRSENSE
)
ThefirstconditionrelatestotheripplecurrentintotheESR
of the output capacitance while the second term guaran-
tees that the output voltage does not significantly dis-
chargeduringtheoperatingfrequencyperiodduetoripple
current. The choice of using smaller output capacitance
increases the ripple voltage due to the discharging term
but can be compensated for by using capacitors of very
low ESR to maintain the ripple voltage at or below 50mV.
TheITHpinOPTI-LOOPcompensationcomponentscanbe
optimized to provide stable, high performance transient
response regardless of the output capacitors selected.
CIN Selection
In continuous mode, the source current of the top
N-channel MOSFET is a square wave of duty cycle VOUT
/
VIN. To prevent large voltage transients, a low ESR input
capacitor sized for the maximum RMS current must be
used. The maximum RMS capacitor current is given by:
1/2
VOUT
V
IN
VOUT
IRMS IO(MAX)
– 1
V
IN
The selection of output capacitors for CPU or other appli-
cations with large load current transients is primarily de-
terminedbythevoltagetolerancespecificationsofthe load.
The resistive component of the capacitor, ESR, multiplied
by the load current change plus any output voltage ripple
must be within the voltage tolerance of the load (CPU).
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
usedfordesignbecauseevensignificantdeviationsdonot
offermuchrelief.Notethatcapacitormanufacturer’sripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. Always
consult the manufacturer if there is any question.
The required ESR due to a load current step is:
RESR < ∆V/∆I
where∆Iisthechangeincurrentfromfullloadtozeroload
(orminimumload)and∆Vistheallowedvoltagedeviation
(not including any droop due to finite capacitance).
COUT Selection
The amount of capacitance needed is determined by the
maximum energy stored in the inductor. The capacitance
mustbesufficienttoabsorbthechangeininductorcurrent
when a high current to low current transition occurs. The
oppositeloadcurrenttransitionisgenerallydeterminedby
the control loop OPTI-LOOP components, so make sure
not to over compensate and slow down the response. The
minimum capacitance to assure the inductors’ energy is
adequately absorbed is:
The selection of COUT is primarily determined by the
effectiveseriesresistance(ESR)tominimizevoltageripple.
The output ripple (∆VOUT) in continuous mode is deter-
mined by:
1
∆VOUT ≈ ∆IL ESR +
8fCOUT
where f = operating frequency, COUT = output capacitance,
and ∆IL= ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. Typically, once the ESR requirement
for COUT has been met, the RMS current rating generally
far exceeds the IRIPPLE(P-P) requirement. With ∆IL =
0.3IOUT(MAX) and allowing for 2/3 of the ripple due to ESR,
L ∆I 2
( )
COUT
>
2 ∆V VOUT
(
)
where ∆I is the change in load current.
13
LTC1735-1
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Manufacturers such as Nichicon, United Chemicon and
Sanyo can be considered for high performance through-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.
INTVCC and PGND IC pins is highly recommended. Good
bypassing is required to supply the high transient cur-
rents required by the MOSFET gate drivers.
Higher input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC1735-1 to be
exceeded. The system supply current is normally domi-
nated by the gate charge current. Additional loading of
INTVCC also needs to be taken into account for the power
dissipation calculations. The total INTVCC current can be
supplied by either the 5.2V internal linear regulator or by
the EXTVCC input pin. When the voltage applied to the
EXTVCC pin is less than 4.7V, all of the INTVCC current is
supplied by the internal 5.2V linear regulator. Power
dissipationfortheICinthiscaseishighest, (VIN)(IINTVCC),
and overall efficiency is lowered. The gate charge current
is dependant on operating frequency as discussed in the
Efficiency Consideration section. The junction tempera-
ture can be estimated by using the equations given in Note
2 of the Electrical Characteristics. For example, the
LTC1735CS-1 is limited to less than 17mA from a 30V
supply when not using the EXTVCC pin as follows:
In surface mount applications, multiple capacitors may
need to be used in parallel to meet the ESR, RMS current
handling and load step requirements of the application.
Aluminum electrolytic, dry tantalum and special polymer
capacitorsareavailableinsurfacemountpackages.Special
polymer surface mount capacitors offer very low ESR but
have much lower capacitive density per unit volume than
other capacitor types. These capacitors offer a very cost-
effective output capacitor solution and are an ideal choice
when combined with a controller having high loop
bandwidth. Tantalum capacitors offer the highest
capacitancedensityandareoftenusedasoutputcapacitors
for switching regulators having controlled soft-start.
Several excellent surge-tested choices are the AVX TPS,
AVX TPSV or the KEMET T510 series of surface mount
tantalums, available in case heights ranging from 2mm to
4mm. Aluminum electrolytic capacitors can be used in
cost-driven applications providing that consideration is
given to ripple current ratings, temperature and long-term
reliability.Atypicalapplicationwillrequireseveraltomany
aluminumelectrolyticcapacitorsinparallel.Acombination
of the above mentioned capacitors will often result in
maximizing performance and minimizing overall cost.
OthercapacitortypesincludeSanyoOS-CON,NichiconPL
series and Sprague 595D series. Consult manufacturers
for other specific recommendations.
TJ = 70°C + (17mA)(30V)(110°C/W) = 126°C
UseoftheEXTVCC inputpinreducesthejunctiontempera-
ture to:
TJ = 70°C + (17mA)(5V)(110°C/W) = 79°C
To prevent maximum junction temperature from being
exceeded, the input supply current must be checked
operating in continuous mode at maximum VIN.
EXTVCC Connection
The LTC1735-1 contains an internal P-channel MOSFET
switch connected between the EXTVCC and INTVCC pins.
Whenever the EXTVCC pin is above 4.7V the internal 5.2V
regulator shuts off, the switch closes and INTVCC power is
supplied via EXTVCC until EXTVCC drops below 4.5V. This
allows the MOSFET gate drive and control power to be
derived from the output or other external source during
normal operation. When the output is out of regulation
(start-up,shortcircuit)powerissuppliedfromtheinternal
regulator. Do not apply greater than 7V to the EXTVCC pin
and ensure that EXTVCC < VIN.
INTVCC Regulator
AninternalP-channellowdropoutregulatorproducesthe
5.2V supply that powers the drivers and internal circuitry
within the LTC1735-1. The INTVCC pin can supply a
maximum RMS current of 50mA and must be bypassed
to ground with a minimum of 4.7µF tantalum, 10µF
special polymer or low ESR type electrolytic capacitor. A
1µF ceramic capacitor placed directly adjacent to the
14
LTC1735-1
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V
OUT
Significant efficiency gains can be realized by powering
INTVCC from the output, since the VIN current resulting
from the driver and control currents will be scaled by a
factor of (Duty Cycle)/(Efficiency). For 5V regulators this
R2
V
OSENSE
R1
LTC1735-1
SGND
47pF
simply means connecting the EXTVCC pin directly to VOUT
.
1735-1 F03
However, for dynamic (VID-like) programmed regulators
and other lower voltage regulators, additional circuitry is
required to derive INTVCC power from the output.
Figure 3. Setting the LTC1735-1 Output Voltage
The resistive divider is connected to the output as shown
in Figure 3 allowing remote voltage sensing.
The following list summarizes the four possible connec-
tions for EXTVCC:
Theoutputvoltagecanbedigitallysettovoltagesbetween
any two levels with the addition of a resistor and small
signal N-channel MOSFET as shown in the circuit of
Figure1.Dynamicoutputvoltageselectioncanbeaccom-
plished with this technique. Output voltages of 1.30V and
1.55V are set by the resistors R1 to R3. With the gate of
the MOSFET low, (VG = 0), the output voltage is set by the
ratio of R1 to R2. When the MOSFET is on (VG = high), the
output voltage is the ratio of R1 to the parallel combina-
tion of R2 and R3. With the available power good output
(PGOOD), the circuit in Figure 1 creates a low cost Intel
Pentium III mobile processor compliant supply.
1. EXTVCC LeftOpen(orGrounded).ThiswillcauseINTVCC
tobepoweredfromtheinternal5.2Vregulatorresulting
in an efficiency penalty of up to 10% at high input
voltages.
2. EXTVCC connected directly to VOUT. This is the normal
connectionfora5Vto7Voutputregulatorandprovides
thehighestefficiency.Foroutputvoltages>5V,EXTVCC
is required to connect to VOUT so the SENSE pins
absolute maximum ratings are not exceeded.
3. EXTVCC Connected to an External Supply (This Option
is the Most Likely Used). If an external supply is
available in the 5V to 7V range, such as notebook main
5V system power, it may be used to power EXTVCC
providing it is compatible with the MOSFET gate drive
requirements. This is the typical case as the 5V power
isalmostalwayspresentandisderivedbyanotherhigh
efficiency regulator.
TheLTC1735-1hasremotesensecapability.Thetopofthe
internal resistive divider is connected to VOSENSE and is
referenced to the SGND pin. This allows a kelvin connec-
tionforremotelysensingtheoutputvoltagedirectlyacross
the load, eliminating any PC board trace resistance errors.
Topside MOSFET Driver Supply (CB, DB)
4. EXTVCC Connected to an Output-Derived Boost Net-
work. For low output voltage regulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derivedvoltagethathasbeenboostedtogreater
than 4.7V. This can be done with either the inductive
boost winding or capacitive charge pump circuits.
Refer to the LTC1735 data sheet for details. The charge
pump has the advantage of simple magnetics.
AnexternalbootstrapcapacitorCBconnectedtotheBOOST
pin supplies the gate drive voltage for the topside
MOSFET. CapacitorCBintheFunctionalDiagramischarged
though external diode DB from INTVCC when the SW pin is
low. Note that the voltage across CB is about a diode drop
below INTVCC. When the topside MOSFET is to be turned
on, thedriverplacestheCB voltageacrossthegate-source
of the MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage SW rises to
VIN and the BOOST pin rises to VIN + INTVCC. The value of
the boost capacitor CB needs to be 100 times greater than
thetotalinputcapacitanceofthetopsideMOSFET. Inmost
applications 0.1µF to 0.33µF is adequate. The reverse
breakdown on DB must be greater than VIN(MAX) .
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following formula:
R2
VOUT = 0.8V 1+
R1
15
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capacitor CSS. If RUN/SS has been pulled all the way to
ground there is a delay before starting of approximately:
When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If you make a change
and the input current decreases, then you improved the
efficiency. If there is no change in input current, then there
is no change in efficiency.
1.5V
TDELAY
=
C
SS = 1.25s/µF CSS
(
)
1.2µA
SENSE+/SENSE– Pins
When the voltage on RUN/SS reaches 1.5V the
LTC1735-1 begins operating with a current limit at ap-
proximately 25mV/RSENSE. As the voltage on RUN/SS
increases from 1.5V to 3V, the internal current limit is
increased from 25mV/RSENSE to 75mV/RSENSE. The out-
put current limit ramps up slowly, taking an additional
1.25s/µF to reach full current. Ramping the output cur-
rent slowly reduces the starting surge current
required from the input supply.
The common mode input range of the current comparator
is from 0V to 1.1(INTVCC). Continuous linear operation is
guaranteed throughout this range allowing output volt-
ages anywhere from 0.8V to 7V. A differential NPN input
stage is used and is biased with internal resistors from an
internal 2.4V source as shown in the Functional Diagram.
This causes current either to be sourced or sunk by these
pinsdependingontheoutputvoltage. Iftheoutputvoltage
is below 2.4V, current will flow out of both SENSE pins to
the main output. This forces a minimum load current that
can be fulfilled by the VOUT resistive divider. The maxi-
mum current flowing out of the SENSE pins is:
Diode D1 in Figure 4 and Figure 5 reduces the start delay
while allowing CSS to charge up slowly for the soft-start
function. This diode and CSS can be deleted if soft-start is
not needed. The RUN/SS pin has an internal 6V zener
clamp (see Functional Diagram).
ISENSE+ + ISENSE– = (2.4V – VOUT)/24k
3.3V OR 5V
RUN/SS
RUN/SS
SinceVOSENSEisservoedtothe0.8Vreferencevoltage, we
can choose R1 in Figure 3 to have a maximum value to
absorb this current:
D1
C
SS
C
SS
1735-1 F04
0.8V
R1(Max) = 24k
Figure 4. RUN/SS Pin Interfacing
2.4V – VOUT
V
INTV
IN
CC
R
Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32k. Note that for output voltages above
2.4V no maximum value of R1 is necessary to absorb the
sense currents; however, R1 is still bounded by the
VOSENSE feedback current.
3.3V OR 5V
RUN/SS
R
SS
SS
D1
RUN/SS
D1
C
SS
C
SS
Soft-Start/Run Function
1735-1 F05
(a)
(b)
The RUN/SS pin is a multipurpose pin that provides a soft-
start function and a means to shut down the LTC1735-1.
Soft-start reduces surge currents from VIN by gradually
increasing the controller’s current limit ITH(MAX). This pin
can also be used for power supply sequencing.
Figure 5. RUN/SS Pin Interfacing with Latchoff Defeated
Fault Conditions: Overcurrent Latchoff
The RUN/SS pin also provides the ability to shut off the
controller and latchoff when an overcurrent condition is
detected. The RUN/SS capacitor CSS is used initially to
turn on and limit the inrush current of the controller. After
the controller has been started and given adequate time to
charge up the output capacitor and provide full load
Pulling the RUN/SS pin below 1.5V puts the LTC1735-1
into a low quiescent current shutdown (IQ < 25µA). This
pin can be driven directly from logic as shown in Figures
4 and 5. Releasing the RUN/SS pin allows an internal
1.2µA current source to charge up the external soft-start
16
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current, CSS is used as a short-circuit timer. If the output
voltage falls to less than 70% of its nominal output voltage
after CSS reaches 4.1V, the assumption is made that the
output is in a severe overcurrent and/or short-circuit
condition and CSS begins discharging. If the condition
lasts for a long enough period as determined by the size of
CSS, the controller will be shut down until the RUN/SS pin
voltage is recycled.
The LTC1735-1 includes current foldback to help further
limit load current when the output is shorted to ground. If
the output falls by more than half, then the maximum
sense voltage is progressively lowered from 75mV to
30mV. Under short-circuit conditions with very low duty
cycles, the LTC1735-1 will begin cycle skipping in order to
limit the short-circuit current. In this situation the bottom
MOSFET will be conducting the peak current. The short-
circuit ripple current is determined by the minimum on-
time tON(MIN) of the LTC1735-1 (less than 200ns), the
input voltage, and inductor value:
This built-in latchoff can be overridden by providing a
current >5µA at a compliance of 5V to the RUN/SS pin as
shown in Figure 5a. This current shortens the soft-start
period but also prevents net discharge of the RUN/SS
capacitor during a severe overcurrent and/or short-circuit
conditions. When deriving the 5µA current from VIN as in
Figure 5a, current latchoff is always defeated. The diode
connectingthispull-upresistortoINTVCC , asinFigure5b,
eliminates any extra supply current during shutdown
while eliminating the INTVCC loading from preventing
controller start-up. If the voltage on CSS does not exceed
4.1V, the overcurrent latch is not armed and the function
is disabled.
∆IL(SC) = tON(MIN)(VIN/L)
The resulting short circuit-current is:
30mV
RSENSE
1
2
ISC
=
+ ∆IL(SC)
The current foldback function is always active and is not
effected by the current latchoff function.
Fault Conditions: Output Overvoltage Protection
(Crowbar)
Why should you defeat current latchoff? During the
prototypingstageofadesign,theremaybeaproblemwith
noise pickup or poor layout causing the protection circuit
to latch off. Defeating this feature will easily allow trouble-
shooting of the circuit and PC layout. The internal short
circuit and foldback current limiting still remains active,
thereby protecting the power supply system from failure.
After the design is complete, a decision can be made
whether to enable the latchoff feature.
The output overvoltage crowbar is designed to blow a
system fuse in the input lead when the output of the
regulator rises much higher than nominal levels. This
conditioncauseshugecurrentstoflow,muchgreaterthan
in normal operation. This feature is designed to protect
against a shorted top MOSFET; it does not protect against
a failure of the controller itself.
The comparator (OV in the Functional Diagram) detects
overvoltage faults greater than 7.5% above the nominal
output voltage. When this condition is sensed the top
MOSFET is turned off and the bottom MOSFET is forced
on. The bottom MOSFET remains on continuously for as
long as the OV condition persists; if VOUT returns to a safe
level, normal operation automatically resumes. Note that
dynamically changing the output voltage may cause over-
voltage protection to be momentarily activated during
output voltage decreases. This will not cause permanent
latchoff nor will it disrupt the desired voltage change.
The value of the soft-start capacitor CSS will need to be
scaled with output current, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
C
SS > (COUT )(VOUT) (10–4) (RSENSE
)
The minimum recommended soft-start capacitor of
CSS = 0.1µF will be sufficient for most applications.
Fault Conditions: Current Limit and Current Foldback
Withsoft-latchovervoltageprotection,dynamicallychang-
ing the output voltage is allowed and the overvoltage
protection tracks the newly programmed output voltage,
always protecting the load (CPU).
TheLTC1735-1currentcomparatorhasamaximumsense
voltage of 75mV resulting in a maximum MOSFET current
of 75mV/RSENSE
.
17
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Minimum On-Time Considerations
PGOOD Pin Operation
Minimum on-time tON(MIN) is the smallest amount of time
that the LTC1735-1 is capable of turning the top MOSFET
on and off again. It is determined by internal timing delays
and the gate charge required to turn on the top MOSFET.
Low duty cycle applications may approach this minimum
on-time limit and care should be taken to ensure that:
ThePGOODpinisamultifunctionpinintendedprimarilyto
indicate when the output voltage is within ±7.5% of its
nominal set point. A window comparator monitors the
V
OSENSE pin and activates an open-drain internal MOSFET
that pulls down the PGOOD pin when the output voltage is
out of regulation. Normally a 10k to 100k pull-up resistor
is connected to this pin from a voltage source such as
INTVCC. Do not apply a voltage greater than INTVCC to this
pin.Dynamicallychangingtheoutputvoltagebetweentwo
voltage levels greater that 7.5% apart from each other will
invoke the power good indication, causing the PGOOD
output to go low until the new output voltage is reached.
VOUT
tON(MIN)
<
V (f)
IN
Ifthedutycyclefallsbelowwhatcanbeaccommodatedby
the minimum on-time, the LTC1735-1 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
When the DC voltage on the PGOOD pin drops below its
0.8V threshold, continuous mode operation is forced. In
this case, the top and bottom MOSFETs continue to be
driven synchronously regardless of the load on the main
output. Burst Mode operation is disabled and current
reversal is allowed in the inductor. This mode is forced
whenever the output voltage is not within its 7.5%
window.
The minimum on-time for the LTC1735-1 in a properly
configuredapplicationislessthan200ns. However, asthe
peak sense voltage decreases, the minimum on-time
gradually increases as shown in Figure 6. This is of
particular concern in forced continuous applications with
low ripple current at light loads. If the duty cycle drops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with corre-
spondingly larger current and voltage ripple.
In addition to providing a power good output, the PGOOD
pin provides a logic input to force continuous synchro-
nous operation and allow synchronization to an external
clock.
If an application can operate close to the minimum on-
time limit, an inductor must be chosen that is low enough
to provide sufficient ripple amplitude to meet the mini-
mum on-time requirement. As a general rule keep the
inductor ripple current equal or greater than 30% of
The internal LTC1735-1 oscillator can be synchronized to
an external oscillator by applying a clock signal to the
PGOOD pin though a series resistor with a signal ampli-
tude above 1.5VP-P. When synchronized to an external
frequency, Burst Mode operation is disabled but cycle
skipping is allowed at low load currents since current
reversal is inhibited. The bottom gate will come on every
10 clock cycles to assure the bootstrap capacitor is kept
refreshed. The rising edge of an external clock applied to
the PGOOD pin starts a new cycle. If the output voltage is
not within the 7.5% window around its nominal set point,
the open-drain PGOOD output will pull low, disabling the
external synchronization.
IOUT(MAX) at VIN(MAX)
.
250
200
150
100
50
The following table summarizes the possible states avail-
able on the PGOOD pin.
0
0
10
20
30
40
∆I /I
L
(%)
OUT(MAX)
1736-1 F06
Figure 6. Minimum On-Time vs ∆IL
18
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Table 1
and control currents. VIN current results in a small
(<0.1%) loss that increases with VIN.
PGOOD PIN
CONDITION
DC Voltage: 0V to 0.7V
No Power Good Indication
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTVCC to ground. The resulting dQ/dt is a current
out of INTVCC that is typically much larger than the
Burst Mode Operation Disabled/Forced
Continuous Current Reversal Enabled
Resistor Pull-Up to
Power Good Indication
Burst Mode, No Current Reversal
When Power is Good
INT
(or Other DC
VCC
Voltage Less Than INTV
)
CC
Resistor to Ext Clock:
(0V to 1.5V)
No Power Good Indication
Burst Mode Operation Disabled
No Current Reversal
control circuit current. In continuous mode, IGATECHG
=
The circuit shown in Figure 7 provides a power good
output and forces continuous operation. Transistor Q1
keeps the voltage at the PGOOD pin below 0.8V thus
disabling Burst Mode operation. When the window com-
parator indicates the output voltage is not within its 7.5%
window, the base of Q1 is pulled to ground and the power
good output appearing at the collector of Q2 goes low.
f(QT + QB), where QT and QB are the gate charges of the
topside and bottom-side MOSFETs.
BypoweringEXTVCC fromanoutput-derivedsource(or
other high efficiency source), the additional VIN current
resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Efficiency). For
example, in a 15V to 1.8V application, 10mA of INTVCC
current results in approximately 1.2mA of VIN current.
This reduces the midcurrent loss from 10% or more (if
the driver was powered directly from VIN) to only a few
percent.
INTV
CC
470k
100k
10k
POWER
GOOD
Q2
PGOOD
PIN 4
Q1
3. I2R losses are predicted from the DC resistances of the
MOSFETs, inductor and current shunt. In continuous
mode, the average output current flows through L and
RSENSE, but is “chopped” between the topside main
MOSFET and the synchronous MOSFET. If the two
MOSFETs have approximately the same RDS(ON), then
the resistance of one MOSFET can simply be summed
with the resistances of L and RSENSE to obtain I2R
losses. For example, if each RDS(ON) = 0.02Ω, RL =
0.03Ω, and RSENSE = 0.01Ω, then the total resistance is
0.06Ω. This results in losses ranging from 3% to 17%
as the output current increases from 1A to 5A for a 1.8V
output, or 4% to 20% for a 1.5V output. Efficiency
varies as the inverse square of VOUT for the same
external components and power level. I2R losses cause
the efficiency to drop at high output currents.
1735-1 F07
Figure 7. Forced Continuous Operation with Power Good Indication
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1735-1 circuits: 1) LTC1735-1 VIN current,
2) INTVCC current, 3) I2R losses, 4) Topside MOSFET
transition losses.
4. Transition losses apply only to the topside MOSFET(s),
and only become significant when operating at high
input voltages (typically 12V or greater). Transition
losses can be estimated from:
2
1. The VIN current is the DC supply current given in the
electricalcharacteristicswhichexcludesMOSFETdriver
Transition Loss = (1.7) VIN IO(MAX) CRSS
f
19
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determined. The output capacitors need to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulseof20%to100%offullloadcurrenthavingarisetime
of 1µs to 10µs will produce output voltage and ITH pin
waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. The initial
outputvoltagestepmaynotbewithinthebandwidthofthe
feedback loop, so the standard second order overshoot/
DC ratio cannot be used to determine phase margin. The
gain of the loop will be increased by increasing RC and the
bandwidth of the loop will be increased by decreasing CC.
If RC is increased by the same factor that CC is decreased,
the zero frequency will be kept the same, thereby keeping
the phase shift the same in the most critical frequency
range of the feedback loop. The output voltage settling
behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses in the
designofasystem.Theinternalbatteryandfuseresistance
losses can be minimized by making sure that CIN has
adequate charge storage and a very low ESR at the
switching frequency. A 25W supply will typically require
a minimum of 20µF to 40µF of capacitance having a
maximum of 0.01Ω to 0.02Ω of ESR. Other losses
including Schottky conduction losses during dead-time
and inductor core losses generally account for less than
2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD (ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The availability of the ITH pin not only
allows optimization of control loop behavior but also
providesaDCcoupledandACfilteredclosed-loopresponse
test point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantlysecondordersystem,phasemarginand/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
external components shown in the Figure 1 circuit will
provide an adequate starting point for most applications.
Improve Transient Response and Reduce Output
Capacitance with Active Voltage Positioning
Fast load transient response, limited board space and low
cost are normal requirements of microprocessor power
supplies. Active voltage positioning improves transient
response and reduces the output capacitance required to
power a microprocessor where a typical load step can be
from 0.2A to 15A in 100ns or 15A to 0.2A in 100ns. The
voltage at the microprocessor must be held to about
±0.1V of nominal in spite of these load current steps.
Since the control loop cannot respond this fast, the output
capacitors must supply the load current until the control
loop can respond. Capacitor ESR and ESL primarily deter-
mine the amount of droop or overshoot in the output
voltage. Normally, several capacitors in parallel are re-
quired to meet microprocessor transient requirements.
Active voltage positioning is a form of deregulation. It
sets the output voltage high for light loads and low for
heavy loads. When load current suddenly increases, the
output voltage starts from a level higher than nominal so
the output voltage can droop more and stay within the
specified voltage range. When load current suddenly
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
20
LTC1735-1
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decreases the output voltage starts at a level lower than
nominal so the output voltage can have more overshoot
and stay within the specified voltage range. Less output
capacitance is required when voltage positioning is used
because more voltage variation is allowed on the output
capacitors.
accuracy is ±1%. Using 1% tolerance resistors, the total
feedback divider accuracy is about 1% because both
feedback resistors are close to the same value. The result-
ing setpoint accuracy is ±2% so the output transient
voltage cannot exceed ±0.082V. For VOUT = 1.5V, the
maximum output voltage change controlled by the ITH pin
would be:
Active voltage positioning can be implemented using the
OPTI-LOOP architecture of the LTC1735-1 and two resis-
tors connected to the ITH pin. An input voltage offset is
introducedwhentheerroramplifierhastodrivearesistive
load. This offset voltage is limited to ±30mV at the input
of the error amplifier. The resulting change in output
voltage is the product of input offset voltage and the
feedback voltage divider ratio.
Input Offset Voltage • VOUT
∆VOSENSE
=
=
VREF
±0.03V •1.5
= ±56mV
0.8V
With optimum resistor values at the ITH pin, the output
voltage will swing from 1.55V at minimum load to 1.44V
atfullload. Atthisoutputvoltage, activevoltageposition-
ing provides an additional ±56mV to the allowable tran-
sientvoltageontheoutputcapacitors,a68%improvement
over the ±82mV allowed without active voltage
positioning.
Figure 8 shows a CPU-core-voltage regulator with active
voltage positioning. Resistors R1 and R5 force the input
voltage offset that adjusts the output voltage according to
the load current level. To select values for R1 and R5, first
determinetheamountofoutputderegulationallowed. The
actual specification for a typical microprocessor allows
the output to vary ±0.112V. The LTC1735-1 reference
R3 680k
V
IN
7.5V TO
24V
C12 TO C14
10µF
35V
C7
0.1µF
R4 100k
R5 100k
PGOOD
R1
27k
GND
C9, C19: TAIYO YUDEN JMK107BJ105
C10: KEMET T494A475M010AS
C12 TO C14: TAIYO YUDEN GMK325F106
C15 TO C18: PANASONIC EEFUE0G181R
D1: CENTRAL SEMI CMDSH-3
C1
39pF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q1
C
TG
BOOST
SW
OSC
FDS6680A
C2
0.1µF
D2: MOTOROLA MBRS340
L1: PANASONIC ETQP6F1R0SA
Q1 TO Q3: FAIRCHILD FDS6680A
R5: IRC LRF2512-01-R003-J
RUN/SS
C3
100pF
C8
R2
0.22µF
100k
U1: LINEAR TECHNOLOGY LTC1735CS-1
I
TH
C4
100pF
U1
LTC1735-1
PGOOD
L1
1µH
R6
0.003Ω
D1
V
1.5V
15A
OUT
V
IN
CMDSH-3
C11
330pF
D2
C19
1µF
–
+
SENSE
SENSE
V
INTV
CC
MBRS340
R7
10k
C5
1000pF
Q2, Q3
FDS6680A
×2
C15 TO
+
BG
C18
180µF
4V
C6
47pF
C10
4.7µF
10V
+
R8
C9
1µF
11.5k
GND
PGND
OSENSE
SGND
5V (OPTIONAL)
EXTV
CC
1735-1 F08
Figure 8. CPU-Core-Voltage Regulator with Active Voltage Positioning
21
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The next step is to calculate the ITH pin voltage, VITH, scale
factor. The VITH scale factor reflects the ITH pin voltage
required for a given load current in continuous inductor
current operation. VITH controls the peak sense resistor
voltage, which represents the DC output current plus one
half of the peak-to-peak inductor current. The no load to
full load VITH range is from 0.3V to 2.4V, which controls
the sense resistor voltage from 0V to the ∆VSENSE(MAX)
voltage of 75mV. For the circuit shown in Figure 8, the
calculated VITH scale factor is:
VITH from 0.40V at light load to 1.77V at full load, a 1.37V
change. During Burst Mode operation, the LTC1735-1
output voltage is controlled by a comparator, not the error
amplifier. Even though the error amplifier is not used in
Burst Mode operation, it is necessary to assume linear
operation for all error amplifier gain calculations.
To create the ±30mV input offset error, the voltage gain of
the error amplifier must be limited. The desired gain is:
∆V
1.37V
ITH
AV =
=
= 22.8
Input Offset Error 2(0.03V)
V
ITH Range • SenseResistor Value
VITH ScaleFactor =
Connectingaresistortotheoutputofthetransconductance
error amplifier will limit the voltage gain. The value of this
resistor is:
∆VSENSE(MAX)
(2.4V – 0.3V)• 0.003
=
= 0.084V/A
0.075V
AV
22.8
RITH
=
=
= 17.54k
Assuming continuous inductor current, VITH is:
Error Amplifier gm 1.3ms
∆IL
2
To center the output voltage variation, VITH must be
centered so that no ITH pin current flows when the output
voltage is nominal. VITH(NOM) is the average voltage be-
tween VITH at maximum output current and minimum
output current:
V
ITH = IOUTDC
+
• VITH ScaleFactor
+VITH Offset
At full load current:
V
ITH(MAX) – V
ITH(MIN)
5AP−P
V
=
=
+ V
ITH(MIN)
ITH(NOM)
V
=
15A +
• 0.084V/A + 0.3V
ITH(MAX)
2
2
1.77V – 0.40V
+ 0.40V = 1.085V
= 1.77V
At minimum load current:
2
The Thevenin equivalent of the gain limiting resistance
value of 17.54k is made up of a resistor R5 that sources
current into the ITH pin and resistor R1 that sinks current
to SGND.
2AP−P
2
V
=
0.2A +
• 0.084V/A + 0.3V
ITH(MIN)
= 0.40V
To calculate the resistor values, first determine the ratio
between them:
Noticethat∆IL,thepeak-to-peakinductorcurrent,changes
from light load to full load. Increasing the DC inductor
current decreases the permeability of the inductor core
material, which decreases the inductance and increases
∆IL. The amount of inductance change is a function of the
inductor design.
V
INTVCC – V
5.2V – 1.085V
1.085V
ITH(NOM)
k =
=
= 3.79
V
ITH(NOM)
VINTVCC is equal to VEXTVCC or 5.2V if EXTVCC is not used.
Resistor R5 is:
If the circuit shown in Figure 8 sustained continuous in-
ductorcurrentoperation, theerroramplifierwouldcontrol
R5 = (k +1)•RITH = (3.79 +1)•17.54k = 84.0k
22
LTC1735-1
U
W U U
APPLICATIO S I FOR ATIO
Resistor R1 is:
Automotive Considerations: Plugging Into the
Cigarette Lighter
(k + 1)•RITH (3.79 + 1)•17.54k
R1=
=
= 22.17k
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserveorevenrechargebatterypacksduringoperation.
But before you connect, be advised: you are plugging into
the supply from hell. The main power line in an auto is the
sourceofanumberofnastypotentialtransients, including
load dump, reverse battery and double battery.
k
3.79
Unfortunately,PCBnoisecanaddtothevoltagedeveloped
across the sense resistor, R6, causing the ITH pin voltage
to be slightly higher than calculated for a given output
current. The amount of noise is proportional to the output
current level. This PCB noise does not present a serious
problem but it does change the effective value of R6 so the
calculated values of R1 and R5 may need to be adjusted to
achieve the required results. Since PCB noise is a function
ofthelayout,itwillbethesameonallboardswiththesame
layout.
Load dump is the result of a loose battery cable. When the
cablebreaksconnection,thefieldcollapseinthealternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse battery is
just what it says, while double battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
Figures 9 and 10 show the transient response before and
after active voltage positioning is implemented. Notice
that active voltage positioning reduced the transient re-
The network shown in Figure 11 is the most straight
forward approach to protect a DC/DC converter from the
ravages of an automotive power line. The series diode
prevents current from flowing during reverse battery,
while the transient suppressor clamps the input voltage
during load dump. Note that the transient suppressor
should not conduct during double-battery operation, but
must still clamp the input voltage below breakdown of the
converter. Although the LTC1735-1 has a maximum input
voltage of 36V, most applications will be limited to 30V by
sponse from almost 200mVP-P to a little over 100mVP-P
.
Refer to Design Solutions 10 for more information about
active voltage positioning.
VIN = 12V
FIGURE 8 CIRCUIT
VOUT = 1.5V
1.582V
1.50V
100mV/DIV
OUTPUT
VOLTAGE
1.418V
15A
LOAD
CURRENT
the MOSFET BVDSS
.
0.2A
0A
5A/DIV
50A I RATING
PK
50µs/DIV
1735-1 F09
V
IN
12V
Figure 9. Transient Response Without Active Voltage Positioning
LTC1735-1
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
VIN = 12V
VOUT = 1.5V
FIGURE 8 CIRCUIT
1.582V
OUTPUT
VOLTAGE
100mV/DIV 1.50V
1735-1 F11
1.418V
15A
LOAD
CURRENT
Figure 11. Plugging Into the Cigarette Lighter
0.2A
5A/DIV
0A
50µs/DIV
1735-1 F10
Figure 10. Transient Response with Active Voltage Positioning
23
LTC1735-1
U
W U U
APPLICATIO S I FOR ATIO
Design Example
22V – 1.5V
22V
= 959mW
2
P
=
12A 1.1 0.0065Ω
(
) ( )(
)
SYNC
As a design example, assume VIN = 12V (nominal), VIN =
22V (max), VOUT = 1.5V, IMAX = 12A and f = 300kHz,
RSENSE and COSC can immediately be calculated:
Thanks to current foldback, the bottom MOSFET dissipa-
tion in short circuit will be less than under full-load
conditions.
RSENSE = 50mV/12A = 0.042Ω
COSC = 1.61(107)/(300kHz) – 11pF = 43pF
CIN is chosen for an RMS current rating of at least 6A at
temperature. COUT is chosen with an ESR of 0.01Ωfor low
outputripple. Theoutputrippleincontinuousmodewillbe
highest at the maximum input voltage. The output voltage
ripple due to ESR is approximately:
Assume a 1.2µH inductor and check the actual value of the
ripple current. The following equation is used :
VOUT
(f)(L)
VOUT
∆IL =
1–
V
IN
V
ORIPPLE = RESR(∆IL) = 0.01Ω(3.9A) = 39mVP-P
The highest value of the ripple current occurs at the
maximum input and output voltages:
Sincetheoutputvoltageisbelow2.4V,theoutputresistive
divider will need to be sized to not only set the output
voltage but also to absorb the SENSE pins specified input
current.
1.5V
300kHz(1.2µH)
1.5V
22V
∆IL =
1–
= 3.9A
0.8V
R1(MAX) = 24k
= 21.3k
The maximum ripple current is 32% of maximum output
current, which is about right.
2.4V – 1.5V
Choosing 1% resistors: R1 = 21k and R2 = 18.7k yields an
output voltage of 1.512V.
Next, verify the minimum on-time of 200ns is not violated.
The minimum on-time occurs at maximum VIN and mini-
mum VOUT
.
PC Board Layout Checklist
VOUT
1.5V
tON(MIN)
=
=
= 227ns
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1735-1. These items are also illustrated graphically in
the layout diagram of Figure 12. Check the following in
your layout:
V
IN(MAX)f 22V(300kHz)
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Fairchild FDS6612A results
in; RDS(ON) = 0.03Ω, CRSS = 80pF. At maximum input
voltage with T(estimated) = 50°C:
1. Are the signal and power grounds segregated? The
LTC1735-1 PGND pin should tie to the ground plane
close to the input capacitor(s). The SGND pin should
then connect to PGND and all components that connect
to SGND should make a single-point tie to the SGND
pin. The synchronous MOSFET source should connect
to the input capacitor(s) ground.
1.5V
22V
2
PMAIN
=
12 1+(0.005)(50°C – 25°C) 0.03Ω
( )
(
]
)
[
2
+1.7 22V 12A 80pF 300kHz
(
) (
)(
)(
)
= 568mW
Because the duty cycle of the bottom MOSFET is much
greater than the top, two larger MOSFETs must be paral-
leled. Choosing Fairchild FDS6680A MOSFETs yields a
parallel RDS(ON) of 0.0065Ω. The total power dissipation
for both bottom MOSFETs, again assuming T = 50°C, is:
2. Does the VOSENSE pin connect directly to the feedback
resistors? The resistive divider R1, R2 must be con-
nectedbetweenthe(+)plateofCOUT andsignalground.
The 47pF capacitor from VOSENSE to SGND should be
as close as possible to the LTC1735-1. Be careful
locating the feedback resistors too far away from the
24
LTC1735-1
U
W U U
APPLICATIO S I FOR ATIO
LTC1735-1. The VOSENSE line should not be routed
close to any other nodes with high slew rates.
5. Is the INTVCC decoupling capacitor connected closely
betweenINTVCC andthepowergroundpin?Thiscapaci-
tor carries the MOSFET driver peak currents. An addi-
tional1µFceramicplacedimmediatelynexttotheINTVCC
and PGND pins can help improve noise performance.
3. AretheSENSE+ andSENSE– leadsroutedtogetherwith
minimum PC trace spacing? The filter capacitor be-
tween SENSE+ and SENSE– should be as close as
possible to the LTC1735-1. Ensure accurate current
sensing with kelvin connections to the SENSE resistors
shown in Figure 13. Series resistance can be added to
the SENSE lines to increase noise rejection.
6. Keeptheswitchingnode(SW),TopGatenode(TG),and
Boost node (BOOST) away from sensitive small-signal
nodes, especially from the voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and therefore should be kept on the
“output side” (Pins 9 to 16) of the LTC1735-1 and
occupy minimum PC trace area.
4. Does the (+) terminal of CIN connect to the drain of the
topsideMOSFET(s)ascloselyaspossible?Thiscapaci-
tor provides the AC current to the MOSFET(s).
INTV
CC
+
C
C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OSC
Q1
C
TG
OSC
C
C
SS
R
RUN/SS
BOOST
C
C
IN
C
I
LTC1735-1 SW
TH
+
C2
V
IN
C
PGOOD
V
IN
D
B
B
D1
–
SENSE
SENSE
INTV
CC
1000pF
+
+
BG
4.7µF
V
PGND
OSENSE
47pF
SGND
EXTV
CC
Q2
–
L1
–
R1
C
V
OUT
OUT
+
R
SENSE
R2
+
1735-1 F12
Figure 12. LTC1735-1 Layout Diagram
HIGH CURRENT PATH
1735-1 F13
CURRENT SENSE
RESISTOR
(R
SENSE
)
+
–
SENSE SENSE
Figure 13. Kelvin Sensing RSENSE
25
LTC1735-1
U
TYPICAL APPLICATIONS
1.8V/5A Converter with Power Good
V
IN
INTV
CC
4.5V TO 22V
C
C
IN
100k
1
OSC
43pF
22µF
50V
16
15
14
13
12
11
10
9
Q1
C
TG
BOOST
SW
OSC
CER
Si4412DY
C
C
B
SS
0.1µF
0.1µF
2
3
4
5
6
7
8
RUN/SS
C
C
R
C
470pF
33k
I
TH
LTC1735-1
PGOOD
L1
3.3µH
R
SENSE
D
POWER
GOOD
B
V
1.8V
5A
0.01Ω
OUT
C
220pF
V
C2
IN
CMDSH-3
R2
–
32.4k
1%
C
SENSE
SENSE
V
INTV
CC
OUT
+
+
150µF
6.3V
×2
1000pF
4.7µF
Q2
Si4410DY
+
R1
BG
25.5k
1%
PANASONIC SP
47pF
MBRS140T3
PGND
OSENSE
SGND
OPTIONAL:
SGND
EXTV
CC
C
C
: PANASONIC EEFUEOG151R
OUT
: MARCON THCR70LE1H226ZT
CONNECT TO 5V
IN
L1: PANASONIC ETQP6F3R3HFA
: IRC LR 2010-01-R010F
R
SENSE
1735-1 TA02
CPU Core Voltage Regulator for 2-Step Applications (VIN = 5V) with Burst Mode Operation Disabled
V
IN
5V
100k*
C
IN
C
39pF
150µF
6.3V
×2
OSC
1
16
15
14
13
12
11
10
9
Q1
C
TG
BOOST
SW
OSC
FDS6680A
C
C
B
SS
0.1µF
0.22µF
2
3
4
5
6
7
8
RUN/SS
INTV
CC
C
C
R
C
220pF
20k
10k 100k
470k
I
TH
C
C2
220pF
POWER
GOOD
LTC1735-1
PGOOD
L1
0.78µH
R
SENSE
D
B
V
1.5V
12A
0.004Ω
OUT
Q5
V
IN
MBR0530
Q4
R2
–
SENSE
SENSE
V
INTV
CC
32.4k
1%
100pF
C
OUT
C
+
+
O
180µF
4V
1000pF
4.7µF
47µF
Q2, Q3
FDS6680A
×2
10V
+
R1
25.5k
1%
BG
×3
1µF
47pF
MBRD835L
PGND
OSENSE
SGND
C
IN
: PANASONIC EEFUEOG181R
OUT
V
IN
5V
SGND
EXTV
CC
C
: PANASONIC EEFUEOJ151R
C : TAIYO YUDEN LMK550BJ476MM-B
O
L1: COILCRAFT 1705022P-781HC
Q4, Q5: 2N2222
R
: IRC LRF 2512-01-R004-J
SENSE
1735-1 TA03
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
26
LTC1735-1
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
0.009
(0.229)
REF
16 15 14 13 12 11 10 9
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
2
3
4
5
6
7
8
0.015 ± 0.004
(0.38 ± 0.10)
× 45°
0.053 – 0.068
(1.351 – 1.727)
0.004 – 0.0098
(0.102 – 0.249)
0.007 – 0.0098
(0.178 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.0250
(0.635)
BSC
0.008 – 0.012
(0.203 – 0.305)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 1098
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
16
15
14
13
12
11
10
9
0.150 – 0.157**
0.228 – 0.244
(3.810 – 3.988)
(5.791 – 6.197)
5
7
8
1
2
3
4
6
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0° – 8° TYP
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
TYP
0.016 – 0.050
(0.406 – 1.270)
S16 1098
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC1735-1
U
TYPICAL APPLICATIO
High Efficiency Dynamic Output Voltage Selectable CPU Power Supply for SpeedStep Enabled Processors
PGOOD RUN
V
IN
4.5V TO 24V
JP1
LATCH-OFF
DISABLE
R7
100k
R6
680k
R8
4.7Ω
INTV
CC
C
IN
22µF
50V
CERAMIC
×2
C
C
C
: MARCON THCR70E1H226ZT
F1
IN
0.1µF
: PANASONIC EEFVE06181R
OUT
C
C
47pF
L1: PANASONIC ETQP6F1R2HFA
1
2
3
4
5
6
7
8
OSC
16
Q1
FDS6680A
C
TG
OSC
RUN/SS
LTC1735-1 SW
PGOOD
R
: IRC CRF2512-01-R004F
SENSE
C
0.1µF
15
14
13
12
11
10
9
SS
BOOST
L1
R
33k
R
C
0.22µF
C1
SENSE
B
330pF
C2
1.2µH
V
0.004Ω
I
OUT
TH
C
47pF
1.35V OR 1.60V
D1
CMDSH-3
C1
V
IN
12A
D2
R1
–
SENSE
SENSE
V
INTV
CC
C2
MBRS340T3
10k
C1
47pF
+
C4
1µF
C
C2
S1
C
OUT
180µF
4V
SP
×4
+
47pF
0.5%
Q2, Q3
FDS6680A
×2
BG
1000pF
4.7µF
+
R3
33.2k
1%
PGND
C3
47pF
OSENSE
SGND
5V
INPUT
(OPTIONAL)
EXTV
CC
Q4
2N7002
V
V
= 1: V
= 0: V
= 1.60V
= 1.35V
SEL
SEL
OUT
OUT
R5 10Ω
R4 10Ω
R2
14.3k
0.5%
GND
1735-1 TA01
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Adaptive Power and PolyPhase are trademarks of Linear Technology Corporation.
17351f LT/TP 0100 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1999
28 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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