LTC1736IG_技术文档

LTC1736

5-Bit Adjustable

High Efficiency Synchronous

Step-Down Switching Regulator

U

FEATURES

DESCRIPTIO

The LTC^®1736 is a synchronous step-down switching

■

Dual N-Channel MOSFET Synchronous Drive

■

Synchronizable/Programmable Fixed Frequency

Wide V_INRange: 3.5V to 36V Operation

regulator controller optimized for CPU power. The output

voltage is programmed by a 5-bit digital-to-analog con-

verter (DAC) that adjusts the output voltage from 0.925V

to 2.00V according to Intel mobile VID specifications. The

0.8V reference is compatible with future microprocessor

generations.

■

5-Bit Digital-to-Analog V_OUTSelection:

0.925V to 2.00V Range with 50mV/25mV Steps

OPTI-LOOP^TMCompensation Minimizes C_OUT

■

±

1% Output Voltage Accuracy

Power Good Output Voltage Monitor

Active Voltage Positioning Compatible

Output Overvoltage Crowbar Protection

Internal Current Foldback

The operating frequency (synchronizable up to 500kHz) is

set by an external capacitor allowing maximum flexibility

inoptimizingefficiency.Theoutputvoltageismonitoredby

a power good window comparator that indicates when the

output is within 7.5% of its programmed value.

Latched Short-Circuit Shutdown Timer

with Defeat Option

Forced Continuous Control Pin

Optional Programmable Soft-Start

Remote Output Voltage Sense

■

Protection features include: internal foldback current lim-

iting, output overvoltage crowbar and optional short-cir-

cuitshutdown.Soft-startisprovidedbyanexternalcapaci-

tor that can be used to properly sequence supplies. The

operatingcurrentlevelisuser-programmableviaanexter-

nal current sense resistor. Wide input supply range allows

operation from 3.5V to 30V (36V maximum).

Pin defeatable Burst Mode^TMoperation provides high effi-

ciency at low load currents. OPTI-LOOP compensation

allows the transient response to be optimized over a wide

range of output capacitance and ESR values.

^{Available in 24-L}U^{ead SSOP Package}

APPLICATIO S

■

Notebook and Palmtop Computers, PDAs

Power Supply for Mobile Pentium^®II and

■

Pentium III Processors

Low Voltage Power Supplies

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

OPTI-LOOP and Burst Mode are trademarks of Linear Technology Corporation.

Pentium is a registered trademark of Intel Corporation.

U

TYPICAL APPLICATIO

V

C

IN

OSC

5V TO 24V

47pF

C

V

IN

OSC

C

IN

C

SS

0.1µF

22µF/50V

×2

M1

TG

L1

1.2µH

FDS6680A

R

CERAMIC

SENSE

0.004Ω

RUN/SS

V

OUT

C

C1

330pF

SW

1.35V TO 1.60V

12A

R

C

33k

D

B

LTC1736

VIDV

CMDSH-3

CC

C

B

0.22µF

I

TH

+

C

OUT

C

C2

47pF

INTV

180µF/4V

×4

PGOOD

VID4

BOOST

+

VID3

4.7µF

VID2

M2

FDS6680A

×2

D1

BG

VID1

MBRS340T3

C

: PANASONIC EEFUEOG181R

OUT

VID0

C

: MARCON THCR70EIH226ZT

IN

SGND

PGND

+

L1: PANASONIC ETQP6RZIR20HFA

: IRC LRF2010-01-R004J

–

V

SENSE SENSE

1000pF

OSENSE

R

SENSE

47pF

1736 F01

Figure 1. High Efficiency Step-Down Converter

1

LTC1736

W W

U W

U

W

U

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

TOP VIEW

Input Supply Voltage (V_IN).........................36V to –0.3V

Topside Driver Supply Voltage (BOOST)....42V to –0.3V

Switch Voltage (SW) ....................................36V to –5V

EXTV_CC, VIDV_CC, (BOOST – SW) Voltages ..7V to –0.3V

SENSE⁺, SENSE^–.......................... 1.1(INTV_CC) to –0.3V

FCB Voltage ............................(INTV_CC+ 0.3V) to –0.3V

I_TH, V_OSENSE, V_FBVoltage .........................2.7V to –0.3V

RUN/SS, VID0 to VID4, PGOOD Voltages ....7V to –0.3V

Peak Driver Output Current <10µs (TG, BG) .............. 3A

INTV_CCOutput Current ......................................... 50mA

Operating Ambient Temperature Range

LTC1736C ............................................... 0°C to 85°C

LTC1736I............................................ –40°C to 85°C

Junction Temperature (Note 2)............................. 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

ORDER PART

NUMBER

1

2

TG

24

23

22

21

20

19

18

17

16

15

14

13

C

OSC

BOOST

SW

RUN/SS

LTC1736CG

LTC1736IG

3

I

TH

4

V

IN

FCB

SGND

5

INTV

CC

6

BG

PGOOD

–

7

PGND

SENSE

+

8

EXTV

CC

SENSE

9

VIDV

CC

V

FB

10

11

12

VID4

VID3

VID2

V

OSENSE

VID0

VID1

G PACKAGE

24-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 110°C/W

Consult factory for Military grade parts.

ELECTRICAL CHARACTERISTICS ^The● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V, V_RUN/SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loop

V

Output Voltage Set Accuracy

(Note 3) See Table 1

●

1

%

OSENSE

∆V

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

= 3.6V to 30V (Note 3)

IN

0.001

0.02

%/V

LINEREG

(Note 3)

Measured in Servo Loop; V = 0.7V

Measured in Servo Loop; V = 2V

LOADREG

●

0.1

– 0.1

0.3

–0.3

%

ITH

g

Transconductance Amplifier g

Forced Continuous Threshold

Forced Continuous Current

1.3

0.8

mmho

m

V

●

0.76

0.84

–0.3

0.88

V

µA

V

FCB

I

V

= 0.85V

FCB

– 0.17

0.86

FCB

V

Feedback Overvoltage Lockout

OVL

I

Input DC Supply Current

Normal Mode

(Note 4)

Q

450

15

µA

Shutdown

V

= 0V

25

1.9

4.5

RUN/SS

V

Run Pin Start Threshold

, Ramping Positive

= 0V

1.0

1.5

4.1

–1.2

2

V

RUN/SS

SCL

Run Pin Begin Latchoff Threshold

Soft-Start Charge Current

RUN/SS Discharge Current

I

–0.7

0.5

µA

Soft Short Condition, V = 0.5V,

4

FB

V

= 4.5V

RUN/SS

UVLO

∆V

Undervoltage Lockout

Measured at V Pin (V Ramping Down)

●

3.5

75

3.9

85

V

mV

µA

IN

Maximum Current Sense Threshold

SENSE Pins Total Source Current

Minimum On-Time

V

= 0.7V

FB

60

SENSE(MAX)

–

+

I

t

= V

= 0.8V

60

80

SENSE

ON(MIN)

SENSE

Tested with a Square Wave (Note 8)

160

200

ns

TG Transition Time:

Rise Time

Fall Time

(Note 9)

TG t

C

= 3300pF

50

90

ns

r

f

LOAD

2

LTC1736

ELECTRICAL CHARACTERISTICS ^The● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V, V_RUN/SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

BG Transition Time:

Rise Time

Fall Time

(Note 9)

BG t

C

= 3300pF

50

40

90

80

ns

r

f

LOAD

TG/BG T1D

Top Gate Off to Synchronous

Gate-On Delay Time

C

= 3300pF Each Driver

100

ns

LOAD

TG/BG T2D

Synchronous Gate Off to Top

Gate-On Delay Time

C

= 3300pF Each Driver

70

ns

LOAD

Internal V Regulator

CC

V

Internal V Voltage

6V < V < 30V, V = 4V

EXTVCC

5.0

4.5

5.2

0.2

130

4.7

0.2

5.4

1

V

%

INTVCC

CC

IN

Internal V Load Regulation

I

= 0mA to 20mA, V

= 4V

EXTVCC

LDO(INT)

LDO(EXT)

EXTVCC

CC

EXTV Drop Voltage

= 20mA, V

= 5V

200

mV

V

CC

EXTVCC

EXTV Switchover Voltage

= 20mA, EXTV Ramping Positive

●

CC

EXTV Hysteresis

V

EXTVCC(HYS)

CC

Oscillator

f

Oscillator Frequency

(Note 5), C

= 43pF

OSC

265

0.9

300

1.3

1.2

335

kHz

V

OSC

f /f

Maximum Sync Frequency Ratio

FCB Pin Threshold For Sync

H

OSC

f

Ramping Negative

FCB(SYNC)

PGOOD Output

V

PGOOD Voltage Low

PGOOD Leakage Current

PGOOD Trip Level

I

= 2mA

= 5V

110

200

mV

PGL

PGOOD

I

V

±1

µA

PGOOD

V

with Respect to Set Output Voltage

PG

OSENSE

V

Ramping Negative

Ramping Positive

–6.0

6.0

–7.5

7.5

–9.5

9.5

%

OSENSE

VID Control

VIDV

VID Operating Supply Voltage

VID Supply Current

2.7

5.5

5

V

µA

kΩ

%

CC

I

(Note 6) VIDV = 3.3V

0.01

10

VIDVCC

CC

R

Resistance Between V and V

OSENSE FB

VFB/VOSENSE

RATIO

Resistor Ratio Accuracy

Programmed from 0.925V to 2.00V

±0.05

40

VID0 to VID4 Pull-Up Resistance

VID Input Voltage Threshold

VID Input Leakage Current

VID Pull-Up Voltage

(Note 7) V

= 0.6V

DIODE

kΩ

V

PULL-UP

IDT

V

0.4

1.0

1.6

I

(Note 7) VIDV < VID < 7V

0.01

±1

µA

VIDLEAK

CC

V

VIDV = 3.3V

2.8

4.5

V

PULL-UP

CC

VIDV = 5V

CC

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 6: With all five VID inputs floating (or tied to VIDV ) the VIDV

CC CC

current is typically <1µA. However, the VIDV current will rise and be

CC

approximately equal to the number of grounded VID input pins times

Note 2: T is calculated from the ambient temperature T and power

J

A

(VIDV – 0.6V)/40k. (See the Applications Information section for more

CC

dissipation P according to the following formulas:

D

detail.)

LTC1736CG, LTC1736IG: T = T + (P • 110°C/W)

J

A

D

Note 7: Each built-in pull-up resistor attached to the VID inputs also has a

Note 3: The LTC1736 is tested in a feedback loop that servos V to the

FB

series diode to allow input voltages higher than the VIDV supply without

CC

balance point for the error amplifier (V = 1.2V).

ITH

damage or clamping. (See the Applications Information section for more

detail.)

Note 8: The minimum on-time condition corresponds to the on inductor

Note 4: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note 5: Oscillator frequency is tested by measuring the C

charge

OSC

peak-to-peak ripple current ≥40% of I

(see minimum on-time

MAX

current (I ) and applying the formula:

OSC

considerations in the Applications Information section).

Note 9: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

–1

8.477(10¹¹)

_OSC(pF)+ 11 I_CHGI_DIS

1

f_OSC

=

+

C

3

LTC1736

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Load Current

(3 Operating Modes)

Efficiency vs Load Current

Efficiency vs Input Voltage

100

95

90

85

80

75

70

100

90

80

70

60

50

40

100

90

80

70

60

50

40

30

20

EXTV = 5V

CC

EXTV OPEN

CC

EXTV = 5V

CC

OUT

FIGURE 1

V

= 1.6V

BURST

SYNC

V

= 5V

IN

I

= 5A

OUT

CONT

V

= 15V

IN

V

= 24V

IN

I

= 0.5A

OUT

V

= 5V

IN

OUT

S

= 1.6V

R

= 0.01Ω

= 300kHz

f

O

0.1

0.01

LOAD CURRENT (A)

0

10

15

20

25

30

0.001

1

10

10mA

100mA

1A

10A

5

LOAD CURRENT (A)

INPUT VOLTAGE (V)

1736 G01

1736 G02

1736 G03

Efficiency vs Input Voltage

Load Regulation

I_THVoltage vs Load Current

2.5

2.0

1.5

1.0

100

95

90

85

80

75

70

0

–0.1

–0.2

–0.3

–0.4

EXTV OPEN

CC

OUT

FIGURE 1

FCB = 0V

V = 15V

V

= 5V

IN

OUT

V

= 1.6V

= 0.01Ω

IN

FIGURE 1

R

f

SENSE

= 300kHz

O

I

= 5A

OUT

CONTINUOUS

MODE

SYNCHRONIZED f = f

O

I

= 0.5A

OUT

Burst Mode

OPERATION

0.5

0

2

3

4

5

6

0

10

15

20

25

30

0

2

4

6

8

10

12

1

5

LOAD CURRENT (A)

INPUT VOLTAGE (V)

LOAD CURRENT (A)

1736 G06

1736 G04

1736 G05

Input and Shutdown Currents

vs Input Voltage

EXTV_CCSwitch Drop

vs INTV_CCLoad Current

INTV_CCLine Regulation

500

400

300

200

100

0

100

80

60

40

20

0

6

5

4

3

500

400

300

200

100

0

ALL VID BITS OPEN

1mA LOAD

EXTV OPEN

CC

2

1

0

SHUTDOWN

EXTV = 5V

CC

0

5

10

15

20

25

30

35

20

INPUT VOLTAGE (V)

30

35

0

5

10

15

25

0

10

20

30

40

50

INPUT VOLTAGE (V)

INTV LOAD CURRENT (mA)

CC

1736 G07

1736 G08

1736 G09

4

LTC1736

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Maximum Current Sense Threshold

vs Normalized Output Voltage

(Foldback)

Maximum Current Sense Threshold

vs V_RUN/SS

Maximum Current Sense Threshold

vs Sense Common Mode Voltage

80

76

72

68

64

60

80

70

60

50

40

30

20

10

0

80

60

40

20

V

= 1.6V

SENSE(CM)

0

50

NORMALIZED OUTPUT VOLTAGE (%)

0

1

2

3

4

5

6

0.5

COMMON MODE VOLTAGE (V)

0

25

75

100

0

1

1.5

2

V

(V)

RUN/SS

1736 G10

1736 G11

1736 G12

Maximum Current Sense Threshold

vs I_THVoltage

Maximum Current Sense Threshold

vs Temperature

V_ITHvs V_RUN/SS

90

80

2.5

2.0

1.5

1.0

80

75

70

65

V

= 0.7V

V

= 1.6V

OSENSE

SENSE(CM)

70

60

50

40

30

20

10

0

0.5

0

–10

–20

–30

60

0

0.5

1

1.5

(V)

2

2.5

0

2

3

4

5

6

1

–40 –15 10

35

60

85 110 135

V

(V)

TEMPERATURE (°C)

V

RUN/SS

ITH

1736 G13

1736 G15

1736 G18

RUN/SS Pin Current

vs Temperature

FCB Pin Current vs Temperature

Output Current vs Duty Cycle

0

–1

–2

–3

–4

–5

0

–0.2

–0.4

–0.6

–0.8

–1.0

100

80

V

= 0V

V

= 0.85V

RUN/SS

FCB

I

/I

OUT MAX

(SYNCHRONIZED)

I

/I

OUT MAX

(FREE RUN)

60

40

20

0

f

= f

O

SYNC

–40 –15 10

35

60

85 110 135

60

TEMPERATURE (°C)

135

–40 –15 10

35

85 110

0

40

60

80

100

20

TEMPERATURE (°C)

DUTY CYCLE (%)

1736 G16

1736 G17

1736 G14

5

LTC1736

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Oscillator Frequency

vs Temperature

Dynamic VID Change,

Burst Mode Operation Defeated

Burst Mode Operation Enabled

300

290

280

270

260

250

FCB = PGOOD

C

OSC

= 47pF

FCB = 0V

V_OUT

100mV/DIV

I_L

5A/DIV

PGOOD

5V/DIV

PGOOD

5V/DIV

1736 G20

1736 G21

20µs/DIV

–40 –15 10

35

60

85 110 135

TEMPERATURE (°C)

1736 G19

V_OUT(RIPPLE)

(Burst Mode Operation)

Start-Up

V_OUT(RIPPLE)(Synchronized)

I_LOAD= 10mA

I_LOAD= 50mA

V_OUT

1V/DIV

V_OUT

10mV/DIV

V_OUT

20mV/DIV

V_RUN/SS

5V/DIV

I_L

5A/DIV

I_L

5A/DIV

1736 G22

1736 G23

1736 G24

5ms/DIV

10µs/DIV

50µs/DIV

V_IN= 15V

EXT SYNC (f = f_O)

FCB = 5V

V_OUT= 1.6V

V

_IN= 15V

V_IN= 15V

R

_LOAD= 0.16Ω

V_OUT= 1.6V

Load Step

(Burst Mode Operation)

V_OUT(RIPPLE)

(Burst Mode Operation)

Load Step (Continuous Mode)

I_LOAD= 1.5A

V_OUT

20mV/DIV

V_OUT

50mV/DIV

V_OUT

50mV/DIV

I_L

5A/DIV

1736 G25

1736 G26

1736 G27

5µs/DIV

10µs/DIV

FCB = 5V

V_IN= 15V

V_OUT= 1.6V

10mA TO

11A LOAD STEP

FCB = 5V

V_IN= 15V

V_OUT= 1.6V

0A TO

11A LOAD STEP

FCB = 0V

V_IN= 15V

V_OUT= 1.6V

6

LTC1736

U

PI FU CTIO S

VID0 to VID4 (Pins 11 to 15): Digital Inputs for controlling

the output voltage from 0.925V to 2.0V. Table 1 specifies

the V_OSENSEvoltages for the 32 combinations of digital

inputs. The LSB (VID0) represents 50mV increments in

the upper voltage range (2.00V to 1.30V) and 25mV

increments in the lower voltage range (1.275V to 0.925V).

Logic Low = GND, Logic High = VIDV_CCor Float.

C_OSC(Pin 1): External capacitor C_OSCfrom this pin to

ground sets the operating frequency.

RUN/SS (Pin 2): Combination of Soft-Start and Run

Control Inputs. A capacitor to ground at this pin sets the

ramptimetofulloutputcurrent. Thetimeisapproximately

1.25s/µF. Forcing this pin below 1.5V causes the device to

be shut down. In shutdown all functions are disabled.

Latchoff overcurrent protection is also invoked via this pin

as described in the Applications Information section.

VIDV_CC(Pin 16): VID Input Supply Voltage. Can range

from 2.7V to 7V. Typically this pin is tied to INTV_CC.

EXTV_CC(Pin 17): Input to the Internal Switch Connected

to INTV_CC. This switch closes and supplies V_CCpower

whenever EXTV_CCis higher than 4.7V. See EXTV_CCcon-

nection in the Applications Information section. Do not

exceed 7V to this pin and ensure EXTV_CC≤ V_IN.

I_TH(Pin 3): Error Amplifier Compensation Point. The

current comparator threshold increases with this control

voltage. Nominal voltage range for this pin is 0V to 2.4V.

FCB (Pin 4): Forced Continuous/Synchronization Input.

Tie this pin to ground for continuous synchronous opera-

tion, to a resistive divider from the secondary output when

using a secondary winding, or to INTV_CCto enable Burst

Modeoperationatlowloadcurrents.Clockingthispinwith

a signal above 1.5V_P-Pdisables Burst Mode operation but

allows cycle skipping at low load currents and synchro-

nizes the internal oscillator with the external clock.

PGND (Pin 18): Driver Power Ground. This pin connects

to the source of the bottom N-channel MOSFET, the anode

of the Schottky diode and the (–) terminal of C_IN.

BG (Pin 19): High Current Gate Drive for Bottom

N-Channel MOSFET. Voltage swing at this pin is from

ground to INTV_CC

.

SGND (Pin 5): Small-Signal Ground. All small-signal

components such as C_OSC, C_SSplus the loop compensa-

tion resistors and capacitor(s) should single-point tie to

this pin. This pin should, in turn, connect to PGND.

INTV_CC(Pin20):OutputoftheInternal5.2VRegulatorand

EXTV_CCSwitch. The driver and control circuits are pow-

ered from this voltage. Decouple to power ground with a

1µF ceramic capacitor placed directly adjacent to the IC

together with a minimum of 4.7µF tantalum or other low

ESR capacitor.

PGOOD (Pin 6): Open-Drain Logic Output. PGOOD is

pulled to ground when the voltage on the V_OSENSEpin is

not within ±7.5% of its set point.

SENSE^–(Pin 7): The (–) Input to the Current Comparator.

V_IN(Pin 21): Main Supply Pin. This pin must be closely

decoupled to power ground.

SENSE⁺(Pin 8): The (+) Input to the Current Comparator.

Built-in offsets between SENSE^–and SENSE⁺pins in

conjunction with R_SENSEset the current trip threshold.

SW (Pin 22): Switch Node Connection to Inductor and

Bootstrap Capacitor. Voltage swing at this pin is from a

Schottky diode (external) voltage drop below ground to

V_IN.

V_FB(Pin 9): Divided Down V_OSENSEVoltage Feeding the

Error Amplifier of the Regulator. The VID inputs program

a resistive divider between V_OSENSEand SGND; the tap

pointonthedividerisV_FB. ThevoltageonV_FBis0.8Vwhen

the output is in regulation. This pin can be bypassed to

SGND with 50pF to 100pF.

BOOST (Pin 23): Supply to Topside Floating Driver. The

bootstrap capacitor is returned to this pin. Voltage swing

at this pin is from a diode drop below INTV_CCto V_IN

INTV_CC.

+

TG (Pin 24): High Current Gate Drive for Top N-Channel

MOSFET. This is the output of a floating driver with a

voltage swing equal to INTV_CCsuperimposed on the

switch node voltage SW.

V_OSENSE(Pin 10): Receives the remotely sensed feedback

voltage from the output.

7

LTC1736

U

U W

FU CTIO AL DIAGRA

V

IN

R4

R3

+

V

21

IN

C

IN

C

OSC

UVL

TOP

0.8V

REF

INTV

CC

PGOOD

0.17µA

FCB

4

6

1

OSC

FC

D

B

C

BOOST

23

F

–

+

SYNC

OSC

V

SEC

+

1.2V

0.8V

C

B

TG

24

FORCE BOT

DROP

OUT

–

+

SW

22

C

SEC

DET

BOT

0.74V

SWITCH

LOGIC

OV

S

R

D

1

TOP ON

0.55V

+

–

•

Q

B

+

–

0.86V

•

V

OSENSE

10

2.4V

SD

IREV

2k

R2

45k

–

V

C

V

OUT

FB

Ω

10k

V

FB

0.8V

g

=1.3m

ICMP

m

–

BOT

+

–

+

9

I1

I2

–

+

–

EA

R1

OUT

+

INTV

CC

47pF

INTV

SGND

5

0.86V

V

20

3mV

IN

BURST

DISABLE

FC

SD

+

C

INTVCC

5.2V

LDO

REG

INTV

CC

RUN

SOFT

VIDV

CC

1.2µA

A

16

4(V

)

CC

FB

BUFFERED

TH

START

+

OVER-

CURRENT

I

BG

19

4.8V

+

30k

6V

–

40k

SLOPE COMP

LATCH-OFF

VID4 15

PGND

18

R

C

VID

DECODER

+

–

2

3

8

7

17

CC

RUN/SS

I

TH

SENSE

EXTV

VID3 14

VID2 13

VID1 12

VID0 11

C

SS

R

SENSE

1736 FD

U

(Refer to Functional Diagram)

OPERATIO

Main Control Loop

new load current. While the top MOSFET is off, the

bottom MOSFET is turned on until either the inductor

current starts to reverse, as indicated by current com-

parator I2, or the beginning of the next cycle.

The LTC1736 uses a constant frequency, current mode

step-down architecture. During normal operation, the

top MOSFET is turned on each cycle when the oscillator

sets the RS latch, and turned off when the main current

comparator I1 resets the RS latch. The peak inductor

currentatwhichI1resetstheRSlatchiscontrolledbythe

voltage on Pin I_TH, which is the output of the error

amplifierEA.PinV_OSENSE,describedinthePinFunctions,

allows EA to receive an output feedback voltage V_FBfrom

the internal resistive divider. When the load current

increases, itcausesaslightdecreaseinV_FBrelativetothe

0.8V reference, which in turn causes the I_THvoltage to

increase until the average inductor current matches the

The top MOSFET driver is powered from a floating

bootstrap capacitor C_B. This capacitor is normally re-

chargedfromINTV_CCthroughanexternalSchottkydiode

when the top MOSFET is turned off. As V_INdecreases

towards V_OUT, the converter will attempt to turn on the

topMOSFETcontinuously(‘’dropout’’).Adropoutcounter

detects this condition and forces the top MOSFET to turn

off for about 500ns every tenth cycle to recharge the

bootstrap capacitor.

8

LTC1736

U

(Refer to Functional Diagram)

OPERATIO

The main control loop is shut down by pulling Pin 2 (RUN/

SS) low. Releasing RUN/SS allows an internal 1.2µA

current source to charge soft-start capacitor C_SS. When

C_SSreaches1.5V,themaincontrolloopisenabledwiththe

This forces continuous operation and can assist second-

ary winding regulation.

When the FCB pin is driven by an external oscillator, a low

noise cycle-skipping mode is invoked and the internal

oscillator is synchronized to the external clock by com-

parator C. In this mode the 25% minimum inductor

current clamp is removed, providing constant frequency

discontinuous operation over the widest possible output

current range. This constant frequency operation is not

quite as efficient as Burst Mode operation, but provides a

lower noise, constant frequency spectrum.

I

_THvoltageclampedatapproximately30%ofitsmaximum

value. As C_SScontinues to charge, I_THis gradually re-

leased allowing normal operation to resume. If V_OUThas

not reached 70% of its final value when C_SShas charged

to 4.1V, latchoff can be invoked as described in the

Applications Information section.

The internal oscillator can be synchronized to an external

clock applied to the FCB pin and can lock to a frequency

between 90% and 130% of its nominal rate set by capaci-

The FCB pin is tied to ground when forced continuous

operation is desired. This operation is the least efficient

mode, but is desirable in certain applications. The output

can source or sink current in this mode. When sinking

current while in forced continuous operation, current will

be forced back into the main power supply potentially

boosting the input supply to dangerous voltage levels—

BEWARE.

tor C_OSC

.

An overvoltage comparator OV guards against transient

overshoots (>7.5%) as well as other more serious condi-

tions that may overvoltage the output. In this case, the top

MOSFETisturnedoffandthebottomMOSFETisturnedon

until the overvoltage condition is cleared.

Foldback current limiting for an output shorted to ground

is provided by amplifier A. As V_FBdrops below 0.6V, the

buffered I_THinput to the current comparator is gradually

pulled down to a 0.86V clamp. This reduces peak inductor

current to about 1/4 of its maximum value.

Foldback Current, Short-Circuit Detection

and Short-Circuit Latchoff

The RUN/SS capacitor, C_SS, is used initially to limit the

inrush current of the switching regulator. After the con-

troller has been started and been given adequate time to

charge up the output capacitors and provide full load

current, C_SSis used as a short-circuit time-out circuit. If

the output voltage falls to less than 70% of its nominal

outputvoltage, C_SSbeginsdischargingontheassumption

that the output is in an overcurrent and/or short-circuit

condition. If the condition lasts for a long enough period

as determined by the size of the C_SS, the controller will be

shut down until the RUN/SS pin voltage is recycled. This

built-in latchoff can be overridden by providing a current

>5µA at a compliance of 5V to the RUN/SS pin. This

currentshortensthesoft-startperiodbutalsopreventsnet

discharge of C_SSduring an overcurrent and/or short-

circuit condition. Foldback current limiting is activated

when the output voltage falls below 70% of its nominal

level whether or not the short-circuit latchoff circuit is

enabled.

Low Current Operation

The LTC1736 has three low current modes controlled by

the FCB pin. Burst Mode operation is selected when the

FCB pin is above 0.8V (typically tied to INTV_CC). During

Burst Mode operation, if the error amplifier drives the I_TH

voltage below 0.86V, the buffered I_THinput to the current

comparatorwillbeclampedat0.86V. Theinductorcurrent

peak is then held at approximately 20mV/R_SENSE(about 1/

4 of maximum output current). If I_THthen drops below

0.5V, the Burst Mode comparator B will turn off both

MOSFETs to maximize efficiency. The load current will be

supplied solely by the output capacitor until I_THrises

above the 60mV hysteresis of the comparator and switch-

ing is resumed. Burst Mode operation is disabled by

comparator F when the FCB pin is brought below 0.8V.

9

LTC1736

U

(Refer to Functional Diagram)

OPERATIO

INTV_CC/EXTV_CCPower

VID Control

Power for the top and bottom MOSFET drivers and most

of the internal circuitry of the LTC1736 is derived from the

INTV_CCpin. When the EXTV_CCpin is left open, an internal

5.2V low dropout regulator supplies the INTV_CCpower

from V_IN. If EXTV_CCis raised above 4.7V, the internal

regulator is turned off and an internal switch connects

EXTV_CCto INTV_CC. This allows a high efficiency source,

such as the notebook main 5V system supply or a second-

ary output of the converter itself, to provide the INTV_CC

power. Voltages up to 7V can be applied to EXTV_CCfor

additional gate drive capability.

Bits VID0 to VID4 are logic inputs setting the output volt-

age using an internal 5-bit DAC as a feedback resistive

voltage divider. The output voltage can be set in 50mV or

25mV increments from 0.925V to 2.0V according to

Table 1. Pins VID0 to VID4 are internally pulled up to

VIDV_CC.

PGOOD

A window comparator monitors the output voltage and its

open-drain output is pulled low when the divided down

outputvoltageisnotwithin±7.5%ofthereferencevoltage

of 0.8V.

To provide clean start-up and to protect the MOSFETs,

undervoltage lockout is used to keep both MOSFETs off

until the input voltage is above 3.5V.

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APPLICATIO S I FOR ATIO

The basic LTC1736 application circuit is shown in

Figure 1 on the first page of this data sheet. External

component selection is driven by the load requirement

and begins with the selection of R_SENSE. Once R_SENSEis

known, C_OSCand L can be chosen. Next, the power MOS-

FETsandD1areselected. Theoperatingfrequencyandthe

inductor are chosen based largely on the desired amount

of ripple current. Finally, C_INis selected for its ability to

handle the large RMS current into the converter and C_OUT

is chosen with low enough ESR to meet the output voltage

ripple and transient specifications. The circuit shown in

Figure 1 can be configured for operation up to an input

voltage of 28V (limited by the external MOSFETs).

50mV

I_MAX

R_SENSE

=

C_OSCSelection for Operating Frequency

and Synchronization

The choice of operating frequency and inductor value is a

trade-off between efficiency and component size. Low

frequency operation improves efficiency by reducing

MOSFET switching losses, both gate charge loss and

transition loss. However, lower frequency operation re-

quires more inductance for a given amount of ripple

current.

TheLTC1736usesaconstant-frequencyarchitecturewith

the frequency determined by an external oscillator capaci-

tor C_OSC. Each time the topside MOSFET turns on, the

voltage on C_OSCis reset to ground. During the on-time

C_OSCischargedbyafixedcurrent.Whenthevoltageonthe

capacitor reaches 1.19V, C_OSCis reset to ground. The

process then repeats.

R_SENSESelection For Output Current

R_SENSEis chosen based on the required output current.

The LTC1736 current comparator has a maximum thresh-

old of 75mV/R_SENSEand an input common mode range of

SGND to 1.1(INTV_CC). The current comparator threshold

sets the peak of the inductor current, yielding a maximum

average output current I_MAXequal to the peak value less

half the peak-to-peak ripple current, ∆I_L.

The value of C_OSCis calculated from the desired operating

frequency assuming no external clock input on the FCB

pin:

Allowing a margin for variations in the LTC1736 and

external component values yields:

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APPLICATIO S I FOR ATIO

cyclestorechargethebootstrapcapacitor.Thisminimizes

audiblenoisewhilemaintainingreasonablyhighefficiency.

1.61(10⁷)

Frequency

C_OSC(pF) =

– 11

Inductor Value Calculation

A graph for selecting C_OSCversus frequency is given in

Figure 2. The maximum recommended switching fre-

quency is 550kHz .

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because of

MOSFET gate-charge losses. In addition to this basic

trade-off, the effect of inductor value on ripple current and

low current operation must also be considered.

The internal oscillator runs at its nominal frequency (f_O)

when the FCB pin is pulled high to INTV_CCor connected to

ground. Clocking the FCB pin above and below 0.8V will

cause the internal oscillator to lock to an external clock

signalwithafrequencybetween0.9f_Oand1.3f_O. Theclock

high level must exceed 1.3V for at least 0.3µs, and the

clock low level must be less than 0.3V for at least 0.3µs.

The top MOSFET turn-on will synchronize with the rising

edge of the external clock.

Theinductorvaluehasadirecteffectonripplecurrent.The

inductor ripple current ∆I_Ldecreases with higher induc-

tance or frequency and increases with higher V_INor V_OUT

:

Attempting to synchronize to too high an external fre-

quency (above 1.3f_O) can result in inadequate slope com-

pensation and possible loop instability at high duty cycles.

If this condition exists simply lower the value of C_OSCso

f_EXT= f_Oaccording to Figure 2.

1

V

OUT

V

IN

∆I =

V

1–

L

OUT

(f)(L)

Accepting larger values of ∆I_Lallows the use of low

inductances, but results in higher output voltage ripple

and greater core losses. A reasonable starting point for

setting ripple current is∆I_L= 0.3 to 0.4(I_MAX). Remember,

the maximum ∆I_Loccurs at the maximum input voltage.

100.0

87.5

75.0

62.5

50.0

37.5

25.0

12.5

0

The inductor value also has an effect on low current

operation. The transition to low current operation begins

when the inductor current reaches zero while the bottom

MOSFET is on. Burst Mode operation begins when the

averageinductorcurrentrequiredresultsinapeakcurrent

below 25% of the current limit determined by R_SENSE

.

0

100

200

300

400

500

600

Lower inductor values (higher ∆I_L) will cause this to occur

at higher load currents, which can cause a dip in efficiency

in the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to decrease.

OPERATING FREQUENCY (kHz)

1736 F02

Figure 2. Timing Capacitor Value

When synchronized to an external clock, Burst Mode op-

eration is disabled but the inductor current is not allowed

to reverse. The 25% minimum inductor current clamp

present in Burst Mode operation is removed, providing

constantfrequencydiscontinuousoperationoverthewid-

est possible output current range. In this mode the

synchronous MOSFET is forced on once every 10 clock

Inductor Core Selection

Once the value for L is known, the type of inductor must

be selected. High efficiency converters generally cannot

afford the core loss found in low cost powdered iron

cores, forcing the use of more expensive ferrite,

11

LTC1736

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APPLICATIO S I FOR ATIO

molypermalloy or Kool Mµ^®cores. Actual core loss is

independent of core size for a fixed inductor value, but it

is very dependent on the inductance selected. As induc-

tance increases, core losses go down. Unfortunately,

increased inductance requires more turns of wire and

therefore copper losses will increase.

V_OUT

Main SwitchDuty Cycle =

V

IN

V – V_OUT

IN

Synchronous SwitchDuty Cycle =

V

IN

The MOSFET power dissipations at maximum output

current are given by:

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

2

V_OUT

P_MAIN

=

I

1+ δ R

+

(

_MAX) (

)

DS(ON)

V

IN

2

k V

I

C

f

(

_IN) (_MAX)( _RSS)( )

2

V – V_OUT

IN

P_SYNC

=

I

1+ δ R

(

_MAX) (

)

DS(ON)

V

IN

Molypermalloy (from Magnetics, Inc.) is a very good, low

losscorematerialfortoroids,butitismoreexpensivethan

ferrite. A reasonable compromise from the same manu-

facturer is Kool Mµ. Toroids are very space efficient,

especially when you can use several layers of wire. Be-

cause they generally lack a bobbin, mounting is more

difficult. However, designsforsurfacemountareavailable

that do not increase the height significantly.

where δ is the temperature dependency of R_DS(ON)and k

is a constant inversely related to the gate drive current.

Both MOSFETs have I²R losses while the topside

N-Channel equation includes an additional term for tran-

sition losses, which are highest at high input voltages. For

V_IN< 20V the high current efficiency generally improves

with larger MOSFETs, while for V_IN> 20V the transition

losses rapidly increase to the point that the use of a higher

R_DS(ON)device with lower C_RSSactually provides higher

efficiency. The synchronous MOSFET losses are greatest

athighinputvoltageorduringashortcircuitwhentheduty

cycle in this switch is nearly 100%.

Power MOSFET and D1 Selection

Two external power MOSFETs must be selected for use

with the LTC1736: An N-channel MOSFET for the top

(main) switch and an N-channel MOSFET for the bottom

(synchronous) switch.

The term (1 + δ) is generally given for a MOSFET in the

form of a normalized R_DS(ON)vs Temperature curve, but

δ = 0.005/°C can be used as an approximation for low

voltageMOSFETs.C_RSSisusuallyspecifiedintheMOSFET

characteristics. The constant k = 1.7 can be used to

estimate the contributions of the two terms in the main

switch dissipation equation.

The peak-to-peak gate drive levels are set by the INTV_CC

voltage. Thisvoltageistypically5.2Vduringstart-up. (See

EXTV_CCPinConnection.)Consequently,logic-levelthresh-

old MOSFETs must be used in most LTC1736 applica-

tions. The only exception is when low input voltage is

expected (V_IN< 5V); then, sublogic level threshold

MOSFETs (V_GS(TH)< 3V) should be used. Pay close

attention to the BV_DSSspecification for the MOSFETs as

well; most of the logic level MOSFETs are limited to 30V or

less.

The Schottky diode D1 shown in Figure 1 conducts during

the dead-time between the conduction of the two power

MOSFETs. This prevents the body diode of the bottom

MOSFET from turning on and storing charge during the

dead-time, which could cost as much as 1% in efficiency.

A 3A Schottky is generally a good size for 10A to 12A

regulators due to the relatively small average current.

SelectioncriteriaforthepowerMOSFETsincludethe“ON”

resistance R_DS(ON), reverse transfer capacitance C_RSS

,

input voltage and maximum output current. When the

LTC1736 is operating in continuous mode the duty cycles

for the top and bottom MOSFETs are given by:

Kool Mµ is a registered trademark of Magnetics, Inc.

12

LTC1736

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APPLICATIO S I FOR ATIO

Largerdiodescanresultinadditionaltransitionlossesdue

to their larger junction capacitance. The diode may be

omitted if the efficiency loss can be tolerated.

C_OUTrequired ESR < 2.2 R_SENSE

C_OUT> 1/(8fR_SENSE

)

ThefirstconditionrelatestotheripplecurrentintotheESR

of the output capacitance while the second term guaran-

tees that the output capacitance does not significantly

discharge during the operating frequency period due to

ripple current. The choice of using smaller output capaci-

tance increases the ripple voltage due to the discharging

term but can be compensated for by using capacitors of

very low ESR to maintain the ripple voltage at or below

50mV. The I_THpin OPTI-LOOP compensation compo-

nents can be optimized to provide stable, high perfor-

mancetransientresponseregardlessoftheoutputcapaci-

tors selected.

C_INSelection

In continuous mode, the source current of the top

N-channel MOSFET is a square wave of duty cycle V_OUT

/

V_IN. To prevent large voltage transients, a low ESR input

capacitor sized for the maximum RMS current must be

used. The maximum RMS capacitor current is given by:

1/2

V_OUT

V

IN

V_OUT

I_RMSI_O(MAX)

– 1

V

IN

This formula has a maximum at V_IN= 2V_OUT, where I_RMS

= I_OUT/2. This simple worst-case condition is commonly

usedfordesignbecauseevensignificantdeviationsdonot

offer much relief. Note that capacitor manufacturers’

ripple current ratings are often based on only 2000 hours

of life. This makes it advisable to further derate the

capacitor, or to choose a capacitor rated at a higher

temperaturethanrequired.Severalcapacitorsmayalsobe

paralleled to meet size or height requirements in the

design. Always consult the manufacturer if there is any

question.

The selection of output capacitors for CPU or other appli-

cations with large load current transients is primarily

determined by the voltage tolerance specifications of the

load. The resistive component of the capacitor, ESR,

multiplied by the load current change plus any output

voltage ripple must be within the voltage tolerance of the

load (CPU).

The required ESR due to a load current step is:

R_ESR< ∆V/∆I

where∆Iisthechangeincurrentfromfullloadtozeroload

(orminimumload)and∆Vistheallowedvoltagedeviation

(not including any droop due to finite capacitance).

C_OUTSelection

The selection of C_OUTis primarily determined by the

effectiveseriesresistance(ESR)tominimizevoltageripple.

The output ripple (∆V_OUT) in continuous mode is deter-

mined by:

The amount of capacitance needed is determined by the

maximum energy stored in the inductor. The capacitance

mustbesufficienttoabsorbthechangeininductorcurrent

when a high current to low current transition occurs. The

oppositeloadcurrenttransitionisgenerallydeterminedby

the control loop OPTI-LOOP components, so make sure

not to over compensate and slow down the response. The

minimum capacitance to assure the inductors’ energy is

adequately absorbed is:

1

∆V_OUT≈ ∆I_LESR +

8fC_OUT

Where f = operating frequency, C_OUT= output capaci-

tance, and ∆I_L= ripple current in the inductor. The output

ripple is highest at maximum input voltage since ∆I_L

increases with input voltage. Typically, once the ESR

requirement for C_OUThas been met, the RMS current

rating generally far exceeds the I_RIPPLE(P-P)requirement.

With ∆I_L= 0.3I_OUT(MAX)the output ripple will be less than

50mV at max V_INassuming:

L ∆I ²

( )

C_OUT

>

2 ∆V V_OUT

(

)

where ∆I is the change in load current.

13

LTC1736

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APPLICATIO S I FOR ATIO

Manufacturers such as Nichicon, United Chemicon and

Sanyo can be considered for high performance through-

hole capacitors. The OS-CON semiconductor dielectric

capacitor available from Sanyo has the lowest (ESR)(size)

product of any aluminum electrolytic at a somewhat

higher price. An additional ceramic capacitor in parallel

with OS-CON capacitors is recommended to reduce the

inductance effects.

INTV_CCRegulator

An internal P-channel low dropout regulator produces the

5.2V supply that powers the drivers and internal circuitry

within the LTC1736. The INTV_CCpin can supply a maxi-

mum RMS current of 50mA and must be bypassed to

ground with a minimum of 4.7µF tantalum, 10µF special

polymer or low ESR type electrolytic capacitor. Good

bypassingisrequiredtosupplythehightransientcurrents

required by the MOSFET gate drivers.

In surface mount applications multiple capacitors may

need to be used in parallel to meet the ESR, RMS current

handling, and load step requirements of the application.

Aluminum electrolytic, dry tantalum and special polymer

capacitors are available in surface mount packages. Spe-

cial polymer surface mount capacitors offer very low ESR

but have much lower capacitive density per unit volume

than other capacitor types. These capacitors offer a very

cost-effective output capacitor solution and are an ideal

choice when combined with a controller having high loop

bandwidth. Tantalum capacitors offer the highest capaci-

tance density and are often used as output capacitors for

switching regulators having controlled soft-start. Several

excellent surge-tested choices are the AVX TPS, AVX

TPSV or the KEMET T510 series of surface mount

tantalums, available in case heights ranging from 2mm to

4mm. Aluminum electrolytic capacitors can be used in

cost-driven applications providing that consideration is

given to ripple current ratings, temperature and long-term

reliability.Atypicalapplicationwillrequireseveraltomany

aluminum electrolytic capacitors in parallel. A combina-

tion of the above mentioned capacitors will often result in

maximizing performance and minimizing overall cost.

Other capacitor types include Nichicon PL series, NEC

Neocap, Panasonic SP and Sprague 595D series. Consult

manufacturers for other specific recommendations.

HigherinputvoltageapplicationsinwhichlargeMOSFETs

are being driven at high frequencies may cause the

maximumjunctiontemperatureratingfortheLTC1736to

be exceeded. The system supply current is normally

dominated by the gate charge current. Additional loading

of INTV_CCalso needs to be taken into account for the

power dissipation calculations. The total INTV_CCcurrent

can be supplied by either the 5.2V internal linear regulator

or by the EXTV_CCinput pin. When the voltage applied to

the EXTV_CCpin is less than 4.7V, all of the INTV_CCcurrent

is supplied by the internal 5.2V linear regulator. Power

dissipationfortheICinthiscaseishighest:(V_IN)(I_INTVCC),

and overall efficiency is lowered. The gate charge is

dependent on operating frequency as discussed in the

Efficiency Considerations section. The junction tempera-

ture can be estimated by using the equations given in

Note 2 of the Electrical Characteristics. For example, the

LTC1736Gislimitedtolessthan17mAfroma30Vsupply

when not using the EXTV_CCpin as follows:

T_J= 70°C + (17mA)(30V)(110°C/W) = 126°C

UseoftheEXTV_CCinputpinreducesthejunctiontempera-

ture to:

T_J= 70°C + (17mA)(5V)(110°C/W) = 79°C

To prevent maximum junction temperature from being

exceeded, the input supply current must be checked

operating in continuous mode at maximum V_IN.

Like all components, capacitors are not ideal. Each ca-

pacitor has its own benefits and limitations. Combina-

tions of different capacitor types have proven to be a very

cost effective solution. Remember also to include high

frequency decoupling capacitors. They should be placed

as close as possible to the power pins of the load. Any

inductance present in the circuit board traces negates

their usefulness.

EXTV_CCConnection

The LTC1736 contains an internal P-channel MOSFET

switch connected between the EXTV_CCand INTV_CCpins.

Whenever the EXTV_CCpin is above 4.7V the internal 5.2V

14

LTC1736

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APPLICATIO S I FOR ATIO

regulator shuts off, the switch closes and INTV_CCpower is

supplied via EXTV_CCuntil EXTV_CCdrops below 4.5V. This

allows the MOSFET gate drive and control power to be

derived from the output or other external source during

normal operation. When the output is out of regulation

(start-up,shortcircuit)powerissuppliedfromtheinternal

regulator. Do not apply greater than 7V to the EXTV_CCpin

and ensure that EXTV_CC< V_IN.

Output Voltage Programming

Theoutputvoltageisdigitallysettolevelsbetween0.925V

and 2.00V using the voltage identification (VID) inputs

VID0 to VID4. The internal 5-bit DAC configured as a

precision resistive voltage divider sets the output voltage

in 50mV or 25mV increments according to Table 1.

The VID codes (00000-11110) are engineered to be com-

patible with Intel Mobile Pentium II and Pentium III pro-

cessor specifications for output voltages from 0.925V to

2.00V.

Significant efficiency gains can be realized by powering

INTV_CCfrom the output, since the V_INcurrent resulting

from the driver and control currents will be scaled by a

factor of (Duty Cycle)/(Efficiency). For 5V regulators this

The LSB (VID0) represents 50mV increments in the upper

voltage range (1.30V to 2.00V) and 25mV increments in

the lower voltage range (0.925V to 1.275V). The MSB is

VID4. When all bits are low, or grounded, the output

voltage is 2.00V.

simply means connecting the EXTV_CCpin directly to V_OUT

.

However, for VID programmed regulators and other lower

voltage regulators, additional circuitry is required to de-

rive INTV_CCpower from the output.

Between the V_FBpin and ground is a variable resistor, R1,

whose value is controlled by the five input pins (VID0 to

VID4). Another resistor, R2, between the V_OSENSEand the

V_FBpins completes the resistive divider. The output volt-

age is thus set by the ratio of (R1 + R2) to R1.

The following list summarizes the three possible connec-

tions for EXTV_CC:

1. EXTV_CCLeftOpen(orGrounded).ThiswillcauseINTV_CC

tobepoweredfromtheinternal5.2Vregulatorresulting

in a low current efficiency penalty of up to 10% at high

input voltages.

The LTC1736 has remote sense capability. The top of the

internal resistive divider is connected to V_OSENSE, and it is

referenced to the SGND pin. This allows a kelvin connec-

tionforremotelysensingtheoutputvoltagedirectlyacross

the load, eliminating any PC board trace resistance errors.

2. EXTV_CCConnectedtoanExternalSupply(thisoptionis

the most likely used). If an external supply is available

in the 5V to 7V range, such as notebook main 5V

systempower, itmaybeusedtopowerEXTV_CCprovid-

ing it is compatible with the MOSFET gate drive

requirements. This is the typical case as the 5V power

isalmostalwayspresentandisderivedbyanotherhigh

efficiency regulator.

Each VID digital input is pulled up by a 40k resistor in

series with a diode from VIDV_CC. Therefore, it must be

grounded to get a digital low input, and can be either

floated or connected to VIDV_CCto get a digital high input.

The series diode is used to prevent the digital inputs from

being damaged or clamped if they are driven higher than

VIDV_CC. The digital inputs accept CMOS voltage levels.

3. EXTV_CCConnected to an Output-Derived Boost Net-

work. For this low output voltage regulator, efficiency

gains can still be realized by connecting EXTV_CCto an

output-derivedvoltagethathasbeenboostedtogreater

than 4.7V. This can be done with either the inductive

boost winding or the capacitive charge pump circuits.

Refer to the LTC1735 data sheet for details. The charge

pump has the advantage of simple magnetics.

VIDV_CCis the supply voltage for the VID section. It is

normally connected to INTV_CCbut can be driven from

other sources such as a 3.3V supply. If it is driven from

another source, that source MUST be in the range of 2.7V

to 5.5V and MUST be alive prior to enabling the LTC1736.

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Table 1. VID Output Voltage Programming

Topside MOSFET Driver Supply (C_B, D_B)

VID4

0

1

VID3

0

1

0

1

VID2

0

1

0

1

0

1

0

1

VID1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

V

(V)

OUT

AnexternalbootstrapcapacitorC_BconnectedtotheBOOST

pinsuppliesthegatedrivevoltageforthetopsideMOSFET.

Capacitor C_Bin the Functional Diagram is charged though

external diode D_Bfrom INTV_CCwhen the SW pin is low.

NotethatthevoltageacrossC_Bisaboutadiodedropbelow

INTV_CC. When the topside MOSFET is to be turned on, the

driver places the C_Bvoltage across the gate-source of the

MOSFET. This enhances the MOSFET and turns on the

topside switch. The switch node voltage SW rises to V_IN

and the BOOST pin rises to V_IN+ INTV_CC. The value of the

boost capacitor C_Bneeds to be 100 times greater than the

total input capacitance of the topside MOSFET. In most

applications 0.1µF to 0.33µF is adequate. The reverse

breakdown on D_Bmust be greater than V_{IN(MAX) .}

2.000V

1.950V

1.900V

1.850V

1.800V

1.750V

1.700V

1.650V

1.600V

1.550V

1.500V

1.450V

1.400V

1.350V

1.300V

*

When adjusting the gate drive level, the final arbiter is the

total input current for the regulator. If you make a change

and the input current decreases, then you improve the

efficiency. If there is no change in input current, then there

is no change in efficiency.

1.275V

1.250V

1.225V

1.200V

1.175V

1.150V

1.125V

1.100V

1.075V

1.050V

1.025V

1.000V

0.975V

0.950V

0.925V

**

SENSE⁺/SENSE^–Pins

The common mode input range of the current comparator

is from 0V to 1.1(INTV_CC). Continuous linear operation is

guaranteed throughout this range allowing output volt-

ages anywhere from 0.8V to 7V (although the VID control

pins only program a 0.925V to 2.00V output range). A

differential NPN input stage is used and is biased with

internal resistors from an internal 2.4V source as shown

in the Functional Diagram. This causes current to flow out

of both sense pins to the main output. This forces a

minimum load current which is sunk by the internal

resistive divider resistors R1 and R2. The maximum

current flowing out of the sense pins is:

+

–

I_SENSE+ I_SENSE= (2.4V – V_OUT)/24k

Remembertotakethiscurrentintoaccountifresistanceis

placed in series with the sense pins for filtering.

Note: *, ** represents codes without a defined output voltage as specified in

Intel specifications. The LTC1736 interprets these codes as valid inputs and

produces output voltages as follows: [01111] = 1.250V, [11111] = 0.900V.

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Soft-Start/Run Function

Fault Conditions: Overcurrent Latchoff

The RUN/SS pin is a multipurpose pin that provides a soft-

start function and a means to shut down the LTC1736.

Soft-start reduces surge currents from V_INby gradually

increasing the controller’s current limit I_TH(MAX). This pin

can also be used for power supply sequencing.

The RUN/SS pin also provides the ability to shut off the

controller and latchoff when an overcurrent condition is

detected. The RUN/SS capacitor C_SSis used initially to

turn on and limit the inrush current of the controller. After

the controller has been started and given adequate time to

charge up the output capacitor and provide full load

current, C_SSis used as a short-circuit timer. If the output

voltage falls to less than 70% of its nominal output voltage

after C_SSreaches 4.1V, the assumption is made that the

output is in a severe overcurrent and/or short-circuit

condition and C_SSbegins discharging. If the condition

lasts for a long enough period as determined by the size of

C_SS, the controller will be shut down until the RUN/SS pin

voltage is recycled.

Pulling the RUN/SS pin below 1.5V puts the LTC1736 into

alowquiescentcurrentshutdown(I_Q<25µA).Thispincan

be driven directly from logic as shown in Figure 3. Releas-

ing the RUN/SS pin allows an internal 1.2µA current

source to charge up the external soft-start capacitor C_SS.

If RUN/SS has been pulled all the way to ground there is

a delay before starting of approximately:

1.5V

1.2µA

t_DELAY

=

C

_SS= 1.25s /µF C_SS

(

)

This built-in latchoff can be overridden by providing a

current >5µA at a compliance of 5V to the RUN/SS pin as

shown in Figure 4. This current shortens the soft-start

period but also prevents net discharge of the RUN/SS

capacitor during a severe overcurrent and/or short-circuit

condition. When deriving the 5µA current from V_INas in

Figure 4a, current latchoff is always defeated. A diode

connectingthispull-upresistortoINTV_CC, asinFigure4b,

eliminatesanyextrasupplycurrentduringcontrollershut-

down while eliminating the INTV_CCloading from prevent-

ingcontrollerstart-up.IfthevoltageonC_SSdoesnotexceed

4.1V, the overcurrent latch is not armed and the function

is disabled.

When the voltage on RUN/SS reaches 1.5V the LTC1736

begins operating with a current limit at approximately

25mV/R_SENSE. As the voltage on RUN/SS increases from

1.5V to 3.0V, the internal current limit is increased from

25mV/R_SENSEto 75mV/R_SENSE. The output current limit

ramps up slowly, taking an additional 1.25s/µF to reach

full current. The output current thus ramps up slowly

reducingthestartingsurgecurrentrequiredfromtheinput

power supply.

Diode D1 in Figure 3 reduces the start delay while allowing

C_SSto charge up slowly for the soft-start function. This

diode and C_SScan be deleted if soft-start is not needed.

The RUN/SS pin has an internal 6V zener clamp (See

Functional Diagram).

INTV

CC

R

SS

V

IN

3.3V OR 5V

RUN/SS

3.3V OR 5V

RUN/SS

D1

R

SS

D1

C

SS

C

SS

C

SS

C

SS

1736 F03

1736 F04

(a)

(b)

(a)

(b)

Figure 3. RUN/SS Pin Interfacing

Figure 4. RUN/SS Pin Interfacing with Latchoff Defeated

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Why should you defeat overcurrent latchoff? During the

prototypingstageofadesign,theremaybeaproblemwith

noise pickup or poor layout causing the protection circuit

to latch off. Defeating this feature will easily allow trouble-

shooting of the circuit and PC layout. The internal short-

circuit and foldback current limiting still remains active,

thereby protecting the power supply system from failure.

After the design is complete, a decision can be made

whether to enable the latchoff feature.

The resulting short circuit current is:

30mV

R_SENSE

1

2

I_SC=

+ ∆I_L(SC)

The current foldback function is always active and is not

effected by the current latchoff function.

Fault Conditions: Output Overvoltage Protection

(Crowbar)

The value of the soft-start capacitor C_SSwill need to be

scaled with output voltage, output capacitance and load

current characteristics. The minimum soft-start capaci-

tance is given by:

The output overvoltage crowbar is designed to blow a

system fuse in the input lead when the output of the

regulator rises much higher than nominal levels. This

conditioncauseshugecurrentstoflow,muchgreaterthan

in normal operation. This feature is designed to protect

against a shorted top MOSFET; it does not protect against

a failure of the controller itself.

C

_SS> (C_OUT)(V_OUT)(10^–4)(R_SENSE

)

The minimum recommended soft-start capacitor of C_SS

0.1µF will be sufficient for most applications.

=

The comparator (OV in the Functional Diagram) detects

overvoltage faults greater than 7.5% above the nominal

output voltage. When this condition is sensed, the top

MOSFET is turned off and the bottom MOSFET is forced

on. The bottom MOSFET remains on continuously for as

long as the OV condition persists; if V_OUTreturns to a safe

level, normal operation automatically resumes. Note that

VID controlled output voltage decreases may cause the

overvoltage protection to be momentarily activated. This

will not cause permanent latchoff nor will it disrupt the

desired voltage change.

Fault Conditions: Current Limit and Current Foldback

The LTC1736 current comparator has a maximum sense

voltage of 75mV resulting in a maximum MOSFET current

of 75mV/R_SENSE

.

The LTC1736 includes current foldback to help further

limit load current when the output is shorted to ground.

The foldback circuit is active even when the overload

shutdown latch described above is defeated. If the output

falls by more than half, then the maximum sense voltage

is progressively lowered from 75mV to 30mV. Under

short-circuit conditions with very low duty cycle, the

LTC1736 will begin cycle skipping in order to limit the

short-circuit current. In this situation the bottom MOSFET

will be conducting the peak current. The short-circuit

ripple current is determined by the minimum on-time

t_ON(MIN)of the LTC1736 (less than 200ns), the input

voltage, and inductor value:

With soft-latch overvoltage protection, dynamic VID code

changesareallowedandtheovervoltageprotectiontracks

the new VID code, always protecting the load (CPU). If

dynamic VID code changes are anticipated and the mini-

mum load current is light, it may be necessary to either

force continuous operation by pulling FCB low during the

transition to maximize current sinking capability or con-

nect PGOOD to FCB to automatically force continuous

operation during VID transitions.

∆I_L(SC)= t_ON(MIN)V_IN/L.

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Minimum On-Time Considerations

inductor ripple current equal or greater than 30% of

I

_OUT(MAX)at V_IN(MAX)

.

Minimum on-time t_ON(MIN)is the smallest amount of time

that the LTC1736 is capable of turning the top MOSFET on

andoffagain.Itisdeterminedbyinternaltimingdelaysand

the gate charge required to turn on the top MOSFET. Low

duty cycle applications may approach this minimum on-

time limit and care should be taken to ensure that:

FCB Pin Operation

When the DC voltage on the FCB pin drops below its 0.8V

threshold, continuous mode operation is forced. In this

case, the top and bottom MOSFETs continue to be driven

synchronously regardless of the load on the main output.

Burst Mode operation is disabled and current reversal is

allowed in the inductor.

V_OUT

t_ON(MIN)

<

V (f)

IN

In addition to providing a logic input to force continuous

synchronous operation and external synchronization, the

FCB pin provides a means to regulate a flyback winding

output. During continuous mode, current flows continu-

ouslyinthetransformerprimary.Thesecondarywinding(s)

drawcurrentonlywhenthebottomsynchronousswitchis

on. When primary load currents are low and/or the

V_IN/V_OUTratio is low, the synchronous switch may not be

on for a sufficient amount of time to transfer power from

the output capacitor to the secondary load. Forced con-

tinuous operation will support secondary windings pro-

vided there is sufficient synchronous switch duty factor.

Thus, the FCB input pin removes the requirement that

power must be drawn from the inductor primary in order

toextractpowerfromtheauxiliarywindings. Withtheloop

incontinuousmode,theauxiliaryoutputmaynominallybe

loaded without regard to the primary output load.

Ifthedutycyclefallsbelowwhatcanbeaccommodatedby

the minimum on-time, the LTC1736 will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple current and voltage will increase.

The minimum on-time for the LTC1736 in a properly

configured application is generally less than 200ns. How-

ever, as the peak sense voltage decreases, the minimum

on-time gradually increases as shown in Figure 5. This is

of particular concern in forced continuous applications

withlowripplecurrentatlightloads.Ifthedutycycledrops

below the minimum on-time limit in this situation, a

significant amount of cycle skipping can occur with corre-

spondingly larger current and voltage ripple.

If an application can operate close to the minimum on-

time limit, an inductor must be chosen that is low enough

in value to provide sufficient ripple amplitude to meet the

minimum on-time requirement. As a general rule keep the

The secondary output voltage V_SECis normally set as

shownintheFunctionalDiagrambytheturnsratioNofthe

transformer:

250

200

150

100

50

V_SEC(N + 1) V_OUT

However, if the controller goes into Burst Mode operation

and halts switching due to a light primary load current,

then V_SECwill droop. An external resistive divider from

V_SECto the FCB pin sets a minimum voltage V_SEC(MIN)

:

R4

R3

V

≈ 0.8V 1+

SEC(MIN)

0

10

20

30

0

40

∆I /I

(%)

L

OUT(MAX)

If V_SECdrops below this level, the FCB voltage forces

continuous switching operation until V_SECis again above

its minimum.

1736 F05

Figure 5. Minimum On-Time vs ∆I_L

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In order to prevent erratic operation if no external connec-

tions are made to the FCB pin, the FCB pin has a 0.17µA

internal current source pulling the pin high. Remember to

include this current when choosing resistor values R3 and

R4.

where L1, L2, etc., are the individual losses as a percent-

age of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC1736 circuits: 1) LTC1736 V_INcurrent, 2)

INTV_CCcurrent, 3) I²R losses, 4) Topside MOSFET transi-

tion losses.

The internal LTC1736 oscillator can be synchronized to an

external oscillator by clocking the FCB pin with a signal

above 1.5V_P-P. When synchronized to an external fre-

quency, Burst Mode operation is disabled, but cycle skip-

ping is allowed at low load currents since current reversal

is inhibited. The bottom gate will come on every 10 clock

cycles to assure the boostrap cap, C_B, is kept refreshed.

The rising edge of an external clock applied to the FCB pin

starts a new cycle.

1. The V_INcurrent is the DC supply current given in the

electricalcharacteristicswhichexcludesMOSFETdriver

and control currents. V_INcurrent results in a small

(<0.1%) loss that increases with V_IN.

2. INTV_CCcurrent is the sum of the MOSFET driver and

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge dQ moves

from INTV_CCto ground. The resulting dQ/dt is a current

out of INTV_CCthat is typically much larger than the

The range of synchronization is from 0.9f_Oto 1.3f_O, with

f_Oset by C_OSC. Attempting to synchronize to a higher

frequency than 1.3f_Ocan result in inadequate slope

comensation and cause loop instability with high duty

cycles. If loop instability is observed while synchronized,

additional slope compensation can be obtained by simply

control circuit current. In continuous mode, I_GATECHG

=

f(Q_T+ Q_B), where Q_Tand Q_Bare the gate charges of the

topside and bottom-side MOSFETs.

decreasing C_OSC

.

The following table summarizes the possible states avail-

able on the FCB pin:

Supplying INTV_CCpower through the EXTV_CCswitch

input from an output-derived or other high efficiency

source will scale the V_INcurrent required for the driver

and control circuits by a factor of (Duty Cycle)/(Effi-

ciency).Forexample,ina15Vto1.8Vapplication,10mA

ofINTV_CCcurrentresultsinapproximately1.2mAofV_IN

current. This reduces the low current loss from 10% or

more(ifthedriverwaspowereddirectlyfromV_IN)toonly

a few percent.

Table 2

FCB Pin

Condition

DC Voltage: 0V to 0.7V

Burst Disabled/Forced Continuous

Current Reversal Enabled

DC Voltage: >0.9V

Feedback Resistors

Ext Clock: (0V to V

Burst Mode Operation, No Current Reversal

Regulating a Secondary Winding

Burst Mode Operation Disabled

)

FCBSYNC

(V

FCBSYNC

≥ 1.5V) No Current Reversal

3. I²R Losses are predicted from the DC resistances of the

MOSFETs, inductor and current shunt. In continuous

mode the average output current flows through L and

R_SENSE, but is “chopped” between the topside main

MOSFET and the synchronous MOSFET. If the two

MOSFETs have approximately the same R_DS(ON), then

the resistance of one MOSFET can simply be summed

with the resistances of L and R_SENSEto obtain I²R

losses. For example, if each R_DS(ON)= 0.02Ω, R_L=

0.03Ω, and R_SENSE= 0.01Ω, then the total resistance is

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can be

expressed as:

%Efficiency = 100% - (L1 + L2 + L3 + ...)

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0.06Ω. This results in losses ranging from 3% to 17%

as the output current increases from 1A to 5A for a 1.8V

output, or 4% to 20% for a 1.5V output. Efficiency

varies as the inverse square of V_OUTfor the same

external components and power level. I²R losses cause

the efficiency to drop at high output currents.

DC coupled and AC filtered closed-loop response test

point. The DC step, rise time and settling at this test point

truly reflects the closed-loop response. Assuming a pre-

dominantly second order system, phase margin and/or

damping factor can be estimated using the percentage of

overshoot seen at this pin. The bandwidth can also be

estimated by examining the rise time at the pin. The I_TH

external components shown in the Figure 1 circuit will

provide an adequate starting point for most applications.

4. Transition losses apply only to the topside MOSFET(s),

and only become significant when operating at high

input voltages (typically 12V or greater). Transition

losses can be estimated from:

The I_THseries R_C-C_Cfilter sets the dominant pole-zero

loop compensation. The values can be modified slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the final PC layout is done and the

particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

feedbackfactorgainandphase. Anoutputcurrentpulseof

20% to 100% of full-load current having a rise time of 1µs

to10µswillproduceoutputvoltageandI_THpinwaveforms

that will give a sense of the overall loop stability without

breaking the feedback loop. The initial output voltage step

may not be within the bandwidth of the feedback loop, so

the standard second-order overshoot/DC ratio cannot be

used determine phase margin. The gain of the loop will be

increased by increasing R_Cand the bandwidth of the loop

willbeincreasedbydecreasingC_C.IfR_Cisincreasedbythe

same factor that C_Cis decreased, the zero frequency will

be kept the same, thereby keeping the phase the same in

themostcriticalfrequencyrangeofthefeedbackloop. The

outputvoltagesettlingbehaviorisrelatedtothestabilityof

the closed-loop system and will demonstrate the actual

overall supply performance. For a detailed explanation of

optimizing the compensation components, including a

review of control loop theory, refer to Application Note 76.

Transition Loss = (1.7)(V_IN²)(I_O(MAX))(C_RSS)(f)

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efficiency degradation in portable systems. It is very

important to include these “system” level losses in the

design of a system. The internal battery and fuse resis-

tancelossescanbeminimizedbymakingsurethatC_INhas

adequate charge storage and very low ESR at the switch-

ing frequency. A 25W supply will typically require a

minimum of 20µF to 40µF of capacitance having a maxi-

mum of 0.01Ω to 0.02Ω of ESR. Other losses including

Schottky conduction losses during dead-time and induc-

tor core losses generally account for less than 2% total

additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, V_OUTshifts by an

amount equal to ∆I_LOAD(ESR), where ESR is the effective

series resistance of C_OUT. ∆I_LOADalso begins to charge or

discharge C_OUTgenerating the feedback error signal that

forces the regulator to adapt to the current change and

return V_OUTto its steady-state value. During this recovery

time V_OUTcan be monitored for excessive overshoot or

ringing, which would indicate a stability problem. OPTI-

LOOP compensation allows the transient response to be

optimized over a wide range of output capacitance and

ESR values. The availability of the I_THpin not only allows

optimization of control loop behavior but also provides a

Improve Transient Response and Reduce Output

Capacitance with Active Voltage Positioning

Fast load transient response, limited board space and low

cost are requirements of microprocessor power supplies.

Active voltage positioning improves transient response

and reduces the output capacitance required to power a

microprocessorwhereatypicalloadstepcanbefrom0.2A

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to 15A in 100ns or 15A to 0.2A in 100ns. The voltage at the

microprocessor must be held to about ±0.1V of nominal

in spite of these load current steps. Since the control loop

cannot respond this fast, the output capacitors must

supply the load current until the control loop can respond.

Capacitor ESR and ESL primarily determine the amount of

droop or overshoot in the output voltage. Normally, sev-

eral capacitors in parallel are required to meet micropro-

cessor transient requirements.

capacitance is required when voltage positioning is used

because more voltage variation is allowed on the output

capacitors.

Active voltage positioning can be implemented using the

OPTI-LOOP architecture of the LTC1736 with two external

resistors. An input voltage offset is introduced when the

error amplifier has to drive a resistive load. This offset is

limited to ±30mV at the input of the error amplifier. The

resulting change in output voltage is the product of input

offset and the feedback voltage divider ratio.

Active voltage positioning is a form of deregulation. It

sets the output voltage high for light loads and low for

heavy loads. When load current suddenly increases, the

output voltage starts from a level higher than nominal so

the output voltage can droop more and stay within the

specified voltage range. When load current suddenly

decreases the output voltage starts at a level lower than

nominal so the output voltage can have more overshoot

and stay within the specified voltage range. Less output

Figure 6 shows a CPU-core-voltage regulator with active

voltage positioning. Resistors R1 and R5 force the input

voltage offset that sets the output voltage according to the

load current level. To select values for R1 and R5, first

determinetheamountofoutputderegulationallowed. The

actual specification for a typical microprocessor allows

the output to vary ±0.112V. The LTC1736 output voltage

R3 680k

V

IN

7.5V TO 24V

R4 100k

R5 100k

C8

C12 TO C14

10µF

POWER

GOOD

R1

0.1µF

27k

35V

GND

C1 39pF

C2 0.1µF

C3 100pF

1

2

24

23

22

21

20

19

18

17

16

15

14

13

M1

C

OSC

TG

BOOST

SW

FDS6680A

C9 0.22µF

RUN/SS

R2 100k

C4 100pF

3

L1

R6

0.003Ω

I

TH

1µH

V

OUT

0.9V TO 2V

15A

4

D1

FCB LTC1736

SGND

V

IN

CMDSH-3

5

INTV

CC

+

C15 TO C17

180µF/4V

×4

M2, M3

FDS6680A

×2

6

C5

PGOOD

BG

D2

MBRS340

+

1000pF

C11

4.7µF

10V

7

C18

1µF

–

SENSE

PGND

C6

47pF

8

+

C10

1µF

SENSE

EXTV

CC

9

GND

V

VIDV

FB

CC

C7 330pF

10

11

12

5V (OPTIONAL)

VID4

OSENSE

VID0

VID1

VID2

VID3

VID4

VID0

VID1

VID3

VID2

1736 F06

VID

INPUT

C10, C18: TAIYO YUDEN JMK107BJ105

C11: KEMET T494A475M010AS

C12 TO C14: TAIYO YUDEN GMK325F106

C15 TO C17: PANASONIC EEFUE0G181R

D1: CENTRAL SEMI CMDSH-3

D2: MOTOROLA MBRS340

L1: PANASONIC ETQP6F1R0SA

M1 TO M3: FAIRCHILD FDS6680A

R6: IRC LRF2512-01-R003-J

U1: LINEAR TECHNOLOGY LTC1736CG

Figure 6. CPU-Core-Voltage Regulator with Active Voltage Positioning

22

LTC1736

U

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APPLICATIO S I FOR ATIO

At minimum load current:

accuracy is ±1%, so the output transient voltage cannot

exceed ±0.097V. At V_OUT= 1.5V, the maximum output

voltage change controlled by the I_THpin would be:

2A_P−P

2

V

=

0.2A +

• 0.084V/A + 0.3V

ITH(MIN)

Input Offset • V_OUT

∆V_OSENSE

=

= 0.40V

V_REF

±0.03V •1.5

0.8V

In this circuit, V_ITHchanges from 0.40V at light load to

1.77V at full load, a 1.37V change. Notice that ∆I_L, the

peak-to-peak inductor current, changes from light load to

full load. Increasing the DC inductor current decreases the

permeability of the inductor core material, which de-

creases the inductance and increases ∆I_L. The amount of

inductance change is a function of the inductor design.

= ±56mV

With optimum resistor values at the I_THpin, the output

voltage will swing from 1.55V at minimum load to 1.44V

at full load. At this output voltage, active voltage position-

ingprovidesanadditional56mVtotheallowable transient

voltage on the output capacitors, a 58% improvement

over the 97mV allowed without active voltage positioning.

To create the 30mV input offset, the gain of the error

amplifier must be limited. The desired gain is:

The next step is to calculate the I_THpin voltage, V_ITH, scale

factor. The V_ITHscale factor reflects the I_THpin voltage

required for a given load current. V_ITHcontrols the peak

sense resistor voltage, which represents the DC output

current plus one half of the peak-to-peak inductor current.

The no load to full load V_ITHrange is from 0.3V to 2.4V,

which controls the sense resistor voltage from 0V to the

∆V_SENSE(MAX)voltage of 75mV. The calculated V_ITHscale

factor with a 0.003Ω sense resistor is:

∆V

1.37V

ITH

A_V=

=

= 22.8

Input Offset 2(0.03V)

Connectingaresistortotheoutputofthetransconductance

error amplifier will limit the voltage gain. The value of this

resistor is:

A_V

22.8

R_ITH

=

= 17.54k

Error Amplifier g_m1.3ms

V

_ITHRange • SenseResistor Value

V_ITHScaleFactor =

To center the output voltage variation, V_ITHmust be

centered so that no I_THpin current flows when the output

voltage is nominal. V_ITH(NOM)is the average voltage be-

tween V_ITHat maximum output current and minimum

output current:

∆V_SENSE(MAX)

(2.4V – 0.3V)• 0.003

=

V_ITHat any load current is:

∆I_L

= 0.084V/A

0.075V

V

_ITH(MAX)– V

ITH(MIN)

V

=

+ V

ITH(MIN)

ITH(NOM)

V

_ITH= I_OUT(DC)

+

• V_ITHScaleFactor

2

1.77V – 0.40V

+ 0.40V = 1.085V

+V_ITHOffset

At full load current:

2

The Thevenin equivalent of the gain limiting resistance

value of 17.54k is made up of a resistor R5 that sources

current into the I_THpin and resistor R1 that sinks current

to SGND.

5A_P−P

2

V

=

15A +

• 0.084V/A + 0.3V

ITH(MAX)

= 1.77V

23

LTC1736

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APPLICATIO S I FOR ATIO

To calculate the resistor values, first determine the ratio

between them:

V_IN= 12V

V_OUT= 1.5V

FIGURE 6 CIRCUIT

1.582V

1.5V

OUTPUT

VOLTAGE

100mV/DIV

V

_INTVCC– V

5.2V – 1.085V

1.085V

ITH(NOM)

1.418V

k =

=

= 3.79

V

ITH(NOM)

15A

V_INTVCCis equal to V_EXTVCCor 5.2V if EXTVCC is not used.

Resistor R5 is:

LOAD

CURRENT

10A/DIV

0A

R4 = (k +1)•R_ITH= (3.79 +1)•17.54k = 84.0k

Resistor R1 is:

50µs/DIV

1736 F08

Figure 8. Transient Response with Active Voltage Positioning

(k + 1)•R_ITH(3.79 + 1)•17.54k

R1=

=

= 22.17k

k

3.79

Automotive Considerations:

Plugging into the Cigarette Lighter

Unfortunately,PCBnoisecanaddtothevoltagedeveloped

across the sense resistor, R6, causing the ITH pin voltage

to be slightly higher than calculated for a given output

current. The amount of noise is proportional to the output

current level. This PCB noise does not present a serious

problem but it does change the effective value of R6 so the

calculated values of R1 and R5 may need to be adjusted to

achieve the required results. Since PCB noise is a function

ofthelayout,itwillbethesameonallboardswiththesame

layout.

As battery-powered devices go mobile, there is a natural

interest in plugging into the cigarette lighter in order to

conserveorevenrechargebatterypacksduringoperation.

But before you connect, be advised: you are plugging into

thesupplyfromhell. Themainpowerlineinanautomobile

is the source of a number of nasty potential transients,

including load dump, reverse battery, and double battery.

Load dump is the result of a loose power cable. When the

cablebreaksconnection,thefieldcollapseinthealternator

can cause a positive spike as high as 60V which takes

several hundred milliseconds to decay. Reverse battery is

just what it says, while double battery is a consequence of

tow truck operators finding that a 24V jump start cranks

cold engines faster than 12V.

Figures 7 and 8 show the transient response before and

after active voltage positioning is implemented. Notice

that the output voltage droop and overshoot levels don’t

change but the peak-to-peak output voltage reduces con-

siderably with active voltage positioning.

Refer to Design Solutions 10 for more information about

active voltage positioning.

ThenetworkshowninFigure9isthemoststraightforward

approach to protect a DC/DC converter from the ravages

of an automotive power line. The series diode prevents

current from flowing during reverse battery, while the

transient suppressor clamps the input voltage during load

dump. Note that the transient suppressor should not

conduct during double-battery operation, but must still

clamptheinputvoltagebelowbreakdownoftheconverter.

Although the LTC1736 has a maximum input voltage of

36V, most applications will be limited to 30V by the

FIGURE 6 CIRCUIT

V_IN= 12V

V_OUT= 1.5V

OUTPUT

VOLTAGE

1.5V

100mV/DIV

15A

10A/DIV

0A

LOAD

CURRENT

MOSFET BV_DSS

.

50µs/DIV

1736 F07

Figure 7. Normal Transient Response (Without R1, R5)

24

LTC1736

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APPLICATIO S I FOR ATIO

50A I RATING

PK

in: R_DS(ON)= 0.03Ω, C_RSS= 80pF. At maximum input

voltage with T(estimated) = 50°C:

V

IN

12V

LTC1736

TRANSIENT VOLTAGE

SUPPRESSOR

GENERAL INSTRUMENT

1.5KA24A

2

1.6V

22V

P_MAIN

=

12 1+(0.005)(50°C – 25°C) 0.03Ω

( )

(

]

)

[

2

+1.7 22V 12A 80pF 275kHz

(

) (

)(

) (

)

1736 F09

= 571mW

Figure 9. Plugging into the Cigarette Lighter

Because the duty cycle of the bottom MOSFET is much

greater than the top, two larger MOSFETs must be paral-

leled. Choosing Fairchild FDS6680A MOSFETs yields a

parallel R_DS(ON)of 0.0065Ω. The total power dissipaton

for both bottom MOSFETs, again assuming T = 50°C, is:

Design Example

As a design example, assume V_IN= 12V(nominal), V_IN=

22V(max),V_OUT=1.6V(nominal),1.8Vto1.3Vrange,I_MAX

= 12A and f = 275kHz. R_SENSEand C_OSCcan immediately

be calculated:

2

22V – 1.6V

P_SYNC

=

12A 1.1 0.0065Ω

R_SENSE= 50mV/12A = 0.0042Ω

C_OSC= 1.61(10⁷)/(275kHz) – 11pF = 47pF

(

) ( )(

)

22V

= 955mW

Assume a 1.2µH inductor and check the actual value of the

ripple current. The following equation is used :

Thankstocurrentfoldback,thebottomMOSFETdissipaton

in short circuit will be less than under full-load conditions.

C_INis chosen for an RMS current rating of at least 6A at

temperature. C_OUTis chosen with an ESR of 0.01Ωfor low

outputripple. Theoutputrippleincontinuousmodewillbe

highest at the maximum input voltage. The output voltage

ripple due to ESR is approximately:

V

(f)(L)

V

OUT

V

IN

OUT

∆I =

1–

L

The highest value of the ripple current occurs at the

maximum input and output voltages:

V_ORIPPLE= R_ESR(∆I_L) = 0.01Ω(5A) = 50mV_P-P

1.8V

275kHz(1.2µH)

1.8V

22V

∆I_L=

1–

= 5A

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1736. These items are also illustrated graphically in

the layout diagram of Figure 10. Check the following in

your layout:

The maximum ripple current is 42% of maximum output

current, which is about right.

Next, verify the minimum on-time of 200ns is not violated.

The minimum on-time occurs at maximum V_INand mini-

mum V_OUT

.

1. Are the signal and power grounds segregated? The

LTC1736 PGND pin should tie to the GND plane close to

the input capacitor. The SGND pin should then connect

to PGND and all components that connect to SGND

should make a single point tie to the SGND pin. The low

side FET source pins should connect directly to the

input capacitor ground.

V_OUT

1.3V

22V(275kHz)

t_ON(MIN)

=

= 215ns

V

f

^IN(MAX)( )

The power dissipation on the topside MOSFET can be

easily estimated. Choosing a Fairchild FDS6612A results

25

LTC1736

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W

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APPLICATIO S I FOR ATIO

2. Does the V_OSENSEpin connect as close as possible to

the load? The optional 50pF to 100pF capacitor from

V_FBto SGND should be as close as possible to the

LTC1736.

3. AretheSENSE^–andSENSE⁺leadsroutedtogetherwith

minimum PC trace spacing? The filter capacitor be-

tween SENSE⁺and SENSE^–should be as close as

possibletotheLTC1736.Ensureaccuratecurrentsens-

ing with kelvin connections as shown in Figure 11.

Series resistance can be added to the SENSE lines to

increase noise rejection.

5. Is the INTV_CCdecoupling capacitor connected closely

between INTV_CCand the power ground pin? This ca-

pacitor carries the MOSFET driver peak currents. An

additional 1µF ceramic capacitor placed immediately

next to the INTV_CCand PGND pins can help improve

noise performance.

6. Keep the switching node (SW), Top Gate node (TG) and

Boost node (BOOST) away from sensitive small-signal

nodes, especially from the voltage and current sensing

feedback pins. All of these nodes have very large and

fast moving signals and therefore should be kept on the

“output side” (Pins 13 to 24) of the LTC1736 and

occupy minimum PC trace area.

4. Does the (+) terminal of C_INconnect to the drain of the

topsideMOSFET(s)ascloselyaspossible?Thiscapaci-

tor provides the AC current to the MOSFET(s).

+

C

OSC

1

2

24

23

22

21

20

19

18

17

16

15

14

13

C

TG

BOOST

SW

M1

OSC

C

IN

C

SS

+

RUN/SS

R

C

C1

3

V

IN

I

TH

D1

4

C2

C

FCB LTC1736

SGND

V

D

B

IN

5

INTV

CC

M2

+

6

47pF

PGOOD

BG

4.7µF

7

–

SENSE

PGND

–

1000pF

8

EXTERNAL EXTV

CONNECTION

+

CC

SENSE

EXTV

VIDV

CC

9

V

FB

10

11

12

VID4

VID3

VID2

OSENSE

VID0

VID1

L1

–

+

C

V

OUT

+

R

SENSE

1736 F10

Figure 10. LTC1736 Layout Diagram

HIGH CURRENT PATH

1736 F11

CURRENT SENSE

RESISTOR

(R

)

SENSE

+

–

SENSE SENSE

Figure 11. Kelvin Sensing R_SENSE

26

LTC1736

U

PACKAGE DESCRIPTION

Dimensions in inches (millimeters) unless otherwise noted.

G Package

24-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

8.07 – 8.33*

(0.318 – 0.328)

24 23 22 21 20 19 18 17 16 15 14

13

7.65 – 7.90

(0.301 – 0.311)

5

7

8

1

2

3

4

6

9 10 11 12

5.20 – 5.38**

(0.205 – 0.212)

1.73 – 1.99

(0.068 – 0.078)

0° – 8°

0.65

(0.0256)

BSC

0.13 – 0.22

0.55 – 0.95

(0.005 – 0.009)

(0.022 – 0.037)

0.05 – 0.21

(0.002 – 0.008)

0.25 – 0.38

(0.010 – 0.015)

NOTE: DIMENSIONS ARE IN MILLIMETERS

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.152mm (0.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

G24 SSOP 1098

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

27

LTC1736

U

TYPICAL APPLICATIO

12A Converter with FCB Tied to PGOOD for CPU Power; Optimized for Output Voltages of 1.3V to 1.6V

C

OSC

V

IN

47pF

PGOOD

4.75V TO 24V

C

1

2

3

4

5

6

7

8

9

24

23

22

21

20

19

18

17

16

15

14

13

M1

IN

+

C

TG

BOOST

SW

OSC

22µF/30V

×2

FDS6680A

C

SS

01.µF

RUN/SS

R

33k

C

330pF

C

0.22µF

OS-CON

C

C1

B

L1

1.2µH

R

SENSE

0.004Ω

I

TH

V

OUT

C

47pF

D

C2

B

1.35V TO 1.6V

12A

FCB LTC1736

SGND

V

IN

CMDSH-3

INTV

+

C

CC

OUT

100k

+

1µF

180µF/4V

×4

INTV

PGOOD

BG

M2

FDS6680A

×2

D1

MBRS340T3

4.7µF

CC

–

SENSE

PGND

1000pF

+

47pF

SENSE

EXTV

CC

OPTIONAL:

CONNECT

TO 5V

SGND

V

FB

VIDV

CC

10

11

12

V

VID4

OSENSE

VID0

VID1

VID3

VID2

OUTPUT VOLTAGE

PROGRAMMING

10Ω

1736 TA02

C

: 4-180µF/4V PANASONIC EEFUEOG181R (AS SHOWN)

3-470µF/6.3V KEMIT T51CX447M006AS (ALTERNATE)

OUT

1-820µF/4V SANYO 4SP820M + 1-180µF/4V PANASONIC EEFUE0G181R (ALTERNATE)

: SANYO OS-CON 305C22M

C

IN

L1: PANASONIC ETQP6RZ1RZ0HFA

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are trademarks of Linear Technology Corporaton.

SENSE

1736f LT/TP 1299 4K • PRINTED IN USA

28 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408)432-1900 FAX:(408)434-0507 www.linear-tech.com

LINEAR TECHNOLOGY CORPORATION 1999


型号：	LTC1736IG
厂家：	Linear
描述：	5-Bit Adjustable High Efficiency Synchronous Step-Down Switching Regulator 5位可调式高效率同步降压型开关稳压器稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管
文件：	总28页 (文件大小：325K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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