LTC1741 [Linear]
14-Bit, 80Msps Low Power 3V ADC; 14位，80Msps低功率3V ADC
| 型号： | LTC1741 |
| 厂家： | 
Linear |
| 描述： | 14-Bit, 80Msps Low Power 3V ADC |
| 文件： | 总20页 (文件大小：464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2249
14-Bit, 80Msps
Low Power 3V ADC
U
FEATURES
DESCRIPTIO
The LTC®2249 is a 14-bit 80Msps, low power 3V A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2249 is perfect for de-
manding imaging and communications applications with
AC performance that includes 73dB SNR and 90dB SFDR
for signals well beyond the Nyquist frequency.
■
Sample Rate: 80Msps
■
Single 3V Supply (2.7V to 3.4V)
■
Low Power: 222mW
■
73dB SNR at 70MHz Input
■
90dB SFDR at 70MHz Input
■
No Missing Codes
■
Flexible Input: 1VP-P to 2VP-P Range
DCspecsinclude±1LSBINL(typ), ±0.5LSBDNL(typ)and
no missing codes over temperature. The transition noise
■
575MHz Full Power Bandwidth S/H
■
Clock Duty Cycle Stabilizer
is a low 1.2LSBRMS
.
■
Shutdown and Nap Modes
■
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.3V
logic.
Pin Compatible Family
80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit)
65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit)
40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit)
25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit)
10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit)
32-Pin (5mm × 5mm) QFN Package
U
Asingle-endedCLKinputcontrolsconverteroperation.An
optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
■
Wireless and Wired Broadband Communication
■
Imaging Systems
■
Ultrasound
■
Spectral Analysis
■
Portable Instrumentation
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TYPICAL APPLICATIO
SNR vs Input Frequency,
–1dB, 2V Range
75
74
73
REFH
FLEXIBLE
REFERENCE
REFL
OV
DD
72
71
70
69
68
67
66
65
D13
+
14-BIT
PIPELINED
ADC CORE
•
•
•
CORRECTION
LOGIC
ANALOG
INPUT
OUTPUT
DRIVERS
INPUT
S/H
–
D0
OGND
CLOCK/DUTY
CYCLE
CONTROL
0
50
100
150
200
INPUT FREQUENCY (MHz)
2229 TA01
2249 G09
CLK
2249f
1
LTC2249
W W U W
U
W
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ABSOLUTE AXI U RATI GS
OVDD = VDD (Notes 1, 2)
PACKAGE/ORDER I FOR ATIO
TOP VIEW
Supply Voltage (VDD)................................................. 4V
Digital Output Ground Voltage (OGND) .......–0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage................–0.3V to (OVDD + 0.3V)
Power Dissipation............................................ 1500mW
Operating Temperature Range
LTC2249C ............................................... 0°C to 70°C
LTC2249I.............................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
32 31 30 29 28 27 26 25
LTC2249CUH
LTC2249IUH
+
–
AIN
AIN
1
2
3
4
5
6
7
8
24 D10
23 D9
REFH
REFH
REFL
REFL
D8
OV
22
21
DD
33
20 OGND
D7
19
QFN PART*
MARKING
V
18 D6
17 D5
DD
GND
9
10 11 12 13 14 15 16
UH PACKAGE
2249
32-LEAD (5mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD IS GND (PIN 33)
MUST BE SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
U
CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN
14
TYP
MAX
UNITS
Bits
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
●
●
●
●
●
Differential Analog Input (Note 5)
Differential Analog Input
(Note 6)
–4
±1
±0.5
±2
4
1
LSB
–1
LSB
–12
–2.5
12
2.5
mV
Gain Error
External Reference
±0.5
±10
%FS
µV/°C
Offset Drift
Full-Scale Drift
Internal Reference
External Reference
±30
±15
ppm/°C
ppm/°C
Transition Noise
SENSE = 1V
1
LSB
RMS
U
U
A ALOG I PUT
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
1V to 2V
1.5
MAX
UNITS
V
+
–
V
V
Analog Input Range (A –A
)
2.7V < V < 3.4V (Note 7)
●
●
●
●
●
IN
IN
IN
DD
Analog Input Common Mode
Differential Input (Note 7)
1
1.9
1
V
IN,CM
+
–
I
I
I
t
t
Analog Input Leakage Current
SENSE Input Leakage
MODE Pin Leakage
0V < A , A < V
DD
–1
–3
–3
µA
µA
µA
ns
IN
IN
IN
0V < SENSE < 1V
3
SENSE
MODE
AP
3
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Time Jitter
Analog Input Common Mode Rejection Ratio
0
0.2
80
ps
RMS
JITTER
CMRR
dB
2249f
2
LTC2249
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DY A IC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS
MIN
TYP
73
MAX
UNITS
dB
SNR
Signal-to-Noise Ratio
5MHz Input
40MHz Input
70MHz Input
140MHz Input
5MHz Input
●
●
●
●
70.8
73
dB
73
dB
72.6
90
dB
SFDR
SFDR
S/(N+D)
Spurious Free Dynamic Range
2nd or 3rd Harmonic
dB
40MHz Input
70MHz Input
140MHz Input
5MHz Input
75
81
90
dB
90
dB
85
dB
Spurious Free Dynamic Range
4th Harmonic or Higher
95
dB
40MHz Input
70MHz Input
140MHz Input
5MHz Input
95
dB
95
dB
90
dB
Signal-to-Noise Plus Distortion Ratio
72.9
72.8
72.8
72.1
90
dB
40MHz Input
70MHz Input
140MHz Input
70.2
dB
dB
dB
I
Intermodulation Distortion
Full Power Bandwidth
f
= 28.2MHz, f = 26.8MHz
dB
MD
IN1
IN2
Figure 8 Test Circuit
575
MHz
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I TER AL REFERE CE CHARACTERISTICS
(Note 4)
PARAMETER
CONDITIONS
= 0
MIN
TYP
MAX
UNITS
V
V
V
V
V
Output Voltage
Output Tempco
Line Regulation
Output Resistance
I
1.475 1.500 1.525
CM
CM
CM
CM
OUT
±30
3
ppm/°C
mV/V
Ω
2.7V < V < 3.4V
DD
–1mA < I
< 1mA
4
OUT
2249f
3
LTC2249
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS
LOGIC INPUTS (CLK, OE, SHDN)
MIN
2
TYP
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V
V
V
= 3V
●
●
●
V
V
IH
IL
DD
DD
IN
= 3V
0.8
10
I
= 0V to V
–10
µA
pF
IN
DD
C
Input Capacitance
(Note 7)
3
IN
LOGIC OUTPUTS
OV = 3V
DD
C
Hi-Z Output Capacitance
Output Source Current
Output Sink Current
OE = High (Note 7)
3
pF
mA
mA
OZ
I
I
V
V
= 0V
= 3V
50
50
SOURCE
SINK
OUT
OUT
V
High Level Output Voltage
I = –10µA
I = –200µA
O
2.995
2.99
V
V
OH
O
●
●
2.7
V
Low Level Output Voltage
I = 10µA
0.005
0.09
V
V
OL
O
I = 1.6mA
O
0.4
OV = 2.5V
DD
V
V
High Level Output Voltage
Low Level Output Voltage
I = –200µA
2.49
0.09
V
V
OH
OL
O
I = 1.6mA
O
OV = 1.8V
DD
V
V
High Level Output Voltage
Low Level Output Voltage
I = –200µA
1.79
0.09
V
V
OH
OL
O
I = 1.6mA
O
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POWER REQUIRE E TS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
(Note 9)
MIN
2.7
TYP
3
MAX
3.4
UNITS
V
V
Analog Supply Voltage
Output Supply Voltage
Supply Current
●
●
●
●
DD
OV
(Note 9)
0.5
3
3.6
V
DD
IV
74
222
2
86
mA
mW
mW
mW
DD
P
P
P
Power Dissipation
Shutdown Power
Nap Mode Power
258
DISS
SHDN
NAP
SHDN = H, OE = H, No CLK
SHDN = H, OE = L, No CLK
15
2249f
4
LTC2249
W U
TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
t
Sampling Frequency
CLK Low Time
(Note 9)
●
1
80
MHz
s
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On (Note 7)
●
●
5.9
5
6.25
6.25
500
500
ns
ns
L
t
CLK High Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On (Note 7)
●
●
5.9
5
6.25
6.25
500
500
ns
ns
H
t
t
Sample-and-Hold Aperture Delay
CLK to DATA Delay
0
ns
ns
AP
D
C = 5pF (Note 7)
●
●
●
1.4
2.7
4.3
3.3
6
5.4
10
L
Data Access Time After OE↓
BUS Relinquish Time
C = 5pF (Note 7)
L
ns
(Note 7)
8.5
ns
Pipeline
Latency
Cycles
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with GND and OGND
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V , they
will be clamped by internal diodes. This product can handle input currents
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and
11 1111 1111 1111.
DD
of greater than 100mA below GND or above V without latchup.
Note 7: Guaranteed by design, not subject to test.
DD
Note 4: V = 3V, f
drive, unless otherwise noted.
= 80MHz, input range = 2V with differential
Note 8: V = 3V, f
differential drive.
= 80MHz, input range = 1V with
SAMPLE P-P
DD
SAMPLE
P-P
DD
Note 9: Recommended operating conditions.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
8192 Point FFT, fIN = 5MHz,
–1dB, 2V Range
Typical INL, 2V Range
Typical DNL, 2V Range
0
–10
1.0
0.8
2.0
1.5
–20
0.6
–30
1.0
0.4
–40
0.5
0.2
–50
0
–60
0
–70
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
–80
–90
–100
–110
–120
8192
0
5
10
0
4096
12288
16384
15 20
25 30 35
FREQUENCY (MHz)
40
8192
0
4096
12288
16384
CODE
CODE
2249 G01
2249 G03
2249 G02
2249f
5
LTC2249
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TYPICAL PERFOR A CE CHARACTERISTICS
8192 Point FFT, fIN = 30MHz,
–1dB, 2V Range
8192 Point FFT, fIN = 70MHz,
–1dB, 2V Range
8192 Point FFT, fIN = 140MHz,
–1dB, 2V Range
0
–10
0
–10
0
–10
–20
–20
–20
–30
–30
–30
–40
–40
–40
–50
–50
–50
–60
–60
–60
–70
–70
–70
–80
–80
–80
–90
–90
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
2249 G04
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
2249 G05
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
2249 G06
8192 Point 2-Tone FFT,
fIN = 28.2MHz and 26.8MHz,
–1dB, 2V Range
SNR vs Input Frequency,
–1dB, 2V Range
Grounded Input Histogram
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
75
74
73
72
71
70
69
68
67
66
65
0
–10
43161
35969
–20
–30
–40
–50
25292
–60
–70
–80
12558
–90
6150
1987
–100
–110
–120
5194
552
178
26
0
8201
8203
8205
CODE
8207
8209
0
50
100
150
200
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
2249 G07
INPUT FREQUENCY (MHz)
2249 G08
2249 G09
SNR and SFDR vs Sample Rate,
2V Range, fIN = 5MHz, –1dB
SNR and SFDR
SFDR vs Input Frequency,
–1dB, 2V Range
vs Clock Duty Cycle
100
95
90
85
80
75
70
100
95
SFDR: DCS ON
90
80
SFDR
SNR
90
SFDR: DCS OFF
85
80
75
70
65
70
60
50
SNR: DCS ON
SNR: DCS OFF
40 45 50 55
CLOCK DUTY CYCLE (%)
70
30 35
60 65
50
100
200
10 20 30
60 70
0
150
0
40 50
80
90 100
110
INPUT FREQUENCY (MHz)
SAMPLE RATE (Msps)
2249 G12
2249 G10
2249 G11
2249f
6
LTC2249
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TYPICAL PERFOR A CE CHARACTERISTICS
SNR vs Input Level,
SFDR vs Input Level,
f
IN = 70MHz, 2V Range
f
IN = 70MHz, 2V Range
120
110
100
90
80
70
60
50
40
30
20
10
0
80
70
60
50
dBFS
dBFS
dBc
40
30
dBc
100dBc SFDR
REFERENCE LINE
20
10
0
–40 –30
–10
–70 –60 –50
0
–20
–40
–60
INPUT LEVEL (dBFS)
–80
–20
0
INPUT LEVEL (dBFS)
2249 G13
2249 G14
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB, OVDD = 1.8V
IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
7
6
5
85
80
75
2V RANGE
1V RANGE
70
65
60
55
4
3
2
1
50
0
0
30
50 60 70 80 90 100
0
30
50 60 70 80 90 100
10 20
40
10 20
40
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
2249 G15
2249 G16
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U
U
PI FU CTIO S
AIN+ (Pin 1): Positive Differential Analog Input.
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
AIN- (Pin 2): Negative Differential Analog Input.
VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF
ceramic chip capacitors.
REFH(Pins3,4):ADCHighReference.Shorttogetherand
bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 5, 6 with
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
GND (Pin 8): ADC Power Ground.
CLK (Pin 9): Clock Input. The input sample starts on the
positive edge.
REFL (Pins 5, 6): ADC Low Reference. Short together and
bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 3, 4 with
SHDN (Pin 10): Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
2249f
7
LTC2249
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U
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PI FU CTIO S
operation with the outputs enabled. Connecting SHDN to
GND and OE to VDD results in normal operation with the
outputs at high impedance. Connecting SHDN to VDD and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to VDD and OE to VDD
results in sleep mode with the outputs at high impedance.
straight binary output format and turns the clock duty
cycle stabilizer off. 1/3 VDD selects straight binary output
formatandturnstheclockdutycyclestabilizeron. 2/3VDD
selects 2’s complement output format and turns the clock
duty cycle stabilizer on. VDD selects 2’s complement
output format and turns the clock duty cycle stabilizer off.
OE (Pin 11): Output Enable Pin. Refer to SHDN pin
SENSE(Pin30):ReferenceProgrammingPin.Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. VDD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±VSENSE. ±1V is the largest valid input range.
function.
D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24,
25, 26, 27): Digital Outputs. D13 is the MSB.
OGND (Pin 20): Output Driver Ground.
OVDD (Pin 21): Positive Supply for the Output Drivers.
Bypass to ground with 0.1µF ceramic chip capacitor.
VCM (Pin 31): 1.5V Output and Input Common Mode Bias.
Bypass to ground with 2.2µF ceramic chip capacitor.
OF (Pin 28): Over/Under Flow Output. High when an over
or under flow has occurred.
GND (Exposed Pad) (Pin 33): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
MODE (Pin 29): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
U
U
W
FUNCTIONAL BLOCK DIAGRA
+
A
IN
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
SIXTH PIPELINED
ADC STAGE
–
A
IN
V
CM
1.5V
REFERENCE
SHIFT REGISTER
AND CORRECTION
2.2µF
RANGE
SELECT
REFH
REFL
INTERNAL CLOCK SIGNALS
OV
DD
REF
BUF
SENSE
OF
D13
D0
CLOCK/DUTY
DIFF
REF
AMP
CONTROL
LOGIC
OUTPUT
DRIVERS
•
•
•
CYCLE
CONTROL
2249 F01
REFH
REFL
0.1µF
2.2µF
OGND
SHDN
CLK
MODE
OE
1µF
1µF
Figure 1. Functional Block Diagram
2249f
8
LTC2249
W U
W
TI I G DIAGRA
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
N + 5
t
H
N + 1
t
L
CLK
t
D
N – 6
N – 5
N – 4
N – 3
N – 2
N – 1
D0-D13, OF
2249 TD01
W U U
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APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Total Harmonic Distortion
Spurious Free Dynamic Range (SFDR)
Total harmonic distortion is the ratio of the RMS sum of all
harmonicsoftheinputsignaltothefundamentalitself.The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
THD = 20Log √(V22 + V32 + V42 + . . . Vn2)/V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
secondthroughnthharmonics. TheTHDcalculatedinthis
data sheet uses all the harmonics up to the fifth.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
2249f
9
LTC2249
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APPLICATIO S I FOR ATIO
Aperture Delay Time
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third, fourth and fifth stages, resulting in a fifth stage
residue that is sent to the sixth stage ADC for final
evaluation.
ThetimefromwhenCLKreachesmid-supply totheinstant
that the input signal is held by the sample and hold circuit.
Aperture Delay Jitter
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
thattheresultscanbeproperlycombinedinthecorrection
logic before being sent to the output buffer.
Thevariationintheaperturedelaytimefromconversionto
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π) • fIN • tJITTER
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
CONVERTER OPERATION
As shown in Figure 1, the LTC2249 is a CMOS pipelined
multistep converter. The converter has six pipelined ADC
stages; a sampled analog input will result in a digitized
valuesixcycleslater(seetheTimingDiagramsection).For
optimal AC performance the analog inputs should be
driven differentially. For cost sensitive applications, the
analog inputs can be driven single-ended with slightly
worseharmonicdistortion.TheCLKinputissingle-ended.
The LTC2249 has two phases of operation, determined by
the state of the CLK input pin.
Figure 2 shows an equivalent circuit for the LTC2249
CMOSdifferentialsample-and-hold.Theanaloginputsare
connected to the sampling capacitors (CSAMPLE) through
NMOStransistors. Thecapacitorsshownattachedtoeach
input (CPARASITIC) are the summation of all other capaci-
tance associated with each input.
LTC2249
V
DD
C
C
SAMPLE
4pF
15Ω
15Ω
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
outputbytheresidueamplifier.Successivestagesoperate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
A
+
–
IN
IN
C
PARASITIC
1pF
V
DD
SAMPLE
4pF
A
C
PARASITIC
1pF
V
DD
CLK
2249 F02
WhenCLKislow, theanaloginputissampleddifferentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during
this high phase of CLK. When CLK goes back low, the first
stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When CLK goes back high,
Figure 2. Equivalent Input Circuit
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage.
When CLK transitions from low to high, the sampled input
voltageisheldonthesamplingcapacitors.Duringthehold
phase when CLK is high, the sampling capacitors are
disconnectedfromtheinputandtheheldvoltageispassed
to the ADC core for processing. As CLK transitions from
2249f
10
LTC2249
U
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APPLICATIO S I FOR ATIO
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportionaltothechangeinvoltagebetweensampleswill
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2249 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Terminating on the trans-
former secondary is desirable, as this provides a common
modepathforchargingglitchescausedbythesampleand
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen by
the ADC does not exceed 100Ω for each ADC input. A
disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
+
DNLwillremainunchanged.Forasingle-endedinput,AIN
should be driven with the input signal and AIN– should be
connected to 1.5V or VCM
.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.5V. The VCM output pin (Pin
31) may be used to provide the common mode bias level.
VCM can be tied directly to the center tap of a transformer
tosettheDCinputlevelorasareferenceleveltoanopamp
differentialdrivercircuit. TheVCM pinmustbebypassedto
ground close to the ADC with a 2.2µF or greater capacitor.
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. Theadvantageofthismethodisthatitprovideslow
frequencyinputresponse;however,thelimitedgainband-
width of most op amps will limit the SFDR at high input
frequencies.
V
CM
2.2µF
0.1µF T1
+
25Ω
A
IN
1:1
ANALOG
INPUT
LTC2249
Input Drive Impedance
0.1µF
25Ω
25Ω
12pF
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2249 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and reactance can
influence SFDR. At the falling edge of CLK, the sample-
and-holdcircuitwillconnectthe4pFsamplingcapacitorto
the input pin and start the sampling period. The sampling
period ends when CLK rises, holding the sampled input on
the sampling capacitor. Ideally the input circuitry should
be fast enough to fully charge the sampling capacitor
during the sampling period 1/(2FENCODE); however, this is
not always possible and the incomplete settling may
degradetheSFDR. The sampling glitchhasbeendesigned
to be as linear as possible to minimize the effects of
incomplete settling.
–
A
IN
25Ω
T1 = MA/COM ETC1-1T
2249 F03
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
V
CM
2.2µF
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
+
25Ω
25Ω
A
IN
LTC2249
ANALOG
INPUT
+
+
CM
12pF
–
–
–
A
IN
2249 F04
Figure 4. Differential Drive with an Amplifier
2249f
11
LTC2249
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APPLICATIO S I FOR ATIO
V
Figure 5 shows a single-ended input circuit. The imped-
ance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
CM
2.2µF
0.1µF
0.1µF
+
–
6.8nH
0.1µF
A
IN
IN
ANALOG
INPUT
LTC2249
25Ω
25Ω
V
CM
T1
2.2µF
6.8nH
10k 10k
25Ω
A
0.1µF
+
IN
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS, INDUCTORS
ARE 0402 PACKAGE SIZE
A
ANALOG
INPUT
2249 F08
LTC2249
12pF
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 300MHz
–
IN
25Ω
A
2249 F05
0.1µF
Reference Operation
Figure 5. Single-Ended Drive
Figure9showstheLTC2249referencecircuitryconsisting
of a 1.5V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage refer-
ence can be configured for two pin selectable input ranges
of2V(±1Vdifferential)or1V(±0.5Vdifferential).Tyingthe
SENSE pin to VDD selects the 2V range; tying the SENSE
pin to VCM selects the 1V range.
The25Ωresistorsand12pFcapacitorontheanaloginputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input.
For input frequencies above 70MHz, the input circuits of
Figure 6, 7 and 8 are recommended. The balun trans-
former gives better high frequency response than a flux
coupled center tapped transformer. The coupling capaci-
tors allow the analog inputs to be DC biased at 1.5V. In
Figure 8, the series inductors are impedance matching
elements that maximize the ADC bandwidth.
The 1.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to gener-
ate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.5V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
V
CM
2.2µF
0.1µF
0.1µF
+
–
12Ω
A
IN
ANALOG
INPUT
LTC2249
0.1µF
25Ω
25Ω
T1
8pF
A
The difference amplifier generates the high and low refer-
ence for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 9.
12Ω
IN
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2249 F06
Figure 6. Recommended Front End Circuit for
Input Frequencies Between 70MHz and 170MHz
Other voltage ranges in-between the pin selectable ranges
can be programmed with two external resistors as shown
inFigure10.Anexternalreferencecanbeusedbyapplying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
levelasclosetotheconverteraspossible. IftheSENSEpin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1µF ceramic capacitor.
V
CM
2.2µF
0.1µF
0.1µF
+
–
A
IN
IN
ANALOG
INPUT
LTC2249
0.1µF
25Ω
25Ω
T1
A
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2249 F07
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 170MHz and 300MHz
2249f
12
LTC2249
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APPLICATIO S I FOR ATIO
U
CLEAN
SUPPLY
LTC2249
4.7µF
4Ω
V
CM
1.5V BANDGAP
REFERENCE
1.5V
FERRITE
BEAD
2.2µF
1V
0.5V
0.1µF
RANGE
DETECT
AND
1k
0.1µF
SINUSOIDAL
CLOCK
CLK
LTC2249
INPUT
CONTROL
TIE TO V FOR 2V RANGE;
DD
50Ω 1k
NC7SVU04
SENSE
REFH
TIE TO V FOR 1V RANGE;
CM
RANGE = 2 • V
FOR
< 1V
SENSE
SENSE
BUFFER
0.5V < V
2249 F11
INTERNAL ADC
HIGH REFERENCE
1µF
Figure 11. Sinusoidal Single-Ended CLK Drive
The noise performance of the LTC2249 can depend on the
clock signal quality as much as on the analog input. Any
noise present on the clock signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
2.2µF
1µF
0.1µF
DIFF AMP
REFL
INTERNAL ADC
LOW REFERENCE
In applications where jitter is critical, such as when digitiz-
ing high input frequencies, use as large an amplitude as
possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
2249 F09
Figure 9. Equivalent Reference Circuit
1.5V
V
CM
2.2µF
Maximum and Minimum Conversion Rates
12k
LTC2249
0.75V
12k
SENSE
ThemaximumconversionratefortheLTC2249is80Msps.
For the ADC to operate properly, the CLK signal should
have a 50% (±5%) duty cycle. Each half cycle must have
at least 5.9ns for the ADC internal circuitry to have enough
settling time for proper operation.
1µF
2249 F10
Figure 10. 1.5V Range ADC
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
fallingedgeisgeneratedbyaphase-lockedloop. Theinput
clock duty cycle can vary from 40% to 60% and the clock
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require a hundred
clockcyclesforthePLLtolockontotheinputclock.Touse
the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3VDD or 2/3VDD using external resistors.
Input Range
The input range can be set based on the application. The
2Vinputrangewillprovidethebestsignal-to-noiseperfor-
mance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 5.7dB. See the Typical Performance Charac-
teristics section.
Driving the Clock Input
The CLK input can be driven directly with a CMOS or TTL
levelsignal. Asinusoidalclockcanalsobeusedalongwith
a low-jitter squaring circuit before the CLK pin (see
Figure 11).
2249f
13
LTC2249
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APPLICATIO S I FOR ATIO
The lower limit of the LTC2249 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architectureofthisADCreliesonstoringanalogsignalson
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating fre-
quency for the LTC2249 is 1Msps.
Data Format
Using the MODE pin, the LTC2249 parallel digital output
can be selected for offset binary or 2’s complement
format. Connecting MODE to GND or 1/3VDD selects
straight binary output format. Connecting MODE to
2/3VDD or VDD selects 2’s complement output format.
An external resistor divider can be used to set the 1/3VDD
or 2/3VDD logic values. Table 1 shows the logic states for
the MODE pin.
DIGITAL OUTPUTS
Digital Output Buffers
Table 1. MODE Pin Function
Clock Duty
MODE Pin
Figure 12 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
Output Format
Straight Binary
Straight Binary
2’s Complement
2’s Complement
Cycle Stablizer
0
Off
On
On
Off
1/3V
2/3V
DD
DD
V
DD
Overflow Bit
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2249 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF.
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
exampleiftheconverterisdrivingaDSPpoweredbya1.8V
supply,thenOVDD shouldbetiedtothatsame1.8Vsupply.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
OVDD can be powered with any voltage from 500mV up to
theVDD ofthepart.OGNDcanbepoweredwithanyvoltage
from GND up to 1V and must be less than OVDD. The logic
outputs will swing between OGND and OVDD.
LTC2249
OV
DD
0.5V
TO V
DD
V
DD
V
DD
0.1µF
OV
DD
Output Enable
DATA
FROM
LATCH
PREDRIVER
LOGIC
43Ω
TYPICAL
DATA
OUTPUT
Theoutputsmaybedisabledwiththeoutputenablepin,OE.
OEhighdisablesalldataoutputsincludingOF.Thedataac-
cess and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed op-
eration.TheoutputHi-Zstateisintendedforuseduringlong
periods of inactivity.
OE
OGND
2249 F12
Figure 12. Digital Output Buffer
2249f
14
LTC2249
W U U
APPLICATIO S I FOR ATIO
U
Sleep and Nap Modes
High quality ceramic bypass capacitors should be used at
theVDD, OVDD, VCM, REFH, andREFLpins. Bypasscapaci-
tors must be located as close to the pins as possible. Of
particular importance is the 0.1µF capacitor between
REFH and REFL. This capacitor should be placed as close
to the device as possible (1.5mm or less). A size 0402
ceramic capacitor is recommended. The large 2.2µF ca-
pacitor between REFH and REFL can be somewhat further
away. The traces connecting the pins and bypass capaci-
tors must be kept short and should be made as wide as
possible.
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normaloperation. Connecting SHDN to VDD andOE to VDD
results in sleep mode, which powers down all circuitry
includingthereferenceandtypicallydissipates1mW.When
exiting sleep mode it will take milliseconds for the output
datatobecomevalidbecausethereferencecapacitorshave
torechargeandstabilize. ConnectingSHDNtoVDD andOE
to GND results in nap mode, which typically dissipates
15mW. In nap mode, the on-chip reference circuit is kept
on,sothatrecoveryfromnapmodeisfasterthanthatfrom
sleepmode,typicallytaking100clockcycles.Inbothsleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
The LTC2249 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
Grounding and Bypassing
Heat Transfer
The LTC2249 requires a printed circuit board with a clean,
unbroken ground plane. A multilayer board with an inter-
nal ground plane is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
linesareseparatedasmuchaspossible. Inparticular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.
Most of the heat generated by the LTC2249 is transferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad
should be soldered to a large grounded pad on the PC
board. It is critical that all ground pins are connected to a
ground plane of sufficient area.
2249f
15
LTC2249
W U U
U
APPLICATIO S I FOR ATIO
2249f
16
LTC2249
W U U
APPLICATIO S I FOR ATIO
U
Topside
Silkscreen Top
Inner Layer 2 GND
2249f
17
LTC2249
W U U
U
APPLICATIO S I FOR ATIO
Bottomside
Inner Layer 3 Power
Silkscreen Bottom
2249f
18
LTC2249
U
PACKAGE DESCRIPTIO
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.45 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
BOTTOM VIEW—EXPOSED PAD
0.23 TYP
(4 SIDES)
R = 0.115
TYP
0.75 ± 0.05
5.00 ± 0.10
(4 SIDES)
31 32
0.00 – 0.05
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.45 ± 0.10
(4-SIDES)
(UH) QFN 0603
0.200 REF
0.25 ± 0.05
0.50 BSC
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
NOTE:
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2249f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC2249
RELATED PARTS
PART NUMBER
LTC1741
LTC1742
LTC1743
LTC1744
LTC1745
LTC1746
LTC1747
LTC1748
LTC1749
LTC1750
LTC2220
LTC2221
LTC2222
LTC2223
LTC2224
LTC2225
LTC2226
LTC2227
LTC2228
LTC2229
LTC2230
LTC2231
LTC2232
LTC2233
LTC2234
LTC2236
LTC2237
LTC2238
LTC2239
LTC2245
LTC2246
LTC2247
LTC2248
LT5512
DESCRIPTION
COMMENTS
12-Bit, 65Msps ADC
14-Bit, 65Msps ADC
12-Bit, 50Msps ADC
14-Bit, 50Msps ADC
12-Bit, 25Msps ADC
14-Bit, 25Msps ADC
12-Bit, 80Msps ADC
14-Bit, 80Msps ADC
12-Bit, 80Msps Wideband ADC
14-Bit, 80Msps Wideband ADC
12-Bit, 170Msps ADC
12-Bit, 135Msps ADC
12-Bit, 105Msps ADC
12-Bit, 80Msps ADC
12-Bit, 135Msps ADC
12-Bit, 10Msps ADC
12-Bit, 25Msps ADC
12-Bit, 40Msps ADC
12-Bit, 65Msps ADC
12-Bit, 80Msps ADC
10-Bit, 170Msps ADC
10-Bit, 135Msps ADC
10-Bit, 105Msps ADC
10-Bit, 80Msps ADC
10-Bit, 135Msps ADC
10-Bit, 25Msps ADC
10-Bit, 40Msps ADC
10-Bit, 65Msps ADC
10-Bit, 80Msps ADC
14-Bit, 10Msps ADC
14-Bit, 25Msps ADC
14-Bit, 40Msps ADC
14-Bit, 65Msps ADC
DC-3GHz High Signal Level Downconverting Mixer
72dB SNR, 87dB SFDR, 48-Pin TSSOP Package
76.5dB SNR, 90dB SFDR, 48-Pin TSSOP Package
72.5dB SNR, 90dB SFDR, 48-Pin TSSOP Package
77dB SNR, 90dB SFDR, 48-Pin TSSOP Package
72.2dB SNR, 380mW SFDR, 48-Pin TSSOP Package
77.5dB SNR, 390mW SFDR, 48-Pin TSSOP Package
72dB SNR, 87dB SFDR, 48-Pin TSSOP Package
76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package
Up to 500MHz IF Undersampling, 87dB SFDR
Up to 500MHz IF Undersampling, 90dB SFDR
890mW, 67.7dB SNR, 9mm x 9mm QFN Package
630mW, 67.8dB SNR, 9mm x 9mm QFN Package
475mW, 68.4dB SNR, 7mm x 7mm QFN Package
366mW, 68.5dB SNR, 7mm x 7mm QFN Package
630mW, 67.6dB SNR, 7mm x 7mm QFN Package
60mW, 71.3dB SNR, 5mm x 5mm QFN Package
75mW, 71.4dB SNR, 5mm x 5mm QFN Package
120mW, 71.4dB SNR, 5mm x 5mm QFN Package
205mW, 71.3dB SNR, 5mm x 5mm QFN Package
211mW, 70.6dB SNR, 5mm x 5mm QFN Package
890mW, 61.2dB SNR, 9mm x 9mm QFN Package
630mW, 61.2dB SNR, 9mm x 9mm QFN Package
475mW, 61.3dB SNR, 7mm x 7mm QFN Package
366mW, 61.3dB SNR, 7mm x 7mm QFN Package
630mW, 61.2dB SNR, 7mm x 7mm QFN Package
75mW, 61.8dB SNR, 5mm × 5mm QFN Package
120mW, 61.8dB SNR, 5mm × 5mm QFN Package
205mW, 61.8dB SNR, 5mm × 5mm QFN Package
211mW, 61.6dB SNR, 5mm × 5mm QFN Package
60mW, 74.4dB SNR, 5mm × 5mm QFN Package
75mW, 74.5dB SNR, 5mm × 5mm QFN Package
120mW, 74.4dB SNR, 5mm × 5mm QFN Package
205mW, 74.3dB SNR, 5mm × 5mm QFN Package
DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514
Ultralow Distortion IF Amplifier/ADC Driver
with Digitally Controlled Gain
450MHz 1dB BW, 47dB OIP3, Digital Gain Control
10.5dB to 33ddB in 1.5dB/Step
LT5515
LT5516
LT5517
LT5522
1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator
0.8GHz to 1.5GHz Direct Conversion Quadrature Demodulator
20dBm IIP3, Integrated LO Quadrature Generator
21.5dBm IIP3, Integrated LO Quadrature Generator
40MHz to 900MHz Direct Conversion Quadrature Demodulator 21dBm IIP3, Integrated LO Quadrature Generator
600MHz to 2.7GHz High Linearity Downconverting Mixer
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz,
NF = 12.5dB, 50Ω Single-Ended RF and LO Ports
2249f
LT/TP 1004 1K • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
©LINEAR TECHNOLOGY CORPORATION 2004
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LTC1741IFW#PBF
LTC1741 - 12-Bit, 65Msps Low Noise ADC; Package: TSSOP; Pins: 48; Temperature Range: -40°C to 85°C
Linear
LTC1742IFW#PBF
LTC1742 - 14-Bit, 65Msps Low Noise ADC; Package: TSSOP; Pins: 48; Temperature Range: -40°C to 85°C
Linear
LTC1742IFW#TR
LTC1742 - 14-Bit, 65Msps Low Noise ADC; Package: TSSOP; Pins: 48; Temperature Range: -40°C to 85°C
Linear
LTC1742IFW#TRPBF
LTC1742 - 14-Bit, 65Msps Low Noise ADC; Package: TSSOP; Pins: 48; Temperature Range: -40°C to 85°C
Linear
LTC1743CFW#PBF
LTC1743 - 12-Bit, 50Msps ADC; Package: TSSOP; Pins: 48; Temperature Range: 0°C to 70°C
Linear
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