LTC1771ES8#PBF_技术文档

LTC1771

10µA Quiescent Current

High Efficiency Step-Down

DC/DC Controller

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FEATURES

DESCRIPTIO

The LTC^®1771 is a high efficiency current mode step-

down DC/DC controller that draws as little as 10µA DC

supply current to regulate the output at no load while

maintaining high efficiency for loads up to several amps.

■

Very Low Standby Current: 10µA

■

Available in Space-Saving 8-Lead MSOP Package

■

Output Currents: Up to 5A

■

Wide V_INRange: 2.8V to 20V Operation

■

V_OUTRange: 1.23V to 18V

TheLTC1771drivesanexternalP-channelpowerMOSFET

using a current mode, constant off-time architecture. An

external sense resistor is used to program the operating

current level. Current mode control provides short-circuit

protection, excellent transient response and controlled

start-up behavior. Burst Mode operation enables the

LTC1771 to maintain high efficiency down to extremely

low currents. Shutdown mode further reduces the supply

current to a mere 2µA. For low noise applications, Burst

Mode operation can be easily disabled with the MODE pin.

■

High Efficiency: Over 93% Possible

■

±2% Output Accuracy

■

Very Low Dropout Operation: 100% Duty Cycle

■

Current Mode Operation for Excellent Line and

Load Transient Response

Defeatable Burst Mode^TMOperation

■

Short-Circuit Protected

Optional Programmable Soft-Start

■

Micropower Shutdown: I_Q= 2µA

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Wide input supply range of 2.8V to 18V (20V maximum)

and 100% duty cycle operation for low dropout make the

LTC1771 ideal for a wide variety of battery-powered appli-

cations where maximizing battery life is important.

APPLICATIO S

■

Cellular Telephones and Wireless Modems

■

1- to 4-Cell Lithium-Ion-Powered Applications

■

Portable Instruments

The LTC1771’s availability in both 8-lead MSOP and SO

packages provides for a minimum area solution.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode is a trademark of Linear Technology Corporation.

■

Battery-Powered Equipment

■

Battery Chargers

■

Scanners

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TYPICAL APPLICATIO

V

IN

4.5V TO 18V

LTC1771 Efficiency

+

100

R

22µF

25V

SENSE

0.05Ω

V

IN

= 5V

90

80

70

60

50

40

V

= 10V

IN

M1

V

SENSE

PGATE

IN

RUN/SS

Si6447DQ

L1

V

IN

= 15V

15µH

V

3.3V

2A

OUT

C

SS

0.01µF

LTC1771

I

TH

R

C

V

MODE

UPS5817

+

C

FB

IN

OUT

10k

GND

150µF

R2

1.64M

1%

C

6.3V

22OpF

R1

V

= 3.3V

SENSE

OUT

1M

1%

R

= 0.05Ω

C

FF

5pF

1771 F01

0.1

1

10

100

1000

10000

LOAD CURRENT (mA)

1771 F01b

Figure 1. High Efficiency Step-Down Converter

1

LTC1771

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ABSOLUTE AXI U RATI GS _{(Note 1)}

Input Supply Voltage (V_IN)........................ –0.3V to 20V

Peak Driver Output Current < 10µs (PGATE) ............. 1A

RUN/SS Voltage ......................... –0.3V to (V_IN+ 0.3V)*

MODE Voltage .......................................... –0.3V to 20V

I_TH, V_FBVoltage .......................................... –0.3V to 5V

SENSE Voltage (V_IN> 12V)..(V_IN– 12V) to (V_IN+ 0.3V)*

SENSE Voltage (V_IN≤ 12V) ........ –0.3V to (V_IN+ 0.3V)*

Junction Temperature (Note 2)............................ 125°C

Operating Temperature Range (Note 3)

LTC1771E......................................... –40°C to 85°C

LTC1771I ......................................... –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

*RUN/SS and SENSE cannot exceed 20V.

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PACKAGE/ORDER I FOR ATIO

ORDER PART

NUMBER

ORDER PART

TOP VIEW

NUMBER

TOP VIEW

RUN/SS

1

2

3

4

8

7

6

5

MODE

SENSE

RUN/SS 1

8 MODE

7 SENSE

LTC1771ES8

LTC1771IS8

LTC1771EMS8

I

TH

I

V

2

3

TH

FB

6 V

IN

V

FB

IN

5 PGATE

GND 4

GND

PGATE

MS8 PACKAGE

8-LEAD PLASTIC MSOP

S8 PART MARKING

MS8 PART MARKING

LTKD

S8 PACKAGE

8-LEAD PLASTIC SO

T_JMAX= 125°C, θ_JA= 200°C/ W

1771

1771I

T_JMAX= 125°C, θ_JA= 110°C/ W

Consult factory for Military grade parts.

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.

A

V_IN= 10V, V_RUN= open unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

(Note 5)

MIN

TYP

1.230

1

MAX

1.255

10

UNITS

V

Feedback Voltage

●

1.205

FB

I

Feedback Current

(Note 5)

nA

FB

SUPPLY

No-Load Supply Current

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

IN

V

IN

= 10V, I

= 0 (Note 6)

LOAD

10

µA

∆V

= 5V to 15V (Note 5)

●

0.003

0.25

0.03

1

%/V

%

LINEREG

I

= 0.5V to 2V, Burst Disabled (Note 5)

LOADREG

TH

I

Input DC Supply Current

Active Mode (PGATE = 0V)

Sleep Mode (Note 6)

Shutdown

(Note 4)

Q

V

IN

V

IN

V

IN

V

IN

= 2.8V to 18V

= 2.8V to 18V, V = 1.5V

= 2.8V to 18V, V

= 2.8V to 18V, V = 0V

150

9

2

235

15

6

µA

FB

= 0V

RUN

Short Circuit

175

275

FB

∆V

Maximum Current Sense Threshold

Minimum Current Sense Threshold

Sleep Current Sense Threshold

Switch Off Time

V

= V

– 20mV

●

110

140

–25

50

180

mV

SENSE(MAX)

SENSE(MIN)

SENSE(SLEEP)

FB

REF

+ 20mV, Burst Disabled

I

= 1V

TH

t

V

FB

V

FB

at Regulated Value

= 0V

3

3.5

70

4

2

µs

OFF

V

Mode Pin Threshold

V

MODE

Rising

0.5

1.3

V

MODE

2

LTC1771

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.

A

V_IN= 10V, V_RUN= open unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

0.5

TYP

1.0

1

MAX

UNITS

V

RUN/SS Pin Threshold

Source Current

V

Rising

RUN/SS

●

2

3

RUN/SS

RUN

I

= 0V, V = 2.8V to 18V

0.3

µA

RUN

IN

PGATE t , t

PGATE Transition Time (Note 7)

Rise Time

Fall Time

r

f

C

= 2000pF

70

140

ns

LOAD

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 4: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note 2: T is calculated from the ambient temperature T and power

Note 5: The LTC1771 is tested in a feedback loop that servos V to the

FB

J

A

dissipation P according to the following formulas:

balance point for the error amplifier (V = 1.23V).

D

ITH

LTC1771S8: T = T + (P )(110°C/W)

Note 6: No-load supply current consists of sleep mode current (9µA

typical) plus a small switching component necessary to overcome

Schottky diode leakage and feedback resistor current.

J

A

D

LTC1771MS8: T = T + (P )(150°C/W)

J

A

D

Note 3: The LTC1771E is guaranteed to meet performance specifications

from 0°C to 70°C. Specifications over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls. The LTC1771I is guaranteed and tested

over the –40°C to 85°C operating temperature range.

Note 7: t and t are measured at 10% to 90% levels.

r

f

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TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Input Voltage

Efficiency vs Load Current

Line Regulation

100

90

100

90

0.4

0.3

Burst Mode OPERATION

ENABLED

FIGURE 1 CIRCUIT

80

0.2

I

= 1A

70

LOAD

0.1

60

50

I

= 100mA

LOAD

I

= 50mA

LOAD

Burst Mode OPERATION

DISABLED

80

0

40

30

20

10

0

I

= 1mA

–0.1

–0.2

–0.3

–0.4

LOAD

I

= 1A

LOAD

70

V

= 10V

IN

FIGURE 1 CIRCUIT

100 1000

LOAD CURRENT (mA)

60

0.1

1

10

2

4

6

8

10 12 14 16 18 20

INPUT VOLTAGE (V)

0

5

10

15

20

INPUT VOLTAGE (V)

1771 G02

1771 G01

1771 G03

3

LTC1771

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TYPICAL PERFOR A CE CHARACTERISTICS

Sleep Quiescent Current

vs Input Voltage

Active Mode Quiescent Current

vs Input Voltage

Load Regulation

12

10

200

150

100

50

0.4

0.2

0

FIGURE 1 CIRCUIT

T

= 100°C

= –50°C

A

T

= 100°C

A

Burst Mode OPERATION

DISABLED

T

= 25°C

A

V

= 15V

= 5V

8

6

IN

T

T = 25°C

A

–0.2

–0.4

–0.6

–0.8

–1.0

T

A

= –50°C

Burst Mode

OPERATION

ENABLED

V

4

2

0

2

4

6

8

10 12 14 16 18 20

0

2

4

6

8

10 12 14 16 18 20

0.5

1.0

2.0

0

1.5

INPUT VOLTAGE (V)

LOAD CURRENT (A)

1771 G06

1771 G05

1771 G04

Current Sense Voltage

vs Temperature

Shutdown Quiescent Current

vs Input Voltage

Run/SS Current vs Input Voltage

200

150

100

50

8

6

4

2

0

5

4

3

V

= 10V

IN

T

= –50°C

A

MAXIMUM

T

= –50°C

A

T

= 25°C

A

BURST THRESHOLD

MINIMUM

2

1

0

T

= 25°C

A

T

= 100°C

A

0

T

= 100°C

A

–50

0

2

4

6

8

10 12 14 16 18 20

–50 –25

0

25

50

75

100

0

2

4

6

8

10 12 14 16 18 20

TEMPERATURE (°C)

INPUT VOLTAGE (V)

1771 G09

1771 G08

1771 G07

Reference Voltage

vs Temperature

Load Step Transient Response

Burst Mode Operation

1.25

1.24

1.23

1.22

V

IN

= 10V

V_OUT

50mV/DIV

100mV/DIV

INDUCTOR

CURRENT

1A/DIV

INDUCTOR

CURRENT

0.5A/DIV

V_IN= 10V

V_OUT= 3.3V

50µs/DIV

1771 G11

V_IN= 10V

V_OUT= 3.3V

10µs/DIV

1771 G12

I_LOAD= 100mA TO 2A

FIGURE 1 CIRCUIT

I_LOAD= 100mA

FIGURE 1 CIRCUIT

1.21

–50 –25

0

25

50

75

100

TEMPERATURE (°C)

1771 G10

4

LTC1771

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PI FU CTIO S

PGATE (Pin 5): High Current Gate Driver for External

P-Channel MOSFET Switch. Voltage swing is from ground

to V_IN.

RUN/SS (Pin 1): The voltage level on this pin controls

shutdown/run mode (ground = shutdown, open/high =

run). Connecting an external capacitor to this pin provides

soft-start.

V_IN(Pin 6): Main Input Voltage Supply Pin.

I_TH(Pin 2): Error Amplifier Compensation Point. The

current comparator threshold increases with this control

voltage. Nominal voltage range for this pin is 0V to 3V.

SENSE(Pin7):CurrentSenseInputforMonitoringSwitch

Current. Maximum switch current and Burst Mode

threshold is programmed with an external resistor be-

tween SENSE and V_IN.

V

_FB(Pin 3): Feedback of Output Voltage for Comparison

to Internal 1.23V Reference. An external resistive divider

across the output is returned to this pin.

MODE (Pin 8): Burst Mode Enable/Disable Pin. Connect-

ing this pin to V_IN(or above 2V) enables Burst Mode

operation, while connecting this pin to ground disables

Burst Mode operation. Do not leave floating.

GND (Pin 4): Ground Pin.

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FUNCTIONAL BLOCK DIAGRA

V

IN

V

IN

V

6

IN

+

1µA

C

READY

IN

C

SS

1.23V

REFERENCE

RUN/SS

1

22k

R

SENSE

MODE

(BURST ENABLE)

8

10% CURRENT

SOFT-START

–

+

ON

1.23V

+

–

C

EA

SENSE

7

ON

10% CURRENT

V

OUT

SLEEP

READY

*

250k

I

TH

2

2V

R

C

1V

BLANKING

C

V

GND

4

IN

–

B

+

PGATE

5

1V

MODE

ON TRIGGER

D1

*

OPTIONAL FOR FOLDBACK

L

1-SHOT

CURRENT LIMITING

3.5µs

STRETCH

V

OUT

R2

V

FB

+

3

C

OUT

R1

1771 BD

5

LTC1771

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OPERATIO

(Refer to Functional Block Diagram)

Main Control Loop

Burst Mode operation is provided by clamping the mini-

mum I_THvoltage at 1V which represents about 25% of

maximumloadcurrent. Iftheloadfallsbelowthislevel, i.e.

the I_THvoltage tries to fall below 1V, the burst comparator

B switches state signaling the LTC1771 to enter sleep

mode.Duringthistime, EAisreducedto10%ofitsnormal

operating current and the external compensation capaci-

tor is disconnected and clamped to 1V so that the EA can

driveitsoutputwiththeloweravailablecurrent.Astheload

discharges the output capacitor, the internal I_THvoltage

increases. When it exceeds 1V the burst comparator exits

sleep mode, reconnects the external compensation com-

ponentstotheerroramplifieroutput, andreturnsEAtofull

power along with the other necessary circuitry. This

scheme (patent pending) allows the EA to be reduced to

such a low operating current during sleep mode without

adding unacceptable delay to wake up the LTC1771 due to

the compensation capacitor on I_THrequired for stability in

normal operation.

The LTC1771 uses a constant off-time, current mode

step-down architecture. During normal operation, the

P-channel MOSFET is turned on at the beginning of each

cycle and turned off when the current comparator C

triggers the 1-shot timer. The external MOSFET switch

stays off for the 3.5µs 1-shot duration and then turns back

on again to begin a new cycle. The peak inductor current

at which C triggers the 1-shot is controlled by the voltage

on Pin 3 (I_TH), the output of the error amplifier EA. An

external resistive divider connected between V_OUTand

ground allows EA to receive an output feedback voltage

V_FB. When the load current increases, it causes a slight

decrease in V_FBrelative to the 1.23V reference, which in

turn causes the I_THvoltage to increase until the average

inductor current matches the new load current.

The main control loop is shut down by pulling Pin 1

(RUN/SS) low. Releasing RUN/SS allows an internal 1µA

current source to charge soft-start capacitor C_SS. When

C_SSreaches 1V, the main control loop is enabled with the

I_THvoltage clamped at approximately 40% of its maxi-

mum value. As C_SScontinues to charge, I_THis gradually

released allowing normal operation to resume.

Burst Mode operation can be disabled by pulling the

MODE pin to ground. In this mode of operation, the burst

comparator B is disabled and the I_THvoltage allowed to go

allthewayto0V.Theloadcannowbereducedtoabout1%

of maximum load before the loop skips cycles to maintain

regulation. This mode provides a low noise output spec-

trum, useful for reducing both audio and RF interference,

at the expense of reduced efficiency at light loads.

Burst Mode Operation

The LTC1771 provides outstanding low current efficiency

and ultralow no-load supply current by using Burst Mode

operation when the MODE pin is pulled above 2V. During

BurstModeoperation,shortburstcyclesofnormalswitch-

ing are followed by a longer idle period with the switch off

and the load current is supplied by the output capacitor.

During this idle period, only the minimum required cir-

cuitry—1.23V reference and error amp—are left on, and

thesupplycurrentisreducedto9µA.Atnoload,theoutput

capacitor is still discharged very slowly by leakage current

in the Schottky diode and feedback resistor current result-

ing in very low frequency burst cycles that add a few more

microamps to the supply current.

Off-Time

The off-time duration is 3.5µs when the feedback voltage

is close to the reference voltage; however, as the feedback

voltage drops, the off-time lengthens and reaches a maxi-

mum value of about 70µs when V_FBis zero. This ensures

that the inductor current has enough time to decay when

the reverse voltage across the inductor is low such as

during short circuit, thus protecting the MOSFET and

inductor.

6

LTC1771

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APPLICATIO S I FOR ATIO

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The basic LTC1771 application circuit is shown in Figure

1 on the first page. External component selection is driven

by the load requirement and begins with the selection of

where t_OFF= 3.5µs. However, the ripple current at low

loads during Burst Mode operation is:

∆I_L(BURST)≈ 35% of I_PEAK≈ 0.05/R_SENSE

R

_SENSE. Once R_SENSEis known, L can be chosen. Next, the

For best efficiency when Burst Mode operation is enabled,

choose:

MOSFET and D1 are selected. The inductor is chosen

based largely on the desired amount of ripple current and

for Burst Mode operation. Finally C_INis selected for its

ability to handle the required RMS input current and C_OUT

is chosen with low enough ESR to meet the output voltage

ripple and transient specifications.

∆I_L(CONT)≤ ∆I_L(BURST)

so that the inductor current is continuous during the burst

periods. This sets a minimum inductor value of:

L

_MIN= (75µH)(V_OUT+ V_D)(R_SENSE)

R

_SENSESelection

Whenburstisdisabled,ripplecurrentslessthan∆I_L(BURST)

can be achieved by choosing L > L_MIN. Lower ripple

current reduces output voltage ripple and core losses, but

too low of ripple current will adversely effect efficiency.

R_SENSEis chosen based on the required output current.

The LTC1771 current comparator has a maximum thresh-

old of 140mV/R_SENSE. The current comparator threshold

sets the peak inductor current, yielding a maximum aver-

age output current I_MAXequal to the peak less half the

peak-to-peak ripple current ∆I_L. For best performance

when Burst Mode operation is enabled, choose ∆I_Lequal

to 35% of peak current. Allowing a margin for variations in

theLTC1771andexternalcomponentsgivesthefollowing

Inductor Core Selection

Once the value of L is known, the type of inductor must be

selected. High efficiency converters generally cannot

afford the core loss found in low cost powdered iron

cores, forcing the use of more expensive ferrite,

molypermalloy or Kool Mµ^®cores. Actual core loss is

independent of core size for a fixed inductor value, but is

very dependent on inductance selected. As inductance

increases, core losses go down. Unfortunately, increased

inductance requires more turns of wire and therefore

copper losses will increase.

equation for choosing R_SENSE

:

R_SENSE= 100mV/I_MAX

At higher supply voltages, the peak currents may be

slightly higher due to overshoot from current comparator

delay and can be predicted from the second term in the

following equation:

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent increase in voltage ripple.

Do not allow the core to saturate!

1/2

0.14

R_SENSE

V – V_OUT

IN

I_PEAK

+ 0.5

L(µH)

Inductor Value Selection

Once R_SENSEis known, the inductor value can be deter-

mined. The inductance value has a direct effect on ripple

current. The ripple current decreases with higher induc-

tance and increases with higher V_OUT. The ripple current

during continuous mode operation is set by the off-time

and inductance to be:

Molypermalloy (from Magnetics, Inc.) is a very good, low

losscorematerialfortoroids,butitismoreexpensivethan

ferrite. A reasonable compromise from the same manu-

facturer is Kool Mµ. Toroids are space efficient, especially

when you can use several layers of wire. Because they

generally lack a bobbin, mounting is more difficult. How-

ever, designs for surface mount are available that do not

increase the height significantly.

V

_OUT+ V_D

∆I_L(CONT)= t_OFF

L

Kool Mµ is a registered trademark of Magnetics, Inc.

7

LTC1771

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APPLICATIO S I FOR ATIO

diode conducts most of the time. As V_INapproaches V_OUT

the diode conducts only a small fraction of the time. The

most stressful condition for the diode is when the output

is short-circuited. Under this condition, the diode must

safely handle I_PEAKat close to 100% duty cycle.

Power MOSFET Selection

An external P-channel power MOSFET must be selected

for use with the LTC1771. The main selection criteria for

the power MOSFET are the threshold voltage V_GS(TH)and

the “on” resistance R_DS(ON), reverse transfer capacitance

and total gate charge.

To maximize both low and high current efficiencies, a fast

switching diode with low forward drop and low reverse

leakage should be used. Low reverse leakage current is

critical to maximize low current efficiency since the leak-

age can potentially exceed the magnitude of the LTC1771

supply current. Low forward drop is critical for high

current efficiency since loss is proportional to forward

drop. The effect of reverse leakage and forward drop on

no-loadsupplycurrentandefficiencyforvariousSchottky

diodes is shown in Table 1. As can be seen, these are

conflicting parameters and the user must weigh the

importance of each spec in choosing the best diode for the

application.

Since the LTC1771 can operate down to input voltages as

low as 2.8V, a sublogic level threshold MOSFET (R_DS(ON)

guaranteed at V_GS= 2.5V) is required for applications that

workclosetothisvoltage.WhentheseMOSFETsareused,

makesurethattheinputsupplytotheLTC1771islessthan

the absolute maximum V_GSrating (typically 12V), as the

MOSFET gate will see the full supply voltage.

The required R_DS(ON)of the MOSFET is governed by its

allowable power dissipation. For applications that may

operate the LTC1771 in dropout, i.e. 100% duty cycle, at

its worst case the required R_DS(ON)is given by:

Table 1. Effect of Catch Diode on Performance

P_P

R_DS(ON)

=

LEAKAGE

NO-LOAD

EFFICIENCY

2

DIODE

(V = 3.3V) V @ 1A SUPPLY CURRENT AT 10V/1A

R

F

I

(

1+ δ

(

P

)

OUT(MAX)

MBR0540

UPS5817

0.25µA

0.50V

10.4µA

11.8µA

12.2µA

14.0µA

20.0µA

86.3%

88.2%

88.4%

87.9%

89.4%

89.8%

where P_Pis the allowable power dissipation and δ_Pis the

temperature dependency of R_DS(ON). (1 + δ_P) is generally

given for a MOSFET in the form of a normalized R_DS(ON)vs

temperature curve, but = 0.005/°C can be used as an

approximation for low voltage MOSFETs.

2.8µA

3.7µA

4.4µA

8.3µA

19.7µA

0.41V

0.36V

0.43V

0.32V

0.29V

MBR0520

MBRS120T3

MBRM120LT3

MBRS320

In applications where the maximum duty cycle is less than

100%andtheLTC1771isincontinuousmode,theR_DS(ON)

is governed by:

C_INand C_OUTSelection

At higher load currents, when the inductor current is

continuous, the source current of the P-channel MOSFET

is a square wave of duty cycle V_OUT/V_IN. To prevent large

voltage transients, a low ESR input capacitor sized for the

maximum RMS current must be used. The maximum

capacitor current is given by:

P_P

R_DS(ON)

=

2

DC I_OUT1+ δ_P

(

)

(

)

V

_OUT+ V_D

DC =

V + V_D

IN

1/2

]

where DC is the maximum operating duty cycle of the

LTC1771.

I_MAX

V

V − V

(

)

[

OUT IN OUT

C_INrequired I_RMS

=

V_IN

Catch Diode Selection

This formula has a maximum at V_IN= 2V_OUT, where

I_RMS= I_OUT/2. This simple worst-case condition is com-

monlyusedfordesignbecauseevensignificantdeviations

donotoffermuchrelief.Notethatcapacitormanufacturer’s

The catch diode carries load current during the off-time.

The average diode current is therefore dependent on the

P-channel switch duty cycle. At high input voltages the

8

LTC1771

W U U

APPLICATIO S I FOR ATIO

U

ripplecurrentratingsareoftenbasedon2000hoursoflife.

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Do not underspecify this component. An addi-

tional 0.1µF ceramic capacitor is also helpful on V_INfor

high frequency decoupling.

size of any aluminum electrolytic at a somewhat higher

price. Typically once the ESR requirement is satisfied, the

RMS current rating generally far exceeds the I_RIPPLE(P-P)

requirement.

In surface mount applications multiple capacitors may

have to be paralleled to meet the ESR or RMS current

handling requirements of the application. Aluminum

electrolyticsanddrytantalumcapacitorsarebothavailable

in surface mount configurations. In case of tantalum, it is

critical that the capacitors are surge tested for use in

switching power supplies. An excellent choice is the

AVX TPS, AVX TPSV and KEMET T510 series of surface

mount tantalums, available in case heights ranging from

2mm to 4mm. Other capacitor types include Sanyo

OS-CON, Sanyo POSCAP, Nichicon PL series and

Panasonic SP.

The selection of C_OUTis driven by the required effective

series resistance (ESR). Typically, once the ESR require-

ment is satisfied, the capacitance is adequate for filtering.

The output ripple (∆V_OUT) in continuous mode is approxi-

mated by:

1

∆V_OUT≈I_RIPPLEESR +

8fC_OUT

where f is the operating frequency, C_OUTis the output

capacitance and I_RIPPLEis the ripple current in the

inductor. For output ripple less than 100mV, assure C_OUT

Efficiency Considerations

required ESR is <2R_SENSE

.

The efficiency of a switching regulator is equal to the

output power divided by the input power times 100%. It is

oftenusefultoanalyzeindividuallossestodeterminewhat

is limiting efficiency and which change would produce the

most improvement. Efficiency can be expressed as:

ThefirstconditionrelatestotheripplecurrentintotheESR

of the output capacitance while the second term guaran-

tees that the output capacitance does not significantly

discharge during the operating frequency period due to

ripple current. The choice of using smaller output capaci-

tance increases the ripple voltage due to the discharging

term but can be compensated for by using capacitors of

very low ESR to maintain the ripple voltage at or below

50mV. The I_THpin OPTI-LOOP^TMcompensation compo-

nents can be optimized to provide stable, high perfor-

mance transient response regardless of the output

capacitors selected.

Efficiency = 100% – (L1 + L2 +L3 + ...)

whereL1, L2, etc. aretheindividuallossesasapercentage

of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in the LTC1771 circuits: the LTC1771 DC bias

current, MOSFET gate charge current, I²R losses and

catch diode losses.

Whenrunningintodropout, extrainputandoutputcapaci-

tance may be necessary for optimal performance due to

the drop in frequency as the duty cycle approaches 100%.

Compare Figure 1 to the low dropout regulators shown in

the Typical Applications section for recommended C_IN,

C_OUT, C_FFand C_Cvalues for low dropout regulators vs

regulators not requiring low dropout.

1. The DC bias current is 9µA at no load and increases

proportionally with load up to a constant 150µA during

continuous mode. This bias current is so small that this

loss is negligible at loads above a milliamp but at no

load accounts for nearly all of the loss.

2. The MOSFET gate charge current results from switch-

ing the gate capacitance of the power MOSFET switch.

Each time the gate is switched from high to low to high

again, a packet of charge dQ moves from V_INto ground.

The resulting dQ/dt is the current out of V_INwhich is

typically much larger than the DC bias current. In

Manufacturers such as Nichicon, United Chemicon and

Sanyoshouldbeconsideredforhighperformancethrough-

hole capacitors. The OS-CON semiconductor dielectric

capacitor available from Sanyo has the lowest ESR for its

OPTI-LOOP is a trademark of Linear Technology Corporation.

9

LTC1771

W U U

U

APPLICATIO S I FOR ATIO

continuous mode, I_GATECHG= fQ_Pwhere Q_Pis the gate

chargeoftheinternalswitch. BoththeDCbiasandgate

charge losses are proportional to V_INand thus their

effects will be more pronounced at higher supply

voltages.

To minimize no-load supply current, resistor values in the

megohm range should be used. The increase in supply

current due to the feedback resistors can be calculated

from:

V_OUTV_OUT

R1+ R2 V_IN

3. I²Rlossesarepredictedfromtheinternalswitch,induc-

tor and current sense resistor. In continuous mode the

averageoutputcurrentflowsthroughLbutis“chopped”

between the P-channel MOSFET in series with R_SENSE

andtheoutputdiode.TheMOSFETR_DS(ON)plusR_SENSE

multiplied by the duty cycle can be summed with the

resistance of L to obtain I²R losses.

∆I_VIN

=

A 5pF feedforward capacitor across R2 is recommended

tominimizeoutputvoltagerippleinBurstModeoperation.

Run/Soft-Start Function

The RUN/SS pin is a dual purpose pin that provides the

soft-startfunctionandameanstoshutdowntheLTC1771.

Soft-start reduces the input surge current from V_INby

gradually increasing the internal current limit. Power

supply sequencing can also be accomplished using

this pin.

4. Thecatchdiodelossisproportionaltotheforwarddrop

asthediodeconductscurrentduringtheoff-timeandis

more pronounced at high supply voltages where the

off-time is long. However, as discussed in the Catch

Diode section, diodes with lower forward drops often

have higher leakage currents, so although efficiency is

improved, the no-load supply current will increase. The

diode loss is calculated by multiplying the forward

voltage drop times the diode duty cycle multiplied by

the load current.

An internal 1µA current source charges up an external

capacitor C_SS. When the voltage on the RUN/SS reaches

1V, the LTC1771 begins operating. As the voltage on the

RUN/SS continues to ramp from 1V to 2.2V, the internal

current limit is also ramped at a proportional linear rate.

The current limits begins near 40% maximum load at

Other losses including C_INand C_OUTESR dissipative

losses, and inductor core losses, generally account for

less than 2% total additional loss.

V_RUN/SS= 1V and ends at maximum load at V_RUN/SS

=

2.2V. The output current thus ramps up slowly, reducing

the starting surge current required from the input power

supply. If the RUN/SS has been pulled all the way to

ground, there will be a delay before the current limit starts

increasing and is given by:

Output Voltage Programming

Theoutputvoltageisprogrammedwithanexternaldivider

from V_OUTto V_FB(Pin 1) as shown in Figure 2. The

regulated voltage is determined by:

t_DELAY≈ C_SS/I_CHG

where I_CHG1µA. Pulling the RUN/SS pin below 0.5V

puts the LTC1771 into a low quiescent current shutdown

(I_Q< 2µA).

R2

V_OUT= 1.23 1+

R1

V

OUT

Foldback Current Limiting

As described in the Catch Diode Selection, the worst-case

dissipation for diode occurs with a short-circuit output,

when the diode conducts the current limit value almost

continuously. In most applications this will not cause

excessive heating, even for extended fault intervals. How-

ever, when heat sinking is at a premium or higher forward

voltage drop diodes are being used, foldback current

C

FF

5pF

R2

V

FB

R1

LTC1771

GND

1771 F02

Figure 2. LTC1771 Adjustable Configuaration

10

LTC1771

W U U

U

APPLICATIO S I FOR ATIO

limiting should be added to reduce the current in propor-

tion to the severity of the fault.

Mode Pin

Burst Mode operation is disabled by pulling MODE (Pin 8)

below 0.5V. Disabling Burst Mode operation provides a

lownoiseoutputspectrum, usefulforreducingbothaudio

and RF interference. It does this by keeping the frequency

constant (for fixed V_IN) down to much lower load current

(1% to 2% of I_MAX) and reducing the amount of output

voltage and current ripple at light loads. When Burst Mode

operation is disabled, efficiency is reduced at light loads

and no load supply current increases to 175µA.

Foldback current limiting is implemented by adding two

diodes in series between the output and the I_THpin as

shown in the Functional Diagram. In a hard short (V_OUT

=

0V) the current will be reduced to approximately 25% of

the maximum output current.

Minimum On-Time Considerations

Minimum on-time t_ON(MIN)is the smallest amount of time

that the LTC1771 is capable of turning the top MOSFET on

andoffagain.Itisdeterminedbyinternaltimingdelaysand

the amount of gate charge required to turn on the

P-channel MOSFET. Low duty cycle applications may

approach this minimum on-time limit and care should be

taken to ensure that:

Low Supply Operation

Although the LTC1771 can function down to 2.8V, the

maximum allowable output current is reduced when V_IN

decreases below 3.2V. Figure 4 shows the amount of

change as the supply is reduced below 3.2V, where 100%

of maximum load equals 0.1/R_SENSE. To ensure adequate

output current at V_IN< 3.2V, simply lower R_SENSEby the

same percentage as the current reduction in Figure 4.

V

_OUT+ V_D

t

_ON= t_OFF

> t_ON(MIN)

V_IN− V_OUT

where t_OFF= 3.5µs and t_ON(MIN)is generally about 0.4µs

140

120

for the LTC1771.

As the on-time approaches t_ON(MIN), the LTC1771 will

remain in Burst Mode operation for an increasingly larger

portion of the load range (see Figure 3) and at or below

t_ON(MIN)will remain in Burst Mode operation 100% of the

time. The output voltage will continue to be regulated, but

the ripple current and ripple voltage will increase.

100

80

60

40

20

0

100

80

60

40

20

0

3.0

3.5

INPUT VOLTAGE (V)

5.0

2.5

4.0

4.5

1771 F04

Figure 4. Maximum Load vs Input Voltage

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1771. These items are also illustrated graphically in

the layout diagram of Figure 5. Check the following in your

layout:

0

0.5

1.0

1.5

2.0

2.5

ON-TIME (µs)

1771 F03

Figure 3. Burst Threshold vs On-Time

1. Is the Schottky diode closely connected to the drain of

the external MOSFET and the input cap ground?

11

LTC1771

W U U

U

APPLICATIO S I FOR ATIO

2. Is the 0.1µF input decoupling capacitor closely con-

nected between V_IN(Pin 6) and ground (Pin 4)? This

capacitor carries the high frequency peak currents.

Design Example

As a design example, assume V_IN= 10V (nominal), V_IN=

15V_(MAX), V_OUT= 3.3V, and I_MAX= 2A. With this informa-

tion, wecaneasilycalculatealltheimportantcomponents.

3. Does the V_FBpin connect directly to the feedback

resistors? The resistive divider R1 and R2 must be

connected between the (+) plate of C_OUTand signal

ground. Locate the feedback resistors right next to the

LTC1771. TheV_FBlineshouldnotberoutedclosetoany

nodes with high slew rates.

R_SENSE= 100mV/2A = 0.05Ω

To optimize low current efficiency, MODE pin is tied to V_IN

to enable Burst Mode operation, thus the minimum induc-

tance necessary is:

L_MIN= 70µH(3.3V + 0.5)(0.05Ω) = 13.3µH

15µH is chosen for the application.

4. Is the 1000pF decoupling capacitor for the current

sense resistor connected as close as possible to Pins 6

and 7? Ensure accurate current sensing with Kelvin

connections to the sense resistor.

3.3V + 0.5V

∆I_L= 3.5µs

= 0.89A

15µH

5. Is the (+) plate of C_INclosely connected to the sense

resistor ? This capacitor provides the AC current to the

MOSFET.

For the feedback resistors, choose R1 = 1M to minimize

supply current. R2 can then be calculated to be:

6. Are the signal and power grounds segregated? The

signal ground consists of the (–) plate of C_OUT, Pin 4 of

theLTC1771andtheresistivedivider.Thepowerground

consists of the Schottky diode anode and the (–) plate

of C_INwhich should have as short lead lengths as

possible.

R2 = (V_OUT/1.23 – 1) • R1 = 1.68M

Assume that the MOSFET dissipation is to be limited to

P_P= 0.25W.

If T_A= 70°C and the thermal resistance of the MOSFET is

83°C/W, then the junction temperatures will be 91°C and

δ_P= 0.33. The required R_DS(ON)for the MOSFET can now

be calculated:

7. Keep the switching node (SW) and the gate node

(PGATE) away from sensitive small signal nodes, espe-

cially the voltage sensing feedback pin (V_FB), and mini-

mize their PC trace area.

0.25W

P -Channel R_DS(ON)

=

2

3.3V + 0.5V

10V + 0.5V

C

SS

2A 1.33

( ) (

)

1

2

3

4

8

7

6

5

RUN/SS

MODE

SENSE

C

ITH

R

ITH

= 0.130Ω

I

TH

LTC1771

R1

V

FB

V

IN

SincethegateoftheMOSFETwillseethefullinputvoltage,

a MOSFET must be selected whose V_GS(MAX)> 15V. A

P-channel MOSFET that meets both the V_GS(MAX)and

R_DS(ON)requirement is the Si6447DQ.

Q1

L

+

C

GND

PGATE

D1

IN

R2

C

FF

C

0.1µF

OUT

The most stringent requirement for the Schottky diode

occurs when V_OUT= 0V (i.e., short circuit) at maximum

V_IN. In this case the worst-case dissipation rises to:

V

OUT

1771 F05

BOLD LINES INDICATE HIGH CURRENT PATHS

Figure 5. LTC1771 Layout Diagram

V_IN

V + V_D

IN

P_D= I_SC(AVG)

V

( )

D

12

LTC1771

W U U

APPLICATIO S I FOR ATIO

U

With a 0.05Ω sense resistor I_SC(AVG)= 2A will result,

increasing the 0.5V Schottky diode dissipation to 1W.

output ripple. The output voltage ripple due to ESR is

approximately:

C_INis chosen for a RMS current rating of at least 1A at

V_ORIPPLE≈ (R_ESR)(∆I_L) = 0.05Ω (0.89A_P-P) = 45mV_P-P

temperature. C_OUTis chosen with an ESR of 0.05Ω for low

U

TYPICAL APPLICATIO S

3.3V to 2.5V/1A Regulator with Burst Mode Operation Enabled

0.01µF

1

2

3

4

8

7

6

5

RUN/SS

MODE

SENSE

220pF

10k

I

TH

1000pF

LTC1771

V

FB

V

IN

V

IN

3.3V

R

+

SENSE

C

GND

TO 12V

PGATE

IN

0.1Ω

33µF

16V

Si3443DV

D1

L1

22µH

1M

1%

1.02M

1%

V

2.5V

1A

OUT

C

OUT

5pF

150µF

6.3V

1771 TA01

C

: AVX TPSC336M016R0300

OUT

IN

: SANYO POSCAP 6TPB150M

D1: MICROSEMI UPS5817

L1: SUMIDA CDRH6D38-220

Low Dropout 5V/2A Regulator with Burst Mode Operation Disabled

0.01µF

1

2

3

4

8

7

6

5

RUN/SS

MODE

SENSE

330pF

10k

I

TH

1000pF

LTC1771

V

FB

IN

V

IN

5.5V

C

R

TO 18V

IN

GND

SENSE

PGATE

+

22µF

25V

×2

0.05Ω

Si6447DQ

D1

L1

22µH

1M

1%

3.09M

1%

V

5V

2A

OUT

C

OUT

15pF

150µF

6.3V

1771 TA04

C

: AVX TPSD226M025R0200

OUT

IN

: SANYO POSCAP 6TPB150M

D1: MICROSEMI UPS5817

L1: SUMIDA CR75-220

13

LTC1771

U

TYPICAL APPLICATIO S

Low Dropout Single Cell Lithium-Ion to 3V

0.01µF

1

8

MODE

RUN/SS

MODE

SENSE

330pF

10k

2

3

4

7

6

5

I

TH

1000pF

LTC1771

V

FB

V

IN

GND

PGATE

+

C

R

IN

Li-Ion

SENSE

47µF

0.05Ω

L1

3.4V TO 4.2V

10V

Si3443DV

D1

15µH

1M

1%

1.43M

1%

V

3V

2A

OUT

C

OUT

15pF

220µF

4V

1771 TA02

C

: TAIYO YUDEN LMK550BJ476MM

OUT

IN

: SANYO POSCAP 4TPB220M

D1: MICROSEMI UPS5817

L1: SUMIDA CR75-150

12V/1A Zeta Converter

V

IN

V

(V)

I

(A)

0.01µF

IN

LOAD(MAX)

1

2

3

4

8

4.5

0.7

0.9

1.8

2.4

2.6

RUN/SS

MODE

SENSE

3.01M

1%

5

220pF

10

15

18

10k

Q1

7

6

5

I

TH

280k

1%

1000pF

LTC1771

V

IN

FB

V

IN

5V

402k

1%

GND

PGATE

C

TO 18V

R

IN

SENSE

+

22µF

25V

×2

0.025Ω

Si6459DQ

1M

1%

8.66M

1%

V

12V

1A

5pF

OUT

•

L1B

47µH

•

L1A

47µH

+

C

OUT

C1

33µF

20V

×2

D1

100µF

C

: AVX TPSD226M025R0200

OUT

20V

IN

: AVX TPSV107M020R0085

1771 TA05

C1: AVX TPSD336M020R0200

D1: MOTOROLA MBRS140T3

L1A, L1B: COILTRONICS VP4-0075, B H ELECTRONICS Q10549

Q1: MOTOROLA MMBT2N2222LT1

2.5V/1A Regulator with Foldback Current Limit

0.01µF

1

2

3

4

8

7

6

5

MODE

RUN/SS

MODE

SENSE

220pF

10k

I

TH

1000pF

LTC1771

V

FB

V

IN

V

IN

2.8V

GND

PGATE

+

C

R

IN

TO 12V

SENSE

0.1Ω

33µF

16V

1M

1%

1.02M

1%

4

5

3

6

2

1

I

U1

TH

5pF

1N4148

L1

22µH

×2

C

: AVX TPSC336M016R0300

: SANYO POSCAP 6TPB150M

L1: SUMIDA CDRH6D38-220

U1: INTERNATIONAL RECTIFIER

FETKY ^TMIRF7422D2

IN

OUT

V

2.5V

1A

OUT

7

8

+

C

OUT

150µF

6.3V

1771 TA06

14

LTC1771

U

TYPICAL APPLICATIONS

4-NiCd/NiMH Battery Charger

0.01µF

1

8

MODE

RUN/SS

MODE

220pF

10k

2

3

4

7

6

5

I

SENSE

LTC1771

TH

1000pF

V

FB

IN

V

IN

8V

R

+

SENSE

C

IN

TO 18V

GND

PGATE

0.1Ω

22µF

25V

Si6447DQ

D1

L1

D2

47µH

1M

1%

4.69M

1%

V

OUT

4-NiCd

1A

C

OUT

5pF

100µF

10V

1771 TA07

C

: AVX TPSD226M025R0200

IN

: SANYO POSCAP 10TPB100M

OUT

D1, D2: MICROSEMI UPS5817

L1: COILTRONICS UP2B-470, GOWANDA SMP3316-472M

U

PACKAGE DESCRIPTIO

Dimension in inches (millimeters) unless otherwise noted.

MS8 Package

8-Lead Plastic MSOP

(LTC DWG # 05-08-1660)

0.118 ± 0.004*

(3.00 ± 0.102)

8

7

6

5

0.040 ± 0.006

(1.02 ± 0.15)

0.034 ± 0.004

(0.86 ± 0.102)

0.007

(0.18)

0° – 6° TYP

0.118 ± 0.004**

(3.00 ± 0.102)

SEATING

PLANE

0.193 ± 0.006

(4.90 ± 0.15)

0.012

(0.30)

REF

0.021 ± 0.006

(0.53 ± 0.015)

0.006 ± 0.004

(0.15 ± 0.102)

0.0256

(0.65)

BSC

MSOP (MS8) 1098

1

2

3

4

* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,

PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

S8 Package

8-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.189 – 0.197*

(4.801 – 5.004)

0.010 – 0.020

(0.254 – 0.508)

7

5

8

6

× 45°

0.053 – 0.069

(1.346 – 1.752)

0.004 – 0.010

(0.101 – 0.254)

0.008 – 0.010

(0.203 – 0.254)

0°– 8° TYP

0.150 – 0.157**

(3.810 – 3.988)

0.228 – 0.244

(5.791 – 6.197)

0.016 – 0.050

(0.406 – 1.270)

0.050

(1.270)

BSC

0.014 – 0.019

(0.355 – 0.483)

TYP

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

SO8 1298

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

1

3

4

2

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

15

LTC1771

U

TYPICAL APPLICATIO

5V/1A Zeta Converter

V

(V)

I

(A)

IN

2.8

LOAD(MAX)

0.8

0.01µF

3.3

5

7.5

10

12

1.1

1

8

1.7

MODE

RUN/SS

MODE

SENSE

220pF

2.3

10k

2

3

4

7

2.7

I

TH

2.9

1000pF

6

LTC1771

V

FB

IN

V

IN

2.8V

5

GND

PGATE

C

TO 12V

R

IN

SENSE

0.025Ω

+

33µF

20V

×2

Si3443DV

1M

1%

3.09M

1%

V

5V

1A

5pF

OUT

•

L1B

22µH

+

C

OUT

C1

100µF

10V

L1A

D1

100µF

C

: AVX TPSD336M020R0200

: SANYO POSCAP 10TPB100M

22µH

IN

OUT

10V

C1: AVX TPSD107M010R065

D1: MICROSEMI UPS5817

1771 TA03

L1A, L1B: COILTRONICS CTX10-4, BH ELECTRONICS S10-1013

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High Efficiency Step-Down DC/DC Converters

with Internal Schottky Diode

LTC1174 with Internal Schottky Diode

LTC1622

Low Input Voltage Step-Down DC/DC Controller

Constant Frequency, 2V to 10V V , MS8

IN

LTC1624

High Efficiency SO-8 N-Channel Switching Regulator Controller

100mA, Low Noise, LDO Micropower Regulators in SOT-23

500mA, Low Noise, LDO Micropower Regulators

95% DC, 3.5V to 36V V

IN

LT^®1761 Series

LT1763 Series

LTC1772

20µA Quiescent Current, 20µV

30µA Quiescent Current, 20µV

Noise

RMS

Constant Frequency Step-Down DC/DC Controller

High Efficiency Monolithic Step-Down Regulator

SOT-23, 2.2V to 9.8V V

IN

LTC1877

550kHz, MS8, V Up to 10V, I = 10µA,

IN Q

I

to 600mA

OUT

LTC1878

High Efficiency Monolithic Step-Down Regulator

550kHz, MS8, V Up to 6V, I = 10µA,

IN Q

I

to 600mA

OUT

1771f LT/TP 1000 4K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

16

●

(408)432-1900 FAX:(408)434-0507 www.linear-tech.com

LINEAR TECHNOLOGY CORPORATION 2000


型号：	LTC1771ES8#PBF
厂家：	Linear
描述：	LTC1771 - 10µA Quiescent Current High Efficiency Step-Down DC/DC Controller; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C 开关光电二极管
文件：	总16页 (文件大小：236K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1771ES8#PBF [Linear]

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