LTC1771IS8 [Linear]

Low Quiescent Current High Efficiency Step-Down DC/DC Controller; 低静态电流高效率降压型DC / DC控制器


型号：	LTC1771IS8
厂家：	Linear
描述：	Low Quiescent Current High Efficiency Step-Down DC/DC Controller 低静态电流高效率降压型DC / DC控制器开关光电二极管控制器
文件：	总16页 (文件大小：208K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Final Electrical Specifications

LTC1771

Low Quiescent Current

High Efficiency Step-Down

DC/DC Controller

February 2000

FEATURES

DESCRIPTIO

The LTC^®1771 is a high efficiency current mode step-

down DC/DC controller that draws as little as 10µA DC

supply current to regulate the output at no load while

maintaining high efficiency for loads up to several amps.

■

Very Low Standby Current: 10µA

■

Available in Space-Saving 8-Lead MSOP Package

■

High Output Currents

■

Wide V_INRange: 2.8V to 20V Operation

■

V_OUTRange: 1.23V to 18V

TheLTC1771drivesanexternalP-channelpowerMOSFET

using a current mode, constant off-time architecture. An

external sense resistor is used to program the operating

current level. Current mode control provides short-circuit

protection, excellent transient response and controlled

start-up behavior. Burst Mode operation enables the

LTC1771 to maintain high efficiency down to extremely

low currents. Shutdown mode further reduces the supply

current to a mere 2µA. For low noise applications, Burst

Mode operation can be easily disabled with the MODE pin.

■

High Efficiency: Over 93% Possible

■

±2% Output Accuracy

■

Very Low Dropout Operation: 100% Duty Cycle

■

Current Mode Operation for Excellent Line and

Load Transient Response

Defeatable Burst Mode^TMOperation

■

Short-Circuit Protected

Optional Programmable Soft-Start

■

Micropower Shutdown: I_Q= 2µA

Wide input supply range of 2.8V to 18V (20V maximum)

and 100% duty cycle operation for low dropout make the

LTC1771 ideal for a wide variety of battery-powered appli-

cations where maximizing battery life is important.

APPLICATIO S

■

Cellular Telephones and Wireless Modems

■

1- to 4-Cell Lithium-Ion-Powered Applications

■

Portable Instruments

The LTC1771’s availability in both 8-lead MSOP and SO

packages provides for a minimum area solution.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode is a trademark of Linear Technology Corporation.

■

Battery-Powered Equipment

■

Battery Chargers

■

Scanners

TYPICAL APPLICATIO

4.5V TO 18V

LTC1771 Efficiency

100

10µF

25V

CER

SENSE

0.05Ω

= 5V

= 10V

SENSE

PGATE

RUN/SS

Si6447DQ

= 15V

15µH

3.3V

OUT

0.01µF

LTC1771

MODE

UPS5817

OUT

10k

GND

150µF

1.64M

6.3V

22OpF

= 3.3V

SENSE

OUT

= 0.05Ω

5pF

0.1

100

1000

10000

1771 F01

LOAD CURRENT (mA)

1771 F01b

Figure 1. High Efficiency Step-Down Converter

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

LTC1771

W W

U W

ABSOLUTE AXI U RATI GS _{(Note 1)}

Input Supply Voltage (V_IN)........................ –0.3V to 20V

Peak Driver Output Current < 10µs (PGATE) ............. 1A

RUN/SS Voltage ........................... –0.3V to (V_IN+ 0.3V)

MODE Voltage .......................................... –0.3V to 20V

I_TH, V_FBVoltage .......................................... –0.3V to 5V

SENSE Voltage (V_IN> 12V)...(V_IN– 12V) to (V_IN+ 0.3V)

SENSE Voltage (V_IN≤ 12V) .......... –0.3V to (V_IN+ 0.3V)

Junction Temperature (Note 2)............................ 125°C

Operating Temperature Range (Note 3)

LTC1771E......................................... –40°C to 85°C

LTC1771I ......................................... –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

U W

PACKAGE/ORDER I FOR ATIO

ORDER PART

NUMBER

ORDER PART

TOP VIEW

NUMBER

TOP VIEW

RUN/SS

MODE

SENSE

RUN/SS 1

8 MODE

7 SENSE

LTC1771ES8

LTC1771IS8

LTC1771EMS8

6 V

5 PGATE

GND 4

GND

PGATE

MS8 PACKAGE

8-LEAD PLASTIC MSOP

S8 PART MARKING

MS8 PART MARKING

LTKD

S8 PACKAGE

8-LEAD PLASTIC SO

T_JMAX= 125°C, θ_JA= 150°C/ W

1771

1771I

T_JMAX= 125°C, θ_JA= 110°C/ W

Consult factory for Military grade parts.

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.

V_IN= 10V, V_RUN= open unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

(Note 5)

MIN

TYP

1.230

MAX

1.255

UNITS

Feedback Voltage

●

1.205

Feedback Current

(Note 5)

SUPPLY

No-Load Supply Current

Reference Voltage Line Regulation

Output Voltage Load Regulation

= 10V, I

= 0 (Note 6)

LOAD

µA

∆V

= 5V to 15V (Note 5)

●

0.003

0.25

0.03

%/V

LINEREG

= 0.5V to 2V, Burst Disabled (Note 5)

LOADREG

Input DC Supply Current

Active Mode (PGATE = 0V)

Sleep Mode (Note 6)

Shutdown

(Note 4)

= 2.8V to 18V

= 2.8V to 18V, V = 1.5V

= 2.8V to 18V, V

= 2.8V to 18V, V = 0V

150

235

µA

= 0V

RUN

Short Circuit

175

275

∆V

Maximum Current Sense Threshold

Minimum Current Sense Threshold

Sleep Current Sense Threshold

Switch Off Time

= V

– 20mV

●

110

0.5

140

–25

180

SENSE(MAX)

SENSE(MIN)

SENSE(SLEEP)

REF

+ 10mV, Burst Disabled

= 1V

at Regulated Value

= 0V

3.5

µs

OFF

Mode Pin Threshold

MODE

Rising

1.3

MODE

LTC1771

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.

V_IN= 10V, V_RUN= open unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

0.5

TYP

1.0

MAX

UNITS

RUN/SS Pin Threshold

Source Current

Rising

RUN/SS

●

RUN/SS

RUN

= 0V, V = 2.8V to 18V

0.3

µA

RUN

PGATE t , t

PGATE Transition Time (Note 7)

Rise Time

Fall Time

= 2000pF

LOAD

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 4: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note 2: T is calculated from the ambient temperature T and power

Note 5: The LTC1771 is tested in a feedback loop that servos V to the

dissipation P according to the following formulas:

balance point for the error amplifier (V = 1.23V).

ITH

LTC1771S8: T = T + (P )(110°C/W)

Note 6: No-load supply current consists of sleep mode current (9µA

typical) plus a small switching component necessary to overcome

Schottky diode leakage and feedback resistor current.

LTC1771MS8: T = T + (P )(150°C/W)

Note 3: The LTC1771E is guaranteed to meet performance specifications

from 0°C to 70°C. Specifications over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls. The LTC1771I is guaranteed and tested

over the –40°C to 85°C operating temperature range.

Note 7: t and t measured at 10% to 90% levels.

PI FU CTIO S

PGATE (Pin 5): High Current Gate Driver for External

P-Channel MOSFET Switch. Voltage swing is from ground

to V_IN.

RUN/SS (Pin 1): The voltage level on this pin controls

shutdown/run mode (ground = shutdown, open/high =

run). Connecting an external capacitor to this pin provides

soft-start.

V_IN(Pin 6): Main Input Voltage Supply Pin.

I_TH(Pin 2): Error Amplifier Compensation Point. The

current comparator threshold increases with this control

voltage. Nominal voltage range for this pin is 0V to 3V.

SENSE(Pin7):CurrentSenseInputforMonitoringSwitch

Current. Maximum switch current and Burst Mode

threshold is programmed with an external resistor be-

tween SENSE and V_IN.

V_FB(Pin 3): Feedback of Output Voltage for Comparison

to Internal 1.23V Reference. An external resistive divider

across the output is returned to this pin.

MODE (Pin 8): Burst Mode Enable/Disable Pin. Connect-

ing this pin to V_IN(or above 2V) enables Burst Mode

operation, while connecting this pin to ground disables

Burst Mode operation. Do not leave floating.

GND (Pin 4): Ground Pin.

LTC1771

FUNCTIONAL BLOCK DIAGRA

1µA

READY

1.23V

REFERENCE

RUN/SS

22k

SENSE

MODE

(BURST ENABLE)

10% CURRENT

SOFT-START

–

1.23V

–

SENSE

10% CURRENT

OUT

SLEEP

READY

250k

BLANKING

GND

–

MODE

ON TRIGGER

OPTIONAL FOR FOLDBACK

1-SHOT

CURRENT LIMITING

3.5µs

STRETCH

OUT

1771 BD

LTC1771

OPERATIO

(Refer to Functional Block Diagram)

Main Control Loop

Burst Mode operation is provided by clamping the mini-

mum I_THvoltage at 1V which represents about 25% of

maximumloadcurrent. Iftheloadfallsbelowthislevel, i.e.

the I_THvoltage tries to fall below 1V, the burst comparator

B switches state signaling the LTC1771 to enter sleep

mode.Duringthistime, EAisreducedto10%ofitsnormal

operating current and the external compensation capaci-

tor is disconnected and clamped to 1V so that the EA can

driveitsoutputwiththeloweravailablecurrent.Astheload

discharges the output capacitor, the internal I_THvoltage

increases. When it exceeds 1V the burst comparator exits

sleep mode, reconnects the external compensation com-

ponentstotheerroramplifieroutput, andreturnsEAtofull

power along with the other necessary circuitry. This

scheme (patent pending) allows the EA to be reduced to

such a low operating current during sleep mode without

adding unacceptable delay to wake up the LTC1771 due to

the compensation capacitor on I_THrequired for stability in

normal operation.

The LTC1771 uses a constant off-time, current mode

step-down architecture. During normal operation, the

P-channel MOSFET is turned on at the beginning of each

cycle and turned off when the current comparator C

triggers the 1-shot timer. The external MOSFET switch

stays off for the 3.5µs 1-shot duration and then turns back

on again to begin a new cycle. The peak inductor current

at which C triggers the 1-shot is controlled by the voltage

on Pin 3 (I_TH), the output of the error amplifier EA. An

external resistive divider connected between V_OUTand

ground allows EA to receive an output feedback voltage

V_FB. When the load current increases, it causes a slight

decrease in V_FBrelative to the 1.23V reference, which in

turn causes the I_THvoltage to increase until the average

inductor current matches the new load current.

The main control loop is shut down by pulling Pin 1

(RUN/SS) low. Releasing RUN/SS allows an internal 1µA

current source to charge soft-start capacitor C_SS. When

C_SSreaches 1V, the main control loop is enabled with the

I_THvoltage clamped at approximately 40% of its maxi-

mum value. As C_SScontinues to charge, I_THis gradually

released allowing normal operation to resume.

Burst Mode operation can be disabled by pulling the

MODE pin to ground. In this mode of operation, the burst

comparator B is disabled and the I_THvoltage allowed to go

allthewayto0V.Theloadcannowbereducedtoabout1%

of maximum load before the loop skips cycles to maintain

regulation. This mode provides a low noise output spec-

trum, useful for reducing both audio and RF interference,

at the expense of reduced efficiency at light loads.

Burst Mode Operation

The LTC1771 provides outstanding low current efficiency

and ultralow no-load supply current by using Burst Mode

operation when the MODE pin is pulled above 2V. During

BurstModeoperation,shortburstcyclesofnormalswitch-

ing are followed by a longer idle period with the switch off

and the load current is supplied by the output capacitor.

During this idle period, only the minimum required cir-

cuitry—1.23V reference and error amp—are left on, and

thesupplycurrentisreducedto9µA.Atnoload,theoutput

capacitor is still discharged very slowly by leakage current

in the Schottky diode and feedback resistor current result-

ing in very low frequency burst cycles that add a few more

microamps to the supply current.

Off-Time

The off-time duration is 3.5µs when the feedback voltage

is close to the reference voltage; however, as the feedback

voltage drops, the off-time lengthens and reaches a maxi-

mum value of about 70µs when V_FBis zero. This ensures

that the inductor current has enough time to decay when

the reverse voltage across the inductor is low such as

during short circuit, thus protecting the MOSFET and

inductor.

LTC1771

W U U

APPLICATIO S I FOR ATIO

The basic LTC1771 application circuit is shown in Figure

1 on the first page. External component selection is driven

by the load requirement and begins with the selection of

where t_OFF= 3.5µs. However, the ripple current at low

loads during Burst Mode operation is:

∆I_L(BURST)≈ 35% of I_PEAK≈ 0.05/R_SENSE

_SENSE. Once R_SENSEis known, L can be chosen. Next, the

For best efficiency when Burst Mode operation is enabled,

choose:

MOSFET and D1 are selected. The inductor is chosen

based largely on the desired amount of ripple current and

for Burst Mode operation. Finally C_INis selected for its

ability to handle the required RMS input current and C_OUT

is chosen with low enough ESR to meet the output voltage

ripple and transient specifications.

∆I_L(CONT)≤ ∆I_L(BURST)

so that the inductor current is continuous during the burst

periods. This sets a minimum inductor value of:

_MIN= (70µH)(V_OUT+ V_D)(R_SENSE)

_SENSESelection

Whenburstisdisabled,ripplecurrentslessthan∆I_L(BURST)

can be achieved by choosing L > L_MIN. Lower ripple

current reduces output voltage ripple and core losses, but

too low of ripple current will adversely effect efficiency.

R_SENSEis chosen based on the required output current.

The LTC1771 current comparator has a maximum thresh-

old of 140mV/R_SENSE. The current comparator threshold

sets the peak inductor current, yielding a maximum aver-

age output current I_MAXequal to the peak less half the

peak-to-peak ripple current ∆I_L. For best performance

when Burst Mode operation is enabled, choose ∆I_Lequal

to 35% of peak current. Allowing a margin for variations in

theLTC1771andexternalcomponentsgivesthefollowing

Inductor Core Selection

Once the value of L is known, the type of inductor must be

selected. High efficiency converters generally cannot

afford the core loss found in low cost powdered iron

cores, forcing the use of more expensive ferrite,

molypermalloy or Kool Mµ^®cores. Actual core loss is

independent of core size for a fixed inductor value, but is

very dependent on inductance selected. As inductance

increases, core losses go down. Unfortunately, increased

inductance requires more turns of wire and therefore

copper losses will increase.

equation for choosing R_SENSE

R_SENSE= 100mV/I_MAX

At higher supply voltages, the peak currents may be

slightly higher due to overshoot from current comparator

delay and can be predicted from the second term in the

following equation:

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent increase in voltage ripple.

Do not allow the core to saturate!

1/2

0.14

R_SENSE

V – V_OUT

I_PEAK

+ 0.5

L(µH)

Inductor Value Selection

Once R_SENSEis known, the inductor value can be deter-

mined. The inductance value has a direct effect on ripple

current. The ripple current decreases with higher induc-

tance and increases with higher V_OUT. The ripple current

during continuous mode operation is set by the off-time

and inductance to be:

Molypermalloy (from Magnetics, Inc.) is a very good, low

losscorematerialfortoroids,butitismoreexpensivethan

ferrite. A reasonable compromise from the same manu-

facturer is Kool Mµ. Toroids are space efficient, especially

when you can use several layers of wire. Because they

generally lack a bobbin, mounting is more difficult. How-

ever, designs for surface mount are available that do not

increase the height significantly.

_OUT+ V_D

∆I_L(CONT)= t_OFF

Kool Mµ is a registered trademark of Magnetics, Inc.

LTC1771

W U U

APPLICATIO S I FOR ATIO

diode conducts most of the time. As V_INapproaches V_OUT

the diode conducts only a small fraction of the time. The

most stressful condition for the diode is when the output

is short-circuited. Under this condition, the diode must

safely handle I_PEAKat close to 100% duty cycle.

Power MOSFET Selection

An external P-channel power MOSFET must be selected

for use with the LTC1771. The main selection criteria for

the power MOSFET are the threshold voltage V_GS(TH)and

the “on” resistance R_DS(ON), reverse transfer capacitance

and total gate charge.

To maximize both low and high current efficiencies, a fast

switching diode with low forward drop and low reverse

leakage should be used. Low reverse leakage current is

critical to maximize low current efficiency since the leak-

age can potentially exceed the magnitude of the LTC1771

supply current. Low forward drop is critical for high

current efficiency since loss is proportional to forward

drop. The effect of reverse leakage and forward drop on

no-loadsupplycurrentandefficiencyforvariousSchottky

diodes is shown in Table 1. As can be seen, these are

conflicting parameters and the user must weigh the

importance of each spec in choosing the best diode for the

application.

Since the LTC1771 can operate down to input voltages as

low as 2.8V, a sublogic level threshold MOSFET (R_DS(ON)

guaranteed at V_GS= 2.5V) is required for applications that

workclosetothisvoltage.WhentheseMOSFETsareused,

makesurethattheinputsupplytotheLTC1771islessthan

the absolute maximum V_GSrating (typically 12V), as the

MOSFET gate will see the full supply voltage.

The required R_DS(ON)of the MOSFET is governed by its

allowable power dissipation. For applications that may

operate the LTC1771 in dropout, i.e. 100% duty cycle, at

its worst case the required R_DS(ON)is given by:

Table 1. Effect of Catch Diode on Performance

P_P

R_DS(ON)

LEAKAGE

NO-LOAD

EFFICIENCY

DIODE

(V = 3.3V) V @ 1A SUPPLY CURRENT AT 10V/1A

(

1+ δ

(

)

OUT(MAX)

MBR0540

UPS5817

0.25µA

0.50V

10.4µA

11.8µA

12.2µA

14.0µA

20.0µA

86.3%

88.2%

88.4%

87.9%

89.4%

89.8%

where P_Pis the allowable power dissipation and δ_Pis the

temperature dependency of R_DS(ON). (1 + δ_P) is generally

given for a MOSFET in the form of a normalized R_DS(ON)vs

temperature curve, but = 0.005/°C can be used as an

approximation for low voltage MOSFETs.

2.8µA

3.7µA

4.4µA

8.3µA

19.7µA

0.41V

0.36V

0.43V

0.32V

0.29V

MBR0520

MBRS120T3

MBRM120LT3

MBRS320

In applications where the maximum duty cycle is less than

100%andtheLTC1771isincontinuousmode,theR_DS(ON)

is governed by:

C_INand C_OUTSelection

At higher load currents, when the inductor current is

continuous, the source current of the P-channel MOSFET

is a square wave of duty cycle V_OUT/V_IN. To prevent large

voltage transients, a low ESR input capacitor sized for the

maximum RMS current must be used. The maximum

capacitor current is given by:

P_P

R_DS(ON)

DC I_OUT1+ δ_P

(

)

(

)

_OUT+ V_D

DC =

V + V_D

1/2

]

where DC is the maximum operating duty cycle of the

LTC1771.

I_MAX

V − V

(

)

[

OUT IN OUT

C_INrequired I_RMS

V_IN

Catch Diode Selection

This formula has a maximum at V_IN= 2V_OUT, where

I_RMS= I_OUT/2. This simple worst-case condition is com-

monlyusedfordesignbecauseevensignificantdeviations

donotoffermuchrelief.Notethatcapacitormanufacturer’s

The catch diode carries load current during the off-time.

The average diode current is therefore dependent on the

P-channel switch duty cycle. At high input voltages the

LTC1771

W U U

APPLICATIO S I FOR ATIO

ripplecurrentratingsareoftenbasedon2000hoursoflife.

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Do not underspecify this component. An addi-

tional 0.1µF ceramic capacitor is also helpful on V_INfor

high frequency decoupling.

electrolyticsanddrytantalumcapacitorsarebothavailable

in surface mount configurations. In case of tantalum, it is

critical that the capacitors are surge tested for use in

switching power supplies. An excellent choice is the

AVX TPS, AVX TPSV and KEMET T510 series of surface

mount tantalums, available in case heights ranging from

2mm to 4mm. Other capacitor types include Sanyo

OS-CON, Sanyo POSCAP, Nichicon PL series and

Panasonic SP.

The selection of C_OUTis driven by the required effective

series resistance (ESR). Typically, once the ESR require-

ment is satisfied, the capacitance is adequate for filtering.

The output ripple (∆V_OUT) in continuous mode is approxi-

mated by:

Efficiency Considerations

The efficiency of a switching regulator is equal to the

output power divided by the input power times 100%. It is

oftenusefultoanalyzeindividuallossestodeterminewhat

is limiting efficiency and which change would produce the

most improvement. Efficiency can be expressed as:

∆V_OUT≈I_RIPPLEESR +

8fC_OUT

where f is the operating frequency, C_OUTis the output

capacitance and I_RIPPLEis the ripple current in the

inductor. For output ripple less than 100mV, assure C_OUT

Efficiency = 100% – (L1 + L2 +L3 + ...)

required ESR is <2R_SENSE

whereL1, L2, etc. aretheindividuallossesasapercentage

of input power.

ThefirstconditionrelatestotheripplecurrentintotheESR

of the output capacitance while the second term guaran-

tees that the output capacitance does not significantly

discharge during the operating frequency period due to

ripple current. The choice of using smaller output capaci-

tance increases the ripple voltage due to the discharging

term but can be compensated for by using capacitors of

very low ESR to maintain the ripple voltage at or below

50mV. The I_THpin OPTI-LOOP^TMcompensation compo-

nents can be optimized to provide stable, high perfor-

mance transient response regardless of the output

capacitors selected.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in the LTC1771 circuits: the LTC1771 DC bias

current, MOSFET gate charge current, I²R losses and

catch diode losses.

1. The DC bias current is 9µA at no load and increases

proportionally with load up to a constant 150µA during

continuous mode. This bias current is so small that this

loss is negligible at loads above a milliamp but at no

load accounts for nearly all of the loss.

2. The MOSFET gate charge current results from switch-

ing the gate capacitance of the power MOSFET switch.

Each time the gate is switched from high to low to high

again, a packet of charge dQ moves from V_INto ground.

The resulting dQ/dt is the current out of V_INwhich is

typically much larger than the DC bias current. In con-

tinuousmode,I_GATECHG=fQ_PwhereQ_Pisthegatecharge

of the internal switch. Both the DC bias and gate charge

losses are proportional to V_INand thus their effects will

be more pronounced at higher supply voltages.

Manufacturers such as Nichicon, United Chemicon and

Sanyoshouldbeconsideredforhighperformancethrough-

hole capacitors. The OS-CON semiconductor dielectric

capacitor available from Sanyo has the lowest ESR for its

size of any aluminum electrolytic at a somewhat higher

price. Typically once the ESR requirement is satisfied, the

RMS current rating generally far exceeds the I_RIPPLE(P-P)

requirement.

In surface mount applications multiple capacitors may

have to be paralleled to meet the ESR or RMS current

handling requirements of the application. Aluminum

3. I²Rlossesarepredictedfromtheinternalswitch,induc-

tor and current sense resistor. In continuous mode the

averageoutputcurrentflowsthroughLbutis“chopped”

OPTI-LOOP is a trademark of Linear Technology Corporation.

LTC1771

W U U

APPLICATIO S I FOR ATIO

between the P-channel MOSFET in series with R_SENSE

andtheoutputdiode.TheMOSFETR_DS(ON)plusR_SENSE

multiplied by the duty cycle can be summed with the

resistance of L to obtain I²R losses.

A 5pF feedforward capacitor across R2 is recommended

tominimizeoutputvoltagerippleinBurstModeoperation.

Run/Soft-Start Function

The RUN/SS pin is a dual purpose pin that provides the

soft-startfunctionandameanstoshutdowntheLTC1771.

Soft-start reduces the input surge current from V_INby

gradually increasing the internal current limit. Power

supply sequencing can also be accomplished using

this pin.

4. Thecatchdiodelossisproportionaltotheforwarddrop

asthediodeconductscurrentduringtheoff-timeandis

more pronounced at high supply voltages where the

off-time is long. However, as discussed in the Catch

Diode section, diodes with lower forward drops often

have higher leakage currents, so although efficiency is

improved, the no-load supply current will increase. The

diode loss is calculated by multiplying the forward

voltage drop times the diode duty cycle multiplied by

the load current.

An internal 1µA current source charges up an external

capacitor C_SS. When the voltage on the RUN/SS reaches

1V, the LTC1771 begins operating. As the voltage on the

RUN/SS continues to ramp from 1V to 2.2V, the internal

current limit is also ramped at a proportional linear rate.

The current limits begins near 40% maximum load at

Other losses including C_INand C_OUTESR dissipative

losses, and inductor core losses, generally account for

less than 2% total additional loss.

V_RUN/SS= 1V and ends at maximum load at V_RUN/SS

2.2V. The output current thus ramps up slowly, reducing

the starting surge current required from the input power

supply. If the RUN/SS has been pulled all the way to

ground, there will be a delay before the current limit starts

increasing and is given by:

Output Voltage Programming

Theoutputvoltageisprogrammedwithanexternaldivider

from V_OUTto V_FB(Pin 1) as shown in Figure 2. The

regulated voltage is determined by:

t_DELAY≈ C_SS/I_CHG

V_OUT= 1.23 1+

where I_CHG1µA. Pulling the RUN/SS pin below 0.5V

puts the LTC1771 into a low quiescent current shutdown

(I_Q< 2µA).

To minimize no-load supply current, resistor values in the

megohm range should be used. The increase in supply

current due to the feedback resistors can be calculated

from:

Foldback Current Limiting

As described in the Catch Diode Selection, the worst-case

dissipation for diode occurs with a short-circuit output,

when the diode conducts the current limit value almost

continuously. In most applications this will not cause

excessive heating, even for extended fault intervals. How-

ever, when heat sinking is at a premium or higher forward

voltage drop diodes are being used, foldback current

limiting should be added to reduce the current in propor-

tion to the severity of the fault.

V_OUTV_OUT

R1+ R2 V_IN

∆I_VIN

OUT

5pF

LTC1771

Foldback current limiting is implemented by adding two

diodes in series between the output and the I_THpin as

GND

shown in the Functional Diagram. In a hard short (V_OUT

1771 F02

0V) the current will be reduced to approximately 25% of

the maximum output current.

Figure 2. LTC1771 Adjustable Configuaration

LTC1771

W U U

APPLICATIO S I FOR ATIO

Minimum On-Time Considerations

1. Is the Schottky diode closely connected to the drain of

the external MOSFET and the input cap ground?

Minimum on-time t_ON(MIN)is the smallest amount of time

that the LTC1771 is capable of turning the top MOSFET on

andoffagain.Itisdeterminedbyinternaltimingdelaysand

the amount of gate charge required to turn on the

P-channel MOSFET. Low duty cycle applications may

approach this minimum on-time limit and care should be

taken to ensure that:

2. Is the 0.1µF input decoupling capacitor closely con-

nected between V_IN(Pin 6) and ground (Pin 4)? This

capacitor carries the high frequency peak currents.

3. Does the V_FBpin connect directly to the feedback

resistors? The resistive divider R1 and R2 must be

connected between the (+) plate of C_OUTand signal

ground. Locate the feedback resistors right next to the

LTC1771. TheV_FBlineshouldnotberoutedclosetoany

nodes with high slew rates.

_OUT+ V_D

_ON= t_OFF

> t_ON(MIN)

V_IN− V_OUT

where t_OFF= 3.5µs and t_ON(MIN)is generally about 0.5µs

4. Is the 1000pF decoupling capacitor for the current

sense resistor connected as close as possible to Pins 6

and 7? Ensure accurate current sensing with Kelvin

connections to the sense resistor.

for the LTC1771.

Ifthedutycyclefallsbelowwhatcanbeaccommodatedby

the minimum on-time, the LTC1771 will remain in Burst

Mode operation even at high load currents. The output

voltage will continue to be regulated, but the ripple current

and ripple voltage will increase.

5. Is the (+) plate of C_INclosely connected to the sense

resistor ? This capacitor provides the AC current to the

MOSFET.

6. Are the signal and power grounds segregated? The

signal ground consists of the (–) plate of C_OUT, Pin 4 of

theLTC1771andtheresistivedivider.Thepowerground

consists of the Schottky diode anode and the (–) plate

of C_INwhich should have as short lead lengths as

possible.

Mode Pin

Burst Mode operation is disabled by pulling MODE (Pin 8)

below 0.5V. Disabling Burst Mode operation provides a

lownoiseoutputspectrum, usefulforreducingbothaudio

and RF interference. It does this by keeping the frequency

constant (for fixed V_IN) down to much lower load current

(1% to 2% of I_MAX) and reducing the amount of output

voltage and current ripple at light loads. When Burst Mode

operation is disabled, efficiency is reduced at light loads

and no load supply current increases to 175µA.

7. Keep the switching node (SW) and the gate node

(PGATE) away from sensitive small signal nodes, espe-

cially the voltage sensing feedback pin (V_FB), and mini-

mize their PC trace area.

8. High impedance nodes such as I_THand V_FBare very

sensitive to leakage paths on the PC board due to stray

flux, solder, epoxy, etc. Make sure PC board is clean.

Water-soluble solder flux can be especially leaky if not

cleaned properly. Leakage on I_THwill manifest itself as

excessive output ripple during Burst Mode operation. If

the problem persists, adding a 10M resistor from Pin 2

to ground should eliminate the problem.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1771. These items are also illustrated graphically in

the layout diagram of Figure 3. Check the following in your

layout:

LTC1771

W U U

APPLICATIO S I FOR ATIO

Design Example

0.25W

P -Channel R_DS(ON)

As a design example, assume V_IN= 10V (nominal), V_IN=

15V_(MAX), V_OUT= 3.3V, and I_MAX= 2A. With this informa-

tion, wecaneasilycalculatealltheimportantcomponents.

3.3V + 0.5V

10V + 0.5V

2A 1.33

( ) (

)

= 0.130Ω

R_SENSE= 100mV/2A = 0.05Ω

SincethegateoftheMOSFETwillseethefullinputvoltage,

a MOSFET must be selected whose V_GS(MAX)> 15V. A

P-channel MOSFET that meets both the V_GS(MAX)and

R_DS(ON)requirement is the Si6447DQ.

To optimize low current efficiency, MODE pin is tied to V_IN

to enable Burst Mode operation, thus the minimum induc-

tance necessary is:

L_MIN= 70µH(3.3V + 0.5)(0.05Ω) = 13.3µH

15µH is chosen for the application.

The most stringent requirement for the Schottky diode

occurs when V_OUT= 0V (i.e., short circuit) at maximum

V_IN. In this case the worst-case dissipation rises to:

3.3V + 0.5V

∆I_L= 3.5µs

= 0.89A

15µH

V_IN

V + V_D

P_D= I_SC(AVG)

( )

For the feedback resistors, choose R1 = 1M to minimize

supply current. R2 can then be calculated to be:

With a 0.05Ω sense resistor I_SC(AVG)= 2A will result,

increasing the 0.5V Schottky diode dissipation to 1W.

R2 = (V_OUT/1.23 – 1) • R1 = 1.68M

Assume that the MOSFET dissipation is to be limited to

P_P= 0.25W.

_INis chosen for a RMS current rating of at least 1A at

temperature. C_OUTis chosen with an ESR of 0.05Ωfor low

output ripple. The output voltage ripple due to ESR is

approximately:

If T_A= 70°C and the thermal resistance of the MOSFET is

83°C/W, then the junction temperatures will be 91°C and

δ_P= 0.33. The required R_DS(ON)for the MOSFET can now

be calculated:

_ORIPPLE≈ (R_ESR)(∆I_L) = 0.05Ω (0.89A_P-P) = 45mV_P-P

RUN/SS

MODE

SENSE

ITH

LTC1771

GND

PGATE

0.1µF

OUT

1771 F03

BOLD LINES INDICATE HIGH CURRENT PATHS

Figure 3. LTC1771 Layout Diagram

LTC1771

TYPICAL APPLICATIO S

3.3V to 2.5V/1A Regulator with Burst Mode Operation Enabled

0.01µF

RUN/SS

MODE

SENSE

220pF

10k

1000pF

LTC1771

3.3V

GND

PGATE

SENSE

TO 12V

0.1Ω

22µF

Si3443DV

25V

22µH

1.02M

2.5V

OUT

5pF

UPS5817

150µF

6.3V

1771 TA01

5V/2A Regulator with Burst Mode Operation Disabled

0.01µF

RUN/SS

MODE

SENSE

220pF

10k

1000pF

LTC1771

5.5V

GND

PGATE

TO 18V

SENSE

22µF

0.05Ω

Si6447DQ

25V

22µH

3.09M

OUT

5pF

UPS5817

150µF

6.3V

1771 TA04

LTC1771

TYPICAL APPLICATIO S

Low Dropout Single Cell Lithium-Ion to 3V

0.01µF

MODE

RUN/SS

220pF

10k

SENSE

1000pF

LTC1771

GND

PGATE

Li-Ion

SENSE

22µF

0.05Ω

3.3V TO 4.2V

Si3443DV

UPS5817

25V

15µH

1.43M

OUT

5pF

150µF

6.3V

1771 TA02

12V/1A Zeta Converter

0.01µF

RUN/SS

MODE

220pF

10k

SENSE

1000pF

LTC1771

GND

PGATE

TO 18V

SENSE

22µF

0.025Ω

Si6435DQ

25V

8.66M

47µH

12V

5pF

OUT

•

OUT

22µF

20V

UPS5817

150µF

47µH

20V

1771 TA05

LTC1771

TYPICAL APPLICATIONS

2.5V/1A Regulator with Foldback Current Limit

0.01µF

RUN/SS

MODE

SENSE

220pF

10k

1000pF

LTC1771

2.8V

GND

PGATE

TO 12V

SENSE

22µF

0.1Ω

25V

1.02M

5pF

1N4148

×2

22µH

2.5V

OUT

U1: INTERNATIONAL RECTIFIER

FETKY ^TMIRF7422D2

OUT

150µF

6.3V

1771 TA06

4-NiCd Battery Charger

0.01µF

RUN/SS

MODE

SENSE

220pF

10k

1000pF

LTC1771

GND

PGATE

SENSE

TO 18V

0.1Ω

22µF

Si6447DQ

25V

UPS5817

47µH

4.69M

OUT

4-NiCd

OUT

5pF

UPS5817

100µF

10V

1771 TA07

LTC1771

PACKAGE DESCRIPTIO

Dimension in inches (millimeters) unless otherwise noted.

MS8 Package

8-Lead Plastic MSOP

(LTC DWG # 05-08-1660)

0.118 ± 0.004*

(3.00 ± 0.102)

0.118 ± 0.004**

(3.00 ± 0.102)

0.193 ± 0.006

(4.90 ± 0.15)

0.040 ± 0.006

0.034 ± 0.004

(0.86 ± 0.102)

(1.02 ± 0.15)

0.007

(0.18)

0° – 6° TYP

SEATING

PLANE

0.012

(0.30)

REF

0.021 ± 0.006

(0.53 ± 0.015)

0.006 ± 0.004

(0.15 ± 0.102)

0.0256

(0.65)

BSC

MSOP (MS8) 1098

* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,

PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

S8 Package

8-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.189 – 0.197*

(4.801 – 5.004)

0.150 – 0.157**

(3.810 – 3.988)

0.228 – 0.244

(5.791 – 6.197)

0.010 – 0.020

(0.254 – 0.508)

× 45°

0.053 – 0.069

(1.346 – 1.752)

0.004 – 0.010

(0.101 – 0.254)

0.008 – 0.010

(0.203 – 0.254)

0°– 8° TYP

0.016 – 0.050

(0.406 – 1.270)

0.050

(1.270)

BSC

0.014 – 0.019

(0.355 – 0.483)

TYP

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

SO8 1298

LTC1771

TYPICAL APPLICATIO

5V/1A Zeta Converter

(V)

2.8

3.3

7.5

(A)

LOAD(MAX)

0.8

0.01µF

1.1

1.7

MODE

RUN/SS

MODE

220pF

2.3

10k

2.7

SENSE

LTC1771

2.9

1000pF

2.8V

GND

PGATE

TO 12V

SENSE

22µF

0.025Ω

Si3443DV

25V

3.09M

22µH

5pF

OUT

•

OUT

22µF

10V

UPS5817

150µF

22µH

6.3V

1771 TA03

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

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1771i LT/TP 0200 4K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408)432-1900 FAX:(408)434-0507 www.linear-tech.com

LINEAR TECHNOLOGY CORPORATION 2000

LTC1771IS8 [Linear]

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