LTC1860IS8 [Linear]
mPower, 12-Bit, 250ksps 1- and 2-Channel ADCs in MSOP; 的mPower ， 12位， 250ksps的1和2通道ADC ，采用MSOP
| 型号： | LTC1860IS8 |
| 厂家： | 
Linear |
| 描述： | mPower, 12-Bit, 250ksps 1- and 2-Channel ADCs in MSOP |
| 文件： | 总12页 (文件大小：170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1860/LTC1861
µPower, 12-Bit, 250ksps
1- and 2-Channel ADCs in MSOP
U
FEATURES
DESCRIPTIO
TheLTC®1860/LTC1861are12-bitA/Dconvertersthatare
offered in MSOP and SO-8 packages and operate on a
single 5V supply. At 250ksps, the supply current is only
850µA. The supply current drops at lower speeds because
the LTC1860/LTC1861 automatically power down to a
typical supply current of 1nA between conversions. These
12-bitswitchedcapacitorsuccessiveapproximationADCs
include sample-and-holds.TheLTC1860hasadifferential
analoginputwithanadjustablereferencepin.TheLTC1861
offers a software-selectable 2-channel MUX and an ad-
justable reference pin on the MSOP version.
■
12-Bit 250ksps ADCs in MSOP Package
■
Single 5V Supply
■
Low Supply Current: 850µA (Typ)
Auto Shutdown Reduces Supply Current
■
to 2µA at 1ksps
True Differential Inputs
■
■
1-Channel (LTC1860) or 2-Channel (LTC1861)
Versions
SPI/MICROWIRETM Compatible Serial I/O
■
■
High Speed Upgrade to LTC1286/LTC1298
■
Pin Compatible with 16-Bit LTC1864/LTC1865
The 3-wire, serial I/O, MSOP or SO-8 package and
extremely high sample rate-to-power ratio make these
ADCs ideal choices for compact, low power, high speed
systems.
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APPLICATIO S
■
High Speed Data Acquisition
Portable or Compact Instrumentation
Low Power Battery-Operated Instrumentation
Isolated and/or Remote Data Acquisition
■
TheseADCscanbeusedinratiometricapplicationsorwith
external references. The high impedance analog inputs
and the ability to operate with reduced spans down to 1V
full scale, allow direct connection to signal sources in
many applications, eliminating the need for external gain
stages.
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
U
TYPICAL APPLICATIO
Supply Current vs Sampling Frequency
Single 5V Supply, 250ksps, 12-Bit Sampling ADC
1000
1µF
100
10
5V
LTC1860
1
2
3
4
8
7
6
V
V
CC
REF
+
1
IN
IN
SCK
SDO
ANALOG INPUT
0V TO 5V
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
–
0.1
0.01
5
GND
CONV
1860 TA01
0.01
0.1
1
10
100
1000
SAMPLING FREQUENCY (kHz)
1860 TA02
18601f
1
LTC1860/LTC1861
W W
U W
ABSOLUTE AXI U RATI GS
(Notes 1, 2)
Power Dissipation.............................................. 400mW
Operating Temperature Range
Supply Voltage (VCC) ................................................. 7V
Ground Voltage Difference
LTC1860C/LTC1861C............................. 0°C to 70°C
LTC1860I/LTC1861I .......................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
AGND, DGND LTC1861 MSOP Package ........... ±0.3V
Analog Input .................... (GND – 0.3V) to (VCC + 0.3V)
Digital Input ..................................... (GND – 0.3V) to 7V
Digital Output .................. (GND – 0.3V) to (VCC + 0.3V)
U W
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
TOP VIEW
TOP VIEW
NUMBER
V
IN
1
2
3
4
8 V
CC
REF
CONV
CH0
1
2
3
4
5
10
9
V
V
SCK
SDO
SDI
REF
CC
+
7 SCK
LTC1860CMS8
LTC1860IMS8
LTC1861CMS
LTC1861IMS
6 SDO
5 CONV
IN¯
CH1
8
GND
AGND
DGND
7
6
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING
MS PART MARKING
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 210°C/W
LTWR
LTWS
LTWT
LTWU
TJMAX = 150°C, θJA = 210°C/W
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
1
2
3
4
8
7
6
5
CONV
CH0
V
CC
1
2
3
4
8
7
6
5
V
V
CC
REF
+
SCK
SDO
SDI
IN
IN
SCK
LTC1860CS8
LTC1860IS8
LTC1861CS8
LTC1861IS8
–
CH1
SDO
CONV
GND
GND
S8 PART MARKING
S8 PART MARKING
S8 PACKAGE
8-LEAD PLASTIC SO
S8 PACKAGE
8-LEAD PLASTIC SO
1861
1861I
1860
1860I
TJMAX = 150°C, θJA = 175°C/W
TJMAX = 150°C, θJA = 175°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
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CO VERTER A D ULTIPLEXER CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.
VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
A
PARAMETER
Resolution
CONDITIONS
MIN
12
TYP
MAX
UNITS
Bits
●
●
●
No Missing Codes Resolution
INL
12
Bits
(Note 3)
±1
LSB
Transition Noise
Gain Error
0.07
LSB
RMS
●
±20
mV
Offset Error
LTC1860 SO-8 and MSOP, LTC1861 MSOP
LTC1861 SO-8
●
●
±2
±3
±5
±7
mV
mV
+
–
Input Differential Voltage Range
Absolute Input Range
V
= IN – IN
●
0
V
V
IN
+
REF
IN Input
–0.05
–0.05
V
+ 0.05
V
V
CC
V
–
IN Input
/2
CC
V
Input Range
LTC1860 S0-8 and MSOP, LTC1861 MSOP
(Note 4)
1
V
V
REF
CC
Analog Input Leakage Current
Input Capacitance
●
±1
µA
C
IN
In Sample Mode
During Conversion
12
5
pF
pF
18601f
2
LTC1860/LTC1861
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DY A IC ACCURACY
T = 25°C. V = 5V, f
SAMPLE
= 250kHz, unless otherwise specified.
CONDITIONS
A
CC
SYMBOL PARAMETER
SNR Signal-to-Noise Ratio
S/(N + D) Signal-to-Noise Plus Distortion Ratio
THD Total Hamonic Distortion Up to 5th Harmonic 100kHz Input Signal
MIN
TYP
72
MAX
UNITS
dB
100kHz Input Signal
71
dB
77
dB
Full Power Bandwidth
20
MHz
kHz
Full Linear BaU ndwidth
S/(N + D) ≥ 68dB
125
DIGITAL A DDCELECTRICALCHARACTERISTICS
The ● denotes specifications which apply
over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
IH
V
IL
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 5.25V
= 4.75V
●
●
●
●
2.4
CC
CC
IN
0.8
2.5
V
I
I
= V
µA
µA
IH
IL
CC
= 0V
–2.5
IN
V
OH
V
CC
V
CC
= 4.75V, I = 10µA
= 4.75V, I = 360µA
●
●
4.5
2.4
4.74
4.72
V
V
O
O
V
Low Level Output Voltage
Hi-Z Output Leakage
Output Source Current
Output Sink Current
V
= 4.75V, I = 1.6mA
●
●
0.4
V
µA
OL
CC
O
I
I
I
I
CONV = V
±3
OZ
CC
V
OUT
V
OUT
= 0V
–25
20
mA
mA
SOURCE
SINK
= V
CC
Reference Current (LTC1860 SO-8, MSOP and CONV = V
LTC1861 MSOP)
●
●
0.001
0.05
3
0.1
µA
mA
REF
CC
f
= f
SMPL
SMPL(MAX)
I
Supply Current
CONV = V After Conversion
●
●
0.001
0.85
3
1.3
µA
mA
CC
CC
f
= f
SMPL
SMPL(MAX)
P
D
Power Dissipation
f
= f
4.25
mW
SMPL
SMPL(MAX)
W U
U
U
U
W
The ● denotes specifications which apply over the
RECO E DED OPERATI G CO DITIO S
full operating temperature range, otherwise specifications are TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
5.25
20
UNITS
V
V
Supply Voltage
4.75
CC
f
t
t
Clock Frequency
●
DC
MHz
µs
SCK
CYC
SMPL
Total Cycle Time
12 • SCK + t
CONV
Analog Input Sampling Time
LTC1860
LTC1861
12
10
SCK
SCK
t
Setup Time CONV↓ Before First SCK↑,
(See Figure 1)
30
ns
suCONV
t
t
t
t
t
Holdtime SDI After SCK↑
Setup Time SDI Stable Before SCK↑
SCK High Time
LTC1861
LTC1861
15
15
ns
ns
hDI
suDI
f
f
= f
SCK(MAX)
= f
SCK(MAX)
40%
40%
1/f
1/f
WHCLK
WLCLK
WHCONV
SCK
SCK
SCK
SCK Low Time
SCK
CONV High Time Between Data
Transfer Cycles
t
µs
CONV
t
t
CONV Low Time During Data Transfer
12
13
SCK
ns
WLCONV
hCONV
Hold Time CONV Low After Last SCK↑
18601f
3
LTC1860/LTC1861
W U
The ● denotes specifications which apply over the full operating temperature
TI I G CHARACTERISTICS
range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating
Conditions, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
µs
t
f
t
Conversion Time (See Figure 1)
Maximum Sampling Frequency
Delay Time, SCK↓ to SDO Data Valid
●
●
2.75
3.2
CONV
250
kHz
SMPL(MAX)
dDO
C
= 20pF
15
20
25
ns
ns
LOAD
●
●
●
●
t
t
t
Delay Time, CONV↑ to SDO Hi-Z
30
30
10
60
60
ns
ns
ns
dis
en
Delay Time, CONV↓ to SDO Enabled
C
C
= 20pF
= 20pF
LOAD
LOAD
Time Output Data Remains
Valid After SCK↓
5
hDO
t
t
SDO Rise Time
SDO Fall Time
C
C
= 20pF
= 20pF
8
4
ns
ns
r
f
LOAD
LOAD
Note 1: Absolute Maximum Ratings are those values beyond which the life
Note 3: Integral nonlinearity is defined as deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 4: Channel leakage current is measured while the part is in sample
mode.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Sampling
Frequency
Sleep Current vs Temperature
Supply Current vs Temperature
1000
800
600
400
200
0
1000
900
800
700
600
500
400
300
200
100
0
1000
100
10
= 5V
CONV = V
CC
CONV LOW = 800ns
TA = 25°C
V
= 5V
CC
1
CONV HIGH = 3.2µS
0.1
f
= 250kHz
SMPL
V
V
= 5V
REF
CC
= 5V
0.01
–50
0
25
50
75 100 125
125
–25
–50
0
50
TEMPERATURE (°C)
25
75 100
–25
0.01
0.1
1.0
10
100
1000
TEMPERATURE (°C)
SAMPLING FREQUENCY (kHz)
1860/61 G02
1860/61 G03
1860/61 G01
18601f
4
LTC1860/LTC1861
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Reference Current vs
Reference Voltage
Reference Current vs
Sample Rate
Reference Current vs
Temperature
60
50
40
30
20
10
0
60
50
40
30
20
10
0
55
54
53
52
51
50
49
48
47
46
45
f
= 250kHz
= 25°C
= 5V
f
V
V
= 250kHz
= 5V
REF
CONV IS LOW FOR 800ns
S
A
CC
S
CC
T
T
V
V
= 25°C
A
V
= 5V
= 5V
CC
= 5V
REF
0
50
100
150
200
250
0
1
2
3
4
5
–50
0
25
50
75 100 125
–25
SAMPLE RATE (kHz)
V
REF
(V)
TEMPERATURE (°C)
1860/61 G04
1860/61 G06
1860/61 G05
Analog Input Leakage vs
Temperature
Typical INL Curve
Typical DNL Curve
100
75
50
25
0
1.0
0.5
1.0
0.5
T
V
V
= 25°C
T
V
V
= 25°C
V
V
= 5V
= 5V
A
A
CC
REF
CONV = 0V
= 5V
= 5V
CC
CC
= 5V
= 5V
REF
REF
0
0
–0.5
–1.0
–0.5
–1.0
–25
0
25
50
75
125
–50
100
0
512
1536 2048 2560 3072
3584
4096
1024
2048
0
512
1536
2560 3072
4096
3584
1024
TEMPERATURE (°C)
CODE
CODE
1860/61 G09
1860/61 G07
1860/61 G07
Change in Gain Error vs
Reference Voltage
Change in Offset Error vs
Reference Voltage
Change in Offset vs Temperature
5
4
1.0
0.8
5
4
T
= 25°C
CC
V
CC
= 5V
V
= 5V
A
CC
V
= 5V
T
A
= 25°C
3
0.6
3
2
0.4
2
1
0.2
1
0
0
0
–1
–2
–3
–4
–5
–0.2
–0.4
–0.6
–0.8
–1.0
–1
–2
–3
–4
–5
0
1
2
3
4
5
–50
0
25
50
75 100 125
0
2
3
4
5
–25
1
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
REFERENCE VOLTAGE(V)
1860/61 G10
1860/61 G11
1860/61 G12
18601f
5
LTC1860/LTC1861
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Signal-to-(Noise + Distortion)
vs Input Level
Change in Gain Error vs
Temperature
4096 Point FFT
0
–20
1.0
0.8
80
70
60
50
40
30
20
10
0
V
V
= 5V
= 5V
f
f
= 204.1kHz
= 99.5kHz
= 25°C
f
= 10kHz
CC
REF
S
IN
A
T
= 25°C
IN
T
V
= 5V
CC
A
0.6
V
= 5V
CC
0.4
–40
0.2
–60
0
–0.2
–0.4
–0.6
–0.8
–1.0
–80
–100
–120
–40 –35 –30 –25 –20 –15 –10 –5
INPUT LEVEL (dB)
0
0
10 20 30 40 50 60 70 80 90 100
f (kHz)
–50
0
25
50
75 100 125
–25
TEMPERATURE (°C)
1195 G20
1860/61 G15
1860/61 G13
Signal-to-(Noise + Distortion)
vs fIN
Total Harmonic Distortion
vs fIN
Spurious Free Dynamic Range
vs fIN
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
TA = 25°C
T
V
V
= 25°C
A
V
CC
V
IN
= 5V
= 0dB
= 5V
CC
= 0dB
IN
SNR
SINAD
T
V
V
= 25°C
A
= 5V
CC
= 0dB
IN
1
10
100
1000
1
10
100
1000
10000
1
10
100
1000
f
(kHz)
f
(kHz)
f
(kHz)
IN
IN
IN
1860/61 G18
1860/61 G17
1860/61 G16
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PI FU CTIO S
LTC1860
high after the A/D conversion is finished, the part powers
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
VREF (Pin 1): Reference Input. The reference input defines
the span of the A/D converter and must be kept free of
noise with respect to GND.
IN+, IN– (Pins 2, 3): Analog Inputs. These inputs must be
free of noise with respect to GND.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this pin.
SCK(Pin7):ShiftClockInput. Thisclocksynchronizesthe
serial data transfer.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
V
CC (Pin 8): Positive Supply. This supply must be kept
CONV (Pin 5): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
free of noise and ripple by bypassing directly to the
analog ground plane.
18601f
6
LTC1860/LTC1861
U
U
U
PI FU CTIO S
LTC1861 (MSOP Package)
LTC1861 (SO-8 Package)
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
high after the A/D conversion is finished, the part powers
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
high after the A/D conversion is finished, the part powers
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to AGND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
AGND (Pin 4): Analog Ground. AGND should be tied
directly to an analog ground plane.
DGND (Pin 5): Digital Ground. DGND should be tied
directly to an analog ground plane.
SDI (Pin 5): Digital Data Input. The A/D configuration
word is shifted into this input.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
SDI (Pin 6): Digital Data Input. The A/D configuration
word is shifted into this input.
SCK(Pin7):ShiftClockInput. Thisclocksynchronizesthe
serial data transfer.
SDO (Pin 7): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK(Pin8):ShiftClockInput. Thisclocksynchronizesthe
VCC (Pin 8): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane. VREF is tied internally to this pin.
serial data transfer.
VCC (Pin 9): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane.
VREF (Pin 10): Reference Input. The reference input de-
fines the span of the A/D converter and must be kept free
of noise with respect to AGND.
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FUNCTIONAL BLOCK DIAGRA
V
CC
(SDI) SCK
CONV
PIN NAMES IN
PARENTHESES
REFER TO LTC1861
SDO
SERIAL
PORT
CONVERT
CLK
BIAS AND
SHUTDOWN
DATA IN
12-BITS
+
IN
+
–
(CH0)
12-BIT
SAMPLING
ADC
DATA OUT
–
IN
(CH1)
1860/61 BD
GND
V
REF
18601f
7
LTC1860/LTC1861
TEST CIRCUITS
Load Circuit for tdDO, tr, tf, tdis and ten
Voltage Waveforms for SDO Rise and Fall Times, tr, tf
TEST POINT
V
OH
SDO
V
OL
V
t
WAVEFORM 2, t
3k
CC dis
en
SDO
t
WAVEFORM 1
dis
t
t
f
1860 TC04
r
20pF
1860 TC01
Voltage Waveforms for ten
Voltage Waveforms for tdis
CONV
V
CONV
IH
SDO
1860 TC03
t
en
SDO
WAVEFORM 1
(SEE NOTE 1)
90%
10%
t
dis
Voltage Waveforms for SDO Delay Times, tdDO and thDO
SDO
WAVEFORM 2
(SEE NOTE 2)
SCK
V
IL
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
t
dDO
t
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
hDO
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
V
V
OH
OL
1860 TC05
SDO
1860 TC02
W U U
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APPLICATIO S I FOR ATIO
LTC1860 OPERATION
Analog Inputs
The LTC1860 has a unipolar differential analog input. The
converter will measure the voltage between the “IN+” and
“IN–” inputs. A zero code will occur when IN+ minus IN–
equals zero. Full scale occurs when IN+ minus IN– equals
VREF minus 1LSB. See Figure 2. Both the “IN+” and
“IN–” inputs are sampled at the same time, so common
mode noise on the inputs is rejected by the ADC. If “IN–”
isgroundedandVREF istiedtoVCC, arail-to-railinputspan
will result on “IN+” as shown in Figure 3.
Operating Sequence
The LTC1860 conversion cycle begins with the rising edge
of CONV. After a period equal to tCONV, the conversion is
finished. If CONV is left high after this time, the LTC1860
goesintosleepmodedrawingonlyleakagecurrent. Onthe
fallingedgeofCONV, theLTC1860goesintosamplemode
and SDO is enabled. SCK synchronizes the data transfer
with each bit being transmitted from SDO on the falling
SCK edge. The receiving system should capture the data
from SDO on the rising edge of SCK. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefinitely. See Figure 1.
Reference Input
ThevoltageonthereferenceinputoftheLTC1860(andthe
LTC1861 MSOP package) defines the full-scale range of
the A/D converter. These ADCs can operate with reference
voltages from VCC to 1V.
18601f
8
LTC1860/LTC1861
W U U
APPLICATIO S I FOR ATIO
U
CONV
t
SMPL
SLEEP MODE
t
CONV
1
2
3
4
5
6
7
8
9 10 11 12
SCK
SDO
B10
B8 B7 B6 B5 B4 B3 B2 B1 B0*
B11
B9
Hi-Z
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER
SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC
WILL OUTPUT ZEROS INDEFINITELY
1860 F01
Figure 1. LTC1860 Operating Sequence
1µF
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
V
CC
•
•
•
LTC1860
1
2
3
4
8
7
6
V
V
REF
+
CC
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
V
= 0V TO V
CC
IN
IN
SCK
V
*
IN
IN
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
–
SDO
5
+
–
*V = IN – IN
GND
CONV
IN
1860 F03
1860 F02
Figure 2. LTC1860 Transfer Curve
Figure 3. LTC1860 with Rail-to-Rail Input Span
LTC1861 OPERATION
Operating Sequence
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following table.
In single-ended mode, all input channels are measured
with respect to GND (or AGND). A zero code will occur
when the “+” input minus the “–” input equals zero. Full
scale occurs when the “+” input minus the “–” input
equals VREF minus 1LSB. See Figure 5. Both the “+” and
“–” inputs are sampled at the same time so common
mode noise is rejected. The input span in the SO-8
package is fixed at VREF = VCC. If the “–” input in
differential mode is grounded, a rail-to-rail input span
will result on the “+” input.
TheLTC1861conversioncyclebeginswiththerisingedge
of CONV. After a period equal to tCONV, the conversion is
finished. If CONV is left high after this time, the LTC1861
goes into sleep mode. The LTC1861’s 2-bit data word is
clocked into the SDI input on the rising edge of SCK after
CONV goes low. Additional inputs on the SDI pin are then
ignored until the next CONV cycle. The shift clock (SCK)
synchronizes the data transfer with each bit being trans-
mitted on the falling SCK edge and captured on the rising
SCK edge in both transmitting and receiving systems. The
data is transmitted and received simultaneously (full du-
plex). After completing the data transfer, if further SCK
clocks are applied with CONV low, SDO will output zeros
indefinitely. See Figure 4.
Reference Input
The reference input of the LTC1861 SO-8 package is
internally tied to VCC. The span of the A/D converter is
therefore equal to VCC. The voltage on the reference input
of the LTC1861 MSOP package defines the span of the A/
D converter. The LTC1861 MSOP package can operate
Analog Inputs
The two bits of the input word (SDI) assign the MUX
configuration for the next requested conversion. For a
with reference voltages from 1V to VCC.
18601f
9
LTC1860/LTC1861
W U U
U
APPLICATIO S I FOR ATIO
CONV
t
SMPL
SLEEP MODE
t
CONV
SDI
S/D O/S
DON’T CARE
DON’T CARE
1
2
3
4
5
6
7
8
9 10 11 12
SCK
SDO
B10
B8 B7 B6 B5 B4 B3 B2 B1 B0*
B11
B9
Hi-Z
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
1860 F04
Figure 4. LTC1861 Operating Sequence
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
Table 1. Multiplexer Channel Selection
•
•
•
MUX ADDRESS
CHANNEL #
SGL/DIFF ODD/SIGN
0
1
GND
1
1
0
0
0
1
0
1
+
–
–
*
SINGLE-ENDED
MUX MODE
DIFFERENTIAL
MUX MODE
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
V
IN
+
–
+
+
–
*V = (SELECTED “+” CHANNEL) –
IN
(SELECTED “–” CHANNEL)
REFER TO TABLE 1
1860 F05
186465 TBL1
Figure 5. LTC1861 Transfer Curve
induce errors or noise in the output code. Bypass the VCC
and VREF pins directly to the analog ground plane with a
minimum of 1µF tantalum. Keep the bypass capacitor
leads as short as possible.
GENERAL ANALOG CONSIDERATIONS
Grounding
The LTC1860/LTC1861 should be used with an analog
ground plane and single point grounding techniques. Do
not use wire wrapping techniques to breadboard and
evaluatethedevice.Toachievetheoptimumperformance,
use a printed circuit board. The ground pins (AGND and
DGND for the LTC1861 MSOP package and GND for the
LTC1860 and LTC1861 SO-8 package) should be tied
directly to the analog ground plane with minimum lead
length.
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1860/
LTC1861 have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem if source resistances are less than 200Ω or high
speed op amps are used (e.g., the LT®1211, LT1469,
LT1807, LT1810, LT1630, LT1226orLT1215). Butiflarge
source resistances are used, or if slow settling op amps
drive the inputs, take care to ensure the transients caused
by the current spikes settle completely before the conver-
sion begins.
Bypassing
For good performance, the VCC and VREF pins must be free
of noise and ripple. Any changes in the VCC/VREF voltage
with respect to ground during the conversion cycle can
18601f
10
LTC1860/LTC1861
U
PACKAGE DESCRIPTIO
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
0.52
(.206)
REF
8
7 6
5
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.88 ± 0.1
(.192 ± .004)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
0.65
(.0256)
BSC
0.42 ± 0.04
1
2
3
4
(.0165 ± .0015)
TYP
0.53 ± 0.015
(.021 ± .006)
1.10
(.043)
MAX
0.86
(.034)
REF
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.18
(.077)
SEATING
PLANE
NOTE:
0.22 – 0.38
(.009 – .015)
0.13 ± 0.05
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
(.005 ± .002)
0.65
(.0256)
BCS
MSOP (MS8) 1001
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
0.497 ± 0.076
(.0196 ± .003)
REF
10 9
8
7 6
5.23
(.206)
MIN
3.00 ± 0.102
(.118 ± .004)
NOTE 4
3.2 – 3.45
(.126 – .136)
4.88 ± 0.10
(.192 ± .004)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
1
2
3
4 5
0.53 ± 0.01
(.021 ± .006)
RECOMMENDED SOLDER PAD LAYOUT
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
NOTE:
0.17 – 0.27
(.007 – .011)
0.13 ± 0.05
(.005 ± .002)
MSOP (MS) 1001
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
0.50
(.0197)
TYP
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
0.010 – 0.020
(0.254 – 0.508)
7
5
8
6
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
SO8 1298
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
4
18601f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.
11
LTC1860/LTC1861
U
TYPICAL APPLICATIO
Sample Two Channels Simultaneously with a Single Input ADC
5V
0.1µF
f
1
+
(0V TO 0.66V)
0.1µF
0.1µF
1µF
1µF
4.096V
REF
100Ω
1/2
LT1492
–
4.096V
REF
100pF
5k
5k
20k
5pF
8
1
REF
SCK
28.7k
V
7
6
5
CC
10k
2
3
+
IN
10k
1µF
LTC1860
SDO
–
IN
5V
CONV
GND
4
0.1µF
0.1µF
f
8
2
+
(0V TO 2V)
100Ω
1/2
LT1492
–
100pF
4
1860 TA03
RELATED PARTS
PART NUMBER
12-Bit Serial I/O ADCs
LTC1286/LTC1298
LTC1400
SAMPLE RATE
POWER DISSIPATION
DESCRIPTION
12.5ksps/11.1ksps
400ksps
1.3mW/1.7mW
75mW
1-Channel with Ref. Input (LTC1286), 2-Channel (LTC1298), 5V
1-Channel, Bipolar or Unipolar Operation, Internal Reference, 5V
SO-8 with Internal Reference, 3V
LTC1401
200ksps
15mW
LTC1402
2.2Msps
90mW
Serial I/O, Bipolar or Unipolar, Internal Reference
SO-8 with Internal Reference, Bipolar or Unipolar, 5V
LTC1404
600ksps
25mW
14-Bit Serial I/O ADCs
LTC1417
400ksps
200ksps
20mW
15mW
16-Pin SSOP, Unipolar or Bipolar, Reference, 5V
Serial/Parallel I/O, Internal Reference, 5V
LTC1418
16-Bit Serial I/O ADCs
LTC1609
200ksps
250ksps
65mW
Configurable Bipolar or Unipolar Input Ranges, 5V
SO-8, MS8, 1-Channel, 5V/SO-8, MS10, 2-Channel, 5V
LTC1864/LTC1865
References
4.25mW
LT1460
Micropower Precision Series Reference
Micropower Low Dropout Reference
Bandgap, 130µA Supply Current, 10ppm/°C, Available in SOT-23
60µA Supply Current, 10ppm/°C, SOT-23
LT1790
18601f
LT/TP 0502 2K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
12
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
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