LTC1860LIMS8#TR [Linear]
LTC1860L - µPower, 3V, 12-Bit, 150ksps 1- and 2-Channel ADCs in MSOP; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C;
| 型号： | LTC1860LIMS8#TR |
| 厂家： | 
Linear |
| 描述： | LTC1860L - µPower, 3V, 12-Bit, 150ksps 1- and 2-Channel ADCs in MSOP; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C 转换器 模数转换器 光电二极管 |
| 文件： | 总12页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1860L/LTC1861L
µPower, 3V, 12-Bit, 150ksps
1- and 2-Channel ADCs in MSOP
U
FEATURES
DESCRIPTIO
The LTC®1860L/LTC1861L are 12-bit A/D converters that
are offered in MSOP and SO-8 packages and operate on a
single 3V supply. At 150ksps, the supply current is only
450µA. The supply current drops at lower speeds because
the LTC1860L/LTC1861L automatically power down be-
tween conversions. These 12-bit switched capacitor suc-
cessive approximation ADCs include sample-and-holds.
The LTC1860L has a differential analog input with an
external reference pin. The LTC1861L offers a software-
selectable2-channelMUXandanexternalreferencepinon
the MSOP version.
■
12-Bit 150ksps ADCs in MSOP Package
■
Single 3V Supply
■
Low Supply Current: 450µA (Typ)
Auto Shutdown Reduces Supply Current
■
to 10µA at 1ksps
True Differential Inputs
■
■
1-Channel (LTC1860L) or 2-Channel (LTC1861L)
Versions
SPI/MICROWIRETM Compatible Serial I/O
■
■
High Speed Upgrade to LTC1285/LTC1288
■
Pin Compatible with 16-Bit LTC1864L/LTC1865L
■
No Minimum Data Transfer Rate
The 3-wire, serial I/O, MSOP or SO-8 package and
extremely high sample rate-to-power ratio make these
ADCs ideal choices for compact, low power, high speed
systems.
U
APPLICATIO S
■
High Speed Data Acquisition
■
Portable or Compact Instrumentation
TheseADCscanbeusedinratiometricapplicationsorwith
external references. The high impedance analog inputs
and the ability to operate with reduced spans down to 1V
fullscaleallowdirectconnectiontosignalsourcesinmany
applications, eliminatingtheneedforexternalgainstages.
■
Low Power Battery-Operated Instrumentation
Isolated and/or Remote Data Acquisition
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
U
TYPICAL APPLICATIO
Supply Current vs Sampling Frequency
1000
Single 3V Supply, 150ksps, 12-Bit Sampling ADC
CONV LOW = 1.5µs
T
= 25°C
A
1µF
V
= 2.7V
CC
100
3V
LTC1860L
10
1
1
2
3
4
8
7
6
V
V
CC
REF
+
IN
IN
SCK
SDO
ANALOG INPUT
0V TO 3V
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
–
5
GND
CONV
1860L TA01
0.1
0.01
0.1
1
10
100
1000
SAMPLING FREQUENCY (kHz)
1860L/61L TA02
18601Lf
1
LTC1860L/LTC1861L
W W U W
ABSOLUTE AXI U RATI GS
Supply Voltage (VCC) ................................................. 7V
Ground Voltage Difference
(Notes 1, 2)
Power Dissipation.............................................. 400mW
Operating Temperature Range
LTC1860LC/LTC1861LC......................... 0°C to 70°C
LTC1860LI/LTC1861LI ...................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
AGND, DGND LTC1861L MSOP Package ......... ±0.3V
Analog Input .................... (GND – 0.3V) to (VCC + 0.3V)
Digital Input ..................................... (GND – 0.3V) to 7V
Digital Output .................. (GND – 0.3V) to (VCC + 0.3V)
U W
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
TOP VIEW
TOP VIEW
NUMBER
V
IN
1
2
3
4
8 V
CC
REF
CONV
CH0
1
2
3
4
5
10
9
V
V
SCK
SDO
SDI
REF
CC
+
7 SCK
LTC1860LCMS8
LTC1860LIMS8
LTC1861LCMS
LTC1861LIMS
6 SDO
5 CONV
IN¯
CH1
8
GND
AGND
DGND
7
6
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING
MS PART MARKING
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 210°C/W
LTD2
LTD3
LTD4
LTD5
TJMAX = 150°C, θJA = 210°C/W
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
1
2
3
4
8
7
6
5
CONV
CH0
V
CC
1
2
3
4
8
7
6
5
V
V
CC
REF
+
SCK
SDO
SDI
IN
IN
SCK
LTC1860LCS8
LTC1860LIS8
LTC1861LCS8
LTC1861LIS8
–
CH1
SDO
CONV
GND
GND
S8 PART MARKING
S8 PART MARKING
S8 PACKAGE
8-LEAD PLASTIC SO
S8 PACKAGE
8-LEAD PLASTIC SO
1861L
1861LI
1860L
1860LI
TJMAX = 150°C, θJA = 175°C/W
TJMAX = 150°C, θJA = 175°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
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CO VERTER A D ULTIPLEXER CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.
VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
A
PARAMETER
CONDITIONS
MIN
12
TYP
MAX
UNITS
Bits
Resolution
●
●
●
No Missing Codes Resolution
INL
12
Bits
(Note 3)
±1
LSB
Transition Noise
Gain Error
0.13
LSB
RMS
●
●
●
±20
±5
mV
Offset Error
±2
mV
V
+
–
Input Differential Voltage Range
Absolute Input Range
V
= IN – IN
0
V
REF
IN
+
IN Input
IN Input
–0.05
–0.05
V
+ 0.05
V
V
CC
V
–
/2
CC
V
Input Range
LTC1860L S0-8 and MSOP, LTC1861L MSOP
(Note 4)
1
V
V
REF
CC
Analog Input Leakage Current
Input Capacitance
●
±1
µA
C
IN
In Sample Mode
During Conversion
12
5
pF
pF
18601Lf
2
LTC1860L/LTC1861L
U W
DY A IC ACCURACY
T = 25°C. V = 3V, V = 3V, f
SAMPLE
= 150kHz, unless otherwise specified.
CONDITIONS
A
CC
SYMBOL PARAMETER
SNR Signal-to-Noise Ratio
S/(N + D) Signal-to-Noise Plus Distortion Ratio
THD
REF
MIN
TYP
72
MAX
UNITS
dB
1kHz Input Signal
72
dB
Total Hamonic Distortion Up to 5th Harmonic 1kHz Input Signal
86
dB
Full Power Bandwidth
10
MHz
kHz
Full Linear BaU ndwidth
S/(N + D) ≥ 68dB
30
DIGITAL A DDCELECTRICALCHARACTERISTICS
The ● denotes specifications which apply
over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 2.7V, VREF = 2.5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
IH
V
IL
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 3.3V
= 2.7V
●
●
●
●
1.9
CC
CC
IN
0.45
2.5
V
I
I
= V
µA
µA
IH
IL
CC
= 0V
–2.5
IN
V
OH
V
CC
V
CC
= 2.7V, I = 10µA
●
●
2.3
2.1
2.6
2.45
V
V
O
= 2.7V, I = 360µA
O
V
Low Level Output Voltage
Hi-Z Output Leakage
Output Source Current
Output Sink Current
V
= 2.7V, I = 400µA
●
●
0.3
V
µA
OL
CC
O
I
I
I
I
CONV = V
±3
OZ
CC
V
OUT
V
OUT
= 0V
–6.5
6.5
mA
mA
SOURCE
SINK
= V
CC
Reference Current (LTC1860L SO-8, MSOP
and LTC1861L MSOP)
CONV = V
●
●
0.001
0.01
3
0.1
µA
mA
REF
CC
f
= f
SMPL
SMPL(MAX)
I
Supply Current
CONV = V After Conversion
●
●
0.5
0.45
10
1.0
µA
mA
CC
CC
f
= f
SMPL
SMPL(MAX)
P
D
Power Dissipation
f
= f
1.22
mW
SMPL
SMPL(MAX)
W U
U
U
U
W
The ● denotes specifications which apply over the
RECO E DED OPERATI G CO DITIO S
full operating temperature range, otherwise specifications are TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
MIN
2.7
TYP
MAX
3.6
8
UNITS
V
V
Supply Voltage
CC
f
t
t
Clock Frequency
●
DC
MHz
µs
SCK
CYC
SMPL
Total Cycle Time
12 • SCK + t
CONV
Analog Input Sampling Time (Note 5)
LTC1860L
LTC1861L
12
10
SCK
SCK
t
Setup Time CONV↓ Before First SCK↑,
(See Figure 1)
60
ns
suCONV
t
t
t
t
t
Holdtime SDI After SCK↑
Setup Time SDI Stable Before SCK↑
SCK High Time
LTC1861L
LTC1861L
30
30
ns
ns
hDI
suDI
f
f
= f
SCK(MAX)
= f
SCK(MAX)
45%
45%
1/f
1/f
WHCLK
WLCLK
WHCONV
SCK
SCK
SCK
SCK Low Time
SCK
CONV High Time Between Data
Transfer Cycles
t
µs
CONV
t
t
CONV Low Time During Data Transfer
12
26
SCK
ns
WLCONV
hCONV
Hold Time CONV Low After Last SCK↑
18601Lf
3
LTC1860L/LTC1861L
W U
The ● denotes specifications which apply over the full operating temperature
TI I G CHARACTERISTICS
range, otherwise specifications are TA = 25°C. VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating
Conditions, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
µs
t
f
t
Conversion Time (See Figure 1)
Maximum Sampling Frequency
Delay Time, SCK↓ to SDO Data Valid
●
●
3.7
4.66
CONV
150
kHz
SMPL(MAX)
dDO
C
= 20pF
45
55
60
ns
ns
LOAD
●
●
●
●
t
t
t
Delay Time, CONV↑ to SDO Hi-Z
55
35
15
120
120
ns
ns
ns
dis
en
Delay Time, CONV↓ to SDO Enabled
C
C
= 20pF
= 20pF
LOAD
LOAD
Time Output Data Remains
Valid After SCK↓
5
hDO
t
t
SDO Rise Time
SDO Fall Time
C
C
= 20pF
= 20pF
25
12
ns
ns
r
f
LOAD
LOAD
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 4: Channel leakage current is measured while the part is in sample
mode.
Note 5: Assumes f
= f
. In the case of the LTC1860L SCK does
SCK(MAX)
Note 2: All voltage values are with respect to GND.
SCK
not have to be clocked during this time if the SDO data word is not
desired. In the case of the LTC1861L a minimum of 2 clocks are required
on the SCK input after CONV falls to configure the MUX during this time.
Note 3: Integral nonlinearity is defined as deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Sampling
Frequency
Sleep Current vs Temperature
Supply Current vs Temperature
600
500
400
300
200
100
0
1000
100
20
15
10
5
CONV LOW = 1.5µs
f
V
V
= 150kHz
= 2.7V
REF
f
V
V
= 150kHz
= 2.7V
CC
S
CC
S
T
= 25°C
A
CC
V
= 2.7V
= 2.5V
= 2.5V
REF
10
1
0
0.1
0.01
0.1
1
10
100
1000
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
SAMPLING FREQUENCY (kHz)
1860L/61L G01
1860L/61L G02
1860L/61L G03
18601Lf
4
LTC1860L/LTC1861L
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Reference Current vs
Reference Voltage
25
Reference Current vs
Sampling Rate
Reference Current vs
Temperature
10
9
8
7
6
5
4
3
2
1
0
25
20
15
10
5
f
V
V
= 150kHz
= 2.7V
REF
f = 150kHz
T = 25°C
A
CONV LOW = 1.5µs
S
CC
S
T
V
V
= 25°C
A
= 2.5V
V
CC
= 3.6V
= 2.7V
CC
20
15
10
5
= 2.5V
REF
0
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
0
0.5
1.5 2.0 2.5 3.0 3.5 4.0
1.0
REFERENCE VOLTAGE (V)
0
25
75
100
125
150
50
SAMPLING FREQUENCY (kHz)
1860L/61L G05
1860L/61L G06
1860L/61L G04
Analog Input Leakage vs
Temperature
Typical INL Curve
Typical DNL Curve
1.0
0.5
1.0
0.5
100
75
50
25
0
CONV = 0V
f
= 150kHz
= 25°C
f
= 150kHz
= 25°C
A
S
A
S
V = 2.7V
CC
V = 2.5V
REF
T
T
V
V
= 2.7V
V
V
= 2.7V
CC
CC
= 2.5V
= 2.5V
REF
REF
0
0
–0.5
–1.0
–0.5
–1.0
0
512
1536 2048 2560 3072
CODE
4096
0
512
1536 2048 2560 3072
CODE
4096
3584
50
TEMPERATURE (°C)
100 125
1024
3584
1024
–50 –25
25
75
0
1860L/61L G07
1860L/61L G08
1860L/61L G09
Change in Gain Error vs
Reference Voltage
Change in Offset vs
Reference Voltage
Change in Offset vs Temperature
1.0
0.8
2
2
1
f
V
V
= 150kHz
= 2.7V
f
= 150kHz
= 25°C
= 3.6V
f
= 150kHz
T = 25°C
A
S
CC
S
A
S
T
= 2.5V
V
V
= 3.6V
CC
REF
CC
0.6
1
0
0.4
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1
–2
–1
–2
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
2
3
2
3
0
4
0
4
1
1
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
1860L/61L G11
1860L/61L G10
1860L/61L G12
18601Lf
5
LTC1860L/LTC1861L
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Change in Gain Error vs
Temperature
4096 Point FFT Non Averaged
SNR vs fIN
1.0
0.8
80
70
60
50
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
f
V
V
= 150kHz
= 2.7V
REF
f
f
= 1kHz
S
CC
IN
S
A
= 150kHz
= 25°C
= 3V
= 2.5V
T
0.6
V
V
CC
REF
0.4
= 3V
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
f
= 150kHz
S
A
T
= 25°C
V
V
V
= 3V
CC
IN
= 0dB
= 3V
REF
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75
(kHz)
1
10
f (kHz)
IN
100
f
IN
1860L/61L G15
1860L/61L G13
1860L/61L G14
Signal-to-(Noise + Distortion)
vs fIN
Total Harmonic Distortion
vs fIN
Spurious Free Dynamic Range
vs fIN
100
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
f
= 150kHz
S
A
T
= 25°C
V
V
V
= 3V
CC
IN
= 0dB
= 3V
REF
f
= 150kHz
= 25°C
= 3V
S
A
CC
f
= 150kHz
S
A
T
T
= 25°C
V
V
V
V
V
V
= 3V
CC
IN
= 0dB
IN
= 0dB
= 3V
REF
= 3V
REF
1
10
100
1
10
100
1
10
100
f (kHz)
IN
f
IN
(kHz)
f
IN
(kHz)
1860L/61L G18
1860L/61L G17
1860L/61L G16
U
U
U
PI FU CTIO S
LTC1860L
high after the A/D conversion is finished, the part powers
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
VREF (Pin 1): Reference Input. The reference input defines
the span of the A/D converter and must be kept free of
noise with respect to GND.
IN+, IN– (Pins 2, 3): Analog Inputs. These inputs must be
free of noise with respect to GND.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this pin.
SCK(Pin7):ShiftClockInput. Thisclocksynchronizesthe
serial data transfer.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
V
CC (Pin 8): Positive Supply. This supply must be kept
CONV (Pin 5): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
free of noise and ripple by bypassing directly to the
analog ground plane.
18601Lf
6
LTC1860L/LTC1861L
U
U
U
PI FU CTIO S
LTC1861L (MSOP Package)
LTC1861L (SO-8 Package)
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
high after the A/D conversion is finished, the part powers
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
high after the A/D conversion is finished, the part powers
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to AGND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
AGND (Pin 4): Analog Ground. AGND should be tied
directly to an analog ground plane.
DGND (Pin 5): Digital Ground. DGND should be tied
directly to an analog ground plane.
SDI (Pin 5): Digital Data Input. The A/D configuration
word is shifted into this input.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
SDI (Pin 6): Digital Data Input. The A/D configuration
word is shifted into this input.
SCK(Pin7):ShiftClockInput. Thisclocksynchronizesthe
serial data transfer.
SDO (Pin 7): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK(Pin8):ShiftClockInput. Thisclocksynchronizesthe
VCC (Pin 8): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane. VREF is tied internally to this pin.
serial data transfer.
VCC (Pin 9): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane.
VREF (Pin 10): Reference Input. The reference input de-
fines the span of the A/D converter and must be kept free
of noise with respect to AGND.
U
U
W
FUNCTIONAL BLOCK DIAGRA
V
CC
(SDI) SCK
CONV
SDO
SERIAL
PORT
CONVERT
CLK
BIAS AND
SHUTDOWN
DATA IN
12-BITS
+
IN
+
–
(CH0)
12-BIT
SAMPLING
ADC
DATA OUT
–
IN
(CH1)
PIN NAMES IN PARENTHESES REFER TO LTC1861L
1860L/61L BD
GND
V
REF
18601Lf
7
LTC1860L/LTC1861L
TEST CIRCUITS
Load Circuit for tdDO, tr, tf, tdis and ten
Voltage Waveforms for SDO Rise and Fall Times, tr, tf
TEST POINT
V
OH
SDO
V
OL
V
t
WAVEFORM 2, t
3k
CC dis
en
SDO
t
WAVEFORM 1
dis
t
t
f
1860 TC04
r
20pF
1860 TC01
Voltage Waveforms for ten
Voltage Waveforms for tdis
CONV
V
CONV
IH
SDO
1860 TC03
t
en
SDO
WAVEFORM 1
(SEE NOTE 1)
90%
10%
t
dis
Voltage Waveforms for SDO Delay Times, tdDO and thDO
SDO
WAVEFORM 2
(SEE NOTE 2)
SCK
V
IL
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
t
dDO
t
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
hDO
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
V
V
OH
OL
1860 TC05
SDO
1860 TC02
W U U
U
APPLICATIO S I FOR ATIO
LTC1860L OPERATION
Analog Inputs
TheLTC1860Lhasaunipolardifferentialanaloginput.The
converter will measure the voltage between the “IN+” and
“IN–” inputs. A zero code will occur when IN+ minus IN–
equals zero. Full scale occurs when IN+ minus IN– equals
VREF minus 1LSB. See Figure 2. Both the “IN+” and
“IN–” inputs are sampled at the same time, so common
mode noise on the inputs is rejected by the ADC. If “IN–”
isgroundedandVREF istiedtoVCC, arail-to-railinputspan
will result on “IN+” as shown in Figure 3.
Operating Sequence
The LTC1860L conversion cycle begins with the rising
edge of CONV. After a period equal to tCONV, the conver-
sion is finished. If CONV is left high after this time, the
LTC1860L goes into sleep mode drawing only leakage
current. On the falling edge of CONV, the LTC1860L goes
into sample mode and SDO is enabled. SCK synchronizes
the data transfer with each bit being transmitted from SDO
on the falling SCK edge. The receiving system should
capture the data from SDO on the rising edge of SCK. After
completing the data transfer, if further SCK clocks are
applied with CONV low, SDO will output zeros indefinitely.
See Figure 1.
Reference Input
The voltage on the reference input of the LTC1860L (and
theLTC1861LMSOPpackage)definesthefull-scalerange
of the A/D converter. These ADCs can operate with refer-
ence voltages from VCC to 1V.
18601Lf
8
LTC1860L/LTC1861L
W U U
APPLICATIO S I FOR ATIO
U
CONV
t
SMPL
SLEEP MODE
t
CONV
1
2
3
4
5
6
7
8
9 10 11 12
SCK
SDO
DON'T CARE
Hi-Z
B10
B8 B7 B6 B5 B4 B3 B2 B1 B0*
B11
B9
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER
SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC
WILL OUTPUT ZEROS INDEFINITELY
1860 F01
Figure 1. LTC1860L Operating Sequence
1µF
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
V
CC
•
•
•
LTC1860L
1
2
3
4
8
7
6
V
V
CC
REF
+
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
V
= 0V TO V
CC
IN
IN
SCK
SDO
V
*
IN
IN
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
–
5
+
–
*V = IN – IN
GND
CONV
IN
1860 F03
1860 F02
Figure 2. LTC1860L Transfer Curve
Figure 3. LTC1860L with Rail-to-Rail Input Span
LTC1861L OPERATION
Operating Sequence
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and“–”signsintheselectedrowofTable1.Insingle-ended
mode, all input channels are measured with respect to
GND (or AGND). A zero code will occur when the “+”
input minus the “–” input equals zero. Full scale occurs
whenthe“+”inputminusthe“–”inputequalsVREF minus
1LSB. See Figure 5. Both the “+” and “–” inputs are
sampled at the same time so common mode noise is
rejected. The input span in the SO-8 package is fixed at
VREF = VCC. If the “–” input in differential mode is
grounded, a rail-to-rail input span will result on the “+”
input.
The LTC1861L conversion cycle begins with the rising
edge of CONV. After a period equal to tCONV, the conver-
sion is finished. If CONV is left high after this time, the
LTC1861L goes into sleep mode. The LTC1861L’s 2-bit
data word is clocked into the SDI input on the rising edge
of SCK after CONV goes low. Additional inputs on the SDI
pin are then ignored until the next CONV cycle. The shift
clock (SCK) synchronizes the data transfer with each bit
beingtransmitted on the fallingSCK edge and capturedon
the rising SCK edge in both transmitting and receiving
systems. The data is transmitted and received simulta-
neously (full duplex). After completing the data transfer, if
further SCK clocks are applied with CONV low, SDO will
output zeros indefinitely. See Figure 4.
Reference Input
The reference input of the LTC1861L SO-8 package is
internally tied to VCC. The span of the A/D converter is
therefore equal to VCC. The voltage on the reference input
of the LTC1861L MSOP package defines the span of the
A/D converter. The LTC1861L MSOP package can operate
Analog Inputs
The two bits of the input word (SDI) assign the MUX
configuration for the next requested conversion. For a
with reference voltages from 1V to VCC.
18601Lf
9
LTC1860L/LTC1861L
W U U
U
APPLICATIO S I FOR ATIO
CONV
t
SMPL
SLEEP MODE
t
CONV
SDI
S/D O/S
DON’T CARE
DON'T CARE
DON’T CARE
1
2
3
4
5
6
7
8
9 10 11 12
SCK
SDO
B10
B8 B7 B6 B5 B4 B3 B2 B1 B0*
B11
B9
Hi-Z
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
1860 F04
Figure 4. LTC1861L Operating Sequence
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
Table 1. Multiplexer Channel Selection
•
•
•
MUX ADDRESS
CHANNEL #
SGL/DIFF ODD/SIGN
0
1
GND
1
1
0
0
0
1
0
1
+
–
–
*
SINGLE-ENDED
MUX MODE
DIFFERENTIAL
MUX MODE
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
V
IN
+
–
+
+
–
*V = (SELECTED “+” CHANNEL) –
IN
(SELECTED “–” CHANNEL)
REFER TO TABLE 1
1860 F05
186465 TBL1
Figure 5. LTC1861L Transfer Curve
induce errors or noise in the output code. Bypass the VCC
and VREF pins directly to the analog ground plane with a
minimum of 1µF tantalum. Keep the bypass capacitor
leads as short as possible.
GENERAL ANALOG CONSIDERATIONS
Grounding
The LTC1860L/LTC1861L should be used with an analog
ground plane and single point grounding techniques. Do
not use wire wrapping techniques to breadboard and
evaluatethedevice.Toachievetheoptimumperformance,
use a printed circuit board. The ground pins (AGND and
DGND for the LTC1861L MSOP package and GND for the
LTC1860L and LTC1861L SO-8 package) should be tied
directly to the analog ground plane with minimum lead
length.
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1860L/
LTC1861L have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem if source resistances are less than 200Ω or high
speed op amps are used (e.g., the LT®1211, LT1469,
LT1807, LT1810, LT1630, LT1226orLT1215). Butiflarge
source resistances are used, or if slow settling op amps
drive the inputs, take care to ensure the transients caused
by the current spikes settle completely before the conver-
sion begins.
Bypassing
For good performance, the VCC and VREF pins must be free
of noise and ripple. Any changes in the VCC/VREF voltage
with respect to ground during the conversion cycle can
18601Lf
10
LTC1860L/LTC1861L
U
PACKAGE DESCRIPTIO
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
3.00 ± 0.102
0.52
(.206)
REF
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
8
7 6
5
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.90 ± 0.15
(1.93 ± .006)
5.23
(.206)
MIN
DETAIL “A”
0.254
3.2 – 3.45
(.126 – .136)
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4
0.65
(.0256)
BSC
0.42 ± 0.04
(.0165 ± .0015)
TYP
0.53 ± 0.015
(.021 ± .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
RECOMMENDED SOLDER PAD LAYOUT
0.18
(.077)
NOTE:
SEATING
PLANE
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.22 – 0.38
(.009 – .015)
TYP
0.13 ± 0.076
(.005 ± .003)
0.65
(.0256)
BSC
MSOP (MS8) 0802
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
0.889 ± 0.127
(.035 ± .005)
10 9
8
7 6
REF
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.90 ± 0.15
(1.93 ± .006)
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4
5
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.53 ± 0.01
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.18
(.007)
NOTE:
SEATING
PLANE
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.17 – 0.27
(.007 – .011)
TYP
0.13 ± 0.076
(.005 ± .003)
MSOP (MS) 0802
0.50
(.0197)
BSC
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
.160 ±.005
.050 BSC
.010 – .020
(0.254 – 0.508)
7
5
8
6
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
0°– 8° TYP
(0.203 – 0.254)
.245
MIN
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.016 – .050
(0.406 – 1.270)
.050
.014 – .019
(1.270)
(0.355 – 0.483)
NOTE:
BSC
TYP
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
.030 ±.005
TYP
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
1
2
3
4
RECOMMENDED SOLDER PAD LAYOUT
SO8 0303
18601Lf
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.
11
LTC1860L/LTC1861L
U
TYPICAL APPLICATIO
Tiny 2-Chip Data-Acquistion System
1µF
3V
3V
0.1µF
8
V
V
CC
REF
+
4
499Ω
3
1
+
IN
IN
SCK
LTC1860L
V
LTC6910-1
IN
5
–
270pF
–
6
SDO
7
2
GND
CONV
AGND
1µF
ADC
CONTROL
GAIN
CONTROL
LTC6910-1 (IN TSOT-23 PACKAGE) COMPACTLY ADDS 40dB OF INPUT GAIN
RANGE TO THE LTC1860L (IN MSOP 8-PIN PACKAGE). SINGLE 3V SUPPLY
1860L/61L TA03
RELATED PARTS
PART NUMBER
12-Bit Serial I/O ADCs
LTC1286/LTC1298
LTC1400
SAMPLE RATE
POWER DISSIPATION
DESCRIPTION
12.5ksps/11.1ksps
400ksps
1.3mW/1.7mW
75mW
1-Channel with Ref. Input (LTC1286), 2-Channel (LTC1298), 5V
1-Channel, Bipolar or Unipolar Operation, Internal Reference, 5V
SO-8 with Internal Reference, 3V
LTC1401
200ksps
15mW
LTC1402
2.2Msps
90mW
Serial I/O, Bipolar or Unipolar, Internal Reference
SO-8 with Internal Reference, Bipolar or Unipolar, 5V
SO-8, MS8, 1-Channel, 5V/SO-8, MS, 2-Channel, 5V
LTC1404
600ksps
25mW
LTC1860/LTC1861
14-Bit Serial I/O ADCs
LTC1417
250ksps
4.25mW
400ksps
200ksps
20mW
15mW
16-Pin SSOP, Unipolar or Bipolar, Reference, 5V
Serial/Parallel I/O, Internal Reference, 5V
LTC1418
16-Bit Serial I/O ADCs
LTC1609
200ksps
250ksps
150ksps
65mW
4.25mW
1.22mW
Configurable Bipolar or Unipolar Input Ranges, 5V
SO-8, MS8, 1-Channel, 5V/SO-8, MS, 2-Channel, 5V
SO-8, MS8, 1-Channel, 3V/SO-8, MS, 2-Channel, 3V
LTC1864/LTC1865
LTC1864L/LTC1865L
References
LT1460
Micropower Precision Series Reference
Micropower Low Dropout Reference
Bandgap, 130µA Supply Current, 10ppm/°C, Available in SOT-23
60µA Supply Current, 10ppm/°C, SOT-23
LT1790
18601Lf
LT/TP 0303 2K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
12
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
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