LTC1861CS8#TR [Linear]
LTC1861 - µPower, 12-Bit, 250ksps 1- and 2-Channel ADCs in MSOP; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C;
| 型号： | LTC1861CS8#TR |
| 厂家： | 
Linear |
| 描述： | LTC1861 - µPower, 12-Bit, 250ksps 1- and 2-Channel ADCs in MSOP; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C 转换器 模数转换器 光电二极管 |
| 文件： | 总16页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1860/LTC1861
µPower, 12-Bit, 250ksps
1- and 2-Channel ADCs in MSOP
FEATURES
DESCRIPTION
The LTC®1860/LTC1861 are 12-bit A/D converters that are
offeredinMSOPandSO-8packagesandoperateonasingle
5V supply. At 250ksps, the supply current is only 850μA.
The supply current drops at lower speeds because the
LTC1860/LTC1861 automatically power down to a typical
supply current of 1nA between conversions. These 12-bit
switchedcapacitorsuccessiveapproximationADCsinclude
sample-and-holds. The LTC1860 has a differential analog
input with an adjustable reference pin. The LTC1861 offers
a software-selectable 2-channel MUX and an adjustable
reference pin on the MSOP version.
n
12-Bit 250ksps ADCs in MSOP Package
n
Single 5V Supply
n
Low Supply Current: 850μA (Typ)
Auto Shutdown Reduces Supply Current
n
to 2μA at 1ksps
True Differential Inputs
n
n
1-Channel (LTC1860) or 2-Channel (LTC1861)
Versions
SPI/MICROWIRETM Compatible Serial I/O
n
n
High Speed Upgrade to LTC1286/LTC1298
n
Pin Compatible with 16-Bit LTC1864/LTC1865
n
Guaranteed Operation to 125°C (MSOP Package)
The 3-wire, serial I/O, MSOP or SO-8 package and
extremely high sample rate-to-power ratio make these
ADCs ideal choices for compact, low power, high speed
systems.
APPLICATIONS
n
High Speed Data Acquisition
Portable or Compact Instrumentation
Low Power Battery-Operated Instrumentation
Isolated and/or Remote Data Acquisition
n
These ADCs can be used in ratiometric applications or
with external references. The high impedance analog in-
puts and the ability to operate with reduced spans down
to 1V full scale, allow direct connection to signal sources
in many applications, eliminating the need for external
gain stages.
n
n
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Single 5V Supply, 250ksps, 12-Bit Sampling ADC
Supply Current vs Sampling Frequency
1MF
1000
5V
100
10
LTC1860
1
2
3
4
8
7
6
V
V
CC
REF
+
IN
IN
SCK
SDO
ANALOG INPUT
0V TO 5V
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
1
–
5
GND
CONV
1860 TA01
0.1
0.01
0.01
0.1
1
10
100
1000
SAMPLING FREQUENCY (kHz)
1860 TA02
18601fa
1
LTC1860/LTC1861
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Power Dissipation.............................................. 400mW
Operating Temperature Range
LTC1860C/LTC1861C...............................0°C to 70°C
LTC1860I/LTC1861I .......................... –40°C to 85°C
LTC1860H/LTC1861H.........................–40°C to 125°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) ..................300°C
Supply Voltage (V ) .................................................7V
CC
Ground Voltage Difference
AGND, DGND LTC1861 MSOP Package............. 0.3V
Analog Input ....................(GND – 0.3V) to (V + 0.3V)
CC
Digital Input .................................... (GND – 0.3V) to 7V
Digital Output ................... (GND – 0.3V) to (V + 0.3V)
CC
PIN CONFIGURATION
LTC1860
LTC1861
TOP VIEW
TOP VIEW
CONV
CH0
1
2
3
4
5
10
9
V
V
SCK
SDO
SDI
REF
CC
V
1
2
3
4
8 V
CC
REF
+
IN
7 SCK
CH1
8
6 SDO
5 CONV
IN¯
AGND
DGND
7
6
GND
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS PACKAGE
10-LEAD PLASTIC MSOP
T
= 150°C, θ = 210°C/W
JMAX
JA
T
JMAX
= 150°C, θ = 210°C/W
JA
LTC1860
LTC1861
TOP VIEW
TOP VIEW
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
V
CONV
CH0
V
CC
REF
CC
+
IN
SCK
SCK
SDO
SDI
–
IN
SDO
CONV
CH1
GND
GND
S8 PACKAGE
8-LEAD PLASTIC SO
S8 PACKAGE
8-LEAD PLASTIC SO
T
= 150°C, θ = 175°C/W
T = 150°C, θ = 175°C/W
JMAX JA
JMAX
JA
18601fa
2
LTC1860/LTC1861
ORDER INFORMATION
LEAD FREE FINISH
LTC1860CMS8#PBF
LTC1860IMS8#PBF
LTC1860HMS8#PBF
LTC1860CS8#PBF
LTC1860IS8#PBF
LTC1861CMS#PBF
LTC1861IMS#PBF
LTC1861HMS#PBF
LTC1861CS8#PBF
LTC1861IS8#PBF
LEAD BASED FINISH
LTC1860CMS8
TAPE AND REEL
LTC1860CMS8#TRPBF
LTC1860IMS8#PBF
LTC1860HMS8#PBF
LTC1860CS8#PBF
LTC1860IS8#PBF
LTC1861CMS#PBF
LTC1861IMS#PBF
LTC1861HMS#PBF
LTC1861CS8#PBF
LTC1861IS8#PBF
TAPE AND REEL
LTC1860CMS8
LTC1860IMS8
PART MARKING
LTWR
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic SO
LTWS
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTWS
1860
1860I
8-Lead Plastic SO
–40°C to 85°C
0°C to 70°C
LTWT
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
8-Lead Plastic SO
LTWU
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTWU
1861
1861I
8-Lead Plastic SO
–40°C to 85°C
TEMPERATURE RANGE
0°C to 70°C
PART MARKING
LTWR
PACKAGE DESCRIPTION
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic SO
LTC1860IMS8
LTWS
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC1860HMS8
LTC1860CS8
LTC1860HMS8
LTC1860CS8
LTWS
1860
LTC1860IS8
LTC1860IS8
1860I
8-Lead Plastic SO
–40°C to 85°C
0°C to 70°C
LTC1861CMS
LTC1861CMS
LTWT
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
8-Lead Plastic SO
LTC1861IMS
LTC1861IMS
LTWU
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC1861HMS
LTC1861HMS
LTWU
LTC1861CS8
LTC1861CS8
1861
LTC1861IS8
LTC1861IS8
1861I
8-Lead Plastic SO
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
18601fa
3
LTC1860/LTC1861
CONVERTER AND MULTIPLEXER CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.
A
VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
SYMBOL
CONDITIONS
MIN
12
TYP
MAX
UNITS
Bits
l
l
l
Resolution
No Missing Codes Resolution
INL
12
Bits
(Note 3)
1
LSB
Transition Noise
Gain Error
0.07
LSB
RMS
l
20
mV
l
l
Offset Error
LTC1860 SO-8 and MSOP, LTC1861 MSOP
LTC1861 SO-8
2
3
5
7
mV
mV
+
–
l
Input Differential Voltage Range
Absolute Input Range
V
= IN – IN
0
V
V
IN
+
–
REF
IN Input
IN Input
–0.05
–0.05
V
+ 0.05
V
V
CC
V
/2
CC
V
Input Range
LTC1860 SO-8 and MSOP, LTC1861 MSOP
(Note 4)
1
V
V
REF
CC
l
Analog Input Leakage Current
Input Capacitance
1
μA
C
In Sample Mode
During Conversion
12
5
pF
pF
IN
DYNAMIC ACCURACY
T = 25°C. VCC = 5V, fSAMPLE = 250kHz, unless otherwise specified.
A
SYMBOL
SNR
PARAMETER
CONDITIONS
MIN
TYP
72
MAX
UNITS
dB
Signal-to-Noise Ratio
S/(N + D)
THD
Signal-to-Noise Plus Distortion Ratio
Total Hamonic Distortion Up to 5th Harmonic
Full Power Bandwidth
100kHz Input Signal
100kHz Input Signal
71
dB
77
dB
20
MHz
kHz
Full Linear Bandwidth
S/(N + D) ≥ 68dB
125
The ● denotes specifications which apply
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
over the full operating temperature range, otherwise specifications are T = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted.
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
l
l
l
l
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 5.25V
= 4.75V
2.4
IH
IL
CC
CC
IN
V
0.8
2.5
V
I
I
= V
μA
μA
IH
CC
= 0V
–2.5
IL
IN
l
l
V
V
CC
V
CC
= 4.75V, I = 10μA
= 4.75V, I = 360μA
4.5
2.4
4.74
4.72
V
V
OH
OL
O
O
l
V
Low Level Output Voltage
V
CC
= 4.75V, I = 1.6mA
0.4
V
O
18601fa
4
LTC1860/LTC1861
The ● denotes specifications which apply
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
over the full operating temperature range, otherwise specifications are T = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted.
A
SYMBOL
PARAMETER
CONDITIONS
CONV = V
MIN
TYP
MAX
UNITS
μA
l
I
I
I
I
Hi-Z Output Leakage
Output Source Current
Output Sink Current
3
OZ
CC
V
OUT
V
OUT
= 0V
–25
20
mA
SOURCE
SINK
REF
= V
mA
CC
l
l
Reference Current (LTC1860 SO-8,
MSOP and LTC1861 MSOP)
CONV = V
0.001
0.05
3
0.1
μA
mA
CC
f
= f
SMPL
SMPL(MAX)
l
l
l
I
CC
Supply Current
CONV = V After Conversion
0.001
0.001
0.85
3
5
1.3
μA
μA
mA
CC
CONV = V After Conversion, H-Grade
CC
f
= f
SMPL
SMPL(MAX)
P
D
Power Dissipation
f
= f
1.25
mV
SMPL
SMPL(MAX)
The ● denotes specifications which apply over
RECOMMENDED OPERATING CONDITIONS
the full operating temperature range, otherwise specifications are T = 25°C.
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Supply Voltage
Clock Frequency
4.75
5.25
V
CC
l
l
f
20
16.7
MHz
MHz
SCK
H-Grade
t
t
Total Cycle Time
12 • SCK + t
μs
CYC
CONV
Analog Input Sampling Time
LTC1860 (Note 5)
LTC1861 (Note 5)
12
10
SCK
SCK
SMPL
t
Setup Time CONV↓ Before First SCK↑,
60
65
30
30
ns
ns
suCONV
(See Figure 1)
H-Grade
LTC1861
LTC1861
t
t
t
t
t
Holdtime SDI After SCK↑
Setup Time SDI Stable Before SCK↑
SCK High Time
15
15
ns
ns
hDI
suDI
f
f
= f
= f
40%
40%
1/f
1/f
WHCLK
WLCLK
WHCONV
SCK
SCK
SCK(MAX)
SCK(MAX)
SCK
SCK Low Time
SCK
CONV High Time Between Data Transfer (Note 5)
Cycles
t
μs
CONV
t
t
CONV Low Time During Data Transfer
(Note 5)
12
SCK
ns
WLCONV
Hold Time CONV Low After Last SCK↑
13
hCONV
18601fa
5
LTC1860/LTC1861
The ● denotes specifications which apply over the full operating temperature
TIMING CHARACTERISTICS
Conditions, unless otherwise noted.
range, otherwise specifications are T = 25°C. VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating
A
SYMBOL
PARAMETER
CONDITIONS
H-Grade
MIN
TYP
MAX
UNITS
l
l
t
f
t
Conversion Time (See Figure 1)
2.75
2.75
3.2
3.3
μs
μs
CONV
l
l
Maximum Sampling Frequency
250
248
kHz
kHz
SMPL(MAX)
dDO
H-Grade
Delay Time, SCK↓ to SDO Data Valid
C
LOAD
C
LOAD
C
LOAD
= 20pF
15
20
25
30
ns
ns
ns
l
l
= 20pF
= 20pF, H-Grade
l
l
t
t
t
Delay Time, CONV↑ to SDO Hi-Z
30
30
60
65
ns
ns
dis
H-Grade
l
l
Delay Time, CONV↓ to SDO Enabled
C
LOAD
C
LOAD
= 20pF
= 20pF, H-Grade
30
30
60
65
ns
ns
en
l
Time Output Data Remains Valid After
SCK↓
C
= 20pF
5
10
ns
hDO
LOAD
t
t
SDO Rise Time
SDO Fall Time
C
C
= 20pF
= 20pF
8
4
ns
ns
r
f
LOAD
LOAD
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: Integral nonlinearity is defined as deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 4: Channel leakage current is measured while the part is in sample
mode.
Note 5: Guaranteed by design, not subject to test.
Note 2: All voltage values are with respect to GND.
18601fa
6
LTC1860/LTC1861
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Sampling
Frequency
Supply Current vs Temperature
Sleep Current vs Temperature
1000
800
600
400
200
0
1000
1000
100
10
= 5V
CONV = V
CC
CONV LOW = 800ns
900
800
700
600
500
400
300
200
100
0
TA = 25oC
V
CC
= 5V
1
CONV HIGH = 3.2MS
0.1
f
V
V
= 250kHz
SMPL
CC
REF
= 5V
= 5V
0.01
–50
0
25
50
75 100 125
–25
–50
0
25
50
75 100 125
0.01
0.1
1.0
10
100
1000
–25
TEMPERATURE (oC)
TEMPERATURE (oC)
SAMPLING FREQUENCY (kHz)
1860/61 G02
1860/61 G03
1860/61 G01
Reference Current vs
Sample Rate
Reference Current vs
Temperature
Reference Current vs
Reference Voltage
60
50
40
30
20
10
0
55
54
53
52
51
50
49
48
47
46
45
60
50
40
30
20
10
0
f
V
V
= 250kHz
= 5V
REF
f
= 250kHz
= 25oC
= 5V
CONV IS LOW FOR 800ns
S
CC
S
A
CC
T
T
V
V
= 25oC
A
= 5V
V
= 5V
CC
= 5V
REF
0
50
100
150
200
250
–50
0
25
50
75 100 125
–25
0
1
2
3
4
5
SAMPLE RATE (kHz)
TEMPERATURE (oC)
V
(V)
REF
1860/61 G04
1860/61 G05
1860/61 G06
Analog Input Leakage vs
Temperature
Typical INL Curve
Typical DNL Curve
1.0
0.5
100
75
50
25
0
1.0
0.5
T
V
V
= 25oC
T
V
V
= 25oC
V
V
= 5V
= 5V
A
A
CC
REF
CONV = 0V
= 5V
= 5V
CC
CC
= 5V
= 5V
REF
REF
0
0
–0.5
–1.0
–0.5
–1.0
–25
0
25
50
75
125
0
512
1536 2048 2560 3072
CODE
4096
–50
100
1024
3584
0
512
1536 2048 2560 3072
3584
4096
1024
TEMPERATURE (oC)
CODE
1860/61 G07
1860/61 G09
1860/61 G07
18601fa
7
LTC1860/LTC1861
TYPICAL PERFORMANCE CHARACTERISTICS
Change in Offset Error vs
Reference Voltage
Change in Gain Error vs
Reference Voltage
Change in Offset vs Temperature
5
4
1.0
0.8
5
4
V
CC
= 5V
V
CC
= 5V
T
= 25oC
CC
A
T
= 25oC
V
= 5V
A
3
0.6
3
2
0.4
2
1
0.2
1
0
0
0
–1
–2
–3
–4
–5
–0.2
–0.4
–0.6
–0.8
–1.0
–1
–2
–3
–4
–5
0
2
3
4
5
–50
0
25
50
75 100 125
1
–25
0
1
2
3
4
5
REFERENCE VOLTAGE(V)
TEMPERATURE (oC)
REFERENCE VOLTAGE (V)
1860/61 G12
1860/61 G11
1860/61 G10
Change in Gain Error vs
Temperature
Signal-to-(Noise + Distortion)
vs Input Level
4096 Point FFT
1.0
0.8
0
–20
80
V
V
= 5V
REF
CC
f
= 10kHz
= 25oC
= 5V
f
f
= 204.1kHz
= 99.5kHz
= 25oC
IN
A
CC
S
= 5V
T
IN
70
60
50
40
30
20
10
0
V
T
A
0.6
V
= 5V
CC
0.4
–40
0.2
0
–60
–0.2
–0.4
–0.6
–0.8
–1.0
–80
–100
–120
–50
0
25
50
75 100 125
–40 –35 –30 –25 –20 –15 –10 –5
INPUT LEVEL (dB)
0
–25
0
10 20 30 40 50 60 70 80 90 100
f (kHz)
TEMPERATURE (oC)
1860/61 G13
1195 G20
1860/61 G15
Signal-to-(Noise + Distortion)
vs fIN
Total Harmonic Distortion
vs fIN
Spurious Free Dynamic Range
vs fIN
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
TA = 25oC
T
V
V
= 25oC
A
V
CC
V
IN
= 5V
= 0dB
= 5V
CC
= 0dB
IN
SNR
SINAD
T
V
V
= 25oC
A
= 5V
CC
= 0dB
IN
1
10
100
1000
1
10
100
1000
10000
1
10
100
1000
f
(kHz)
f
(kHz)
f
(kHz)
IN
IN
IN
1860/61 G17
1860/61 G18
1860/61 G16
18601fa
8
LTC1860/LTC1861
PIN FUNCTIONS
LTC1860
SDI (Pin 6): Digital Data Input. The A/D configuration
word is shifted into this input.
V
(Pin 1): Reference Input. The reference input defines
REF
the span of the A/D converter and must be kept free of
SDO (Pin 7): Digital Data Output. The A/D conversion
result is shifted out of this output.
noise with respect to GND.
+
–
IN , IN (Pins 2, 3): Analog Inputs. These inputs must be
SCK (Pin 8): Shift Clock Input. This clock synchronizes
the serial data transfer.
free of noise with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
V
(Pin 9): Positive Supply. This supply must be kept
to an analog ground plane.
frCeCe of noise and ripple by bypassing directly to the
analog ground plane.
CONV (Pin 5): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is finished, the part
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
V
REF
(Pin10):ReferenceInput.Thereferenceinputdefines
the span of the A/D converter and must be kept free of
noise with respect to AGND.
LTC1861 (SO-8 Package)
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this pin.
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is finished, the part
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
SCK (Pin 7): Shift Clock Input. This clock synchronizes
the serial data transfer.
V
(Pin 8): Positive Supply. This supply must be kept
frCeCe of noise and ripple by bypassing directly to the
analog ground plane.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
LTC1861 (MSOP Package)
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is finished, the part
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
SDI (Pin 5): Digital Data Input. The A/D configuration
word is shifted into this input.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to AGND.
SCK (Pin 7): Shift Clock Input. This clock synchronizes
the serial data transfer.
AGND(Pin4):AnalogGround.AGNDshouldbetieddirectly
to an analog ground plane.
V
(Pin 8): Positive Supply. This supply must be kept
frCeCeofnoiseandripplebybypassingdirectlytotheanalog
DGND(Pin5):DigitalGround.DGNDshouldbetieddirectly
to an analog ground plane.
ground plane. V is tied internally to this pin.
REF
18601fa
9
LTC1860/LTC1861
FUNCTIONAL BLOCK DIAGRAM
V
CC
(SDI) SCK
CONV
PIN NAMES IN
PARENTHESES
REFER TO LTC1861
SDO
SERIAL
PORT
CONVERT
CLK
BIAS AND
SHUTDOWN
DATA IN
12-BITS
+
IN
+
(CH0)
12-BIT
SAMPLING
ADC
DATA OUT
–
IN
–
(CH1)
1860/61 BD
GND
V
REF
TEST CIRCUITS
Load Circuit for tdDO, tr, tf, tdis and ten
Voltage Waveforms for SDO Rise and Fall Times, tr, tf
TEST POINT
V
OH
SDO
V
OL
V
t
WAVEFORM 2, t
3k
CC dis
en
SDO
t
r
t
f
1860 TC04
t
dis
WAVEFORM 1
20pF
1860 TC01
Voltage Waveforms for ten
Voltage Waveforms for tdis
CONV
V
CONV
SDO
IH
SDO
1860 TC03
90%
10%
WAVEFORM 1
(SEE NOTE 1)
t
en
t
dis
SDO
WAVEFORM 2
(SEE NOTE 2)
Voltage Waveforms for SDO Delay Times, tdDO and thDO
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
SCK
V
IL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
t
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
dDO
1860 TC05
t
hDO
V
V
OH
OL
SDO
1860 TC02
18601fa
10
LTC1860/LTC1861
APPLICATIONS INFORMATION
t
suCONV
CONV
t
SMPL
SLEEP MODE
t
CONV
1
2
3
4
5
6
7
8
9 10 11 12
SCK
SDO
B10
B8 B7 B6 B5 B4 B3 B2 B1 B0*
B9
B11
Hi-Z
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER
Figure 1. LTC1860 Operating Sequence
1MF
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
V
CC
•
•
•
LTC1860
1
2
3
4
8
7
6
V
V
REF
+
CC
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
V
*
IN
V
IN
= 0V TO V
CC
IN
IN
SCK
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
–
+
–
SDO
*V = IN – IN
IN
5
GND
CONV
1860 F03
1860 F02
Figure 2. LTC1860 Transfer Curve
Figure 3. LTC1860 with Rail-to-Rail Input Span
LTC1860 OPERATION
Analog Inputs
The LTC1860 has a unipolar differential analog input. The
Operating Sequence
+
converter will measure the voltage between the “IN ”
–
+
The LTC1860 conversion cycle begins with the rising edge
of CONV. After a period equal to t
and “IN ” inputs. A zero code will occur when IN minus
–
+
–
, the conversion is
CONV
IN equals zero. Full scale occurs when IN minus IN
+
finished. If CONV is left high after this time, the LTC1860
goesintosleepmodedrawingonlyleakagecurrent. Onthe
falling edge of CONV, the LTC1860 goes into sample mode
and SDO is enabled. SCK synchronizes the data transfer
with each bit being transmitted from SDO on the falling
SCK edge. The receiving system should capture the data
from SDO on the rising edge of SCK. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefinitely. See Figure 1.
equals V minus 1LSB. See Figure 2. Both the “IN ” and
REF
–
“IN ” inputs are sampled at the same time, so common
–
mode noise on the inputs is rejected by the ADC. If “IN ”
is grounded and V
span will result on “IN ” as shown in Figure 3.
is tied to V , a rail-to-rail input
REF
CC
+
Reference Input
The voltage on the reference input of the LTC1860 (and the
LTC1861 MSOP package) defines the full-scale range of
the A/D converter. These ADCs can operate with reference
voltages from V to 1V.
CC
18601fa
11
LTC1860/LTC1861
APPLICATIONS INFORMATION
CONV
t
SMPL
SLEEP MODE
t
CONV
SDI
S/D O/S
DON’T CARE
DON’T CARE
1
2
3
4
5
6
7
8
9 10 11 12
SCK
SDO
B10
B8 B7 B6 B5 B4 B3 B2 B1 B0*
B11
B9
Hi-Z
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
1860 F04
Figure 4. LTC1861 Operating Sequence
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
Table 1. Multiplexer Channel Selection
MUX ADDRESS
CHANNEL #
*
V
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
SGL/DIFF ODD/SIGN
0
1
GND
IN
1
1
0
0
0
1
0
1
+
–
–
SINGLE-ENDED
MUX MODE
DIFFERENTIAL
+
–
+
+
–
*V = (SELECTED “+” CHANNEL) –
IN
(SELECTED “–” CHANNEL)
REFER TO TABLE 1
1860 F05
MUX MODE
186465 TBL1
Figure 5. LTC1861 Transfer Curve
LTC1861 OPERATION
Analog Inputs
The two bits of the input word (SDI) assign the MUX
configuration for the next requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and“–”signsintheselectedrowofthefollowingtable. In
single-endedmode, allinputchannelsaremeasuredwith
respect to GND (or AGND). A zero code will occur when
the “+” input minus the “–” input equals zero. Full scale
occurs when the “+” input minus the “–” input equals
Operating Sequence
The LTC1861 conversion cycle begins with the rising edge
of CONV. After a period equal to t
, the conversion is
CONV
finished. If CONV is left high after this time, the LTC1861
goes into sleep mode. The LTC1861’s 2-bit data word is
clocked into the SDI input on the rising edge of SCK after
CONV goes low. Additional inputs on the SDI pin are then
ignored until the next CONV cycle. The shift clock (SCK)
synchronizes the data transfer with each bit being trans-
mitted on the falling SCK edge and captured on the rising
SCK edge in both transmitting and receiving systems.
The data is transmitted and received simultaneously (full
duplex). After completing the data transfer, if further SCK
clocks are applied with CONV low, SDO will output zeros
indefinitely. See Figure 4.
V
minus 1LSB. See Figure 5. Both the “+” and “–”
REF
inputs are sampled at the same time so common mode
noise is rejected. The input span in the SO-8 package is
fixed at V
= V . If the “–” input in differential mode
REF
CC
is grounded, a rail-to-rail input span will result on the
“+” input.
18601fa
12
LTC1860/LTC1861
APPLICATIONS INFORMATION
Reference Input
Bypassing
The reference input of the LTC1861 SO-8 package is
For good performance, the V and V pins must be free
CC REF
internally tied to V . The span of the A/D converter is
of noise and ripple. Any changes in the V /V voltage
CC
CC REF
therefore equal to V . The voltage on the reference input
with respect to ground during the conversion cycle can
CC
of the LTC1861 MSOP package defines the span of the A/D
induce errors or noise in the output code. Bypass the V
CC
converter. The LTC1861 MSOP package can operate with
and V
pins directly to the analog ground plane with
REF
reference voltages from 1V to V .
a minimum of 1μF tantalum. Keep the bypass capacitor
leads as short as possible.
CC
GENERAL ANALOG CONSIDERATIONS
Grounding
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniquesused,theanaloginputsoftheLTC1860/LTC1861
have capacitive switching input current spikes. These cur-
rent spikes settle quickly and do not cause a problem if
source resistances are less than 200Ω or high speed op
ampsareused(e.g.,theLT®1211,LT1469,LT1807,LT1810,
LT1630,LT1226orLT1215).Butiflargesourceresistances
are used, or if slow settling op amps drive the inputs, take
care to ensure the transients caused by the current spikes
settle completely before the conversion begins.
The LTC1860/LTC1861 should be used with an analog
groundplaneandsinglepointgroundingtechniques.Donot
use wire wrapping techniques to breadboard and evaluate
the device. To achieve the optimum performance, use a
printed circuit board. The ground pins (AGND and DGND
for the LTC1861 MSOP package and GND for the LTC1860
and LTC1861 SO-8 package) should be tied directly to the
analog ground plane with minimum lead length.
18601fa
13
LTC1860/LTC1861
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
3.00 p 0.102
(.118 p .004)
(NOTE 3)
0.52
(.0205)
REF
0.889 p 0.127
(.035 p .005)
8
7 6
5
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
5.23
3.20 – 3.45
(.206)
DETAIL “A”
0.254
(.126 – .136)
MIN
(.010)
0o – 6o TYP
GAUGE PLANE
1
2
3
4
0.65
(.0256)
BSC
0.42 p 0.038
(.0165 p .0015)
TYP
0.53 p 0.152
(.021 p .006)
1.10
(.043)
MAX
0.86
(.034)
REF
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
0.1016 p 0.0508
(.009 – .015)
(.004 p .002)
0.65
(.0256)
BSC
TYP
NOTE:
MSOP (MS8) 0307 REV F
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
3.00 p 0.102
(.118 p .004)
(NOTE 3)
0.497 p 0.076
(.0196 p .003)
REF
10 9
8
7 6
0.889 p 0.127
(.035 p .005)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
DETAIL “A”
0o – 6o TYP
5.23
(.206)
MIN
0.254
(.010)
3.20 – 3.45
(.126 – .136)
GAUGE PLANE
1
2
3
4 5
0.50
(.0197)
BSC
0.305 p 0.038
(.0120 p .0015)
TYP
0.53 p 0.152
(.021 p .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
RECOMMENDED SOLDER PAD LAYOUT
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 p 0.0508
(.004 p .002)
0.50
(.0197)
BSC
NOTE:
MSOP (MS) 0307 REV E
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
18601fa
14
LTC1860/LTC1861
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
.045 p.005
NOTE 3
.050 BSC
7
5
8
6
.245
MIN
.160 p.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 p.005
TYP
1
3
4
2
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.508)
s 45o
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0o– 8o TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
SO8 0303
18601fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC1860/LTC1861
TYPICAL APPLICATION
Sample Two Channels Simultaneously with a Single Input ADC
5V
0.1MF
f
1
+
(0V TO 0.66V)
0.1MF
0.1MF
1MF
1MF
4.096V
REF
1007
1/2
LT1492
–
4.096V
REF
100pF
5k
5k
20k
5pF
8
1
REF
SCK
28.7k
V
7
6
5
CC
10k
2
3
+
IN
10k
1MF
LTC1860
SDO
–
IN
5V
CONV
GND
4
0.1MF
0.1MF
f
8
2
+
(0V TO 2V)
1007
1/2
LT1492
–
100pF
4
1860 TA03
RELATED PARTS
PART NUMBER
12-Bit Serial I/o ADCs
LTC1286/LTC1298
LTC1400
SAMPLE RATE
POWER DISSIPATION
DESCRIPTION
12.5ksps/11.1ksps
400ksps
1.3mW/1.7mW
75mW
1-Channel with Ref. Input (LTC1286), 2-Channel (LTC1298), 5V
1-Channel, Bipolar or Unipolar Operation, Internal Reference, 5V
SO-8 with Internal Reference, 3V
LTC1401
200ksps
15mW
LTC1402
2.2Msps
90mW
Serial I/O, Bipolar or Unipolar, Internal Reference
SO-8 with Internal Reference, Bipolar or Unipolar, 5V
LTC1404
600ksps
25mW
14-Bit Serial I/O ADCs
LTC1417
400ksps
200ksps
20mW
15mW
16-Pin SSOP, Unipolar or Bipolar, Reference, 5V
Serial/Parallel I/O, Internal Reference, 5V
LTC1418
16-Bit Serial I/O ADCs
LTC1609
200ksps
250ksps
65mW
Configurable Bipolar or Unipolar Input Ranges, 5V
SO-8, MS8, 1-Channel, 5V/SO-8, MS10, 2-Channel, 5V
LTC1864/LTC1865
References
4.25mW
LT1460
Micropower Precision Series Reference
Micropower Low Dropout Reference
Bandgap, 130μA Supply Current, 10ppm/°C, Available in SOT-23
60μA Supply Current, 10ppm/°C, SOT-23
LT1790
18601fa
LT 1207 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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