LTC1863LCGN [Linear]
Micropower, 3V, 12-/16-Bit, 8-Channel 175ksps ADCs; 微功耗， 3V ， 12位/ 16位， 8通道175ksps模数转换器
| 型号： | LTC1863LCGN |
| 厂家： | 
Linear |
| 描述： | Micropower, 3V, 12-/16-Bit, 8-Channel 175ksps ADCs |
| 文件： | 总16页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1863L/LTC1867L
Micropower, 3V,
12-/16-Bit, 8-Channel
175ksps ADCs
U
FEATURES
DESCRIPTIO
The LTC®1863L/LTC1867L are pin compatible, 8-channel
12-/16-bit A/D converters with serial I/O and an internal
reference.
■
Sample Rate: 175ksps
16-Bit No Missing Codes and ±3LSB Max INL
■
■
8-Channel Multiplexer with:
Single Ended or Differential Inputs and
Unipolar or Bipolar Conversion Modes
The 8-channel input multiplexer can be configured for
either single-ended or differential inputs and unipolar or
bipolar conversions (or combinations thereof). The ADCs
convert 0V to 2.5V unipolar inputs or ±1.25V bipolar
inputs. The ADCs typically draw only 750µA from a single
2.7V supply. The automatic nap and sleep modes benefit
power sensitive applications.
SPI/MICROWIRETM Serial I/O
■
■
2.7V Guaranteed Supply Voltage
Pin Compatible with LTC1863/LTC1867
■
■
True Differential Inputs
On-Chip or External Reference
■
■
Low Power: 750µA at 175ksps, 300µA at 50ksps
■
The LTC1867L’s DC performance is outstanding with a
±3LSBINLspecificationand16-bitnomissingcodesover
temperature.
Sleep Mode
■
Automatic Nap Mode Between Conversions
■
16-Pin Narrow SUSOP Package
Housed in a compact, narrow 16-pin SSOP package, the
LTC1863L/LTC1867L can be used in space-sensitive as
well as low power applications.
APPLICATIO S
■
Industrial Process Control
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
■
High Speed Data Acquisition
■
Battery Operated Systems
■
Multiplexed Data Acquisition Systems
■
Imaging Systems
W
BLOCK DIAGRA
Integral Nonlinearity vs Output Code
(LTC1867L)
LTC1863L/LTC1867L
1
2
3
4
5
6
7
8
CH0
CH1
16
15
14
13
12
11
10
2.0
V
DD
V
f
= 2.7V
SAMPLE
DD
= 175ksps
GND
1.5
1.0
CH2
SDI
ANALOG
INPUT
MUX
CH3
12-/16-BIT
175ksps
ADC
+
–
SDO
SERIAL
PORT
0.5
CH4
SCK
CH5
0
CS/CONV
CH6
V
REF
–0.5
–1.0
–1.5
–2.0
CH7/COM
INTERNAL
1.25V REF
9
REFCOMP
32768
0
16384
49152
65536
1863L7L BD
OUTPUT CODE
1863L7L G01
1863L7Lf
1
LTC1863L/LTC1867L
W W
U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Notes 1, 2)
ORDER PART
Supply Voltage (VDD)................................... –0.3V to 6V
Analog Input Voltage
CH0-CH7/COM (Note 3) .......... –0.3V to (VDD + 0.3V)
VREF, REFCOMP (Note 4)......... –0.3V to (VDD + 0.3V)
Digital Input Voltage (SDI, SCK, CS/CONV)
(Note 4) .................................................–0.3V to 10V
Digital Output Voltage (SDO) ....... –0.3V to (VDD + 0.3V)
Power Dissipation.............................................. 500mW
Operating Temperature Range
LTC1863LC/LTC1867LC/LTC1867LAC .... 0°C to 70°C
LTC1863LI/LTC1867LI/LTC1867LAI .. –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TOP VIEW
NUMBER
CH0
CH1
1
2
3
4
5
6
7
8
16
V
DD
LTC1863LCGN
LTC1863LIGN
LTC1867LCGN
LTC1867LIGN
LTC1867LACGN
LTC1867LAIGN
15 GND
CH2
14
13
12
11
10
9
SDI
CH3
SDO
CH4
SCK
CH5
CS/CONV
CH6
V
REF
CH7/COM
REFCOMP
GN PART MARKING
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
1863L
1863LI
1867L*
TJMAX = 110°C, θJA = 95°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
U
CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 2.7V, external VREF = 1.25V (Notes 5, 6)
LTC1863L
TYP
LTC1867L
TYP
LTC1867LA
TYP
PARAMETER
CONDITIONS
MIN
12
MAX
MIN
16
MAX
MIN
16
MAX
UNITS
Bits
Resolution
●
●
No Missing Codes
Integral Linearity Error
12
15
16
Bits
Unipolar (Note 7)
Bipolar
●
●
±1
±1
±4
±4
±3
±3
LSB
LSB
Differential Linearity Error
Transition Noise
Offset Error
●
±1
–2
–1
LSB
0.1
1.6
1.6
LSB
RMS
Unipolar (Note 8)
Bipolar
●
●
±3
±4
±32
±64
±32
±64
LSB
LSB
Offset Error Match
Unipolar
Bipolar
±1
±1
±4
±4
±3
±3
LSB
LSB
Offset Error Drift
Gain Error
±0.5
±0.5
±0.5
ppm/°C
Unipolar
Bipolar
±6
±6
±96
±96
±64
±64
LSB
LSB
Gain Error Match
Unipolar
Bipolar
±1
±1
±4
±4
±3
±3
LSB
LSB
Gain Error Tempco
Internal Reference
External Reference
±20
±3
±20
±3
±20
±3
ppm/°C
ppm/°C
Power Supply Sensitivity
V
= 2.7V – 3.6V
±1
±3
±3
LSB
DD
U W
DY A IC ACCURACY
VDD = 3V, external VREF = 1.25V (Note 5)
LTC1863L
TYP
LTC1867L/LTC1867LA
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
83.3
82.6
MAX
UNITS
dB
SNR
Signal-to-Noise Ratio
1kHz Input Signal
1kHz Input Signal
73.2
73.1
S/(N+D)
Signal-to-(Noise + Distortion) Ratio
dB
1863L7Lf
2
LTC1863L/LTC1867L
U W
DY A IC ACCURACY
VDD = 3V, external VREF = 1.25V (Note 5)
LTC1863L
TYP
LTC1867L/LTC1867LA
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
dB
THD
Total Harmonic Distortion
1kHz Input Signal, Up to 5th Harmonic
1kHz Input Signal
–92.3
–94.5
–100
1.25
– 91
Peak Harmonic or Spurious Noise
Channel-to-Channel Isolation
–92.8
–112
1.25
dB
100kHz Input Signal
–3dB Point
dB
MHz
U
Full Power BU andwidth
A ALOG I PUT
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
LTC1863L/LTC1867L/LTC1867LA
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Analog Input Range
Unipolar Mode (Note 9)
Bipolar Mode
●
●
0 to 2.5
±1.25
V
V
C
Analog Input Capacitance for CH0 to
CH7/COM
Between Conversions (Sample Mode)
During Conversions (Hold Mode)
32
4
pF
pF
IN
t
Sample-and-Hold Acquisition Time
Input Leakage Current
●
●
2.01
1.68
µs
ACQ
On Channels, CHX = 0V or V
±1
µA
DD
U U
U
(Note 5)
I TER AL REFERE CE CHARACTERISTICS
LTC1863L/LTC1867L/LTC1867LA
PARAMETER
CONDITIONS
MIN
TYP
1.25
±20
0.3
3
MAX
UNITS
V
V
V
V
V
Output Voltage
Output Tempco
Line Regulation
Output Resistance
I
I
= 0
= 0
1.235
1.265
REF
REF
REF
REF
OUT
OUT
ppm/°C
mV/V
kΩ
2.7V ≤ V ≤ 3.6V
DD
⏐I ⏐ ≤0.1mA
OUT
REFCOMP Output Voltage
I
= 0
2.5
V
OUT
U
U
DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1863L/LTC1867L/LTC1867LA
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
V
= 3.6V
= 2.7V
●
●
●
1.9
V
V
IH
IL
DD
DD
IN
0.45
I
= 0V to V
±10
µA
pF
IN
DD
C
V
Digital Input Capacitance
High Level Output Voltage (SDO)
2
IN
V
DD
V
DD
= 2.7V, I = –10µA
= 2.7V, I = –200µA
2.68
2.65
V
V
OH
O
●
●
2.3
O
V
Low Level Output Voltage (SDO)
V
DD
V
DD
= 2.7V, I = 160µA
= 2.7V, I = 1.6mA
0.05
0.15
V
V
OL
O
0.4
O
I
I
Output Source Current
Output Sink Current
SDO = 0V
SDO = V
–9.7
6
mA
mA
SOURCE
SINK
DD
Hi-Z Output Leakage
Hi-Z Output Capacitance
CS/CONV = High, SDO = 0V or V
CS/CONV = High (Note 10)
●
●
±10
15
µA
pF
DD
Data Format
Unipolar
Bipolar
Straight Binary
Two’s Complement
1863L7Lf
3
LTC1863L/LTC1867L
W U
POWER REQUIRE E TS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1863L/LTC1867L/LTC1867LA
SYMBOL
PARAMETER
Supply Voltage
Supply Current
CONDITIONS
MIN
TYP
MAX
3.6
1
UNITS
V
(Note 9)
2.7
V
DD
I
f
= 175ksps, Internal REF
SAMPLE
●
0.75
170
0.2
mA
µA
µA
DD
NAP Mode
SLEEP Mode
●
●
3
P
Power Dissipation
f
= 175ksps
SAMPLE
2
2.7
mW
DISS
W U
TI I G CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1863L/LTC1867L/LTC1867LA
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
3.7
20
UNITS
kHz
µs
f
t
t
f
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Conversion Time
●
●
●
175
SAMPLE
3.2
CONV
Acquisition Time
2.01
40
5
1.68
µs
ACQ
SCK
1
SCK Frequency
MHz
ns
CS/CONV High Time
Short CS/CONV Pulse Mode
●
●
●
●
●
●
100
22
17
20
–6
6
SDO Valid After SCK↓
C = 25pF (Note 11)
L
47
ns
2
SDO Valid Hold Time After SCK↓
SDO Valid After CS/CONV↓
SDI Setup Time Before SCK↑
SDI Hold Time After SCK↑
SLEEP Mode Wake-Up Time
Bus Relinquish Time After CS/CONV↑
C = 25pF
L
ns
3
C = 25pF
L
40
ns
4
15
15
ns
5
ns
6
C
= 10µF, C = 2.2µF
VREF
80
30
ms
ns
7
REFCOMP
C = 25pF
L
●
50
8
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 8: Unipolar offset is the offset voltage measured from +1/2LSB
when the output code flickers between 0000 0000 0000 0000 and
0000 0000 0000 0001 for LTC1867L and between 0000 0000 0000 and
0000 0000 0001 for LTC1863L. Bipolar offset is the offset voltage
measured from –1/2LSB when output code flickers between 0000 0000
0000 0000 and 1111 1111 1111 1111 for LTC1867L, and between
0000 0000 0000 and 1111 1111 1111 for LTC1863L.
Note 2: All voltage values are with respect to GND (unless otherwise
noted).
Note 3: When these pin voltages are taken below GND or above V , they
DD
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA without latchup.
Note 4: When these pin voltages are taken below GND, they will be
clamped by internal diodes. This product can handle input currents of
greater than 100mA below GND without latchup. These pins are not
Note 9: Recommended operating conditions. The input range of ±1.25V
–
for bipolar mode is measured with respect to V = 1.25V. For unipolar
IN
mode, common mode input range is 0V to V for the positive input and
DD
0V to 1.5V for the negative input. For bipolar mode, common mode input
clamped to V
.
DD
range is 0V to V for both positive and negative inputs.
DD
Note 5: V = 2.7V, f
= 175ksps and f
= 20MHz at 25°C,
DD
SAMPLE
SCK
Note 10: Guaranteed by design, not subject to test.
–
t = t = 5ns and V = 1.25V for bipolar mode unless otherwise specified.
r
f
IN
Note 11: t of 47ns maximum allows f
up to 10MHz for rising capture
2
SCK
Note 6: Linearity, offset and gain error specifications apply for both
unipolar and bipolar modes. The INL and DNL are tested in bipolar mode.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
with 50% duty cycle and f
up to 20MHz for falling capture (with 3ns
SCK
setup time for the receiving logic).
1863L7Lf
4
LTC1863L/LTC1867L
U W
TYPICAL PERFOR A CE CHARACTERISTICS (LTC1867L)
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
4096 Points FFT Plot
(VDD = 2.7V, Internal REF)
0
–20
–40
2.0
1.5
2.0
1.5
V
= 2.7V
DD
f
= 175ksps
SAMPLE
1.0
1.0
0.5
0.5
–60
–80
0
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
–100
–120
–140
21.875
43.75
87.5
32768
32768
0
65.625
0
16384
49152
65536
0
16384
49152
65536
FREQUENCY (kHz)
OUTPUT CODE
OUTPUT CODE
1863L7L G03
1863L7L G01
1863L7L G02
4096 Points FFT Plot
(VDD = 3V, REFCOMP = Ext 3V)
Signal-to-(Noise + Distortion)
Ratio vs Input Frequency
Crosstalk vs Input Frequency
–60
–70
0
–20
–40
100
90
80
70
60
50
40
30
20
V = 3V
DD
SAMPLE
f
= 175ksps
SNR
–80
–90
–60
–80
SINAD
–100
–110
–120
–130
–140
ADJACENT PAIR
–100
–120
–140
NONADJACENT
PAIR
V
= 3V
DD
INTERNAL REF
= 175ksps
f
SAMPLE
0.1
1
10
100
1000
21.875
43.75
87.5
0
65.625
1
10
INPUT FREQUENCY (kHz)
100
ACTIVE CHANNEL INPUT FREQUENCY (kHz)
FREQUENCY (kHz)
1863L7L G05
1863L7L G04
1863L7L G06
Supply Current vs fSAMPLE
(LTC1863L/LTC1867L)
Total Harmonic Distortion
vs Input Frequency
Power Supply Feedthrough
vs Ripple Frequency
–20
–30
–40
–50
–60
–70
–80
–90
–100
800
700
600
500
400
300
200
100
–100
–90
–80
–70
–60
–50
–40
–30
–20
V
= 3V
V
= 2.7V
DD
DD
f
= 175ksps
SAMPLE
V
= 10mV
RIPPLE
P-P
SFDR
THD
V
= 3V
DD
INTERNAL REF
= 175ksps
f
SAMPLE
1
10
f
100
(ksps)
1000
1
10
100
1000
1
10
INPUT FREQUENCY (kHz)
100
RIPPLE FREQUENCY (kHz)
SAMPLE
1863L7L G09
1863L7L G08
1863L7L G06
1863L7Lf
5
LTC1863L/LTC1867L
U W
(LTC1863L/LTC1867L)
TYPICAL PERFOR A CE CHARACTERISTICS
Histogram for 4096 Conversions
(LTC1867L)
Supply Current vs Supply Voltage
Supply Current vs Temperature
1200
1000
800
600
400
200
0
1500
1250
1000
750
1200
1100
1000
900
f = 175ksps
SAMPLE
INTERNAL REF
V
= 2.7V
f
= 175ksps
DD
SAMPLE
1044
895
INTERNAL REF
830
3.6V
DD
DD
3.3V
3V
465
DD
800
333
2.7V
DD
261
170
700
58
23
9
7
1
500
600
–50
–25
0
25
50
75
100
20 21 22 23 24 25 26 27 28 29 30 31
CODE
2.7
3
3.3
3.6
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
1863L7L G11
1863L7L G12
1963L7L G10
Offset Drift (LTC1867L)
vs Temperature
Gain Error Drift (LTC1867L)
vs Temperature
REFCOMP vs Load Current
15
10
5
2.510
2.505
2.500
10
5
V
= 2.7V
V
f
= 2.7V
DD
V
= 2.7V
DD
DD
UNIPOLAR
MODE
= 175ksps
= 1.25V
f
= 175ksps
= 1.25V
SAMPLE
EXT V
SAMPLE
EXT V
REF
REF
UNIPOLAR/BIPOLAR
BIPOLAR
MODE
2.495
2.490
2.485
2.480
2.475
0
0
–5
–10
–15
–5
–10
–50
0
25
50
75
100
0.5
1
2
–25
0
1.5
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
LOAD CURRENT (mA)
1863L7L G15
1863L7L G13
1863L7L G14
Differential Nonlinearity
vs Output Code (LTC1863L)
Integral Nonlinearity
vs Output Code (LTC1863L)
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
2048 2560
CODE
2048 2560
CODE
0
512 1024 1536
3072 3584 4096
0
512 1024 1536
3072 3584 4096
1863L7L G16
1863L7L G17
1863L7Lf
6
LTC1863L/LTC1867L
U
U
U
PI FU CTIO S
CHO-CH7/COM (Pins 1-8): Analog Input Pins. Analog
inputs must be free of noise with respect to GND. CH7/
COM can be either a separate channel or the common
minus input for the other channels. Unused channels
should be tied to ground.
SCK (Pin 12): Shift Clock. This clock synchronizes the
serial data transfer.
SDO (Pin 13): Digital Data Output. The A/D conversion
result is shifted out of this output. Straight binary format
for unipolar mode and two’s complement format for
bipolar mode.
REFCOMP(Pin9):ReferenceBufferOutputPin.Bypassto
GND with 10µF tantalum capacitor in parallel with 0.1µF
ceramiccapacitor(2.5VNominal).TooverdriveREFCOMP,
tie VREF to GND.
SDI (Pin 14): Digital Data Input Pin. The A/D configuration
word is shifted into this input.
GND (Pin 15): Analog and Digital GND.
V
REF (Pin 10): 1.25V Reference Output. This pin can also
VDD (Pin 16): Analog and Digital Power Supply. Bypass to
GND with 10µF tantalum capacitor in parallel with 0.1µF
ceramic capacitor.
be used as an external reference buffer input for improved
accuracy and drift. Bypass to GND with 2.2µF tantalum
capacitor in parallel with 0.1µF ceramic capacitor.
CS/CONV (Pin 11): This input provides the dual function
of initiating conversions on the ADC and also frames the
serial data transfer.
U
U
U U U
TYPICAL CO ECTIO DIAGRA
+
2.7V TO 3.6V
10µF
CH0
V
DD
±1.25V
DIFFERENTIAL
INPUTS
CH1
CH2
CH3
CH4
CH5
CH6
GND
SDI
–
LTC1863L/
LTC1867L
SDO
SCK
DIGITAL
I/O
2.5V
SINGLE-ENDED
INPUT
+
CS/CONV
1.25V
V
REF
2.2µF
CH7/COM REFCOMP
2.5V
10µF
1863L7L TCD
TEST CIRCUITS
Load Circuits for Access Timing
Load Circuits for Output Float Delay
2.7V
2.7V
3k
3k
SDO
SDO
SDO
SDO
3k
C
L
C
L
3k
C
C
L
L
(A) V TO Hi-Z
OH
(B) V TO Hi-Z
OL
(A) Hi-Z TO V AND V TO V
OH OL
(B) Hi-Z TO V AND V TO V
OL OH
OH
OL
1863L7L TC02
1863L7L TC01
1863L7Lf
7
LTC1863L/LTC1867L
W U
W
TI I G DIAGRA S
t
(For Short Pulse Mode)
t (SDO Valid After SCK↓),
2
1
t (SDO Valid Hold Time After SCK↓)
3
t
1
t
2
50%
50%
CS/CONV
SCK
SDO
0.45V
t
3
1.9V
0.45V
t (SDI Setup Time Before SCK↑),
5
t (SDO Valid After CS/CONV↓)
4
t (SDI Hold Time After SCK↑)
6
t
t
6
t
4
5
1.9V
CS/CONV
SDO
SCK
SDI
0.45V
Hi-Z
1.9V
0.45V
1.9V
0.45V
1.9V
0.45V
t (SLEEP Mode Wake-Up Time)
7
t (BUS Relinquish Time)
8
t
t
7
8
1.9V
SCK
50%
CS/CONV
SDO
SLEEP BIT (SLP = 0)
READ-IN
90%
10%
Hi-Z
CS/CONV
50%
1863L7L TD
W U U
U
APPLICATIO S I FOR ATIO
Overview
The LTC1863L/LTC1867L are complete, low power, multi-
plexedADCs.Theyconsistofa12-/16-bit,175kspscapaci-
tive successive approximation A/D converter, a precision
internal reference, a configurable 8-channel analog input
multiplexer (MUX) and a serial port for data transfer.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). The input is sucessively compared with the binary
weighted charges supplied by the differential capacitive
DAC. Bit decisions are made by a low power, differential
comparator that rejects common mode noise. At the end
ofaconversion, theDACoutputbalancestheanaloginput.
The SAR content (a 12-/16-bit data word) that represents
the analog input is loaded into the 12-/16-bit output
latches.
Conversions are started by a rising edge on the CS/CONV
input. Once a conversion cycle has begun, it cannot be
restarted.Betweenconversions,theADCsreceiveaninput
word for channel selection and output the conversion
result, and the analog input is acquired in preparation for
thenextconversion.Intheacquirephase,aminimumtime
of 2.01µs will provide enough time for the sample-and-
hold capacitors to acquire the analog signal.
1863L7Lf
8
LTC1863L/LTC1867L
W U U
APPLICATIO S I FOR ATIO
U
Changing the MUX Assignment “On the Fly”
Analog Input Multiplexer
1st Conversion
2nd Conversion
The analog input multiplexer is controlled by a 7-bit input
data word. The input data word is defined as follows:
+
–
+
–
CH2
CH3
–
+
CH2
CH3
SD OS S1 S0 COM UNI SLP
SD = SINGLE/DIFFERENTIAL BIT
OS = ODD/SIGN BIT
{
{
{
{
CH4
CH5
+
+
CH4
CH5
CH7/COM
(UNUSED)
CH7/COM (
)
–
S1 = ADDRESS SELECT BIT 1
S0 = ADDRESS SELECT BIT 0
COM = CH7/COM CONFIGURATION BIT
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
1863L7L AI02
Tables 1 and 2 show the configurations when COM = 0,
and COM = 1.
Table 1. Channel Configuration (When COM = 0, CH7/COM Pin
Is Used as CH7)
Channel Configuration
SD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
OS
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0 COM
“+”
CH0
CH2
CH4
CH6
CH1
CH3
CH5
CH7
CH0
CH2
CH4
CH6
CH1
CH3
CH5
CH7
“–”
CH1
CH3
CH5
CH7
CH0
CH2
CH4
CH6
GND
GND
GND
GND
GND
GND
GND
GND
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Examples of Multiplexer Options
4 Differential
8 Single-Ended
CH0
CH1
+
–
+
–
(
(
)
)
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
+
+
+
+
+
+
+
+
–
{
{
{
{
+
(
(
)
)
CH2
CH3
–
+
+
–
+
–
(
(
)
)
CH4
CH5
–
+
CH6
(
(
)
)
–
CH7/COM
+
GND (
)
–
7 Single-Ended
to CH7/COM
Combinations of Differential
and Single-Ended
CH0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
+
+
+
+
+
+
+
+
{
CH1
–
CH2
CH3
–
{
+
+
+
+
+
CH4
CH5
CH6
CH7/COM
Table 2. Channel Configuration (When COM = 1, CH7/COM Pin
Is Used as COMMON)
CH7/COM (
)
–
GND ( )
–
1863L7L AI01
Channel Configuration
"+"
SD
1
OS
0
S1
0
S0 COM
"–"
0
1
0
1
0
1
0
1
1
1
1
1
1
1
CH0
CH2
CH4
CH6
CH1
CH3
CH5
CH7/COM
CH7/COM
CH7/COM
CH7/COM
CH7/COM
CH7/COM
CH7/COM
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1863L7Lf
9
LTC1863L/LTC1867L
W U U
U
APPLICATIO S I FOR ATIO
Driving the Analog Inputs
The analog inputs of the LTC1863L/LTC1867L are easy to
drive. Each of the analog inputs can be used as a single-
ended input relative to the GND pin (CH0-GND, CH1-GND,
etc)orinpairs(CH0andCH1, CH2andCH3, CH4andCH5,
CH6 and CH7) for differential inputs. In addition, CH7 can
act as a COM pin for both single-ended and differential
modes if the COM bit in the input word is high. Regardless
of the MUX configuration, the “+” and “–” inputs are
sampled at the same instant. Any unwanted signal that is
common mode to both inputs will be reduced by the
common mode rejection of the sample-and-hold circuit.
The inputs draw only one small current spike while charg-
ing the sample-and-hold capacitors during the acquire
mode. In conversion mode, the analog inputs draw only a
small leakage current. If the source impedance of the
driving circuit is low then the LTC1863L/LTC1867L inputs
can be driven directly. More acquisition time should be
allowed for a higher impedance source.
LT1638/LT1639: Dual/quad 1.2MHz, 0.4V/µs amplifiers,
230µA per amplifier, 3V, 5V and ±15V supplies.
LT1881/LT1882: Dual and quad, 200pA bias current, rail-
to-rail output op amps, up to ±15V supplies.
LTC1992-2: Gain of 2 fully differential input/output am-
plifier/driver, 2.5mV offset, CLOAD stable, 2.7V to ±5V
supplies.
LT1995: 30MHz, 1000V/µs gain selectable amplifier, pin
configurable as a difference amplifier, inverting and
noninverting amplifier, ±2.5V to ±15V supplies.
LTC6912: Dual programmable gain amplifiers with SPI
serial interface, 2mV offset, 2.7V to ±5V supplies.
LTC6915: Zero drift, instrumentation amplifier with SPI
programmable gain, 125dB CMRR, 0.1% gain accuracy,
10µV offset.
Input Filtering
The following list is a summary of the op amps that are
suitable for driving the LTC1863L/LTC1867L. More de-
tailed information is available in the Linear Technology
data books or Linear Technology website.
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1863L/LTC1867L noise and distortion. Noisy in-
put circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For instance, Figure 1 shows a 50Ω
source resistor and a 2000pF capacitor to ground on the
input will limit the input bandwidth to 1.6MHz. The source
impedance has to be kept low to avoid gain error and
degradation in the AC performance. The capacitor also
acts as a charge reservoir for the input sample-and-hold
and isolates the ADC input from sampling glitch sensitive
circuitry. High quality capacitors and resistors should be
LT®1468: 90MHz, 22V/µs 16-bit accurate amplifier
LT1469: Dual LT1468
LT1490A/LT1491A: Dual/quad micropower amplifiers,
50µA/amplifier max, 500µV offset, common mode range
extends 44V above V– independent of V+, 3V, 5V and ±15V
supplies.
LT1568: Very low noise, active RC filter building block,
cutoff frequency up to 10MHz, 2.7V to ±5V supplies.
1000pF
50Ω
ANALOG
INPUT
50Ω
CH0
CH0
DIFFERENTIAL
LTC1863L/
2000pF
LTC1863L/
LTC1867L
ANALOG
INPUTS
1000pF
1000pF
LTC1867L
GND
50Ω
CH1
REFCOMP
REFCOMP
10µF
10µF
1863L7L F01a
1863L7L F01b
Figure 1a. Optional RC Input Filtering for Single-Ended Input
Figure 1b. Optional RC Input Filtering for Differential Inputs
1863L7Lf
10
LTC1863L/LTC1867L
W U U
APPLICATIO S I FOR ATIO
U
usedsincethesecomponentscanadddistortion.NPOand
silver mica type dielectric capacitors have excellent linear-
ity. Carbon surface mount resistors can also generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resis-
tors are much less susceptible to both problems.
components at the A/D output. The output is band limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency.Figure3ashowsatypicalSINADof81.4dBwith
a175kHzsamplingrateanda1kHzinput.HigherSINADcan
be obtained with a 3V supply. For example, when an exter-
nal 3V is applied to REFCOMP (tie VREF to GND), a SINAD
of 83.5dB can be achieved as shown in Figure 3b.
DC Performance
0
Onewayofmeasuringthetransitionnoiseassociatedwith
a high resolution ADC is to use a technique where a DC
signal is applied to the input of the ADC and the resulting
output codes are collected over a large number of conver-
sions. For example, in Figure 2 the distribution of output
codes is shown for a DC input that had been digitized 4096
times. The distribution is Gaussian and the RMS code
transition noise is about 1.6LSB.
–20
–40
–60
–80
–100
–120
–140
1200
V
= 2.7V
DD
1044
895
INTERNAL REF
21.875
43.75
87.5
0
65.625
1000
800
600
400
200
0
FREQUENCY (kHz)
830
1863L7L G03
Figure 3a. LTC1867L Nonaveraged 4096 Point
FFT Plot with 2.7V Supply
465
333
0
261
170
–20
–40
58
23
9
7
1
20 21
24 25 26 27 28 29 30 31
CODE
22 23
–60
–80
1863L7L G12
Figure 2. LTC1867L Histogram for 4096 Conversions
–100
–120
–140
Dynamic Performance
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental.
21.875
43.75
87.5
0
65.625
FREQUENCY (kHz)
1863L7L F03b
Figure 3b. LTC1867L Nonaveraged 4096 Point
FFT Plot with 3V Supply
Signal-to-Noise Ratio
Total Harmonic Distortion
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency to the RMS amplitude of all other frequency
Total Harmonic Distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
1863L7Lf
11
LTC1863L/LTC1867L
W U U
U
APPLICATIO S I FOR ATIO
band between DC and half the sampling frequency. THD is
expressed as:
compensation pin, REFCOMP, must be bypassed with a
10µF ceramic or tantalum in parallel with a 0.1µF ceramic
for best noise performance.
2
V22 + V32 + V42... + VN
THD = 20log
Digital Interface
V1
The LTC1863L and LTC1867L have a very simple digital
interface that is enabled by the control input, CS/CONV. A
logic rising edge applied to the CS/CONV input will initiate
a conversion. After the conversion, taking CS/CONV low
will enable the serial port and the ADC will present digital
data in two’s complement format in bipolar mode or
straight binary format in unipolar mode, through the SCK/
SDO serial port.
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the
second through Nth harmonics.
Internal Reference
T
he LTC1863L and LTC1867L have an on-chip, tempera-
ture compensated, curvature corrected, bandgap refer-
ence that is factory trimmed to 1.25V. It is internally
connected to a reference amplifier and is available at VREF
(Pin 10). A 3k resistor is in series with the output so that
it can be easily overdriven by an external reference if
better drift and/or accuracy are required as shown in
Figure4.ThereferenceamplifiergainstheVREF voltageby
2x to 2.5V at REFCOMP (Pin 9). This reference amplifier
Internal Clock
The internal clock is factory trimmed to achieve a typical
conversion time of 3.2µs and a maximum conversion
time, 3.7µs, overthefulloperatingtemperaturerange. The
typical acquisition time is 1.68µs, and a throughput sam-
pling rate of 175ksps is tested and guaranteed.
R1
3k
Automatic Nap Mode
V
10
2.2µF
9
REF
BANDGAP
REFERENCE
1.25V
TheLTC1863LandLTC1867Lgointoautomaticnapmode
when CS/CONV is held high after the conversion is com-
plete. With a typical operating current of 750µA and auto-
matic 170µA nap mode between conversions, the power
dissipation drops with reduced sample rate. The ADC only
keepstheVREFand REFCOMPvoltagesactivewhenthepart
is in the automatic nap mode. The slower the sample rate
allows the power dissipation to be lower (see Figure 5).
REFCOMP
REFERENCE
AMP
2.5V
10µF
R2
R3
GND
15
LTC1863L/LTC1867L
1863L7L F04a
800
V
= 2.7V
DD
Figure 4a. LT1867L Reference Circuit
700
600
500
400
300
200
100
3V
V
IN
LT1790A-1.25
10
2.2µF
9
V
V
OUT
REF
LTC1863L/
LTC1867L
REFCOMP
+
10µF
0.1µF
15
1
10
f
100
(ksps)
1000
GND
SAMPLE
1863L7L F04b
1863L7L G09
Figure 5. Supply Current vs fSAMPLE
Figure 4b. Using the LT1790A-1.25 as an External Reference
1863L7Lf
12
LTC1863L/LTC1867L
W U U
APPLICATIO S I FOR ATIO
U
If the CS/CONV returns low during a bit decision, it can
create a small error. For best performance ensure that the
CS/CONVreturnsloweitherwithin100nsaftertheconver-
sion starts (i.e. before the first bit decision) or after the
conversion ends. If CS/CONV is low when the conversion
ends, the MSB bit will appear on SDO at the end of the
conversion and the ADC will remain powered up.
the common return for these bypass capacitors is essen-
tial to the low noise operation of the ADC. The width for
these tracks should be as wide as possible.
Timing and Control
Conversion start is controlled by the CS/CONV digital
input. The rising edge transition of the CS/CONV will start
aconversion.Onceinitiated,itcannotberestarteduntilthe
conversion is complete. Figures 6 and 7 show the timing
diagrams for two types of CS/CONV pulses.
Sleep Mode
If the SLP = 1 is selected in the input word, the ADC will
enter SLEEP mode and draw only leakage current (pro-
vided that all the digital inputs stay at GND or VDD). After
release from the SLEEP mode, the ADC needs 80ms to
wake up (charge the 2.2µF/10µF bypass capacitors on
VREF/REFCOMP pins).
Example 1 (Figure 6) shows the LTC1863L/LTC1867L
operating in automatic nap mode with CS/CONV signal
staying HIGH after the conversion. Automatic nap mode
provides power reduction at reduced sample rate.
The ADCs can also operate with the CS/CONV signal
returning LOW before the conversion ends. In this mode
(Example 2, Figure 7), the ADCs remain powered up. The
digital output, SDO, will go HIGH immediately after the
conversion is complete if the analog inputs are above half
scaleinunipolarmodeorbelowhalfscaleinbipolarmode.
This is a way to measure the conversion time of the A/D
converter.
Board Layout and Bypassing
To obtain the best performance, a printed circuit board
with a ground plane is required. Layout for the printed
circuit board should ensure digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital signal alongside an
analog signal.
Figures 8 and 9 are the transfer characteristics for the
bipolar and unipolar mode.
All analog inputs should be screened by GND. VREF
REFCOMP and VDD should be bypassed to this ground
plane as close to the pin as possible; the low impedance of
,
1/f
SCK
CS/CONV
t
NAP MODE
CONV
NOT NEEDED FOR LTC1863L
12 13 14 15 16
SCK
SDI
1
2
3
4
5
6
7
8
9
10
11
DON'T CARE
DON'T CARE
SD 0S
MSB
S1 S0 COM UNI SLP
Hi-Z
Hi-Z
SDO
(LTC1863L)
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO
(LTC1867L)
1867 F06
Figure 6. Example 1, CS/CONV Starts a Conversion and Remains HIGH Until Next Data Transfer. With CS/CONV
Remaining HIGH after the Conversion, Automatic Nap Modes Provides Power Reduction at Reduced Sample Rate
1863L7Lf
13
LTC1863L/LTC1867L
U
W U U
APPLICATIO S I FOR ATIO
t
CS/CONV
ACQ
NOT NEEDED FOR LTC1863L
12 13 14 15 16
SCK
SDI
1
2
3
4
5
6
7
8
9
10
11
SD 0S
S1 S0 COM UNI SLP
DON'T CARE
DON'T CARE
t
CONV
SDO
MSB = D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(LTC1863L)
Hi-Z
Hi-Z
t
CONV
SDO
(LTC1867L)
MSB = D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1863L7L F07
Figure 7. Example 2, CS/CONV Starts a Conversion with Short Active HIGH Pulse.
With CS/CONV Returning LOW Before the Conversion, the ADC Remains Powered Up.
111...111
011...111
011...110
111...110
BIPOLAR
ZERO
100...001
100...000
011...111
011...110
000...001
000...000
111...111
111...110
UNIPOLAR
ZERO
FS = 2.5V
FS = 2.5V
n
000...001
000...000
n
1LSB = FS/2
100...001
100...000
1LSB = FS/2
1LSB (LTC1863L) = 610µV
1LSB (LTC1867L) = 38.1µV
1LSB (LTC1863L) = 610µV
1LSB (LTC1867L) = 38.1µV
–1 0V
LSB
INPUT VOLTAGE (V)
1
–FS/2
FS/2 – 1LSB
0V
FS – 1LSB
LSB
INPUT VOLTAGE (V)
1863L7L F09
1863L7L F08
Figure 8. LTC1863L/LTC1867L Bipolar Transfer
Characteristics (Two’s Complement)
Figure 9. LTC1863L/LTC1867L Unipolar Transfer
Characteristics (Straight Binary)
1863L7Lf
14
LTC1863L/LTC1867L
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1863L7Lf
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC1863L/LTC1867L
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1417
14-Bit, 400ksps Serial ADC
20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
Low Input Offset: 75µV/125µV
LT1468/LT1469
LTC1609
Single/Dual 90MHz, 22V/µs, 16-Bit Accurate Op Amps
16-Bit, 200ksps Serial ADC
65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply
60µA Supply Current, 10ppm/°C, SOT-23 Package
LT1790
Micropower Low Dropout Reference
Micropower Precision Series Reference
10-Bit/12-Bit, 8-Channel, 1.25Msps ADC
10-Bit/12-Bit, 8-Channel, 400ksps ADC
12-Bit, 1-/2-Channel 250ksps ADC in MSOP
LT1790A-1.25
LTC1850/LTC1851
LTC1852/LTC1853
LTC1860/LTC1861
Bandgap, 60µA Max Supply Current, 10ppm/°C, SOT-23 Package
Parallel Output, Programmable MUX and Sequencer, 5V Supply
Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply
850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages
450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages
5V Supply, Pin Compatible with LTC1863L/LTC1867L
850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages
450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages
LTC1860L/LTC1861L 3V, 12-Bit, 1-/2-Channel 150ksps ADC
LTC1863/LTC1867
LTC1864/LTC1865
12-/16-Bit, 8-Channel 200ksps ADC
16-Bit, 1-/2-Channel 250ksps ADC in MSOP
LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel 150ksps ADC in MSOP
1863L7Lf
LT/TP 0105 1K • PRINTED IN USA
16 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
©LINEAR TECHNOLOGY CORPORATION 2005
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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