LTC1863LIGN#PBF [Linear]
LTC1863L - Micropower, 3V, 12-bit, 8-Channel 175ksps ADCs; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LTC1863LIGN#PBF |
| 厂家： | 
Linear |
| 描述： | LTC1863L - Micropower, 3V, 12-bit, 8-Channel 175ksps ADCs; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C 光电二极管 转换器 |
| 文件： | 总16页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1863L/LTC1867L
Micropower, 3V,
12-/16-Bit, 8-Channel
175ksps ADCs
FEATURES
DESCRIPTION
The LTC®1863L/LTC1867L are pin compatible, 8-channel
12-/16-bit A/D converters with serial I/O and an internal
reference.
n
Sample Rate: 175ksps
n
16-Bit No Missing Codes and ±±3SB Maꢀ ꢁN3
n
8-Channel Multipleꢀer with:
n
Single Ended or Differential ꢁnputs and
The 8-channel input multiplexer can be configured for
either single-ended or differential inputs and unipolar or
bipolar conversions (or combinations thereof). The ADCs
convert 0V to 2.5V unipolar inputs or 1.25V bipolar
inputs. The ADCs typically draw only 750µA from a single
2.7V supply. The automatic nap and sleep modes benefit
power sensitive applications.
n
Unipolar or Bipolar Conversion Modes
n
SPꢁ/MꢁCROWꢁRE Serial ꢁ/O
n
2.7V Guaranteed Supply Voltage
n
Pin Compatible with 3TC186±/3TC1867
n
True Differential ꢁnputs
On-Chip or Eꢀternal Reference
n
n
Low Power: 750µA at 175ksps, 300µA at 50ksps
Sleep Mode
n
n
n
The LTC1867L’s DC performance is outstanding with a
3LSB INL specification and 16-bit no missing codes
over temperature.
Automatic Nap Mode Between Conversions
16-Pin Narrow SSOP Package
Housed in a compact, narrow 16-pin SSOP package, the
LTC1863L/LTC1867L can be used in space-sensitive as
well as low power applications.
APPLICATIONS
n
Industrial Process Control
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
n
High Speed Data Acquisition
Technology Corporation. All other trademarks are the property of their respective owners.
n
Battery Operated Systems
n
Multiplexed Data Acquisition Systems
n
Imaging Systems
BLOCK DIAGRAM
ꢁntegral Nonlinearity vs Output Code
(3TC18673)
LTC1863L/LTC1867L
1
2
3
4
5
6
7
8
CH0
CH1
16
15
14
13
12
11
10
2.0
V
DD
V
= 2.7V
DD
f
= 175ksps
GND
SAMPLE
1.5
1.0
CH2
SDI
ANALOG
INPUT
MUX
CH3
12-/16-BIT
175ksps
ADC
+
–
SDO
SERIAL
PORT
0.5
CH4
SCK
CH5
0
CS/CONV
CH6
V
REF
–0.5
–1.0
–1.5
–2.0
CH7/COM
INTERNAL
1.25V REF
9
REFCOMP
32768
0
16384
49152
65536
1863L7L BD
OUTPUT CODE
1863L7L G01
1863l7lfd
1
For more information www.linear.com/LTC1863L
LTC1863L/LTC1867L
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltage (V )................................... –0.3V to 6V
DD
TOP VIEW
Analog Input Voltage
CH0
CH1
1
2
3
4
5
6
7
8
16
V
DD
CH0-CH7/COM (Note 3) ...........–0.3V to (V + 0.3V)
DD
DD
15 GND
V
, REFCOMP (Note 4) ......... –0.3V to (V + 0.3V)
REF
CH2
14
13
12
11
10
9
SDI
Digital Input Voltage (SDI, SCK, CS/CONV)
CH3
SDO
(Note 4) ................................................. –0.3V to 10V
CH4
SCK
Digital Output Voltage (SDO) ....... –0.3V to (V + 0.3V)
CH5
CS/CONV
DD
Power Dissipation.............................................. 500mW
Operating Temperature Range
CH6
V
REF
CH7/COM
REFCOMP
LTC1863LC/LTC1867LC/LTC1867LAC ..... 0°C to 70°C
LTC1863LI/LTC1867LI/LTC1867LAI.....–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
= 110°C, θ = 95°C/W
T
JMAX
JA
Consult LTC Marketing for parts specified with wider operating temperature
ranges.
ORDER INFORMATION
3EAD FREE FꢁNꢁSH
LTC1863LCGN#PBF
LTC1863LIGN#PBF
LTC1867LCGN#PBF
LTC1867LIGN#PBF
LTC1867LACGN#PBF
LTC1867LAIGN#PBF
TAPE AND REE3
PART MARKꢁNG*
1863L
PACKAGE DESCRꢁPTꢁON
TEMPERATURE RANGE
0°C to 70°C
LTC1863LCGN#TRPBF
LTC1863LIGN#TRPBF
LTC1867LCGN#TRPBF
LTC1867LIGN#TRPBF
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
1863L
–40°C to 85°C
0°C to 70°C
1867L
1867L
–40°C to 85°C
0°C to 70°C
LTC1867LACGN#TRPBF 1867L
LTC1867LAIGN#TRPBF 1867L
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 2.7V, eꢀternal VREF = 1.25V (Notes 5, 6)
3TC186±3
TYP
3TC18673
TYP
3TC18673A
TYP
PARAMETER
CONDꢁTꢁONS
MꢁN
12
MAX
MꢁN
16
MAX
MꢁN
16
MAX
UNꢁTS
Bits
l
l
Resolution
No Missing Codes
Integral Linearity Error
12
15
16
Bits
l
l
Unipolar (Note 7)
Bipolar
1
1
4
4
3
3
LSB
LSB
l
Differential Linearity Error
Transition Noise
1
–2
–1
LSB
0.1
0.5
1.6
0.5
1.6
0.5
LSB
RMS
l
l
Offset Error
Unipolar (Note 8)
Bipolar
3
4
32
64
32
64
LSB
LSB
Offset Error Match
Offset Error Drift
Unipolar
Bipolar
1
1
4
4
3
3
LSB
LSB
ppm/°C
1863l7lfd
2
For more information www.linear.com/LTC1863L
LTC1863L/LTC1867L
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 2.7V, eꢀternal VREF = 1.25V (Notes 5, 6)
3TC186±3
TYP
3TC18673
TYP
3TC18673A
TYP
PARAMETER
CONDꢁTꢁONS
MꢁN
MAX
MꢁN
MAX
MꢁN
MAX
UNꢁTS
Gain Error
Unipolar
Bipolar
6
6
96
96
64
64
LSB
LSB
Gain Error Match
Unipolar
Bipolar
1
1
4
4
3
3
LSB
LSB
Gain Error Tempco
Power Supply Sensitivity
Internal Reference
External Reference
20
3
20
3
20
3
ppm/°C
ppm/°C
V
= 2.7V – 3.6V
1
3
3
LSB
DD
DYNAMIC ACCURACY VDD = ±V, eꢀternal VREF = 1.25V (Note 5)
3TC186±3
TYP
3TC18673/3TC18673A
SYMBO3
SNR
PARAMETER
CONDꢁTꢁONS
MꢁN
MAX
MꢁN
TYP
83.7
MAX
UNꢁTS
dB
Signal-to-Noise Ratio
1kHz Input Signal
73.1
S/(N+D)
THD
Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal
73
83.1
dB
Total Harmonic Distortion
Peak Harmonic or Spurious Noise
Channel-to-Channel Isolation
Full Power Bandwidth
1kHz Input Signal, Up to 5th Harmonic
–91.8
–94.8
–100
1.25
– 92.3
–95.1
–112
1.25
dB
1kHz Input Signal
100kHz Input Signal
–3dB Point
dB
dB
MHz
The l denotes the specifications which apply over the full operating temperature range, otherwise
ANALOG INPUT
specifications are at TA = 25°C. (Note 5)
3TC186±3/3TC18673/3TC18673A
SYMBO3
PARAMETER
CONDꢁTꢁONS
MꢁN
TYP
MAX
UNꢁTS
l
l
Analog Input Range
Unipolar Mode (Note 9)
Bipolar Mode
0 to 2.5
1.25
V
V
C
Analog Input Capacitance for CH0 to Between Conversions (Sample Mode)
32
4
pF
pF
IN
CH7/COM
During Conversions (Hold Mode)
l
l
t
Sample-and-Hold Acquisition Time
Input Leakage Current
2.01
1.68
µs
ACQ
On Channels, CHX = 0V or V
1
µA
DD
(Note 5)
INTERNAL REFERENCE CHARACTERISTICS
3TC186±3/3TC18673/3TC18673A
PARAMETER
CONDꢁTꢁONS
MꢁN
TYP
1.25
20
MAX
UNꢁTS
V
V
V
V
V
Output Voltage
Output Tempco
Line Regulation
Output Resistance
I
I
= 0
= 0
1.235
1.265
REF
REF
REF
REF
OUT
ppm/°C
mV/V
kΩ
OUT
2.7V ≤ V ≤ 3.6V
0.3
3
DD
I
≤0.1mA
OUT
REFCOMP Output Voltage
I
= 0
2.5
V
OUT
The l denotes the specifications which apply over the
DIGITAL INPUTS AND DIGITAL OUTPUTS
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
3TC186±3/3TC18673/3TC18673A
SYMBO3
PARAMETER
CONDꢁTꢁONS
MꢁN
TYP
MAX
UNꢁTS
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
V
= 3.6V
= 2.7V
1.9
V
IH
IL
DD
DD
V
0.45
V
1863l7lfd
3
For more information www.linear.com/LTC1863L
LTC1863L/LTC1867L
The l denotes the specifications which apply over the
DIGITAL INPUTS AND DIGITAL OUTPUTS
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
3TC186±3/3TC18673/3TC18673A
SYMBO3
PARAMETER
CONDꢁTꢁONS
MꢁN
TYP
MAX
UNꢁTS
µA
l
I
Digital Input Current
V
IN
= 0V to V
DD
10
IN
C
V
Digital Input Capacitance
High Level Output Voltage (SDO)
2
pF
IN
V
V
= 2.7V, I = –10µA
2.68
2.65
V
V
OH
DD
DD
O
= 2.7V, I = –200µA
23
l
l
O
V
Low Level Output Voltage (SDO)
V
DD
V
DD
= 2.7V, I = 160µA
0.05
0.15
V
V
OL
O
= 2.7V, I = 1.6µA
0.4
O
I
I
Output Source Current
Output Sink Current
SDO = 0V
SDO = V
–9.7
6
mA
mA
SOURCE
SINK
DD
l
l
Hi-Z Output Leakage
Hi-Z Output Capacitance
CS/CONV = High, SDO = 0V or V
CS/CONV = High (Note 10)
10
15
µA
pF
DD
Data Format
Unipolar
Bipolar
Straight Binary
Two’s Complement
The l denotes the specifications which apply over the full operating temperature
POWER REQUIREMENTS
range, otherwise specifications are at TA = 25°C. (Note 5)
3TC186±3/3TC18673/3TC18673A
SYMBO3
PARAMETER
CONDꢁTꢁONS
MꢁN
TYP
MAX
3.6
1
UNꢁTS
V
Supply Voltage
Supply Current
(Note 9)
2.7
V
DD
l
I
f
= 175ksps, Internal REF
SAMPLE
0.75
170
0.2
mA
µA
µA
DD
NAP Mode
l
l
SLEEP Mode
3
P
DISS
Power Dissipation
f
= 175ksps
SAMPLE
2
2.7
mW
The l denotes the specifications which apply over the full operating temperature
TIMING CHARACTERISTICS
range, otherwise specifications are at TA = 25°C. (Note 5)
3TC186±3/3TC18673/3TC18673A
SYMBO3
PARAMETER
CONDꢁTꢁONS
MꢁN
TYP
MAX
3.7
20
UNꢁTS
kHz
µs
l
l
l
f
t
t
f
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Conversion Time
175
SAMPLE
3.2
CONV
Acquisition Time
2.01
40
5
1.68
µs
ACQ
SCK
1
SCK Frequency
MHz
ns
l
l
l
l
l
l
CS/CONV High Time
Short CS/CONV Pulse Mode
100
22
17
20
–6
6
SDO Valid After SCK↓
SDO Valid Hold Time After SCK↓
SDO Valid After CS/CONV↓
SDI Setup Time Before SCK↑
SDI Hold Time After SCK↑
SLEEP Mode Wake-Up Time
C = 25pF (Note 11)
L
47
ns
2
C = 25pF
L
ns
3
C = 25pF
L
40
ns
4
15
15
ns
5
ns
6
C
= 10µF, C = 2.2µF
VREF
80
30
ms
ns
7
REFCOMP
l
Bus Relinquish Time After CS/CONV↑ C = 25pF
50
8
L
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note ±: When these pin voltages are taken below GND or above V , they
DD
will be clamped by internal diodes. This product can handle input currents
up to 100mA without latchup.
Note 2: All voltage values are with respect to GND (unless otherwise
noted).
1863l7lfd
4
For more information www.linear.com/LTC1863L
LTC1863L/LTC1867L
The l denotes the specifications which apply over the full operating temperature
TIMING CHARACTERISTICS
range, otherwise specifications are at TA = 25°C. (Note 5)
Note 4: When these pin voltages are taken below GND, they will be
measured from –1/2LSB when output code flickers between 0000 0000
0000 0000 and 1111 1111 1111 1111 for LTC1867L, and between
0000 0000 0000 and 1111 1111 1111 for LTC1863L.
clamped by internal diodes. This product can handle input currents up to
100mA below GND without latchup. These pins are not clamped to V
.
DD
Note 5: V = 2.7V, f
= 175ksps and f
= 20MHz at 25°C,
Note 9: Recommended operating conditions. The input range of 1.25V
DD
SAMPLE
SCK
–
–
t = t = 5ns and V = 1.25V for bipolar mode unless otherwise specified.
for bipolar mode is measured with respect to V = 1.25V. For unipolar
r
f
IN
IN
mode, common mode input range is 0V to V for the positive input and
Note 6: Linearity, offset and gain error specifications apply for both
unipolar and bipolar modes. The INL and DNL are tested in bipolar mode.
DD
0V to 1.5V for the negative input. For bipolar mode, common mode input
range is 0V to V for both positive and negative inputs.
DD
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Unipolar offset is the offset voltage measured from +1/2LSB
when the output code flickers between 0000 0000 0000 0000 and
0000 0000 0000 0001 for LTC1867L and between 0000 0000 0000
and 0000 0000 0001 for LTC1863L. Bipolar offset is the offset voltage
Note 10: Guaranteed by design, not subject to test.
Note 11: t of 47ns maximum allows f
up to 10MHz for rising capture
2
SCK
with 50% duty cycle and f
up to 20MHz for falling capture (with 3ns
SCK
setup time for the receiving logic).
TYPICAL PERFORMANCE CHARACTERISTICS
(3TC18673)
ꢁntegral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
4096 Points FFT Plot
(VDD = 2.7V, ꢁnternal REF)
0
–20
–40
2.0
1.5
2.0
1.5
f
= 175ksps
V
f
= 2.7V
SAMPLE
SAMPLE
IN
DD
f
= 1kHz
= 175ksps
SNR = 82.9dB
SINAD = 81.4dB
THD = 86.8dB
1.0
1.0
0.5
0.5
–60
–80
0
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
–100
–120
–140
32768
0
16384
49152
65536
21.875
43.75
87.5
0
65.625
32768
0
16384
49152
65536
OUTPUT CODE
FREQUENCY (kHz)
OUTPUT CODE
1863L7L G02
1863L7L G03
1863L7L G01
4096 Points FFT Plot
(VDD = ±V, REFCOMP = Eꢀt ±V)
Signal-to-(Noise + Distortion)
Ratio vs ꢁnput Frequency
Crosstalk vs ꢁnput Frequency
–60
–70
0
–20
–40
100
90
80
70
60
50
40
30
20
V = 3V
DD
SAMPLE
f
f
= 175ksps
SAMPLE
IN
f
= 175ksps
= 1kHz
SNR = 84.7dB
SINAD = 83.5dB
THD = 90dB
SNR
–80
–90
–60
–80
SINAD
–100
–110
–120
–130
–140
ADJACENT PAIR
–100
–120
–140
NONADJACENT
PAIR
V
= 3V
DD
INTERNAL REF
= 175ksps
f
SAMPLE
0.1
1
10
100
1000
1
10
INPUT FREQUENCY (kHz)
100
21.875
43.75
87.5
0
65.625
ACTIVE CHANNEL INPUT FREQUENCY (kHz)
FREQUENCY (kHz)
1863L7L G05
1863L7L G06
1863L7L G04
1863l7lfd
5
For more information www.linear.com/LTC1863L
LTC1863L/LTC1867L
TYPICAL PERFORMANCE CHARACTERISTICS
(3TC18673)
Supply Current vs fSAMP3E
(3TC186±3/3TC18673)
Total Harmonic Distortion
vs ꢁnput Frequency
Power Supply Feedthrough
vs Ripple Frequency
–100
–90
–80
–70
–60
–50
–40
–30
–20
–20
–30
–40
–50
–60
–70
–80
–90
–100
800
700
600
500
400
300
200
100
V
= 3V
V
= 2.7V
DD
DD
f
= 175ksps
SAMPLE
V
= 10mV
RIPPLE
P-P
SFDR
THD
V
= 3V
DD
INTERNAL REF
= 175ksps
f
SAMPLE
1
10
100
1000
1
10
f
100
(ksps)
1000
1
10
INPUT FREQUENCY (kHz)
100
RIPPLE FREQUENCY (kHz)
SAMPLE
1863L7L G08
1863L7L G09
1863L7L G07
(3TC186±3/ 3TC18673)
Supply Current vs Supply Voltage
Histogram for 4096 Conversions
(3TC18673)
Supply Current vs Temperature
1200
1000
800
600
400
200
0
1200
1100
1000
900
1500
1250
1000
750
V
= 2.7V
f
= 175ksps
f
= 175ksps
DD
SAMPLE
SAMPLE
1044
895
INTERNAL REF
INTERNAL REF
830
3.6V
3.3V
DD
DD
465
3V
DD
800
333
2.7V
DD
261
170
700
58
23
9
7
1
500
600
20 21
24 25 26 27 28 29 30 31
CODE
22 23
–50
–25
0
25
50
75
100
2.7
3
3.3
3.6
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
1863L7L G12
1863L7L G11
1963L7L G10
Offset Drift (3TC18673)
vs Temperature
Gain Error Drift (3TC18673)
vs Temperature
REFCOMP vs 3oad Current
2.510
2.505
2.500
15
10
5
10
5
V
= 2.7V
DD
V
f
= 2.7V
V
f
= 2.7V
DD
DD
UNIPOLAR
MODE
= 175ksps
= 1.25V
= 175ksps
= 1.25V
SAMPLE
EXT V
SAMPLE
EXT V
REF
REF
UNIPOLAR/BIPOLAR
BIPOLAR
MODE
2.495
2.490
2.485
2.480
2.475
0
0
–5
–10
–15
–5
–10
0.5
1
2
0
1.5
–50
0
25
50
75
100
–25
–50
–25
0
25
50
75
100
LOAD CURRENT (mA)
TEMPERATURE (°C)
TEMPERATURE (°C)
1863L7L G13
1863L7L G15
1863l7lfd
6
For more information www.linear.com/LTC1863L
LTC1863L/LTC1867L
TYPICAL PERFORMANCE CHARACTERISTICS
(3TC186±3/ 3TC18673)
Differential Nonlinearity
vs Output Code (3TC186±3)
ꢁntegral Nonlinearity
vs Output Code (3TC186±3)
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
2048 2560
CODE
2048 2560
CODE
0
512 1024 1536
3072 3584 4096
0
512 1024 1536
3072 3584 4096
1863L7L G16
1863L7L G17
PIN FUNCTIONS
CHO-CH7/COM (Pins 1-8): Analog Input Pins. Analog
inputs must be free of noise with respect to GND. CH7/
COM can be either a separate channel or the common
minus input for the other channels. Unused channels
should be tied to ground.
SCK (Pin 12): Shift Clock. This clock synchronizes the
serial data transfer.
SDO (Pin 1±): Digital Data Output. The A/D conversion
result is shifted out of this output. Straight binary format
for unipolar mode and two’s complement format for
bipolar mode.
REFCOMP (Pin 9): Reference Buffer Output Pin. Bypass
to GND with 10µF tantalum capacitor in parallel with 0.1µF
ceramiccapacitor(2.5VNominal).To overdriveREFCOMP,
SDꢁ (Pin 14): Digital Data Input Pin. The A/D configuration
word is shifted into this input.
tie V to GND.
REF
GND (Pin 15): Analog and Digital GND.
V
(Pin 10): 1.25V Reference Output. This pin can also
REF
V
(Pin 16): Analog and Digital Power Supply. Bypass to
be used as an external reference buffer input for improved
accuracy and drift. Bypass to GND with 2.2µF tantalum
capacitor in parallel with 0.1µF ceramic capacitor.
DD
GND with 10µF tantalum capacitor in parallel with 0.1µF
ceramic capacitor.
CS/CONV (Pin 11): This input provides the dual function
of initiating conversions on the ADC and also frames the
serial data transfer.
1863l7lfd
7
For more information www.linear.com/LTC1863L
LTC1863L/LTC1867L
TYPICAL CONNECTION DIAGRAM
+
2.7V TO 3.6V
10µF
CH0
CH1
CH2
CH3
CH4
CH5
CH6
V
DD
1.25V
DIFFERENTIAL
INPUTS
GND
SDI
–
LTC1863L/
LTC1867L
SDO
SCK
DIGITAL
I/O
2.5V
SINGLE-ENDED
INPUT
+
CS/CONV
1.25V
2.2µF
V
REF
CH7/COM REFCOMP
2.5V
10µF
1863L7L TCD
TEST CIRCUITS
3oad Circuits for Access Timing
3oad Circuits for Output Float Delay
2.7V
2.7V
3k
3k
SDO
SDO
SDO
SDO
3k
C
C
L
3k
C
C
L
L
L
(A) V TO Hi-Z
OH
(B) V TO Hi-Z
OL
(A) Hi-Z TO V AND V TO V
OH OL OH
(B) Hi-Z TO V AND V TO V
OL OH
OL
1863L7L TC02
1863L7L TC01
TIMING DIAGRAMS
t2 (SDO Valid After SCK↓)
t± (SDO Valid Hold Time After SCK↓)
t1 (For Short Pulse Mode)
t
1
t
2
50%
50%
CS/CONV
SCK
0.45V
1863L7L TD01a
t
3
1.9V
0.45V
SDO
1863L7L TD01b
t5 (SDꢁ Setup Time Before SCK↑)
t6 (SDꢁ Hold Time After SCK↑)
t4 (SDO Valid After CS/CONV↓)
t
t
t
4
6
5
1.9V
CS/CONV
SCK
SDI
0.45V
Hi-Z
1.9V
0.45V
1.9V
0.45V
1.9V
0.45V
SDO
1863L7L TD01c
1863L7L TD01d
t7 (S3EEP Mode Wake-Up Time)
t8 (BUS Relinquish Time)
t
t
7
8
1.9V
SCK
50%
CS/CONV
SLEEP BIT (SLP = 0)
READ-IN
90%
10%
Hi-Z
CS/CONV
50%
SDO
1863L7L TD01f
1863L7L TD01e
1863l7lfd
8
For more information www.linear.com/LTC1863L
LTC1863L/LTC1867L
APPLICATIONS INFORMATION
Overview
Eꢀamples of Multipleꢀer Options
4 Differential
8 Single-Ended
The LTC1863L/LTC1867L are complete, low power,
multiplexed ADCs. They consist of a 12-/16-bit, 175ksps
capacitive successive approximation A/D converter, a pre-
cision internal reference, a configurable 8-channel analog
input multiplexer (MUX) and a serial port for data transfer.
CH0
CH1
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
+
–
+
–
(
(
)
)
+
+
+
+
+
+
+
+
–
{
{
{
{
+
(
(
)
)
CH2
CH3
–
+
+
–
+
–
(
(
)
)
CH4
CH5
–
+
CH6
CH7/COM
(
(
)
)
–
+
GND (
)
–
Conversions are started by a rising edge on the CS/CONV
input. Once a conversion cycle has begun, it cannot be
restarted.Betweenconversions,theADCsreceiveaninput
word for channel selection and output the conversion re-
sult, and the analog input is acquired in preparation for the
next conversion. In the acquire phase, a minimum time of
2.01µs will provide enough time for the sample-and-hold
capacitors to acquire the analog signal.
7 Single-Ended
to CH7/COM
Combinations of Differential
and Single-Ended
CH0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
+
+
+
+
+
+
+
+
{
CH1
–
CH2
CH3
–
{
+
+
+
+
+
CH4
CH5
CH6
CH7/COM
CH7/COM (
)
GND ( )
–
–
1863L7L
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from
the most significant bit (MSB) to the least significant bit
(LSB). The input is sucessively compared with the binary
weighted charges supplied by the differential capacitive
DAC. Bit decisions are made by a low power, differential
comparator that rejects common mode noise. At the end
ofaconversion, theDACoutputbalancestheanaloginput.
The SAR content (a 12-/16-bit data word) that represents
theanaloginputisloadedintothe12-/16-bitoutputlatches.
Analog Input Multiplexer
Changing the MUX Assignment “On the Fly”
1st Conversion
2nd Conversion
+
–
+
–
CH2
CH3
–
+
CH2
CH3
{
{
{
{
CH4
CH5
+
+
CH4
CH5
CH7/COM
(UNUSED)
CH7/COM (
)
–
1863L7L AI02
Tables 1 and 2 show the configurations when COM = 0,
and COM = 1.
Table 1. Channel Configuration (When COM = 0, CH7/COM Pin
ꢁs Used as CH7)
Channel Configuration
The analog input multiplexer is controlled by a 7-bit input
data word. The input data word is defined as follows:
SD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
OS
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
COM
0
“+”
“–”
CH0
CH1
0
CH2
CH4
CH6
CH1
CH3
CH5
CH7
CH0
CH2
CH4
CH6
CH1
CH3
CH5
CH7
CH3
CH5
CH7
CH0
CH2
CH4
CH6
GND
GND
GND
GND
GND
GND
GND
GND
SD OS S1 S0 COM UNI SLP
SD = SINGLE/DIFFERENTIAL BIT
OS = ODD/SIGN BIT
0
0
0
0
S1 = ADDRESS SELECT BIT 1
S0 = ADDRESS SELECT BIT 0
COM = CH7/COM CONFIGURATION BIT
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
0
0
0
0
0
0
0
0
0
0
1863l7lfd
9
For more information www.linear.com/LTC1863L
LTC1863L/LTC1867L
APPLICATIONS INFORMATION
LT®1468: 90MHz, 22V/µs 16-bit accurate amplifier
LT1469: Dual LT1468
Table 2. Channel Configuration (When COM = 1, CH7/COM Pin
ꢁs Used as COMMON)
CHANNE3 CONFꢁGURATꢁON
SD
OS
S1
S0
COM
“+”
“–”
LT1490A/LT1491A: Dual/quad micropower amplifiers,
50µA/amplifier max, 500µV offset, common mode range
1
0
0
0
1
CH0
CH7/COM
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
1
1
CH2
CH4
CH6
CH1
CH3
CH5
CH7/COM
CH7/COM
CH7/COM
CH7/COM
CH7/COM
CH7/COM
–
+
extends 44V above V independent of V , 3V, 5V and
15V supplies.
LT1568: Very low noise, active RC filter building block,
cutoff frequency up to 10MHz, 2.7V to 5V supplies.
LT1638/LT1639: Dual/quad 1.2MHz, 0.4V/µs amplifiers,
230µA per amplifier, 3V, 5V and 15V supplies.
Driving the Analog ꢁnputs
LT1881/LT1882: Dual and quad, 200pA bias current, rail-
to-rail output op amps, up to 15V supplies.
The analog inputs of the LTC1863L/LTC1867L are easy
to drive. Each of the analog inputs can be used as a
single-ended input relative to the GND pin (CH0-GND,
CH1-GND, etc) or in pairs (CH0 and CH1, CH2 and CH3,
CH4 and CH5, CH6 and CH7) for differential inputs. In
addition, CH7 can act as a COM pin for both single-ended
and differential modes if the COM bit in the input word is
high. Regardless of the MUX configuration, the “+” and
“–” inputs are sampled at the same instant. Any unwanted
signalthatiscommonmodetobothinputswillbereduced
by the common mode rejection of the sample-and-hold
circuit. The inputs draw only one small current spike while
chargingthesample-and-holdcapacitorsduringtheacquire
mode. In conversion mode, the analog inputs draw only
a small leakage current. If the source impedance of the
driving circuit is low then the LTC1863L/LTC1867L inputs
can be driven directly. More acquisition time should be
allowed for a higher impedance source.
LTC1992-2: Gain of 2 fully differential input/output am-
plifier/driver, 2.5mV offset, C
supplies.
stable, 2.7V to 5V
LOAD
LT1995: 30MHz, 1000V/µs gain selectable amplifier, pin
configurable as a difference amplifier, inverting and non-
inverting amplifier, 2.5V to 15V supplies.
LTC6912: Dual programmable gain amplifiers with SPI
serial interface, 2mV offset, 2.7V to 5V supplies.
LTC6915: Zero drift, instrumentation amplifier with SPI
programmable gain, 125dB CMRR, 0.1% gain accuracy,
10µV offset.
ꢁnput Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
theLTC1863L/LTC1867Lnoiseanddistortion.Noisyinput
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
The following list is a summary of the op amps that are
suitable for driving the LTC1863L/LTC1867L. More de-
tailed information is available in the Linear Technology
data books or Linear Technology website.
1000pF
50Ω
ANALOG
INPUT
50Ω
CH0
CH0
DIFFERENTIAL
LTC1863L/
2000pF
LTC1863L/
LTC1867L
ANALOG
INPUTS
1000pF
1000pF
LTC1867L
GND
50Ω
CH1
REFCOMP
REFCOMP
10µF
10µF
1863L7L F01a
1863L7L F01b
Figure 1a. Optional RC ꢁnput Filtering for Single-Ended ꢁnput
Figure 1b. Optional RC ꢁnput Filtering for Differential ꢁnputs
1863l7lfd
10
For more information www.linear.com/LTC1863L
LTC1863L/LTC1867L
APPLICATIONS INFORMATION
many applications. For instance, Figure 1 shows a 50Ω
source resistor and a 2000pF capacitor to ground on the
input will limit the input bandwidth to 1.6MHz. The source
impedance has to be kept low to avoid gain error and
degradation in the AC performance. The capacitor also
acts as a charge reservoir for the input sample-and-hold
and isolates the ADC input from sampling glitch sensitive
circuitry. High quality capacitors and resistors should be
used since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity.Carbonsurfacemountresistorscanalsogenerate
distortion from self heating and from damage that may
occurduringsoldering.Metalfilmsurfacemountresistors
are much less susceptible to both problems.
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental.
Signal-to-Noise Ratio
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency.Figure3ashowsatypicalSINADof81.4dBwith
a 175kHz sampling rate and a 1kHz input. Higher SINAD
can be obtained with a 3V supply. For example, when an
external 3V is applied to REFCOMP (tie V
to GND), a
REF
SINAD of 83.5dB can be achieved as shown in Figure 3b.
DC Performance
0
f
f
= 175ksps
SAMPLE
IN
One way of measuring the transition noise associated
with a high resolution ADC is to use a technique where
a DC signal is applied to the input of the ADC and the
resulting output codes are collected over a large number
of conversions. For example, in Figure 2 the distribution
of output codes is shown for a DC input that had been
digitized 4096 times. The distribution is Gaussian and the
RMS code transition noise is about 1.6LSB.
= 1kHz
–20
–40
SNR = 82.9dB
SINAD = 81.4dB
THD = 86.8dB
–60
–80
–100
–120
–140
1200
V
= 2.7V
DD
1044
895
0
21.875
43.75
65.625
87.5
INTERNAL REF
1000
800
600
400
200
0
FREQUENCY (kHz)
1863L7L G03
830
Figure ±a. 3TC18673 Nonaveraged 4096 Point
FFT Plot with 2.7V Supply
465
0
333
–20
–40
261
170
58
23
9
7
1
–60
–80
20 21
24 25 26 27 28 29 30 31
CODE
22 23
1863L7L G12
Figure 2. 3TC18673 Histogram for 4096 Conversions
–100
–120
–140
Dynamic Performance
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
21.875
43.75
87.5
0
65.625
FREQUENCY (kHz)
1863L7L F03b
Figure ±b. 3TC18673 Nonaveraged 4096 Point
FFT Plot with ±V Supply
1863l7lfd
11
For more information www.linear.com/LTC1863L
LTC1863L/LTC1867L
APPLICATIONS INFORMATION
Total Harmonic Distortion
pin, REFCOMP, must be bypassed with a 10µF ceramic or
tantalum in parallel with a 0.1µF ceramic for best noise
performance.
Total Harmonic Distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
Digital ꢁnterface
The LTC1863L and LTC1867L have a very simple digital
interface that is enabled by the control input, CS/CONV.
A logic rising edge applied to the CS/CONV input will ini-
tiate a conversion. After the conversion, taking CS/CONV
low will enable the serial port and the ADC will present
digital data in two’s complement format in bipolar mode
or straight binary format in unipolar mode, through the
SCK/SDO serial port.
2
2
2
2
V2 +V3 +V4 ...+VN
THD=20log
V
where V is the RMS amplitude of the fundamental fre-
1
quencyandV throughV aretheamplitudesofthesecond
2
N
through Nth harmonics.
ꢁnternal Reference
ꢁnternal Clock
T
he LTC1863L and LTC1867L have an on-chip, tempera-
The internal clock is factory trimmed to achieve a typical
conversion time of 3.2µs and a maximum conversion
time, 3.7µs, over the full operating temperature range.
The typical acquisition time is 1.68µs, and a throughput
sampling rate of 175ksps is tested and guaranteed.
turecompensated,curvaturecorrected,bandgapreference
that is factory trimmed to 1.25V. It is internally connected
to a reference amplifier and is available at VREF (Pin 10).
A 3k resistor is in series with the output so that it can be
easily overdriven by an external reference if better drift
and/or accuracy are required as shown in Figure 4. The
reference amplifier gains the VREF voltage by 2x to 2.5V at
REFCOMP(Pin9).Thisreferenceamplifiercompensation
Automatic Nap Mode
The LTC1863L and LTC1867L go into automatic nap
mode when CS/CONV is held high after the conversion is
complete. With a typical operating current of 750µA and
automatic 170µA nap mode between conversions, the
power dissipation drops with reduced sample rate. The
R1
3k
V
10
2.2µF
9
REF
BANDGAP
REFERENCE
1.25V
REFCOMP
ADC only keeps the V and REFCOMP voltages active
REF
REFERENCE
AMP
2.5V
when the part is in the automatic nap mode. The slower
the sample rate allows the power dissipation to be lower
(see Figure 5).
10µF
15
R2
R3
GND
LTC1863L/LTC1867L
1863L7L F04a
800
V
= 2.7V
DD
700
600
500
400
300
200
100
Figure 4a. 3TC18673 Reference Circuit
3V
V
IN
LT1790A-1.25
10
2.2µF
9
V
OUT
V
REF
LTC1863L/
LTC1867L
REFCOMP
+
10µF
0.1µF
15
1
10
f
100
(ksps)
1000
GND
SAMPLE
1863L7L G09
1863L7L F04b
Figure 5. Supply Current vs fSAMP3E
Figure 4b. Using the 3T1790A-1.25 as an Eꢀternal Reference
1863l7lfd
12
For more information www.linear.com/LTC1863L
LTC1863L/LTC1867L
APPLICATIONS INFORMATION
If the CS/CONV returns low during a bit decision, it can
create a small error. For best performance ensure that the
CS/CONV returns low either within 100ns after the con-
version starts (i.e. before the first bit decision) or after the
conversion ends. If CS/CONV is low when the conversion
ends, the MSB bit will appear on SDO at the end of the
conversion and the ADC will remain powered up.
Timing and Control
Conversion start is controlled by the CS/CONV digital in-
put. The rising edge transition of the CS/CONV will start a
conversion. Once initiated, it cannot be restarted until the
conversion is complete. Figures 6 and 7 show the timing
diagrams for two types of CS/CONV pulses.
Example 1 (Figure 6) shows the LTC1863L/LTC1867L
operating in automatic nap mode with CS/CONV signal
staying HIGH after the conversion. Automatic nap mode
provides power reduction at reduced sample rate.
Sleep Mode
If the SLP = 1 is selected in the input word, the ADC will
enter SLEEP mode and draw only leakage current (pro-
vided that all the digital inputs stay at GND or V ). After
The ADCs can also operate
with the CS/CONV signal
DD
release from the SLEEP mode, the ADC needs 80ms to
returning LOW before the conversion ends. In this mode
(Example 2, Figure 7), the ADCs remain powered up. The
digital output, SDO, will go HIGH immediately after the
conversion is complete if the analog inputs are above
half scale in unipolar mode or below half scale in bipolar
mode. This is a way to measure the conversion time of
the A/D converter.
wake up (charge the 2.2µF/10µF bypass capacitors on
V /REFCOMP pins).
REF
Board 3ayout and Bypassing
To obtain the best performance, a printed circuit board
with a ground plane is required. Layout for the printed
circuit board should ensure digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital signal alongside
an analog signal.
Forbestperformance,itisrecommendedtokeepSCK,SDI,
and SDO at a constant logic high or low during acquisition
andconversion,eventhoughthesesignalsmaybeignored
by the serial interface (DON’T CARE). Communication
with other devices on the bus should not coincide with
All analog inputs should be screened by GND. V , REF-
REF
the conversion period (t
).
CONV
COMP and V should be bypassed to this ground plane
DD
as close to the pin as possible; the low impedance of the
common return for these bypass capacitors is essential
to the low noise operation of the ADC. The width for these
tracks should be as wide as possible.
Figures 8 and 9 are the transfer characteristics for the
bipolar and unipolar mode.
t
ACQ
1/f
SCK
CS/CONV
t
NAP MODE
CONV
NOT NEEDED FOR LTC1863
13 14 15 16
SCK
SDI
1
2
3
4
5
6
7
8
9
10
11
12
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
SD 0S
MSB
S1 S0 COM UNI SLP
Hi-Z
Hi-Z
SDO
(LTC1863)
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO
(LTC1867)
1863L7L F06
Figure 6. Eꢀample 1, CS/CONV Starts a Conversion and Remains HꢁGH Until Neꢀt Data Transfer. With CS/CONV
Remaining HꢁGH After the Conversion, Automatic Nap Modes Provides Power Reduction at Reduced Sample Rate
1863l7lfd
13
For more information www.linear.com/LTC1863L
LTC1863L/LTC1867L
APPLICATIONS INFORMATION
t
CS/CONV
ACQ
NOT NEEDED FOR LTC1863
SCK
DON'T CARE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SDI
SD 0S
S1 S0 COM UNI SLP
DON'T CARE
CONV
DON'T CARE
t
t
SDO
(LTC1863)
MSB = D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
Hi-Z
CONV
SDO
(LTC1867)
MSB = D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1863L7L F07
Figure 7. Eꢀample 2, CS/CONV Starts a Conversion With Short Active HꢁGH Pulse.
With CS/CONV Returning 3OW Before the Conversion, the ADC Remains Powered Up
011...111
011...110
111...111
BIPOLAR
ZERO
111...110
000...001
000...000
111...111
111...110
100...001
100...000
011...111
011...110
UNIPOLAR
ZERO
FS = 2.5V
FS = 2.5V
n
n
100...001
100...000
000...001
000...000
1LSB = FS/2
1LSB = FS/2
1LSB (LTC1863L) = 610µV
1LSB (LTC1867L) = 38.1µV
1LSB (LTC1863L) = 610µV
1LSB (LTC1867L) = 38.1µV
–1 0V
LSB
INPUT VOLTAGE (V)
1
–FS/2
FS/2 – 1LSB
0V
FS – 1LSB
LSB
INPUT VOLTAGE (V)
1863L7L F08
1863L7L F09
Figure 8. 3TC186±3/3TC18673 Bipolar Transfer
Characteristics (Two’s Complement)
Figure 9. 3TC186±3/3TC18673 Unipolar Transfer
Characteristics (Straight Binary)
1863l7lfd
14
For more information www.linear.com/LTC1863L
LTC1863L/LTC1867L
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.189 – .196*
.045 .005
(4.801 – 4.978)
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 .004
(0.38 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 REV B 0212
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
REVISION HISTORY
REV
DATE
6/14
5/15
DESCRꢁPTꢁON
PAGE NUMBER
B
Fixed the Order Information.
2
C
Adjusted Notes 3 and 4 to specify input currents up to 100mA.
4, 5
1863l7lfd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresentation
15
that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC1863L/LTC1867L
RELATED PARTS
PART NUMBER
DESCRꢁPTꢁON
COMMENTS
LTC1417
14-Bit, 400ksps Serial ADC
20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
Low Input Offset: 75µV/125µV
LT1468/LT1469
LTC1609
Single/Dual 90MHz, 22V/µs, 16-Bit Accurate Op Amps
16-Bit, 200ksps Serial ADC
65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply
Bandgap, 60µA Max Supply Current, 10ppm/°C, SOT-23 Package
Parallel Output, Programmable MUX and Sequencer, 5V Supply
Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply
850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages
450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages
5V Supply, Pin Compatible with LTC1863L/LTC1867L
850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages
450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages
LT1790A
Micropower Precision Series Reference
10-Bit/12-Bit, 8-Channel, 1.25Msps ADC
10-Bit/12-Bit, 8-Channel, 400ksps ADC
12-Bit, 1-/2-Channel 250ksps ADC in MSOP
LTC1850/LTC1851
LTC1852/LTC1853
LTC1860/LTC1861
LTC1860L/LTC1861L 3V, 12-Bit, 1-/2-Channel 150ksps ADC
LTC1863/LTC1867
LTC1864/LTC1865
12-/16-Bit, 8-Channel 200ksps ADC
16-Bit, 1-/2-Channel 250ksps ADC in MSOP
LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel 150ksps ADC in MSOP
1863l7lfd
LT 0515 REV D • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
LINEAR TECHNOLOGY CORPORATION 2005
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC1863L
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