LTC1864ACS8 [Linear]
レPower, 16-Bit, 250ksps 1- and 2-Channel ADCs in MSOP; レ功耗，16位， 250ksps的1和2通道ADC ，采用MSOP
| 型号： | LTC1864ACS8 |
| 厂家： | 
Linear |
| 描述： | レPower, 16-Bit, 250ksps 1- and 2-Channel ADCs in MSOP |
| 文件： | 总20页 (文件大小：372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1864/LTC1865
µPower, 16-Bit, 250ksps
1- and 2-Channel ADCs in MSOP
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FEATURES
DESCRIPTIO
TheLTC®1864/LTC1865are16-bitA/Dconvertersthatare
offered in MSOP and SO-8 packages and operate on a
single 5V supply. At 250ksps, the supply current is only
850µA. The supply current drops at lower speeds because
the LTC1864/LTC1865 automatically power down
between conversions. These 16-bit switched capacitor
successiveapproximationADCsincludesample-and-holds.
The LTC1864 has a differential analog input with an
adjustable reference pin. The LTC1865 offers a software-
selectable 2-channel MUX and an adjustable reference pin
on the MSOP version.
■
16-Bit 250ksps ADCs in MSOP Package
■
Single 5V Supply
■
Low Supply Current: 850µA (Typ)
Auto Shutdown Reduces Supply Current
to 2µA at 1ksps
True Differential Inputs
■
■
■
1-Channel (LTC1864) or 2-Channel (LTC1865)
Versions
SPI/MICROWIRETM Compatible Serial I/O
■
■
16-Bit Upgrade to 12-Bit LTC1286/LTC1298
■
Pin Compatible with 12-Bit LTC1860/LTC1861
The 3-wire, serial I/O, small MSOP or SO-8 package and
extremely high sample rate-to-power ratio make these
ADCs ideal choices for compact, low power, high speed
systems.
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APPLICATIO S
■
High Speed Data Acquisition
■
Portable or Compact Instrumentation
These ADCs can be used in ratiometric applications or
with external references. The high impedance analog
inputs and the ability to operate with reduced spans down
to 1V full scale, allow direct connection to signal sources
in many applications, eliminating the need for external
gain stages.
■
Low Power Battery-Operated Instrumentation
■
Isolated and/or Remote Data Acquisition
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
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TYPICAL APPLICATIO
Supply Current vs Sampling Frequency
1000
Single 5V Supply, 250ksps, 16-Bit Sampling ADC
100
10
1µF
5V
LTC1864
1
1
2
3
4
8
7
6
V
V
CC
REF
+
IN
IN
SCK
SDO
ANALOG INPUT
0V TO 5V
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
0.1
–
5
GND
CONV
0.01
1864 TA01
0.01
0.1
1
10
100
1000
SAMPLING FREQUENCY (kHz)
1864 TA02
sn18645 18645fs
1
LTC1864/LTC1865
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ABSOLUTE AXI U RATI GS
(Notes 1, 2)
Operating Temperature Range
Supply Voltage (VCC) ................................................. 7V
Ground Voltage Difference
LTC1864C/LTC1865C/
LTC1864AC/LTC1865AC ........................ 0°C to 70°C
LTC1864I/LTC1865I/
LTC1864AI/LTC1865AI ..................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
AGND, DGND LTC1865 MSOP Package ........... ±0.3V
Analog Input ............... (GND – 0.3V) to (VCC + 0.3V)
Digital Input ................................(GND – 0.3V) to 7V
Digital Output .............. (GND – 0.3V) to (VCC + 0.3V)
Power Dissipation.............................................. 400mW
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
LTC1865CMS
LTC1864CMS8
LTC1864IMS8
LTC1864ACMS8
LTC1864AIMS8
CONV
CH0
1
2
3
4
5
10
9
V
V
SCK
SDO
SDI
V
IN
1
2
3
4
8 V
CC
REF
CC
REF
+
7 SCK
LTC1865IMS
LTC1865ACMS
LTC1865AIMS
CH1
8
6 SDO
5 CONV
IN¯
AGND
DGND
7
6
GND
MS8 PACKAGE
MS PACKAGE
10-LEAD PLASTIC MSOP
8-LEAD PLASTIC MSOP
MS8 PART MARKING
LTHQ
MS PART MARKING
LTHS
TJMAX = 150°C, θJA = 210°C/W
TJMAX = 150°C, θJA = 210°C/W
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CONV
CH0
V
CC
V
V
CC
REF
+
LTC1864CS8
LTC1864IS8
LTC1864ACS8
LTC1864AIS8
LTC1865CS8
LTC1865IS8
LTC1865ACS8
LTC1865AIS8
SCK
SDO
SDI
IN
IN
SCK
–
CH1
SDO
CONV
GND
GND
S8 PACKAGE
8-LEAD PLASTIC SO
S8 PACKAGE
8-LEAD PLASTIC SO
S8 PART MARKING
S8 PART MARKING
TJMAX = 150°C, θJA = 175°C/W
TJMAX = 150°C, θJA = 175°C/W
1864
1864I
1864A
1864AI
1865
1865I
1865A
1865AI
Consult LTC Marketing for parts specified with wider operating temperature ranges.
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CO VERTER A D ULTIPLEXER CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.
VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
A
LTC1864/LTC1865
LTC1864A/LTC1865A
PARAMETER
Resolution
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Bits
●
●
●
16
14
16
No Missing Codes Resolution
INL
15
Bits
(Note 3)
±8
±6
LSB
Transition Noise
Gain Error
1.1
1.1
LSB
RMS
●
±20
±20
mV
sn18645 18645fs
2
LTC1864/LTC1865
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CO VERTER A D ULTIPLEXER CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.
A
VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1864/LTC1865
LTC1864A/LTC1865A
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Offset Error
LTC1864 SO-8 and MSOP, LTC1865 MSOP
LTC1865 SO-8
●
●
±2
±3
±5
±7
±2
±3
±5
±7
mV
mV
+
–
Input Differential Voltage Range
Absolute Input Range
V
= IN – IN
●
●
0
V
0
V
REF
V
IN
+
REF
IN Input
IN Input
–0.05
–0.05
V
+ 0.05
CC
–0.05
–0.05
V
+ 0.05
V
V
CC
V
CC
V
–
/2
/2
CC
V
REF
Input Range
LTC1864 SO-8 and MSOP,
LTC1865 MSOP
1
V
1
V
CC
V
CC
Analog Input Leakage Current
(Note 4)
±1
±1
µA
C
IN
Input Capacitance
In Sample Mode
During Conversion
12
5
12
5
pF
pF
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DY A IC ACCURACY
TA = 25°C. VCC = 5V, VREF = 5V, fSAMPLE = 250kHz, unless otherwise noted.
LTC1864/LTC1865
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SNR
Signal-to-Noise Ratio
87
dB
S/(N + D) Signal-to-Noise Plus Distortion Ratio
10kHz Input Signal
100kHz Input Signal
83
76
dB
dB
THD
Total Hamonic Distortion Up to 5th Harmonic 10kHz Input Signal
100kHz Input Signal
88
77
dB
dB
Full Power Bandwidth
20
MHz
kHz
Full Linear Bandwidth
S/(N + D) ≥ 75dB
125
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DIGITAL A DDCELECTRICALCHARACTERISTICS
The ● denotes specifications which apply
over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted.
LTC1864/LTC1865
SYMBOL PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
V
V
IH
V
IL
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 5.25V
= 4.75V
●
●
●
●
2.4
CC
CC
IN
0.8
2.5
V
I
I
= V
µA
µA
IH
IL
CC
= 0V
–2.5
IN
V
OH
V
CC
V
CC
= 4.75V, I = 10µA
= 4.75V, I = 360µA
●
●
4.5
2.4
4.74
4.72
V
V
O
O
V
Low Level Output Voltage
Hi-Z Output Leakage
Output Source Current
Output Sink Current
V
= 4.75V, I = 1.6mA
●
●
0.4
V
µA
OL
CC
O
I
I
I
I
CONV = V
±3
OZ
CC
V
OUT
V
OUT
= 0V
–25
20
mA
mA
SOURCE
SINK
= V
CC
Reference Current (LTC1864 SO-8 and
MSOP, LTC1865 MSOP)
CONV = V
●
●
0.001
0.05
3
0.1
µA
mA
REF
CC
f
= f
SMPL
SMPL(MAX)
I
Supply Current
CONV = V After Conversion
●
●
0.001
0.85
3
1.3
µA
mA
CC
CC
f
= f
SMPL
SMPL(MAX)
P
D
Power Dissipation
f
= f
SMPL(MAX)
4.25
mW
SMPL
sn18645 18645fs
3
LTC1864/LTC1865
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U
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W
The ● denotes specifications which apply over the
RECO E DED OPERATI G CO DITIO S
full operating temperature range, otherwise specifications are TA = 25°C.
LTC1864/LTC1865
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
5.25
20
UNITS
V
V
Supply Voltage
4.75
CC
f
t
t
Clock Frequency
●
DC
MHz
µs
SCK
CYC
SMPL
Total Cycle Time
16 • SCK + t
CONV
Analog Input Sampling Time
LTC1864
LTC1865
16
14
SCK
SCK
t
Setup Time CONV↓ Before First SCK↑
(See Figure 1)
30
ns
suCONV
t
t
t
t
t
Hold Time SDI After SCK↑
Setup Time SDI Stable Before SCK↑
SCK High Time
LTC1865
LTC1865
15
15
ns
ns
hDI
suDI
f
f
= f
SCK(MAX)
= f
SCK(MAX)
40%
40%
1/f
1/f
WHCLK
WLCLK
WHCONV
SCK
SCK
SCK
SCK Low Time
SCK
CONV High Time Between Data
Transfer Cycles
t
µs
CONV
t
t
CONV Low Time During Data Transfer
16
13
SCK
ns
WLCONV
hCONV
Hold Time CONV Low After Last SCK↑
W U
The ● denotes specifications which apply over the full operating temperature
TI I G CHARACTERISTICS
range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating
Conditions, unless otherwise noted.
LTC1864/LTC1865
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
µs
t
f
t
Conversion Time (See Figure 1)
Maximum Sampling Frequency
Delay Time, SCK↓ to SDO Data Valid
●
●
2.75
3.2
CONV
250
kHz
SMPL(MAX)
dDO
C
= 20pF
15
20
25
ns
ns
LOAD
●
●
●
●
t
t
t
Delay Time, CONV↑ to SDO Hi-Z
30
30
10
60
60
ns
ns
ns
dis
en
Delay Time, CONV↓to SDO Enabled
C
C
= 20pF
= 20pF
LOAD
LOAD
Time Output Data Remains
Valid After SCK↓
5
hDO
t
t
SDO Rise Time
SDO Fall Time
C
C
= 20pF
= 20pF
8
4
ns
ns
r
f
LOAD
LOAD
Note 1: Absolute Maximum Ratings are those values beyond which the life
Note 3: Integral nonlinearity is defined as deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 4: Channel leakage current is measured while the part is in sample
mode.
sn18645 18645fs
4
LTC1864/LTC1865
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TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Sampling
Sleep Current vs Temperature
Frequency
Supply Current vs Temperature
1000
800
600
400
200
0
1000
1000
100
10
V
A
= 5V
CONV = V = 5V
CC
CC
900
800
700
600
500
400
300
200
100
0
T
= 25°C
CONV LOW = 800ns
1
V
V
f
= 5V
CC
0.1
= 5V
REF
= 250kHz
SAMPLE
CONV HIGH = 3.2µS
50
75 100 125
TEMPERATURE (°C)
0.01
0.1
SAMPLING FREQUENCY (kHz)
1.0
10
100
1000
–50
0
25
–50
0
25
50
75 100 125
0.01
–25
–25
TEMPERATURE (°C)
1864/65 G01
1864/65 G02
1864/65 G03
Reference Current vs
Sampling Rate
Reference Current vs
Temperature
Reference Current vs
Reference Voltage
60
50
40
30
20
10
0
55
54
53
52
51
50
49
48
47
46
45
60
50
40
30
20
10
0
V
V
f
= 5V
= 5V
V
T
= 5V
= 25°C
= 5V
V
T
S
= 5V
CC
REF
CC
CC
A
= 25°C
A
= 250kHz
V
REF
f
= 250kHz
S
CONV LOW = 800ns
0
50
100
150
200
250
0
1
2
3
4
5
–50
0
25
50
75 100 125
–25
SAMPLE RATE (kHz)
V
(V)
TEMPERATURE (°C)
REF
1864/65 G04
1864/65 G06
1864/65 G05
Analog Input Leakage Current vs
Temperature
Typical INL Curve
Typical DNL Curve
100
75
50
25
0
4
2
2
1
V
V
= 5V
REF
CONV = 0V
V
T
= 5V
CC
V
T
= 5V
CC
A
CC
A
= 5V
= 25°C
= 25°C
V
= 5V
V
= 5V
REF
REF
0
0
–2
–4
–1
–2
–25
0
25
50
75
125
–50
100
0
16384
32768
CODE
65536
49152
0
16384
32768
CODE
65536
49152
TEMPERATURE (°C)
1864/65 G09
1864/65 G07
1864/65 G08
sn18645 18645fs
5
LTC1864/LTC1865
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Change in Gain Error vs
Reference Voltage
Change in Offset Error vs
Reference Voltage
Change in Offset vs Temperature
5
4
75
50
20
15
V
V
= 5V
= 5V
V
T
= 5V
CC
REF
V
T
= 5V
CC
A
CC
= 25°C
= 25°C
A
3
10
2
5
1
0
25
0
–1
–2
–3
–4
–5
–5
0
–10
–15
–20
–25
–50
0
25
50
75 100 125
–25
0
1
2
3
4
5
0
2
3
4
5
1
TEMPERATURE (°C)
REFERENCE VOLTAGE(V)
REFERENCE VOLTAGE (V)
1864/65 G11
1864/65 G10
1864/65 G12
Histogram of 4096 Conversions
of a DC Input Voltage
Change in Gain Error vs
Temperature
4096 Point FFT Nonaveraged
5
4
0
–20
1800
1600
1400
1200
1000
800
600
400
200
0
V
T
REF
= 5V
V
V
= 5V
= 5V
f
f
V
V
T
= 203.125kHz
= 99.72763kHz
= 5V
REF
= 25°C
CC
A
V
CC
REF
S
IN
CC
= 25°C
1534
= 5V
3
= 5V
–40
2
A
1178
1
–60
0
729
–80
–1
–2
–3
–4
–5
516
2
–100
–120
–140
127
0
0
12
3
0
0
5
–50
0
25
50
75 100 125
0
CODE
–25
–4 –3 –2 –1
1
4
0
40
60
80
100
120
20
FREQUENCY (kHz)
TEMPERATURE (°C)
1864/65 G13
1864/65 G14
1864/65 G15
SFDR vs Frequency
SINAD vs Frequency
THD vs Frequency
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
SNR
SINAD
V
= 5V
= 5V
V
V
T
= 5V
= 5V
V
= 5V
CC
REF
= 25°C
CC
REF
CC
V
T
V
T
= 5V
REF
= 25°C
= 25°C
A
A
A
V
= 0dB
V
= 0dB
V
= 0dB
IN
IN
IN
1
10
100
1000
1
10
100
1000
1
10
100
1000
F
(kHz)
F
(kHz)
F
(kHz)
IN
IN
IN
1864/5 G18
1864/5 G16
1864/5 G17
sn18645 18645fs
6
LTC1864/LTC1865
U
U
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PI FU CTIO S
LTC1864
VREF (Pin 1): Reference Input. The reference input defines
the span of the A/D converter and must be kept free of
noise with respect to GND.
IN+, IN– (Pins 2, 3): Analog Inputs. These inputs must be
free of noise with respect to GND.
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this pin.
SCK(Pin7):ShiftClockInput. Thisclocksynchronizesthe
serial data transfer.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
V
CC (Pin 8): Positive Supply. This supply must be kept
CONV (Pin 5): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
high after the A/D conversion is finished, the part powers
free of noise and ripple by bypassing directly to the
analog ground plane.
LTC1865 (MSOP Package)
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
high after the A/D conversion is finished, the part powers
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
SDO (Pin 7): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK(Pin8):ShiftClockInput. Thisclocksynchronizesthe
serial data transfer.
VCC (Pin 9): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to AGND.
AGND (Pin 4): Analog Ground. AGND should be tied
directly to an analog ground plane.
VREF (Pin 10): Reference Input. The reference input de-
fines the span of the A/D converter and must be kept free
of noise with respect to AGND.
DGND (Pin 5): Digital Ground. DGND should be tied
directly to an analog ground plane.
SDI (Pin 6): Digital Data Input. The A/D configuration
word is shifted into this input.
LTC1865 (SO-8 Package)
SDI (Pin 5): Digital Data Input. The A/D configuration
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
high after the A/D conversion is finished, the part powers
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
word is shifted into this input.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK(Pin7):ShiftClockInput. Thisclocksynchronizesthe
serial data transfer.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
VCC (Pin 8): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane. VREF is tied internally to this pin.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
sn18645 18645fs
7
LTC1864/LTC1865
U
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FUNCTIONAL BLOCK DIAGRA
V
CC
(SDI) SCK
CONV
PIN NAMES IN
PARENTHESES
REFER TO LTC1865
SDO
SERIAL
PORT
CONVERT
CLK
BIAS AND
SHUTDOWN
DATA IN
16 BITS
+
IN
+
–
(CH0)
16-BIT
SAMPLING
ADC
DATA OUT
–
IN
(CH1)
1864/65 BD
GND
V
REF
TEST CIRCUITS
Load Circuit for tdDO, tr, tf, tdis and ten
Voltage Waveforms for SDO Rise and Fall Times, tr, tf
TEST POINT
V
OH
SDO
V
OL
V
t
WAVEFORM 2, t
en
3k
CC dis
SDO
t
dis
WAVEFORM 1
t
r
t
f
1864 TC04
20pF
1864 TC01
Voltage Waveforms for ten
Voltage Waveforms for tdis
CONV
V
CONV
IH
SDO
1864 TC03
SDO
WAVEFORM 1
(SEE NOTE 1)
90%
10%
t
en
t
dis
SDO
WAVEFORM 2
(SEE NOTE 2)
Voltage Waveforms for SDO Delay Times, tdDO and thDO
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
SCK
V
IL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
t
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
dDO
1864 TC05
t
hDO
V
V
OH
OL
SDO
1864 TC02
sn18645 18645fs
8
LTC1864/LTC1865
W U U
APPLICATIO S I FOR ATIO
LTC1864 OPERATION
U
Analog Inputs
The LTC1864 has a unipolar differential analog input. The
converter will measure the voltage between the “IN+” and
“IN–” inputs. A zero code will occur when IN+ minus IN–
equals zero. Full scale occurs when IN+ minus IN– equals
VREF minus 1LSB. See Figure 2. Both the “IN+” and
“IN–” inputs are sampled at the same time, so common
mode noise on the inputs is rejected by the ADC. If “IN–”
isgroundedandVREF istiedtoVCC, arail-to-railinputspan
will result on “IN+” as shown in Figure 3.
Operating Sequence
The LTC1864 conversion cycle begins with the rising edge
of CONV. After a period equal to tCONV, the conversion is
finished. If CONV is left high after this time, the LTC1864
goesintosleepmodedrawingonlyleakagecurrent. Onthe
fallingedgeofCONV, theLTC1864goesintosamplemode
and SDO is enabled. SCK synchronizes the data transfer
with each bit being transmitted from SDO on the falling
SCK edge. The receiving system should capture the data
from SDO on the rising edge of SCK. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefinitely. See Figure 1.
Reference Input
The voltage on the reference input of the LTC1864 defines
thefull-scalerangeoftheA/Dconverter. TheLTC1864can
operate with reference voltages from VCC to 1V.
CONV
t
SMPL
8
SLEEP MODE
t
CONV
1
2
3
4
5
6
7
9 10 11 12 13 14 15 16
SCK
SDO
B14
B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
B15
B13
Hi-Z
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
1854 F01
Figure 1. LTC1864 Operating Sequence
1µF
V
CC
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
LTC1864
V
•
•
•
1
2
3
4
8
7
6
V
REF
CC
+
V
= 0V TO V
CC
IN
IN
SCK
IN
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
–
V *
IN
SDO
5
GND
CONV
1864 F03
+
–
*V = IN – IN
IN
1864 F02
Figure 2. LTC1864 Transfer Curve
Figure 3. LTC1864 with Rail-to-Rail Input Span
sn18645 18645fs
9
LTC1864/LTC1865
W U U
U
APPLICATIO S I FOR ATIO
LTC1865 OPERATION
single-ended mode, all input channels are measured with
respect to GND. A zero code will occur when the “+” input
minus the “–” input equals zero. Full scale occurs when
the “+” input minus the “–” input equals VREF minus
1LSB. See Figure 5. Both the “+” and “–” inputs are
sampled at the same time so common mode noise is
rejected. The input span in the SO-8 package is fixed at
VREF = VCC. If the “–” input in differential mode is
grounded, a rail-to-rail input span will result on the “+”
input.
Operating Sequence
TheLTC1865conversioncyclebeginswiththerisingedge
of CONV. After a period equal to tCONV, the conversion is
finished. If CONV is left high after this time, the LTC1865
goes into sleep mode drawing only leakage current. The
LTC1865’s 2-bit data word is clocked into the SDI input on
the rising edge of SCK after CONV goes low. Additional
inputs on the SDI pin are then ignored until the next CONV
cycle. Theshiftclock(SCK)synchronizesthedatatransfer
witheachbitbeingtransmittedonthefallingSCKedgeand
captured on the rising SCK edge in both transmitting and
receiving systems. The data is transmitted and received
simultaneously (full duplex). After completing the data
transfer, if further SCK clocks are applied with CONV low,
SDO will output zeros indefinitely. See Figure 4.
Reference Input
The reference input of the LTC1865 SO-8 package is
internally tied to VCC. The span of the A/D converter is
therefore equal to VCC. The voltage on the reference input
of the LTC1865 MSOP package defines the span of the
A/D converter. The LTC1865 MSOP package can operate
with reference voltages from 1V to VCC.
Analog Inputs
Table 1. Multiplexer Channel Selection
The two bits of the input word (SDI) assign the MUX
configuration for the next requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following table. In
MUX ADDRESS
CHANNEL #
SGL/DIFF ODD/SIGN
0
1
GND
1
1
0
0
0
1
0
1
+
–
–
SINGLE-ENDED
MUX MODE
DIFFERENTIAL
MUX MODE
+
–
+
+
–
1864 TBL1
CONV
t
SMPL
SLEEP MODE
t
CONV
SDI
S/D O/S
DON’T CARE
DON’T CARE
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
SCK
SDO
B0*
B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
B14
B15
B13
Hi-Z
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
1864 F04
Figure 4. LTC1865 Operating Sequence
sn18645 18645fs
10
LTC1864/LTC1865
W U U
APPLICATIO S I FOR ATIO
U
induce errors or noise in the output code. Bypass the VCC
and VREF pins directly to the analog ground plane with a
minimum of 1µF tantalum. Keep the bypass capacitor
leads as short as possible.
GENERAL ANALOG CONSIDERATIONS
Grounding
The LTC1864/LTC1865 should be used with an analog
ground plane and single point grounding techniques. Do
not use wire wrapping techniques to breadboard and
evaluatethedevice.Toachievetheoptimumperformance,
use a printed circuit board. The ground pins (AGND and
DGND for the LTC1865 MSOP package and GND for the
LTC1864 and LTC1865 SO-8 package) should be tied
directly to the analog ground plane with minimum lead
length.
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1864/
LTC1865 have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem if source resistances are less than 200Ω or high
speed op amps are used (e.g., the LT®1211, LT1469,
LT1807, LT1810, LT1630, LT1226orLT1215). Butiflarge
source resistances are used, or if slow settling op amps
drive the inputs, take care to ensure the transients caused
by the current spikes settle completely before the conver-
sion begins.
Bypassing
For good performance, the VCC and VREF pins must be free
of noise and ripple. Any changes in the VCC/VREF voltage
with respect to ground during the conversion cycle can
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
*
V
IN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
*V = (SELECTED “+” CHANNEL) –
IN
1864 F05
(SELECTED “–” CHANNEL)
REFER TO TABLE 1
Figure 5. LTC1865 Transfer Curve
sn18645 18645fs
11
LTC1864/LTC1865
W U U
U
APPLICATIO S I FOR ATIO
sn18645 18645fs
12
LTC1864/LTC1865
W U U
APPLICATIO S I FOR ATIO
U
Component Side Silk Screen for LTC1864 Evaluation Circuit
Component Side Showing Traces
(Note Wider Traces on Analog Side)
Bottom Side Showing Traces
(Note Almost No Analog Traces on Board Bottom)
Ground Layer with Separate Analog and Digital Grounds
Supply Layer with 5V Digital Supply and Analog Ground Repeated
sn18645 18645fs
13
LTC1864/LTC1865
APPLICATIO S I FOR ATIO
W U U
U
U11
5V
AN
5V
DIG
15V
LT1121CST-5
R4
2Ω
1
3
V
V
OUT
IN
C26
GND
2
10µF
6.3V
1206
5V
AN
C3
10µF
6.3V
1206
C4
0.1µF
5V
5V
DIG
15V
DIG
LTC1485
RO V
RN1
330
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1V to 5V REFERENCE
0V to V INPUT
V
IN
IN
V
CC
SCK
SDO
REF
CC
B
A
1
2
3
4
8
7
6
5
+
–
REF
RE
DE
DI
GND
CONV
GND
120Ω
U3
LTC1864CMS8
ANALOG GROUND PLANE
4 CONDUCTOR
TELEPHONE WIRES
TO RECEIVER
C23
0.1µF
C24
0.1µF
5V
5V
DIG
DIG
4
2
1
5
500Ω
5V
U12A
U12B
16
16
74AC109
2
74AC109
U9B
74AC00
3
6
7
14
10
9
V
V
CC
CC
J
K
Q
Q
J
K
Q
Q
3
4
1
5
13
12
15
11
MC74VHC1G66
CLK
CLK
CLR
PRE
CLR
PRE
8
8
GND
5V
GND
5V
DIG
DIG
U9A
74AC00
C16
0.1µF
C17
0.1µF
5V
5V
DIG
DIG
5V
DIG
74AC74
Q
74AC86
U6
U7
C18
PRE
D
CLK
CLR
5V
74HC163AD
74HC163AD
0.1µF
DIG
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
RESET
CLK
P0
P1
P2
P3
ENP
GND
RESET
CLK
P0
P1
P2
P3
ENP
GND
V
RCO
V
CC
RCO
CC
15
14
13
12
11
10
9
U10
Q
LTC1799
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
100k
5
4
1
2
3
+
V
5V
DIG
OUT
DIV
GND
SET
74AC74
Q
ENT
LO
ENT
LO
PRE
D
CLK
CLR
U13C
74AC32
Q
CLK
1864/65 AI2
U13B
74AC32
Figure 6. LTC1864 Manchester Transmitter
sn18645 18645fs
14
LTC1864/LTC1865
W U U
APPLICATIO S I FOR ATIO
U
V
V
V
CC
CC
CC
IC3A
IC2B
IC4B
74AC08
74AC74
74AC74
IC2A
5
6
IC6D
74AC32
4
IC5C
IC4A
74AC08
9
8
10
12
11
13
PRE
D
CLK
CLR
Q
Q
74AC74
V
V
CC
CC IC1A
74AC74
PRE
D
CLK
CLR
Q
Q
2
3
1
74AC86
5
6
4
PRE
D
CLK
CLR
Q
Q
CLK
CLK
2
3
1
5
6
4
2
3
1
PRE
D
CLK
CLR
Q
Q
CLK
DATA IN
CLK
9
8
10
PRE
D
CLK
Q
Q
12
11
13
CLK
IC6C
74LS32D
CLR
DATA
DATA
IC1B
74AC74
V
IC3B
CC
IC4D
74AC08
74AC74
IC4C
74AC08
10
12
11
13
9
8
PRE
D
CLK
CLR
Q
Q
STROBE
CLK
IC8
74AC595
RECEIVE CLOCK AT
8 X TRANSMIT
CLOCK FREQUENCY
14
15
1
2
3
4
5
6
7
9
SER
SCK
SCL
RCK
8
QA
QB
QC
QD
QE
QF
QG
QH
QHIN
D15
D14
D13
D12
D11
D10
D9
11
10
12
13
U1
LTC1485
V
CC
V
CC
1
2
3
4
8
7
6
5
RO
RE
DE
DI
V
CC
B
A
D8
GND
OPTIONAL SERIAL TO
PARALLEL CONVERTER
V
CC
IC9
15V SUPPLY TO
TRANSMITTER
74AC595
14
11
10
12
13
15
1
2
3
4
5
6
7
9
SER
SCK
SCL
RCK
8
QA
QB
QC
QD
QE
QF
QG
QH
QHIN
D7
D6
D5
D4
D3
D2
D1
D0
STROBE
IC7B
74AC109
4 CONDUCTOR
TELEPHONE WIRES
TO TRANSMITTER
R1
120Ω
11
14
12
13
10
Q
PRE
J
CLK
K
DATA
15
9
CLR
Q
1864/65 AI3
Figure 7. LTC1864 Manchester Receiver
sn18645 18645fs
15
LTC1864/LTC1865
W U U
U
APPLICATIO S I FOR ATIO
Transmit LTC1864 Data Over Modular Telephone Wire
Using Simple Transmitter/Receiver
zeros, a start bit, followed by the 16 data bits (one sample
every 48 clock cycles) at a clock frequency of 1MHz set by
the LTC1799 oscillator. Sending at least 18 zeros before
each start bit ensures that if synchronization is lost, the
receiver can resynchronize to a start bit under all condi-
tions. The serial to parallel converter shown in Figure 7
requires 18 zeros to avoid triggering on data bits.
Figure 6 shows a simple Manchester encoder and differ-
ential transmitter suitable for use with the LTC1864. This
circuit allows transmission of data over inexpensive tele-
phone wire. This is useful for measuring a remote sensor,
particularly when the cost of preserving the analog signal
over a long distance is high.
The Manchester receiver shown in Figure 7 was adopted
from Xilinx application note 17-30 and would typically be
implemented in an FPGA. The decoder clock frequency is
nominally 8 times the transmit clock frequency and is very
tolerant of frequency errors. The outputs of the decoder
aredataandastrobethatindicatesavaliddatabit.Thedata
can be deserialized using shift registers as shown. The
startbitresetstheJ-K/flip-floponitswayintothefirstshift
register. When it appears at the QHIN output of the second
shiftregister, itsetstheflip-flopthatloadstheparalleldata
into the output register.
Manchester encoding is a clock signal that is modulated
by exclusive ORing with the data signal. The resulting
signalcontainsbothclockanddatainformationandhasan
average duty cycle of 50%, that also allows transformer
coupling. In practice, generating a Manchester encoded
signal with an XOR gate will often produce glitches due to
the skew between data and clock transitions. The D flip-
flops in this encoder retime the clock and data such that
the respective edges are closely aligned, effectively sup-
pressing glitches. The retimed data and clock are then
XORed to produce the Manchester encoded data, which is
interfaced to telephone wire with an LTC1485 RS485
transceiver.
With AC family CMOS logic at 5V the receiver clock
frequency is limited to 20MHz; the corresponding trans-
mitter clock frequency is 2.5MHz. If the receiver is imple-
mented in an FPGA that can be clocked at 160MHz, the
LTC1864 can be clocked at its rated clock frequency of
20MHz.
In order to synchronize to incoming data, the receiver
needs a sequence to indicate the start of a data word. The
transmitter schematic shows logic that will produce 31
sn18645 18645fs
16
LTC1864/LTC1865
U
PACKAGE DESCRIPTIO
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
0.52
(.206)
REF
8
7 6 5
5.23
3.2 – 3.45
(.206)
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.88 ± 0.1
(.192 ± .004)
(.126 – .136)
MIN
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
0.65
(.0256)
BSC
0.42 ± 0.04
(.0165 ± .0015)
TYP
1
2
3
4
0.53 ± 0.015
(.021 ± .006)
1.10
(.043)
MAX
0.86
(.034)
REF
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.18
(.077)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
0.13 ± 0.05
(.005 ± .002)
0.65
(.0256)
BCS
MSOP (MS8) 1001
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
sn18645 18645fs
17
LTC1864/LTC1865
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
0.497 ± 0.076
(.0196 ± .003)
REF
10 9
8
7 6
5.23
3.00 ± 0.102
(.118 ± .004)
NOTE 4
3.2 – 3.45
(.206)
4.88 ± 0.10
(.192 ± .004)
(.126 – .136)
MIN
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
1
2
3
4 5
0.53 ± 0.01
(.021 ± .006)
RECOMMENDED SOLDER PAD LAYOUT
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
0.13 ± 0.05
(.005 ± .002)
MSOP (MS) 1001
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
0.50
(.0197)
TYP
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
sn18645 18645fs
18
LTC1864/LTC1865
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
SO8 1298
1
3
4
2
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
sn18645 18645fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.
19
LTC1864/LTC1865
U
TYPICAL APPLICATIO
Sample Two Channels Simultaneously with a Single Input ADC
4096 Point FFT of Output
5V
0.1µF
f
1
0
10
20
30
40
+
(0V TO 0.66V)
0.1µF
0.1µF
1µF
1µF
4.096V
f
1
f
2
f
S
= 7.507324kHz AT 530mV
P-P
100Ω
1/2
REF
= 45.007324kHz AT 1.7V
= 100kHz
P-P
LT1492
–
4.096V
REF
100pF
5k
20k
8
1
28.7k
50
V
REF
SCK
7
6
5
5pF
60
70
80
90
100
110
120
130
CC
10k
2
3
+
IN
10k
1µF
LTC1864
SDO
–
IN
5V
5k
CONV
GND
4
0.1µF
0.1µF
f
2
8
+
(0V TO 2V)
100Ω
1/2
LT1492
0
5
10 15 20 25 30 35 40 45 50
FREQUENCY (kHz)
–
100pF
4
1864/65 TA03b
1860 TA03
RELATED PARTS
PART NUMBER
14-Bit Serial I/O ADCs
LTC1417
SAMPLE RATE
POWER DISSIPATION
DESCRIPTION
400ksps
200ksps
20mW
15mW
16-Pin SSOP, Unipolar or Bipolar, Reference, 5V or ±5V
Serial/Parallel I/O, Internal Reference, 5V or ±5V
LTC1418
16-Bit Serial I/O ADCs
LTC1609
200ksps
65mW
Configurable Bipolar or Unipolar Input Ranges, 5V
References
LT1460
Micropower Precision Series Reference
Micropower Low Dropout Reference
Bandgap, 130µA Supply Current, 10ppm/°C, Available in SOT-23
60µA Supply Current, 10ppm/°C, SOT-23
LT1790
Op Amps
LT1468/LT1469
LT1806/LT1807
LT1809/LT1810
Single/Dual 90MHz, 16-Bit Accurate Op Amps
Single/Dual 325MHz Low Noise Op Amps
Single/Dual 180MHz Low Distortion Op Amps
22V/µs Slew Rate, 75µV/125µV Offset
140V/µs Slew Rate, 3.5nV/√Hz Noise, –80dBc Distortion
350V/µs Slew Rate, –90dBc Distortion at 5MHz
sn18645 18645fs
LT/TP 0502 2K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
©LINEAR TECHNOLOGY CORPORATION 2001
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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