LTC1871IMS#TR-1_技术文档

LTC1871-1

TM

SENSE

Wide Input Range, No R

Current Mode Boost,

Flyback and SEPIC Controller

U

FEATURES

DESCRIPTIO

The LTC^®1871-1 is a wide input range, current mode,

boost, flyback or SEPIC controller that drives an N-

channel power MOSFET and requires very few external

components. It eliminates the need for a current sense

resistor by utilizing the power MOSFET’s on-resistance,

thereby maximizing efficiency. Higher output voltage

applicationsarepossiblewiththeLTC1871-1byconnect-

ing the SENSE pin to a resistor in the source of the power

MOSFET.

■

High Efficiency (No Sense Resistor Required)

■

Wide Input Voltage Range: 2.5V to 36V

■

Current Mode Control Provides Excellent

Transient Response

■

High Maximum Duty Cycle (92% Typ)

■

±2% RUN Pin Threshold with 100mV Hysteresis

■

±1% Internal Voltage Reference

■

Ultra Low Pulse Skip Threshold for Wide Input

Range Applications

■

Micropower Shutdown: I_Q= 10μA

The IC’s operating frequency can be set with an external

resistorovera50kHzto1MHzrange, andcanbesynchro-

nized to an external clock using the MODE/SYNC pin.

■

Programmable Operating Frequency

(50kHz to 1MHz) with One External Resistor

■

Synchronizable to an External Clock Up to 1.3 × f_OSC

User-Controlled Pulse Skip or Burst Mode^®Operation

The LTC1871-1 differs from the LTC1871 by having a

lower pulse skip threshold, making it ideal for applica-

tions requiring constant frequency operation at light

loads. The lower pulse skip threshold also helps maintain

constant frequency operation in applications with a wide

input voltage range. For applications requiring primary-

to-secondary side isolation, please refer to the LTC1871

datasheet.

■

Internal 5.2V Low Dropout Voltage Regulator

Output Overvoltage Protection

Capable of Operating with a Sense Resistor for High

Output Voltage Applications

Small 10-Lead MSOP Package

■

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APPLICATIO S

TheLTC1871-1isavailableinthe10-leadMSOPpackage.

■

Telecom Power Supplies

Portable Electronic Equipment

, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology

■

Corporation. No R

is a trademark of Linear Technology Corporation. All other

SENSE

trademarks are the property of their respective owners.

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TYPICAL APPLICATIO

V

IN

3.3V

Efficiency of Figure 1

L1

1μH

100

90

80

70

60

50

40

30

D1

RUN

SENSE

V

OUT

5V

Burst Mode

OPERATION

I

TH

V

IN

7A

C

R

OUT1

C

+

(10A PEAK)

LTC1871-1

INTV

150μF

6.3V

×4

22k

FB

PULSE-SKIP

MODE

CC

C

6.8nF

C1

R1

12.1k

1%

C

OUT2

FREQ

GATE

GND

M1

22μF

6.3V

X5R

×2

C

IN

C

VCC

+

R2

37.4k

1%

R

T

80.6k

1%

MODE/SYNC

22μF

6.3V

×2

C

C2

47pF

4.7μF

X5R

GND

1871 F01a

C

:

TAIYO YUDEN JMK325BJ226MM

: PANASONIC EEFUEOJ151R

D1: MBRB2515L

IN

L1: SUMIDA CEP125-H 1R0MH

M1: FAIRCHILD FDS7760A

OUT1

OUT2

0.001

0.01

0.1

1

10

: TAIYO YUDEN JMK325BJ226MM

OUTPUT CURRENT (A)

1871 F01b

Figure 1. High Efficiency 3.3V Input, 5V Output Boost Converter (Bootstrapped)

18711fa

1

LTC1871-1

W W

U W

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ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

TOP VIEW

V_INVoltage ............................................... –0.3V to 36V

INTV_CCVoltage ........................................... –0.3V to 7V

INTV_CCOutput Current ........................................ 50mA

GATE Voltage........................... –0.3V to V_INTVCC+ 0.3V

I_TH, FB Voltages ....................................... –0.3V to 2.7V

RUN, MODE/SYNC Voltages ....................... –0.3V to 7V

FREQ Voltage............................................–0.3V to 1.5V

SENSE Pin Voltage ................................... –0.3V to 36V

Operating Junction Temperature Range (Note 2)

LTC1871E-1 ....................................... –40°C to 85°C

LTC1871I-1 ...................................... –40°C to 125°C

Junction Temperature (Note 3)............................ 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

RUN

TH

FB

FREQ

MODE/

SYNC

1

2

3

4

5

10 SENSE

I

9

8

7

6

V

IN

INTV

GATE

GND

CC

MS PACKAGE

10-LEAD PLASTIC MSOP

T_JMAX= 125°C, θ_JA= 120°C/ W

*MS PART MARKING

ORDER PART NUMBER

LTC1871EMS-1

LTC1871IMS-1

LTCTV

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

*The temperature grade is identified by a label on the shipping container.

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. V_IN= 5V, V_RUN= 1.5V, R_FREQ= 80k, V_MODE/SYNC= 0V, unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loop

V

Minimum Input Voltage

2.5

V

IN(MIN)

I-Grade (Note 2)

(Note 4)

●

I

Input Voltage Supply Current

Continuous Mode

Q

V

= 5V, V = 1.4V, V = 0.75V

550

1000

μA

MODE/SYNC

FB

ITH

V

= 5V, V = 1.4V, V = 0.75V,

●

MODE/SYNC

FB

ITH

I-Grade (Note 2)

Burst Mode Operation, No Load

Shutdown Mode

V

= 0V, V = 0V (Note 5)

250

500

μA

MODE/SYNC

ITH

= 0V, V = 0V (Note 5),

MODE/SYNC

ITH

I-Grade (Note 2)

V

= 0V

10

20

μA

V

RUN

= 0V, I-Grade (Note 2)

10

+

–

V

Rising RUN Input Threshold Voltage

Falling RUN Input Threshold Voltage

1.348

1.248

RUN

1.223

1.198

1.273

1.298

V

●

V

RUN Pin Input Threshold Hysteresis

50

35

100

1

150

175

60

mV

nA

RUN(HYST)

I-Grade (Note 2)

I

RUN Input Current

Feedback Voltage

RUN

V

= 0.4V (Note 5)

1.218

1.212

1.230

1.242

1.248

V

FB

ITH

●

V

= 0.4V (Note 5), I-Grade (Note 2)

= 0.4V (Note 5)

1.205

1.255

60

V

nA

ITH

I

FB Pin Input Current

Line Regulation

18

FB

ΔV

2.5V ≤ V ≤ 30V

0.002

0.02

%/V

FB

IN

2.5V ≤ V ≤ 30V, I-Grade (Note 2)

●

0.002

0.03

%/V

IN

18711fa

2

LTC1871-1

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. V_IN= 5V, V_RUN= 1.5V, R_FREQ= 80k, V_MODE/SYNC= 0V, unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

ΔV

ITH

Load Regulation

V

= 0V, V = 0.5V to 0.9V (Note 5)

●

–1

–0.1

%

FB

MODE/SYNC

ITH

ΔV

V

= 0V, V = 0.5V to 0.9V (Note 5)

–1

–0.1

%

MODE/SYNC

ITH

I-Grade (Note 2)

– V in Percent

FB(NOM)

ΔV

ΔFB Pin, Overvoltage Lockout

Error Amplifier Transconductance

V

2.5

6

10

%

μmho

mV

FB(OV)

g

I

Pin Load = ±5μA (Note 5)

TH

650

195

150

m

V

Burst Mode Operation I Pin Voltage

Falling I Voltage (Note 5)

ITH(BURST)

SENSE(MAX)

TH

Maximum Current Sense Input Threshold

Duty Cycle < 20%

120

100

180

200

50

mV

Duty Cycle < 20%, I-Grade (Note 2)

●

mV

I

SENSE Pin Current (GATE High)

SENSE Pin Current (GATE Low)

V

SENSE

V

SENSE

= 0V

35

μA

SENSE(ON)

SENSE(OFF)

= 30V

0.1

5

Oscillator

f

Oscillator Frequency

R

= 80k

250

50

300

350

1000

97

kHz

%

OSC

FREQ

= 80k, I-Grade (Note 2)

●

FREQ

Oscillator Frequency Range

Maximum Duty Cycle

I-Grade (Note 2)

50

D

87

92

MAX

87

97

%

f

Recommended Maximum Synchronized

Frequency Ratio

f

= 300kHz (Note 6)

1.25

1.30

SYNC/ OSC

OSC

f

= 300kHz (Note 6), I-Grade (Note 2)

●

1.25

25

1.30

OSC

t

MODE/SYNC Minimum Input Pulse Width

MODE/SYNC Maximum Input Pulse Width

Low Level MODE/SYNC Input Voltage

V

= 0V to 5V

ns

V

SYNC(MIN)

SYNC(MAX)

SYNC

0.8/f

OSC

V

0.3

IL(MODE)

I-Grade (Note 2)

●

V

High Level MODE/SYNC Input Voltage

1.2

V

IH(MODE)

V

R

MODE/SYNC Input Pull-Down Resistance

Nominal FREQ Pin Voltage

50

kΩ

V

MODE/SYNC

V

FREQ

0.62

Low Dropout Regulator

V

INTV Regulator Output Voltage

V

= 7.5V

5.0

5.2

8

5.4

25

V

INTVCC

CC

IN

= 7.5V, I-Grade (Note 2)

●

IN

ΔV

INTV Regulator Line Regulation

7.5V ≤ V ≤ 15V

mV

INTVCC

CC

IN

ΔV

IN1

INTV Regulator Line Regulation

15V ≤ V ≤ 30V

70

200

mV

INTVCC

CC

IN

ΔV

IN2

V

INTV Load Regulation

0 ≤ I

≤ 20mA, V = 7.5V

–2

–0.2

280

10

%

mV

μA

LDO(LOAD)

DROPOUT

INTVCC

CC

INTVCC

IN

INTV Regulator Dropout Voltage

INTV Load = 20mA

CC

I

Bootstrap Mode INTV Supply

RUN = 0V, SENSE = 5V

20

30

CC

Current in Shutdown

I-Grade (Note 2)

●

μA

GATE Driver

t

GATE Driver Output Rise Time

GATE Driver Output Fall Time

C = 3300pF (Note 7)

17

8

100

ns

r

f

L

C = 3300pF (Note 7)

L

18711fa

3

LTC1871-1

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: The dynamic input supply current is higher due to power MOSFET

gate charging (Q • f ). See Applications Information.

G

OSC

Note 5: The LTC1871-1 is tested in a feedback loop which servos V to

FB

the reference voltage with the I pin forced to the midpoint of its voltage

TH

Note 2: The LTC1871E-1 is guaranteed to meet performance specifications

from 0°C to 85°C junction temperature. Specifications over the –40°C to

85°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC1871I-1 is guaranteed over the full –40°C to 125°C operating junction

temperature range.

range (0.3V ≤ V ≤ 1.2V, midpoint = 0.75V).

ITH

Note 6: In a synchronized application, the internal slope compensation

gain is increased by 25%. Synchronizing to a significantly higher ratio will

reduce the effective amount of slope compensation, which could result in

subharmonic oscillation for duty cycles greater than 50%.

Note 7: Rise and fall times are measured at 10% and 90% levels.

Note 3: T is calculated from the ambient temperature T and power

J

A

dissipation P according to the following formula:

D

T = T + (P • 110°C/W)

J

A

D

U W

TYPICAL PERFOR A CE CHARACTERISTICS

FB Voltage vs Temp

FB Voltage Line Regulation

FB Pin Current vs Temperature

1.231

1.230

1.229

60

50

40

30

20

10

0

1.25

1.24

1.23

1.22

1.21

0

5

10

15

V

20

(V)

25

30

35

–50

0

25 50 75 100 125 150

50 75

TEMPERATURE (°C)

–25

–50 –25

0

25

100 125 150

TEMPERATURE (°C)

IN

1871 G02

1871 G03

1871 G01

Shutdown Mode I_Qvs V_IN

Shutdown Mode I_Qvs Temperature

Burst Mode I_Qvs V_IN

20

15

10

5

30

20

10

600

500

400

300

200

100

0

V

IN

= 5V

0

–50 –25

0

25 50 75 100 125 150

30

0

10

20

(V)

40

0

10

20

(V)

30

40

TEMPERATURE (°C)

V

IN

1871 G05

1871 G04

1871 G06

18711fa

4

LTC1871-1

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Gate Drive Rise and Fall Time

vs C_L

Burst Mode I_Qvs Temperature

Dynamic I_Qvs Frequency

500

400

300

200

100

0

18

16

14

12

10

8

60

50

40

30

20

10

0

C

= 3300pF

L

I

= 550μA + Qg • f

Q(TOT)

RISE TIME

6

FALL TIME

4

2

0

–50

50

100 125

150

–25

0

25

75

0

4000 6000 8000 10000 12000

2000

0

200

400

FREQUENCY (kHz)

1000 1200

600

800

TEMPERATURE (°C)

C

(pF)

L

1871 G07

1871 G09

1871 G08

RUN Thresholds vs V_IN

RUN Thresholds vs Temperature

R_Tvs Frequency

1000

100

10

1.5

1.4

1.3

1.40

1.35

1.30

1.25

1.20

1.2

30

0

10

20

(V)

40

200

400

600 700 800

1000

900

100

0

300

500

50 75

TEMPERATURE (°C)

–50 –25

0

25

100 125 150

V

FREQUENCY (kHz)

IN

1871 G12

1871 G10

1871 G11

Maximum Sense Threshold

vs Temperature

Frequency vs Temperature

SENSE Pin Current vs Temperature

325

320

315

310

305

300

295

290

285

280

275

35

30

25

160

155

150

145

GATE HIGH

V

= 0V

SENSE

140

–50 –25

0

25 50 75 100 125 150

125

100

150

–50

50

100 125

–50

50

–25

0

25

75

150

–25

0

25

75

TEMPERATURE (°C)

1871 G14

1871 G13

1871 G15

18711fa

5

LTC1871-1

TYPICAL PERFOR A CE CHARACTERISTICS

U W

INTV_CCDropout Voltage

vs Current, Temperature

INTV_CCLoad Regulation

INTV_CCLine Regulation

500

450

400

350

300

250

200

150

100

50

5.4

5.3

5.2

V

= 7.5V

IN

150°C

5.2

125°C

75°C

25°C

5.1

5.0

0°C

–50°C

5.1

0

25 30

10

20

0

5

10 15 20

(V)

35 40

0

5

15

40

0

10 20 30

50 60 70 80

V

INTV LOAD (mA)

CC

IN

INTV LOAD (mA)

CC

1871 G17

1871 G18

1871 G16

U

PI FU CTIO S

RUN (Pin 1): The RUN pin provides the user with an

accurate means for sensing the input voltage and pro-

gramming the start-up threshold for the converter. The

falling RUN pin threshold is nominally 1.248V and the

comparatorhas100mVofhysteresisfornoiseimmunity.

When the RUN pin is below this input threshold, the IC is

shut down and the V_INsupply current is kept to a low

value (typ 10μA). The Absolute Maximum Rating for the

voltage on this pin is 7V.

operating frequency to an external clock. If the MODE/

SYNC pin is connected to ground, Burst Mode operation

is enabled. If the MODE/SYNC pin is connected to IN-

TV_CC, or if an external logic-level synchronization signal

is applied to this input, Burst Mode operation is disabled

and the IC operates in a continuous mode.

GND (Pin 6): Ground Pin.

GATE (Pin 7): Gate Driver Output.

I

NTV_CC(Pin8):TheInternal5.20VRegulatorOutput. The

I_TH(Pin 2): Error Amplifier Compensation Pin. The cur-

rent comparator input threshold increases with this

control voltage. Nominal voltage range for this pin is 0V

to 1.40V.

gate driver and control circuits are powered from this

voltage. Decouple this pin locally to the IC ground with a

minimum of 4.7μF low ESR tantalum or ceramic

capacitor.

FB (Pin 3): Receives the feedback voltage from the

external resistor divider across the output. Nominal

voltage for this pin in regulation is 1.230V.

V_IN(Pin 9): Main Supply Pin. Must be closely decoupled

to ground.

SENSE (Pin 10): The Current Sense Input for the Control

Loop. Connect this pin to the drain of the power MOSFET

for V_DSsensing and highest efficiency. Alternatively, the

SENSE pin may be connected to a resistor in the source

of the power MOSFET. Internal leading edge blanking is

provided for both sensing methods.

FREQ (Pin 4): A resistor from the FREQ pin to ground

programs the operating frequency of the chip. The nomi-

nal voltage at the FREQ pin is 0.6V.

MODE/SYNC (Pin 5): This input controls the operating

mode of the converter and allows for synchronizing the

18711fa

6

LTC1871-1

W

BLOCK DIAGRA

RUN

+

–

1

BIAS AND

START-UP

CONTROL

SLOPE

COMPENSATION

C2

1.248V

V

FREQ

4

IN

V-TO-I

OV

OSC

9

0.6V

I

OSC

MODE/SYNC

5

INTV

CC

GATE

7

PWM LATCH

50k

LOGIC

85mV

S

Q

R

–

+

1.230V

GND

+

BURST

COMPARATOR

CURRENT

COMPARATOR

SENSE

10

+

–

0.175V

+

–

FB

3

C1

EA

–

+

g

m

1.230V

I

TH

2

V-TO-I

SLOPE

R

LOOP

INTV

8

I

CC

LOOP

5.2V

1.230V

TO

LDO

UV

1.230V

–

+

GND

START-UP

CONTROL

BIAS

V

6

1871 BD

REF

2.00V

V

IN

18711fa

7

LTC1871-1

U

OPERATIO

Main Control Loop

to rise, which causes the current comparator C1 to trip at

ahigherpeakinductorcurrentvalue. Theaverageinductor

current will therefore rise until it equals the load current,

thereby maintaining output regulation.

The LTC1871-1 is a constant frequency, current mode

controller for DC/DC boost, SEPIC and flyback converter

applications. The LTC1871-1 is distinguished from con-

ventional current mode controllers because the current

control loop can be closed by sensing the voltage drop

across the power MOSFET switch instead of across a

discrete sense resistor, as shown in Figure 2. This sensing

technique improves efficiency, increases power density,

and reduces the cost of the overall solution.

The nominal operating frequency of the LTC1871-1 is

programmedusingaresistorfromtheFREQpintoground

and can be controlled over a 50kHz to 1000kHz range. In

addition, the internal oscillator can be synchronized to an

external clock applied to the MODE/SYNC pin and can be

locked to a frequency between 100% and 130% of its

nominal value. When the MODE/SYNC pin is left open, it is

pulled low by an internal 50k resistor and Burst Mode

operation is enabled. If this pin is taken above 2V or an

external clock is applied, Burst Mode operation is disabled

and the IC operates in continuous mode. With no load (or

an extremely light load), the controller will skip pulses in

order to maintain regulation and prevent excessive output

ripple.

D

L

V

IN

V

OUT

V

IN

+

SENSE

C

OUT

V

SW

GATE

GND

2a. SENSE Pin Connection for

Maximum Efficiency (V

< 36V)

SW

The RUN pin controls whether the IC is enabled or is in a

low current shutdown state. A micropower 1.248V refer-

ence and comparator C2 allow the user to program the

supply voltage at which the IC turns on and off (compara-

tor C2 has 100mV of hysteresis for noise immunity). With

the RUN pin below 1.248V, the chip is off and the input

supply current is typically only 10μA.

D

L

V

IN

V

OUT

V

SW

V

IN

GATE

+

SENSE

GND

C

OUT

R

S

1871 F02

GND

An overvoltage comparator OV senses when the FB pin

exceeds the reference voltage by 6.5% and provides a

reset pulse to the main RS latch. Because this RS latch is

reset-dominant, the power MOSFET is actively held off for

the duration of an output overvoltage condition.

2b. SENSE Pin Connection for Precise

Control of Peak Current or for V > 36V

SW

Figure 2. Using the SENSE Pin On the LTC1871-1

For circuit operation, please refer to the Block Diagram of

the IC and Figure 1. In normal operation, the power

MOSFET is turned on when the oscillator sets the PWM

latch and is turned off when the current comparator C1

resets the latch. The divided-down output voltage is com-

paredtoaninternal1.230Vreferencebytheerroramplifier

EA,whichoutputsanerrorsignalattheI_THpin.Thevoltage

on the I_THpin sets the current comparator C1 input

threshold. When the load current increases, a fall in the FB

voltage relative to the reference voltage causes the I_THpin

The LTC1871-1 can be used either by sensing the voltage

drop across the power MOSFET or by connecting the

SENSE pin to a conventional shunt resistor in the source

of the power MOSFET, as shown in Figure 2. Sensing the

voltage across the power MOSFET maximizes converter

efficiency and minimizes the component count, but limits

the output voltage to the maximum rating for this pin

(36V). By connecting the SENSE pin to a resistor in the

source of the power MOSFET, the user is able to program

output voltages significantly greater than 36V.

18711fa

8

LTC1871-1

U

OPERATIO

Programming the Operating Mode

powerMOSFETR_DS(ON).IftheI_THpindropsbelow0.175V,

the Burst Mode comparator B1 will turn off the power

MOSFET and scale back the quiescent current of the IC to

250μA(sleepmode).Inthiscondition,theloadcurrentwill

be supplied by the output capacitor until the I_THvoltage

rises above the 50mV hysteresis of the burst comparator.

At light loads, short bursts of switching (where the aver-

age inductor current is 20% of its maximum value) fol-

lowed by long periods of sleep will be observed, thereby

greatlyimprovingconverterefficiency.Oscilloscopewave-

forms illustrating Burst Mode operation are shown in

Figure 3.

For applications where maximizing the efficiency at very

light loads (e.g., <100μA) is a high priority, the current in

the output divider could be decreased to a few micro-

amps and Burst Mode operation should be applied (i.e.,

the MODE/SYNC pin should be connected to ground). In

applications where fixed frequency operation is more

critical than low current efficiency, or where the lowest

outputrippleisdesired,pulse-skipmodeoperationshould

be used and the MODE/SYNC pin should be connected to

the INTV_CCpin. This allows discontinuous conduction

mode (DCM) operation down to near the limit defined by

the chip’s minimum on-time (about 175ns). Below this

output current level, the converter will begin to skip

cycles in order to maintain output regulation. Figures 3

and 4 show the light load switching waveforms for Burst

Mode and pulse-skip mode operation for the converter in

Figure 1.

Pulse-Skip Mode Operation

With the MODE/SYNC pin tied to a DC voltage above 2V,

Burst Mode operation is disabled. The internal, 0.525V

buffered I_THburst clamp is removed, allowing the I_THpin

to directly control the current comparator from no load to

full load. With no load, the I_THpin is driven below 0.175V,

the power MOSFET is turned off and sleep mode is

invoked. Oscilloscopewaveformsillustratingthismodeof

operation are shown in Figure 4.

Burst Mode Operation

Burst Mode operation is selected by leaving the MODE/

SYNC pin unconnected or by connecting it to ground. In

normal operation, the range on the I_THpin corresponding

to no load to full load is 0.30V to 1.2V. In Burst Mode

operation, if the error amplifier EA drives the I_THvoltage

below 0.525V, the buffered I_THinput to the current com-

parator C1 will be clamped at 0.525V (which corresponds

to 25% of maximum load current). The inductor current

peak is then held at approximately 30mV divided by the

When an external clock signal drives the MODE/SYNC pin

at a rate faster than the chip’s internal oscillator, the

oscillatorwillsynchronizetoit.Inthissynchronizedmode,

Burst Mode operation is disabled. The constant frequency

associated with synchronized operation provides a more

controlled noise spectrum from the converter, at the

expense of overall system efficiency of light loads.

MODE/SYNC = 0V

(Burst Mode OPERATION)

MODE/SYNC = INTV_CC

(PULSE-SKIP MODE)

V_IN= 3.3V

V_OUT= 5V

I_OUT= 500mA

V_OUT

50mV/DIV

V_OUT

50mV/DIV

I_L

5A/DIV

I_L

5A/DIV

10μs/DIV

1871 F03

2μs/DIV

1871 F04

Figure 3. LTC1871-1 Burst Mode Operation

(MODE/SYNC = 0V) at Low Output Current

Figure 4. LTC1871-1 Low Output Current Operation with

Burst Mode Operation Disabled (MODE/SYNC = INTV_CC

)

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When the oscillator’s internal logic circuitry detects a

synchronizing signal on the MODE/SYNC pin, the internal

oscillator ramp is terminated early and the slope compen-

sation is increased by approximately 30%. As a result, in

applicationsrequiringsynchronization,itisrecommended

that the nominal operating frequency of the IC be pro-

grammedtobeabout75%oftheexternalclockfrequency.

Attempting to synchronize to too high an external fre-

quency (above 1.3f_O) can result in inadequate slope com-

pensationandpossiblesubharmonicoscillation(orjitter).

pin is used to charge and discharge an internal oscillator

capacitor. A graph for selecting the value of R_Tfor a given

operating frequency is shown in Figure 6.

1000

100

10

The external clock signal must exceed 2V for at least 25ns,

and should have a maximum duty cycle of 80%, as shown

in Figure 5. The MOSFET turn on will synchronize to the

rising edge of the external clock signal.

100 200

400

600 700 800

1000

900

0

300

500

FREQUENCY (kHz)

1871 F06

2V TO 7V

Figure 6. Timing Resistor (R_T) Value

MODE/

SYNC

t

= 25ns

MIN

INTV_CCRegulator Bypassing and Operation

0.8T

T

T = 1/f

O

An internal, P-channel low dropout voltage regulator pro-

duces the 5.2V supply which powers the gate driver and

logiccircuitrywithintheLTC1871-1, asshowninFigure7.

The INTV_CCregulator can supply up to 50mA and must be

bypassed to ground immediately adjacent to the IC pins

with a minimum of 4.7μF tantalum or ceramic capacitor.

Good bypassing is necessary to supply the high transient

currents required by the MOSFET gate driver.

GATE

D = 40%

I

L

1871 F05

For input voltages that don’t exceed 7V (the absolute

maximum rating for this pin), the internal low dropout

regulator in the LTC1871-1 is redundant and the INTV_CC

pin can be shorted directly to the V_INpin. With the INTV_CC

pin shorted to V_IN, however, the divider that programs the

regulated INTV_CCvoltage will draw 10μA of current from

theinputsupply, eveninshutdownmode. Forapplications

that require the lowest shutdown mode input supply

current, do not connect the INTV_CCpin to V_IN. Regardless

of whether the INTV_CCpin is shorted to V_INor not, it is

always necessary to have the driver circuitry bypassed

with a 4.7μF tantalum or low ESR ceramic capacitor to

ground immediately adjacent to the INTV_CCand GND

pins.

Figure 5. MODE/SYNC Clock Input and Switching

Waveforms for Synchronized Operation

Programming the Operating Frequency

The choice of operating frequency and inductor value is a

tradeoff between efficiency and component size. Low

frequency operation improves efficiency by reducing

MOSFET and diode switching losses. However, lower

frequency operation requires more inductance for a given

amount of load current.

The LTC1871-1 uses a constant frequency architecture

that can be programmed over a 50kHz to 1000kHz range

with a single external resistor from the FREQ pin to

ground, as shown in Figure 1. The nominal voltage on the

FREQ pin is 0.6V, and the current that flows into the FREQ

In an actual application, most of the IC supply current is

used to drive the gate capacitance of the power MOSFET.

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U

INPUT

SUPPLY

2.5V TO 30V

V

IN

–

+

1.230V

R2

P-CH

5.2V

C

IN

R1

INTV

CC

+

C

VCC

4.7μF

GATE

GND

LOGIC

DRIVER

M1

GND

PLACE AS CLOSE AS

POSSIBLE TO DEVICE PINS

1871 F07

Figure 7. Bypassing the LDO Regulator and Gate Driver Supply

Asaresult,highinputvoltageapplicationsinwhichalarge

power MOSFET is being driven at high frequencies can

cause the LTC1871-1 to exceed its maximum junction

temperature rating. The junction temperature can be

estimated using the following equations:

Thisdemonstrateshowsignificantthegatechargecurrent

can be when compared to the static quiescent current in

the IC.

Topreventthemaximumjunctiontemperaturefrombeing

exceeded, the input supply current must be checked when

operating in a continuous mode at high V_IN. A tradeoff

between the operating frequency and the size of the power

MOSFET may need to be made in order to maintain a

reliable IC junction temperature. Prior to lowering the

operating frequency, however, be sure to check with

power MOSFET manufacturers for their latest-and-great-

est low Q_G, low R_DS(ON)devices. Power MOSFET manu-

facturing technologies are continually improving, with

newer and better performance devices being introduced

almost yearly.

I_Q(TOT)≈ I_Q+ f • Q_G

P_IC= V_IN• (I_Q+ f • Q_G)

T_J= T_A+ P_IC• R_TH(JA)

The total quiescent current I_Q(TOT)consists of the static

supply current (I_Q) and the current required to charge and

discharge the gate of the power MOSFET. The 10-pin

MSOP package has a thermal resistance of R_TH(JA)

120°C/W.

=

As an example, consider a power supply with V_IN= 5V and

V_O= 12V at I_O= 1A. The switching frequency is 500kHz,

and the maximum ambient temperature is 70°C. The

power MOSFET chosen is the IRF7805, which has a

maximum R_DS(ON)of 11mΩ (at room temperature) and a

maximum total gate charge of 37nC (the temperature

coefficient of the gate charge is low).

Output Voltage Programming

The output voltage is set by a resistor divider according to

the following formula:

R2

R1

⎛

⎝

⎞

⎟

⎠

V = 1.230V • 1+

⎜

O

I_Q(TOT)= 600μA + 37nC • 500kHz = 19.1mA

P_IC= 5V • 19.1mA = 95mW

The external resistor divider is connected to the output as

shown in Figure 1, allowing remote voltage sensing. The

resistors R1 and R2 are typically chosen so that the error

T_J= 70°C + 120°C/W • 95mW = 81.4°C

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caused by the current flowing into the FB pin during

normal operation is less than 1% (this translates to a

maximum value of R1 of about 250k).

The turn-on and turn-off input voltage thresholds are

programmed using a resistor divider according to the

following formulas:

R2

R1

⎛

⎞

V

= 1.248V • 1+

Programming Turn-On and Turn-Off Thresholds

with the RUN Pin

IN(OFF)

⎜

⎝

⎟

⎠

R2

R1

⎛

⎞

⎠

V

= 1.348V • 1+

The LTC1871-1 contains an independent, micropower

voltage reference and comparator detection circuit that

remains active even when the device is shut down, as

showninFigure8.Thisallowsuserstoaccuratelyprogram

an input voltage at which the converter will turn on and off.

The falling threshold voltage on the RUN pin is equal to the

internal reference voltage of 1.248V. The comparator has

100mV of hysteresis to increase noise immunity.

IN(ON)

⎜

⎝

⎟

The resistor R1 is typically chosen to be less than 1M.

For applications where the RUN pin is only to be used as

a logic input, the user should be aware of the 7V

Absolute Maximum Rating for this pin! The RUN pin can

be connected to the input voltage through an external 1M

resistor, as shown in Figure 8c, for “always on” operation.

V

IN

+

R2

R1

RUN

COMPARATOR

RUN

+

BIAS AND

START-UP

CONTROL

6V

INPUT

SUPPLY

–

OPTIONAL

FILTER

CAPACITOR

1.248V

μPOWER

REFERENCE

GND

–

1871 F8a

Figure 8a. Programming the Turn-On and Turn-Off Thresholds Using the RUN Pin

V

IN

+

R2

1M

RUN

COMPARATOR

+

–

RUN

COMPARATOR

6V

INPUT

SUPPLY

RUN

+

–

6V

1.248V

EXTERNAL

LOGIC CONTROL

1.248V

GND

–

1871 F08b

1871 F08c

Figure 8b. On/Off Control Using External Logic

Figure 8c. External Pull-Up Resistor On

RUN Pin for “Always On” Operation

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The maximum duty cycle, D_MAX, should be calculated at

minimum V_IN.

Application Circuits

A basic LTC1871-1 application circuit is shown in

Figure 1. External component selection is driven by the

characteristics of the load and the input supply. The first

topology to be analyzed will be the boost converter,

followed by SEPIC (single ended primary inductance

converter).

χ

Boost Converter: Ripple Current ΔI_Land the ‘ ’ Factor

χ

The constant ‘ ’ in the equation above represents the

percentage peak-to-peak ripple current in the inductor,

relative to its maximum value. For example, if 30% ripple

χ

current is chosen, then = 0.30, and the peak current is

15% greater than the average.

Boost Converter: Duty Cycle Considerations

For a current mode boost regulator operating in CCM,

slope compensation must be added for duty cycles above

50% in order to avoid subharmonic oscillation. For the

LTC1871-1,thisrampcompensationisinternal.Havingan

internally fixed ramp compensation waveform, however,

does place some constraints on the value of the inductor

and the operating frequency. If too large an inductor is

used, theresultingcurrentramp(ΔI_L)willbesmallrelative

to the internal ramp compensation (at duty cycles above

50%), and the converter operation will approach voltage

mode(rampcompensationreducesthegainofthecurrent

loop). If too small an inductor is used, but the converter is

still operating in CCM (near critical conduction mode), the

internalrampcompensationmaybeinadequatetoprevent

subharmonic oscillation. To ensure good current mode

gain and avoid subharmonic oscillation, it is recom-

mended that the ripple current in the inductor fall in the

rangeof20%to40%ofthemaximumaveragecurrent.For

example, if the maximum average input current is 1A,

For a boost converter operating in a continuous conduc-

tion mode (CCM), the duty cycle of the main switch is:

⎛

⎞

V_O+ V_D– V

IN

D =

⎜

⎟

V_O+ V_D

⎝

⎠

where V_Dis the forward voltage of the boost diode. For

converters where the input voltage is close to the output

voltage, the duty cycle is low and for converters that

develop a high output voltage from a low voltage input

supply, the duty cycle is high. The maximum output

voltage for a boost converter operating in CCM is:

V

1–D

IN(MIN)

V_O(MAX)

=

– V_D

(

)

MAX

The maximum duty cycle capability of the LTC1871-1 is

typically 92%. This allows the user to obtain high output

voltages from low input supply voltages.

χ

choose a ΔI_Lbetween 0.2A and 0.4A, and a value ‘ ’

Boost Converter: The Peak and Average Input Currents

between 0.2 and 0.4.

The control circuit in the LTC1871-1 is measuring the

input current (either by using the R_DS(ON)of the power

MOSFET or by using a sense resistor in the MOSFET

source), so the output current needs to be reflected back

to the input in order to dimension the power MOSFET

properly. Based on the fact that, ideally, the output power

is equal to the input power, the maximum average input

current is:

Boost Converter: Inductor Selection

Givenanoperatinginputvoltagerange,andhavingchosen

the operating frequency and ripple current in the inductor,

the inductor value can be determined using the following

equation:

V

IN(MIN)

L =

•D_MAX

I_O(MAX)

1–D_MAX

Thepeak input current is:

ΔI_L• f

I

=

IN(MAX)

where:

I_O(MAX)

1–D_MAX

ΔI_L= χ •

I_O(MAX)

1–D_MAX

χ

2

⎛

⎝

⎞

⎟

⎠

I

= 1+

•

⎜

IN(PEAK)

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Remember that boost converters are not short-circuit

protected. Under a shorted output condition, the inductor

current is limited only by the input supply capability. For

applications requiring a step-up converter that is short-

circuit protected, please refer to the applications section

covering SEPIC converters.

Boost Converter: Inductor Core Selection

Once the value for L is known, the type of inductor must be

selected. High efficiency converters generally cannot af-

ford the core loss found in low cost powdered iron cores,

forcing the use of more expensive ferrite, molypermalloy

or Kool Mμ^®cores. Actual core loss is independent of core

sizeforafixedinductorvalue, butisverydependentonthe

inductance selected. As inductance increases, core losses

go down. Unfortunately, increased inductance requires

more turns of wire and therefore, copper losses will

increase.Generally,thereisatradeoffbetweencorelosses

and copper losses that needs to be balanced.

The minimum required saturation current of the inductor

can be expressed as a function of the duty cycle and the

load current, as follows:

I_O(MAX)

1–D_MAX

χ

2

⎛

⎝

⎞

⎟

⎠

I_L(SAT)≥ 1+

•

⎜

Ferritedesignshaveverylowcorelossesandarepreferred

at high switching frequencies, so design goals can con-

centrate on copper losses and preventing saturation.

Ferrite core material saturates “hard,” meaning that the

inductancecollapsesrapidlywhenthepeakdesigncurrent

is exceeded. This results in an abrupt increase in inductor

ripple current and consequently, output voltage ripple. Do

not allow the core to saturate!

The saturation current rating for the inductor should be

checked at the minimum input voltage (which results in

the highest inductor current) and maximum output

current.

Boost Converter: Operating in Discontinuous Mode

Discontinuous mode operation occurs when the load

current is low enough to allow the inductor current to run

outduringtheoff-timeoftheswitch, asshowninFigure 9.

Once the inductor current is near zero, the switch and

diode capacitances resonate with the inductance to form

damped ringing at 1MHz to 10MHz. If the off-time is long

enough, the drain voltage will settle to the input voltage.

Molypermalloy (from Magnetics, Inc.) is a very good, low

cost core material for toroids, but is more expensive than

ferrite. A reasonable compromise from the same manu-

facturer is Kool Mμ.

Boost Converter: Power MOSFET Selection

Depending on the input voltage and the residual energy in

the inductor, this ringing can cause the drain of the power

MOSFET to go below ground where it is clamped by the

body diode. This ringing is not harmful to the IC and it has

not been shown to contribute significantly to EMI. Any

attempttodampitwithasnubberwilldegradetheefficiency.

The power MOSFET serves two purposes in the LTC1871-

1: it represents the main switching element in the power

path, and its R_DS(ON)represents the current sensing ele-

ment for the control loop. Important parameters for the

power MOSFET include the drain-to-source breakdown

voltage (BV_DSS), the threshold voltage (V_GS(TH)), the on-

resistance (R_DS(ON)) versus gate-to-source voltage, the

gate-to-source and gate-to-drain charges (Q_GSand Q_GD,

respectively), the maximum drain current (I_D(MAX)) and

the MOSFET’s thermal resistances (R_TH(JC)and R_TH(JA)).

I_OUT= 200mA

V_IN= 3.3V

_OUT= 5V

V

MOSFET DRAIN

VOLTAGE

2V/DIV

The gate drive voltage is set by the 5.2V INTV_CClow drop

regulator. Consequently, logic-level threshold MOSFETs

should be used in most LTC1871-1 applications. If low

input voltage operation is expected (e.g., supplying power

INDUCTOR

CURRENT

2A/DIV

2μs/DIV

1871 F09

Figure 9. Discontinuous Mode Waveforms

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from a lithium-ion battery or a 3.3V logic supply), then

Another method of choosing which power MOSFET to use

istocheckwhatthemaximumoutputcurrentisforagiven

sublogic-level threshold MOSFETs should be used.

R

_DS(ON), since MOSFET on-resistances are available in

Pay close attention to the BV_DSSspecifications for the

MOSFETsrelativetothemaximumactualswitchvoltagein

theapplication.Manylogic-leveldevicesarelimitedto30V

or less, and the switch node can ring during the turn-off of

the MOSFET due to layout parasitics. Check the switching

waveforms of the MOSFET directly across the drain and

sourceterminalsusingtheactualPCboardlayout(notjust

on a lab breadboard!) for excessive ringing.

discrete values.

1–D_MAX

I_O(MAX)= V_SENSE(MAX)

•

χ

2

⎛

⎜

⎝

⎞

1+

•R_DS(ON)• ρ_T

⎟

⎠

It is worth noting that the 1 – D_MAXrelationship between

I_O(MAX)and R_DS(ON)can cause boost converters with a

wide input range to experience a dramatic range of maxi-

mum input and output current. This should be taken into

consideration in applications where it is important to limit

the maximum current drawn from the input supply.

During the switch on-time, the control circuit limits the

maximum voltage drop across the power MOSFET to

about 150mV (at low duty cycle). The peak inductor

current is therefore limited to 150mV/R_DS(ON). The rela-

tionship between the maximum load current, duty cycle

and the R_DS(ON)of the power MOSFET is:

Calculating Power MOSFET Switching and Conduction

Losses and Junction Temperatures

Inordertocalculatethejunctiontemperatureofthepower

MOSFET, the power dissipated by the device must be

known. This power dissipation is a function of the duty

cycle, the load current and the junction temperature itself

(duetothepositivetemperaturecoefficientofitsR_DS(ON)).

Asaresult, someiterativecalculationisnormallyrequired

to determine a reasonably accurate value. Since the

controller is using the MOSFET as both a switching and a

sensing element, care should be taken to ensure that the

converteriscapableofdeliveringtherequiredloadcurrent

over all operating conditions (line voltage and tempera-

ture),andfortheworst-casespecificationsforV_SENSE(MAX)

1–D_MAX

R_DS(ON)≤ V_SENSE(MAX)

•

χ

⎛

⎜

⎝

⎞

⎟

⎠

1+

•I_O(MAX)• ρ_T

2

The V_SENSE(MAX)term is typically 150mV at low duty

cycle, and is reduced to about 100mV at a duty cycle of

92% due to slope compensation, as shown in Figure 10.

The ρ_Tterm accounts for the temperature coefficient of

the R_DS(ON)of the MOSFET, which is typically 0.4%/°C.

Figure 11 illustrates the variation of normalized R_DS(ON)

over temperature for a typical power MOSFET.

200

150

100

50

2.0

1.5

1.0

0.5

0

0.2

0.4

0.5

0.8

1.0

–50

50

100

150

0

DUTY CYCLE

JUNCTION TEMPERATURE (°C)

1871 F10

1871 F11

Figure 11. Normalized R_DS(ON)vs Temperature

Figure 10. Maximum SENSE Threshold Voltage vs Duty Cycle

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andtheR_DS(ON)oftheMOSFETlistedinthemanufacturer’s

The R_TH(JA)to be used in this equation normally includes

the R_TH(JC)for the device plus the thermal resistance from

the board to the ambient temperature in the enclosure.

data sheet.

The power dissipated by the MOSFET in a boost converter is:

Remember to keep the diode lead lengths short and to

observe proper switch-node layout (see Board Layout

Checklist) to avoid excessive ringing and increased

dissipation.

2

I_O(MAX)

⎛

⎞

P_FET

=

• R_DS(ON)•D_MAX• ρ_T

⎜

⎟

1– D

⎝

⎠

MAX

I_O(MAX)

1.85

+ k • V_O

•

• C_RSS• f

1– D

)

(

MAX

Boost Converter: Output Capacitor Selection

The first term in the equation above represents the I²R

losses in the device, and the second term, the switching

losses. The constant, k = 1.7, is an empirical factor in-

verselyrelatedtothegatedrivecurrentandhasthedimen-

sion of 1/current.

Contributions of ESR (equivalent series resistance), ESL

(equivalent series inductance) and the bulk capacitance

must be considered when choosing the correct compo-

nent for a given output ripple voltage. The effects of these

three parameters (ESR, ESL and bulk C) on the output

voltage ripple waveform are illustrated in Figure 12e for a

typical boost converter.

From a known power dissipated in the power MOSFET, its

junction temperature can be obtained using the following

formula:

The choice of component(s) begins with the maximum

acceptable ripple voltage (expressed as a percentage of

theoutputvoltage), andhowthisrippleshouldbedivided

between the ESR step and the charging/discharging ΔV.

For the purpose of simplicity we will choose 2% for the

maximum output ripple, to be divided equally between

the ESR step and the charging/discharging ΔV. This

percentage ripple will change, depending on the require-

ments of the application, and the equations provided

below can easily be modified.

T_J= T_A+ P_FET• R_TH(JA)

The R_TH(JA)to be used in this equation normally includes

the R_TH(JC)for the device plus the thermal resistance from

the case to the ambient temperature (R_TH(CA)). This value

of T_Jcan then be compared to the original, assumed value

used in the iterative calculation process.

Boost Converter: Output Diode Selection

To maximize efficiency, a fast switching diode with low

forward drop and low reverse leakage is desired. The

output diode in a boost converter conducts current during

the switch off-time. The peak reverse voltage that the

diode must withstand is equal to the regulator output

voltage. The average forward current in normal operation

isequaltotheoutputcurrent, andthepeakcurrentisequal

to the peak inductor current.

For a 1% contribution to the total ripple voltage, the ESR

of the output capacitor can be determined using the

following equation:

0.01• V_O

ESR_COUT

where:

≤

I_IN(PEAK)

I_O(MAX)

1–D_MAX

χ

2

⎛

⎝

⎞

⎟

⎠

I_O(MAX)

1–D_MAX

χ

2

⎛

⎝

⎞

⎟

⎠

I_D(PEAK)= I_L(PEAK)= 1+

•

⎜

I_IN(PEAK)= 1+

•

⎜

The power dissipated by the diode is:

P_D= I_O(MAX)• V_D

For the bulk C component, which also contributes 1% to

the total ripple:

and the diode junction temperature is:

T_J= T_A+ P_D• R_TH(JA)

I_O(MAX)

0.01• V_O• f

C_OUT

≥

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For many designs it is possible to choose a single capaci-

tor type that satisfies both the ESR and bulk C require-

ments for the design. In certain demanding applications,

however, the ripple voltage can be improved significantly

by connecting two or more types of capacitors in parallel.

For example, using a low ESR ceramic capacitor can

minimize the ESR step, while an electrolytic capacitor can

be used to supply the required bulk C.

tested for use in switching power supplies. An excellent

choice is AVX TPS series of surface mount tantalum. Also,

ceramic capacitors are now available with extremely low

ESR, ESL and high ripple current ratings.

Boost Converter: Input Capacitor Selection

Theinputcapacitorofaboostconverterislesscriticalthan

the output capacitor, due to the fact that the inductor is in

series with the input and the input current waveform is

continuous (see Figure 12b). The input voltage source im-

Once the output capacitor ESR and bulk capacitance have

been determined, the overall ripple voltage waveform

should be verified on a dedicated PC board (see Board

Layout section for more information on component place-

ment). Lab breadboards generally suffer from excessive

series inductance (due to inter-component wiring), and

these parasitics can make the switching waveforms look

significantly worse than they would be on a properly

designed PC board.

L

D

V

OUT

V

SW

C

R

L

IN

OUT

12a. Circuit Diagram

Theoutputcapacitorinaboostregulatorexperienceshigh

RMS ripple currents, as shown in Figure 12. The RMS

output capacitor ripple current is:

I

IN

I

L

V_O– V

IN(MIN)

12b. Inductor and Input Currents

I_RMS(COUT)≈I_O(MAX)

•

V

IN(MIN)

Note that the ripple current ratings from capacitor manu-

facturers are often based on only 2000 hours of life. This

makes it advisable to further derate the capacitor or to

choose a capacitor rated at a higher temperature than

required. Several capacitors may also be placed in parallel

to meet size or height requirements in the design.

I

SW

t

ON

12c. Switch Current

I

D

t

OFF

Manufacturers such as Nichicon, United Chemicon and

Sanyoshouldbeconsideredforhighperformancethrough-

hole capacitors. The OS-CON semiconductor dielectric

capacitor available from Sanyo has the lowest product of

ESR and size of any aluminum electrolytic, at a somewhat

higher price.

I

O

12d. Diode and Output Currents

ΔV

COUT

V

OUT

(AC)

RINGING DUE TO

TOTAL INDUCTANCE

(BOARD + CAP)

In surface mount applications, multiple capacitors may

have to be placed in parallel in order to meet the ESR or

RMS current handling requirements of the application.

Aluminum electrolytic and dry tantalum capacitors are

both available in surface mount packages. In the case of

tantalum, it is critical that the capacitors have been surge

ΔV

ESR

12e. Output Voltage Ripple Waveform

Figure 12. Switching Waveforms for a Boost Converter

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Table 1. Recommended Component Manufacturers

VENDOR

COMPONENTS

Capacitors

TELEPHONE

WEB ADDRESS

avxcorp.com

bhelectronics.com

coilcraft.com

coiltronics.com

diodes.com

AVX

(207) 282-5111

(952) 894-9590

(847) 639-6400

(407) 241-7876

(805) 446-4800

(408) 822-2126

(516) 847-3000

(310) 322-3331

(361) 992-7900

(408) 986-0424

(800) 245-3984

(617) 926-0404

(770) 436-1300

(847) 843-7500

(602) 244-6600

(714) 373-7334

(619) 661-6835

(847) 956-0667

(408) 573-4150

(562) 596-1212

(972) 243-4321

(408) 432-8020

(847) 699-3430

(847) 696-2000

(605) 665-9301

(800) 554-5565

(207) 324-4140

(631) 543-7100

BH Electronics

Coilcraft

Inductors, Transformers

Inductors

Coiltronics

Diodes, Inc

Fairchild

Inductors

Diodes

MOSFETs

fairchildsemi.com

generalsemiconductor.com

irf.com

General Semiconductor

International Rectifier

IRC

Diodes

MOSFETs, Diodes

Sense Resistors

Tantalum Capacitors

Toroid Cores

Diodes

irctt.com

Kemet

kemet.com

Magnetics Inc

Microsemi

Murata-Erie

Nichicon

mag-inc.com

microsemi.com

murata.co.jp

Inductors, Capacitors

Capacitors

nichicon.com

onsemi.com

On Semiconductor

Panasonic

Sanyo

Diodes

Capacitors

panasonic.com

sanyo.co.jp

Capacitors

Sumida

Inductors

sumida.com

Taiyo Yuden

TDK

Capacitors

t-yuden.com

Capacitors, Inductors

Heat Sinks

component.tdk.com

aavidthermalloy.com

tokin.com

Thermalloy

Tokin

Capacitors

Toko

Inductors

tokoam.com

United Chemicon

Vishay/Dale

Vishay/Siliconix

Vishay/Sprague

Zetex

Capacitors

chemi-com.com

vishay.com

Resistors

MOSFETs

vishay.com

Capacitors

vishay.com

Small-Signal Discretes

zetex.com

pedance determines the size of the input capacitor, which

istypicallyintherangeof10μFto100μF.AlowESRcapaci-

tor is recommended, although it is not as critical as for the

output capacitor.

Burst Mode Operation and Considerations

The choice of MOSFET R_DS(ON)and inductor value also

determines the load current at which the LTC1871-1

enters Burst Mode operation. When bursting, the control-

ler clamps the peak inductor current to approximately:

The RMS input capacitor ripple current for a boost con-

verter is:

30mV

R_DS(ON)

V

I_BURST(PEAK)=

IN(MIN)

I_RMS(CIN)= 0.3 •

•D_MAX

L • f

which represents about 20% of the maximum 150mV

SENSE pin voltage. The corresponding average current

depends upon the amount of ripple current. Lower induc-

torvalues(higherΔI_L)willreducetheloadcurrentatwhich

Burst Mode operations begins, since it is the peak current

Please note that the input capacitor can see a very high

surge current when a battery is suddenly connected to the

input of the converter and solid tantalum capacitors can

fail catastrophically under these conditions. Be sure to

specify surge-tested capacitors!

that is being clamped.

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The output voltage ripple can increase during Burst Mode

operation if ΔI_Lis substantially less than I_BURST. This can

occur if the input voltage is very low or if a very large

inductor is chosen. At high duty cycles, a skipped cycle

causes the inductor current to quickly decay to zero.

However, because ΔI_Lis small, it takes multiple cycles for

the current to ramp back up to I_BURST(PEAK). During this

inductor charging interval, the output capacitor must

supply the load current and a significant droop in the

output voltage can occur. Generally, it is a good idea to

choose a value of inductor ΔI_Lbetween 25% and 40% of

1. The supply current into V_IN. The V_INcurrent is the sum

of the DC supply current I_Q(given in the Electrical

Characteristics) and the MOSFET driver and control

currents. The DC supply current into the V_INpin is

typically about 550μA and represents a small power

loss (much less than 1%) that increases with V_IN. The

driver current results from switching the gate capaci-

tance of the power MOSFET; this current is typically

muchlargerthantheDCcurrent.EachtimetheMOSFET

is switched on and then off, a packet of gate charge Q_G

is transferred from INTV_CCto ground. The resulting

dQ/dt is a current that must be supplied to the INTV_CC

capacitor through the V_INpin by an external supply. If

the IC is operating in CCM:

I

_IN(MAX). The alternative is to either increase the value of

the output capacitor or disable Burst Mode operation

using the MODE/SYNC pin.

Burst Mode operation can be defeated by connecting the

MODE/SYNC pin to a high logic-level voltage (either with

a control input or by connecting this pin to INTV_CC). In this

mode, the burst clamp is removed, and the chip can

operate at constant frequency from continuous conduc-

tion mode (CCM) at full load, down into deep discontinu-

ous conduction mode (DCM) at light load. Prior to skip-

ping pulses at very light load (i.e., <5% of full load), the

controller will operate with a minimum switch on-time in

DCM. Pulse skipping prevents a loss of control of the

output at very light loads and reduces output volt-

age ripple.

I_Q(TOT)≈ I_Q= f • Q_G

P_IC= V_IN• (I_Q+ f • Q_G)

2. Power MOSFET switching and conduction losses. The

technique of using the voltage drop across the power

MOSFETtoclosethecurrentfeedbackloopwaschosen

becauseoftheincreasedefficiencythatresultsfromnot

havingasenseresistor.ThelossesinthepowerMOSFET

are equal to:

2

I_O(MAX)

⎛

⎞

P_FET

=

•R_DS(ON)•D_MAX• ρ_T

⎜

⎟

1– D

⎝

⎠

MAX

I_O(MAX)

1.85

Efficiency Considerations: How Much Does V_DS

Sensing Help?

+ k • V_O

•

• C_RSS• f

1– D_MAX

The efficiency of a switching regulator is equal to the

output power divided by the input power (× 100%).

Percent efficiency can be expressed as:

The I²R power savings that result from not having a

discrete sense resistor can be calculated almost by

inspection.

% Efficiency = 100% – (L1 + L2 + L3 + …),

2

I_O(MAX)

⎛

⎞

P_R(SENSE)

=

•R_SENSE•D_MAX

where L1, L2, etc. are the individual loss components as

a percentage of the input power. It is often useful to

analyze individual losses to determine what is limiting the

efficiency and which change would produce the most

improvement. Although all dissipative elements in the

circuit produce losses, four main sources usually account

for the majority of the losses in LTC1871-1 applica-

tion circuits:

⎜

⎟

1– D

⎝

⎠

MAX

To understand the magnitude of the improvement with

this V_DSsensing technique, consider the 3.3V input, 5V

output power supply shown in Figure 1. The maximum

loadcurrentis7A(10Apeak)andthedutycycleis39%.

Assuming a ripple current of 40%, the peak inductor

current is 13.8A and the average is 11.5A. With a

maximum sense voltage of about 140mV, the sense

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V_IN= 3.3V

resistor value would be 10mΩ, and the power dissi-

pated in this resistor would be 514mW at maximum

output current. Assuming an efficiency of 90%, this

sense resistor power dissipation represents 1.3% of

the overall input power. In other words, for this appli-

cation, the use of V_DSsensing would increase the

efficiency by approximately 1.3%.

V_OUT= 5V

MODE/SYNC = INTV_CC

(PULSE-SKIP MODE)

I_OUT

2A/DIV

V_OUT(AC)

100mV/DIV

For more details regarding the various terms in these

equations, please refer to the section Boost Converter:

Power MOSFET Selection.

100μs/DIV

1871 F13

Figure 13. Load Transient Response for a 3.3V Input,

5V Output Boost Converter Application, 0.7A to 7A Step

3. The losses in the inductor are simply the DC input

currentsquaredtimesthewindingresistance. Express-

ing this loss as a function of the output current yields:

A second, more severe transient can occur when connect-

ing loads with large (>1μF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C_O, causing a nearly instantaneous drop in V_O. No

regulator can deliver enough current to prevent this prob-

lem if the load switch resistance is low and it is driven

quickly. The only solution is to limit the rise time of the

switch drive in order to limit the inrush current di/dt to the

load.

2

I_O(MAX)

⎛

⎞

P_R(WINDING)

=

•R_W

⎜

⎟

1– D

⎝

⎠

MAX

4. Losses in the boost diode. The power dissipation in the

boost diode is:

P_DIODE= I_O(MAX)• V_D

The boost diode can be a major source of power loss in

a boost converter. For the 3.3V input, 5V output at 7A

example given above, a Schottky diode with a 0.4V

forward voltage would dissipate 2.8W, which repre-

sents 7% of the input power. Diode losses can become

significant at low output voltages where the forward

voltageisasignificantpercentageoftheoutputvoltage.

Boost Converter Design Example

Thedesignexamplegivenherewillbeforthecircuitshown

in Figure 1. The input voltage is 3.3V, and the output is 5V

at a maximum load current of 7A (10A peak).

1. The duty cycle is:

5. Other losses, including C_INand C_OESR dissipation and

inductor core losses, generally account for less than

2% of the total additional loss.

⎛

⎝

⎞

⎠

V_O+ V_D– V

5 + 0.4 – 3.3

5 + 0.4

IN

D =

=

= 38.9%

⎜

⎟

V_O+ V_D

Checking Transient Response

2. Pulse-skip operation is chosen so the MODE/SYNC pin

is shorted to INTV_CC.

The regulator loop response can be verified by looking at

the load transient response. Switching regulators gener-

ally take several cycles to respond to an instantaneous

step in resistive load current. When the load step occurs,

V_Oimmediatelyshiftsbyanamountequalto(ΔI_LOAD)(ESR),

and then C_Obegins to charge or discharge (depending on

the direction of the load step) as shown in Figure 13. The

regulator feedback loop acts on the resulting error amp

output signal to return V_Oto its steady-state value. During

this recovery time, V_Ocan be monitored for overshoot or

ringing that would indicate a stability problem.

3. The operating frequency is chosen to be 300kHz to

reduce the size of the inductor. From Figure 5, the

resistor from the FREQ pin to ground is 80k.

4. An inductor ripple current of 40% of the maximum load

current is chosen, so the peak input current (which is

also the minimum saturation current) is:

I_O(MAX)

χ

2

7

⎛

⎞

I_IN(PEAK)= 1+

•

= 1.2 •

= 13.8A

⎜

⎝

⎟

⎠

1– D_MAX

1– 0.39

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ESR ceramic. Based on a maximum output ripple

voltage of 1%, or 50mV, the bulk C needs to be great-

er than:

The inductor ripple current is:

I_O(MAX)

7

ΔI_L= χ •

= 0.4 •

= 4.6A

1–D_MAX

1– 0.39

I_OUT(MAX)

And so the inductor value is:

C_OUT

≥

=

0.01• V_OUT• f

7A

V

3.3V

4.6A • 300kHz

IN(MIN)

L =

•D_MAX

=

• 0.39 = 0.93μH

ΔI_L• f

= 466μF

0.01• 5V • 300kHz

The component chosen is a 1μH inductor made by

Sumida (part number CEP125-H 1ROMH) which has a

saturation current of greater than 20A.

The RMS ripple current rating for this capacitor needs

to exceed:

5. With the input voltage to the IC bootstrapped to the

output of the power supply (5V), a logic-level MOSFET

can be used. Because the duty cycle is 39%, the

maximumSENSEpinthresholdvoltageisreducedfrom

its low duty cycle typical value of 150mV to approxi-

mately140mV. AssumingaMOSFETjunctiontempera-

ture of 125°C, the room temperature MOSFET R_DS(ON)

should be less than:

V_O– V

IN(MIN)

I_RMS(COUT)≥I_O(MAX)

•

=

V

IN(MIN)

5V – 3.3V

7A •

= 5A

3.3V

To satisfy this high RMS current demand, four 150μF

Panasonic capacitors (EEFUEOJ151R) are required.

In parallel with these bulk capacitors, two 22μF, low

ESR (X5R) Taiyo Yuden ceramic capacitors

(JMK325BJ226MM)areaddedforHFnoisereduction.

Check the output ripple with a single oscilloscope

probe connected directly across the output capacitor

terminals, where the HF switching currents flow.

1–D_MAX

R_DS(ON)≤ V_SENSE(MAX)

•

χ

⎛

⎜

⎝

⎞

⎟

⎠

1+

•I_O(MAX)• ρ_T

2

1– 0.39

= 0.140V •

= 6.8mΩ

0.4

⎛

⎜

⎝

⎞

⎟

⎠

1+

• 7A •1.5

2

8. The choice of an input capacitor for a boost converter

dependsontheimpedanceofthesourcesupplyandthe

amount of input ripple the converter will safely tolerate.

For this particular design and lab setup a 100μF Sanyo

Poscap (6TPC 100M), in parallel with two 22μF Taiyo

Yuden ceramic capacitors (JMK325BJ226MM) is re-

quired (the input and return lead lengths are kept to a

few inches, but the peak input current is close to 20A!).

As with the output node, check the input ripple with a

single oscilloscope probe connected across the input

capacitor terminals.

The MOSFET used was the Fairchild FDS7760A, which

has a maximum R_DS(ON)of 8mΩ at 4.5V V_GS, a BV_DSS

of greater than 30V, and a gate charge of 37nC at 5V

V_GS.

6. The diode for this design must handle a maximum DC

output current of 10A and be rated for a minimum

reverse voltage of V_OUT, or 5V. A 25A, 15V diode from

On Semiconductor (MBRB2515L) was chosen for its

high power dissipation capability.

7. The output capacitor usually consists of a high valued

bulk C connected in parallel with a lower valued, low

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PC Board Layout Checklist

source of the power MOSFET or the bottom terminal of

the sense resistor, 4) the negative terminal of the input

capacitor and 5) at least one via to the ground plane

immediately adjacent to Pin 6. The ground trace on the

top layer of the PC board should be as wide and short as

possible to minimize series resistance and inductance.

1. In order to minimize switching noise and improve

output load regulation, the GND pin of the LTC1871-1

should be connected directly to 1) the negative termi-

nal of the INTV_CCdecoupling capacitor, 2) the negative

terminal of the output decoupling capacitors, 3) the

V

IN

L1

JUMPER

R3

R4

R

C

J1

C

IN

PIN 1

LTC1871-1

R2

R1

T

C

VCC

SWITCH NODE IS ALSO

THE HEAT SPREADER

FOR L1, M1, D1

M1

PSEUDO-KELVIN

SIGNAL GROUND

CONNECTION

C

OUT

C

OUT

D1

VIAS TO GROUND

PLANE

V

OUT

TRUE REMOTE

OUTPUT SENSING

1871 F14

BULK C

LOW ESR CERAMIC

Figure 14. LTC1871-1 Boost Converter Suggested Layout

V

IN

R3

R4

L1

J1

1

2

10

9

C

SWITCH

NODE

C

RUN

SENSE

R

C

I

V

IN

TH

LTC1871-1

FB

R1

D1

3

4

5

8

7

6

INTV

CC

R2

FREQ

GATE

GND

M1

R

T

+

MODE/

SYNC

C

VCC

IN

GND

C

PSEUDO-KELVIN

GROUND CONNECTION

OUT

+

V

OUT

1871 F15

BOLD LINES INDICATE HIGH CURRENT PATHS

Figure 15. LTC1871-1 Boost Converter Layout Diagram

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pin trace and any high frequency switching nodes. The

LTC1871-1 contains an internal leading edge blanking

time of approximately 180ns, which should be ad-

equate for most applications.

2. BewareofgroundloopsinmultiplelayerPCboards. Try

to maintain one central ground node on the board and

use the input capacitor to avoid excess input ripple for

high output current power supplies. If the ground plane

is to be used for high DC currents, choose a path away

from the small-signal components.

8. For optimum load regulation and true remote sensing,

the top of the output resistor divider should connect

independently to the top of the output capacitor (Kelvin

connection), staying away from any high dV/dt traces.

Place the divider resistors near the LTC1871-1 in order

to keep the high impedance FB node short.

3. Place the C_VCCcapacitor immediately adjacent to the

INTV_CCand GND pins on the IC package. This capacitor

carries high di/dt MOSFET gate drive currents. A low

ESR and ESL 4.7μF ceramic capacitor works well here.

9. For applications with multiple switching power con-

verters connected to the same input supply, make sure

that the input filter capacitor for the LTC1871-1 is not

shared with other converters. AC input current from

anotherconvertercouldcausesubstantialinputvoltage

ripple, and this could interfere with the operation of the

LTC1871-1. A few inches of PC trace or wire (L ≈

100nH) between the C_INof the LTC1871-1 and the

actualsourceV_INshouldbesufficienttopreventcurrent

sharing problems.

4. The high di/dt loop from the bottom terminal of the

output capacitor, through the power MOSFET, through

the boost diode and back through the output capacitors

should be kept as tight as possible to reduce inductive

ringing. Excess inductance can cause increased stress

on the power MOSFET and increase HF noise on the

output. If low ESR ceramic capacitors are used on the

output to reduce output noise, place these capacitors

close to the boost diode in order to keep the series

inductance to a minimum.

5. Check the stress on the power MOSFET by measuring

its drain-to-source voltage directly across the device

terminals(referencethegroundofasinglescopeprobe

directly to the source pad on the PC board). Beware of

inductiveringingwhichcanexceedthemaximumspeci-

fied voltage rating of the MOSFET. If this ringing cannot

be avoided and exceeds the maximum rating of the

device, either choose a higher voltage device or specify

an avalanche-rated power MOSFET. Not all MOSFETs

are created equal (some are more equal than others).

C1

D1

C

L1

V

OUT

•

+

R

V

SW

L2

L

IN

OUT

•

16a. SEPIC Topology

V

IN

V

OUT

•

+

R

V

L

IN

6. Place the small-signal components away from high

frequency switching nodes. In the layout shown in

Figure14,allofthesmall-signalcomponentshavebeen

placed on one side of the IC and all of the power

components have been placed on the other. This also

allows the use of a pseudo-Kelvin connection for the

signal ground, where high di/dt gate driver currents

flow out of the IC ground pin in one direction (to the

bottom plate of the INTV_CCdecoupling capacitor) and

small-signal currents flow in the other direction.

•

16b. Current Flow During Switch On-Time

V

IN

D1

V

OUT

•

+

R

V

L

IN

•

16c. Current Flow During Switch Off-Time

Figures 16. SEPIC Topology and Current Flow

7. If a sense resistor is used in the source of the power

MOSFET,minimizethecapacitancebetweentheSENSE

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SEPIC Converter Applications

independentbutcanalsobewoundonthesamecoresince

identical voltages are applied to L1 and L2 throughout the

switching cycle. By making L1 = L2 and winding them on

the same core the input ripple is reduced along with cost

and size. All of the SEPIC applications information that

follows assumes L1 = L2 = L.

The LTC1871-1 is also well suited to SEPIC (single-ended

primaryinductanceconverter)converterapplications. The

SEPIC converter shown in Figure 16 uses two inductors.

The advantage of the SEPIC converter is the input voltage

may be higher or lower than the output voltage, and the

output is short-circuit protected.

SEPIC Converter: Duty Cycle Considerations

The first inductor, L1, together with the main switch,

resembles a boost converter. The second inductor, L2,

together with the output diode D1, resembles a flyback or

buck-boostconverter. ThetwoinductorsL1andL2canbe

For a SEPIC converter operating in a continuous conduc-

tion mode (CCM), the duty cycle of the main switch is:

⎛

⎞

V_O+ V_D

D =

⎜

⎟

V + V + V

D

⎝

⎠

IN

O

I

IN

I

L1

SW

ON

SW

OFF

where V_Dis the forward voltage of the diode. For convert-

ers where the input voltage is close to the output voltage

the duty cycle is near 50%.

17a. Input Inductor Current

I

O

The maximum output voltage for a SEPIC converter is:

I

L2

D_MAX

1

V_O(MAX)= V + V

– V_D

(

)

1–D_MAX

IN

D

17b. Output Inductor Current

1–D_MAX

I

IN

The maximum duty cycle of the LTC1871-1 is typically

92%.

I

C1

O

SEPIC Converter: The Peak and Average

Input Currents

17c. DC Coupling Capacitor Current

The control circuit in the LTC1871-1 is measuring the

input current (either using the R_DS(ON)of the power

MOSFET or by means of a sense resistor in the MOSFET

source), so the output current needs to be reflected back

to the input in order to dimension the power MOSFET

properly. Based on the fact that, ideally, the output power

is equal to the input power, the maximum input current for

a SEPIC converter is:

I

D1

I

O

17d. Diode Current

V

OUT

(AC)

D_MAX

ΔV

I

= I_O(MAX)•

COUT

IN(MAX)

1–D_MAX

ΔV

ESR

RINGING DUE TO

TOTAL INDUCTANCE

(BOARD + CAP)

Thepeak input current is:

⎛

⎞

χ

2

D_MAX

1–D_MAX

17e. Output Ripple Voltage

I

= 1+

•I_O(MAX)•

IN(PEAK)

⎜

⎟

⎝

⎠

Figures 17. SEPIC Converter Switching Waveforms

The maximum duty cycle, D_MAX, should be calculated at

minimum V_IN.

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χ

Theconstant‘ ’representsthefractionofripplecurrentin

BymakingL1=L2andwindingthemonthesamecore,the

value of inductance in the equation above is replace by 2L

due to mutual inductance. Doing this maintains the same

ripple current and energy storage in the inductors. For

example, aCoiltronixCTX10-4isa10μHinductorwithtwo

windings. With the windings in parallel, 10μH inductance

isobtainedwithacurrentratingof4A(thenumberofturns

hasn’t changed, but the wire diameter has doubled).

Splitting the two windings creates two 10μH inductors

withacurrentratingof2Aeach. Therefore, substituting2L

yields the following equation for coupled inductors:

the inductor relative to its maximum value. For example, if

χ

30% ripple current is chosen, then = 0.30 and the peak

current is 15% greater than the average.

It is worth noting here that SEPIC converters that operate

at high duty cycles (i.e., that develop a high output voltage

from a low input voltage) can have very high input cur-

rents, relative to the output current. Be sure to check that

the maximum load current will not overload the input

supply.

SEPIC Converter: Inductor Selection

V

IN(MIN)

L1= L2 =

•D_MAX

For most SEPIC applications the equal inductor values will

fall in the range of 10μH to 100μH. Higher values will

reduce the input ripple voltage and reduce the core loss.

Lower inductor values are chosen to reduce physical size

and improve transient response.

2 • ΔI_L• f

Specify the maximum inductor current to safely handle

I_L(PK)specified in the equation above. The saturation

current rating for the inductor should be checked at the

minimum input voltage (which results in the highest

inductor current) and maximum output current.

Like the boost converter, the input current of the SEPIC

converter is calculated at full load current and minimum

input voltage. The peak inductor current can be signifi-

cantly higher than the output current, especially with

smaller inductors and lighter loads. The following formu-

las assume CCM operation and calculate the maximum

peak inductor currents at minimum V_IN:

SEPIC Converter: Power MOSFET Selection

The power MOSFET serves two purposes in the LTC1871-

1: it represents the main switching element in the power

path, and its R_DS(ON)represents the current sensing

element for the control loop. Important parameters for the

power MOSFET include the drain-to-source breakdown

voltage (BV_DSS), the threshold voltage (V_GS(TH)), the on-

resistance (R_DS(ON)) versus gate-to-source voltage, the

gate-to-source and gate-to-drain charges (Q_GSand Q_GD,

respectively), the maximum drain current (I_D(MAX)) and

the MOSFET’s thermal resistances (R_TH(JC)and R_TH(JA)).

⎛

⎞

χ

2

V_O+ V_D

I_L1(PEAK)= 1+

•I_O(MAX)•

⎜

⎟

V

⎝

⎛

⎠

IN(MIN)

⎞

V

+ V_D

χ

2

IN(MIN)

I_L2(PEAK)= 1+

•I_O(MAX)•

⎜

⎟

V

⎝

⎠

IN(MIN)

The ripple current in the inductor is typically 20% to 40%

The gate drive voltage is set by the 5.2V INTV_CClow

dropout regulator. Consequently, logic-level threshold

MOSFETs should be used in most LTC1871-1 applica-

tions. If low input voltage operation is expected (e.g.,

supplyingpowerfromalithium-ionbattery),thensublogic-

level threshold MOSFETs should be used.

χ

(i.e., a range of ‘ ’ from 0.20 to 0.40) of the maximum

average input current occurring at V_IN(MIN)and I_O(MAX)

and ΔI_L1= ΔI_L2. Expressing this ripple current as a

function of the output current results in the following

equations for calculating the inductor value:

V

IN(MIN)

The maximum voltage that the MOSFET switch must

sustain during the off-time in a SEPIC converter is equal to

the sum of the input and output voltages (V_O+ V_IN). As a

result, careful attention must be paid to the BV_DSSspeci-

L =

•D_MAX

ΔI_L• f

where:

fications for the MOSFETs relative to the maximum actual

switch voltage in the application. Many logic-level devices

18711fa

D_MAX

1–D_MAX

ΔI_L= χ •I_O(MAX)

•

25

LTC1871-1

W U U

U

APPLICATIO S I FOR ATIO

are limited to 30V or less. Check the switching waveforms

directlyacrossthedrainandsourceterminalsofthepower

MOSFET to ensure the V_DSremains below the maximum

rating for the device.

sensing element, care should be taken to ensure that the

converteriscapableofdeliveringtherequiredloadcurrent

over all operating conditions (load, line and temperature)

and for the worst-case specifications for V_SENSE(MAX)and

the R_DS(ON)of the MOSFET listed in the manufacturer’s

data sheet.

DuringtheMOSFET’son-time,thecontrolcircuitlimitsthe

maximum voltage drop across the power MOSFET to

about 150mV (at low duty cycle). The peak inductor

current is therefore limited to 150mV/R_DS(ON). The rela-

tionship between the maximum load current, duty cycle

and the R_DS(ON)of the power MOSFET is:

ThepowerdissipatedbytheMOSFETinaSEPICconverteris:

2

⎛

⎞

⎠

D_MAX

1– D_MAX

P_FET= I_O(MAX)

•

•R_DS(ON)•D_MAX• ρ_T

⎜

⎝

⎟

+ V_O^1.85•I_O(MAX)

•

• C_RSS• f

D_MAX

1– D_MAX

V_SENSE(MAX)

1

+ k • V

(

)

IN(MIN)

R_DS(ON)

≤

•

χ

I_O(MAX)

⎛

⎞

⎛

⎞

V_O+ V_D

1+

• ρ_T

⎜

⎝

⎟

+ 1

The first term in the equation above represents the I²R

losses in the device and the second term, the switching

losses.Theconstant k=1.7isanempiricalfactorinversely

related to the gate drive current and has the dimension of

1/current.

⎜

⎟

⎠

2

V

⎝

⎠

IN(MIN)

The V_SENSE(MAX)term is typically 150mV at low duty cycle

and is reduced to about 100mV at a duty cycle of 92% due

toslopecompensation,asshowninFigure8.Theconstant

χ

‘ ’ in the denominator represents the ripple current in the

From a known power dissipated in the power MOSFET, its

junction temperature can be obtained using the following

formula:

inductors relative to their maximum current. For example,

χ

if 30% ripple current is chosen, then = 0.30. The ρ_Tterm

accounts for the temperature coefficient of the R_DS(ON)of

the MOSFET, which is typically 0.4%/°C. Figure 9 illus-

trates the variation of normalized R_DS(ON)over tempera-

ture for a typical power MOSFET.

T_J= T_A+ P_FET•R_TH(JA)

The R_TH(JA)to be used in this equation normally includes

the R_TH(JC)for the device plus the thermal resistance from

the board to the ambient temperature in the enclosure.

This value of T_Jcan then be used to check the original

assumption for the junction temperature in the iterative

calculation process.

Another method of choosing which power MOSFET to use

istocheckwhatthemaximumoutputcurrentisforagiven

R_DS(ON)since MOSFET on-resistances are available in

discrete values.

V_SENSE(MAX)

1

SEPIC Converter: Output Diode Selection

I_O(MAX)

≤

•

χ

R_DS(ON)

⎛

⎞

⎛

⎞

V_O+ V_D

To maximize efficiency, a fast-switching diode with low

forward drop and low reverse leakage is desired. The

outputdiodeinaSEPICconverterconductscurrentduring

the switch off-time. The peak reverse voltage that the

diode must withstand is equal to V_IN(MAX)+ V_O. The

averageforwardcurrentinnormaloperationisequaltothe

output current, and the peak current is equal to:

1+

• ρ_T

⎜

⎝

⎟

+ 1

⎜

⎟

⎠

2

V

⎝

⎠

IN(MIN)

Calculating Power MOSFET Switching and Conduction

Losses and Junction Temperatures

In order to calculate the junction temperature of the power

MOSFET, the power dissipated by the device must be

known. This power dissipation is a function of the duty

cycle, the load current and the junction temperature itself.

As a result, some iterative calculation is normally required

to determine a reasonably accurate value. Since the con-

troller is using the MOSFET as both a switching and a

⎛

⎞

χ

2

V_O+ V_D

⎛

⎞

I_D(PEAK)= 1+

•I_O(MAX)

•

+ 1

⎟

⎜

⎝

⎟

⎠

V

⎝

⎠

IN(MIN)

The power dissipated by the diode is:

P_D= I_O(MAX)• V_D

18711fa

26

LTC1871-1

W U U

APPLICATIO S I FOR ATIO

U

For many designs it is possible to choose a single capaci-

tor type that satisfies both the ESR and bulk C require-

ments for the design. In certain demanding applications,

however, the ripple voltage can be improved significantly

by connecting two or more types of capacitors in parallel.

For example, using a low ESR ceramic capacitor can

minimize the ESR step, while an electrolytic or tantalum

capacitor can be used to supply the required bulk C.

and the diode junction temperature is:

T_J= T_A+ P_D• R_TH(JA)

The R_TH(JA)to be used in this equation normally includes

the R_TH(JC)for the device plus the thermal resistance from

the board to the ambient temperature in the enclosure.

SEPIC Converter: Output Capacitor Selection

Because of the improved performance of today’s electro-

lytic, tantalum and ceramic capacitors, engineers need to

considerthecontributionsofESR(equivalentseriesresis-

tance), ESL (equivalent series inductance) and the bulk

capacitance when choosing the correct component for a

given output ripple voltage. The effects of these three

parameters (ESR, ESL, and bulk C) on the output voltage

ripple waveform are illustrated in Figure 17 for a typical

coupled-inductor SEPIC converter.

Once the output capacitor ESR and bulk capacitance have

been determined, the overall ripple voltage waveform

should be verified on a dedicated PC board (see Board

Layout section for more information on component place-

ment). Lab breadboards generally suffer from excessive

series inductance (due to inter-component wiring), and

these parasitics can make the switching waveforms look

significantly worse than they would be on a properly

designed PC board.

The choice of component(s) begins with the maximum

acceptable ripple voltage (expressed as a percentage of

the output voltage), and how this ripple should be divided

between the ESR step and the charging/discharging ΔV.

For the purpose of simplicity we will choose 2% for the

maximum output ripple, to be divided equally between the

ESR step and the charging/discharging ΔV. This percent-

age ripple will change, depending on the requirements of

the application, and the equations provided below can

easily be modified.

The output capacitor in a SEPIC regulator experiences

highRMSripplecurrents, asshowninFigure17. TheRMS

output capacitor ripple current is:

V_O

I_RMS(COUT)= I_O(MAX)

•

V

IN(MIN)

Note that the ripple current ratings from capacitor manu-

facturers are often based on only 2000 hours of life. This

makes it advisable to further derate the capacitor or to

choose a capacitor rated at a higher temperature than

required. Several capacitors may also be placed in parallel

to meet size or height requirements in the design.

For a 1% contribution to the total ripple voltage, the ESR

of the output capacitor can be determined using the

following equation:

Manufacturers such as Nichicon, United Chemicon and

Sanyoshouldbeconsideredforhighperformancethrough-

hole capacitors. The OS-CON semiconductor dielectric

capacitor available from Sanyo has the lowest product of

ESR and size of any aluminum electrolytic, at a somewhat

higher price.

0.01• V_O

I_D(PEAK)

ESR_COUT

where:

≤

⎛

⎞

χ

2

V_O+ V_D

⎛

⎞

⎟

⎠

I_D(PEAK)= 1+

•I

O(MAX)

•

+ 1

⎜

⎟

In surface mount applications, multiple capacitors may

have to be placed in parallel in order to meet the ESR or

RMS current handling requirements of the application.

Aluminum electrolytic and dry tantalum capacitors are

both available in surface mount packages. In the case of

tantalum, it is critical that the capacitors have been surge

⎝

V

⎝

⎠

IN(MIN)

For the bulk C component, which also contributes 1% to

the total ripple:

I_O(MAX)

0.01• V_O• f

C_OUT

≥

tested for use in switching power supplies. An excellent

18711fa

27

LTC1871-1

W U U

U

APPLICATIO S I FOR ATIO

which is typically close to V_IN(MAX). The ripple current

through C1 is:

choice is AVX TPS series of surface mount tantalum. Also,

ceramic capacitors are now available with extremely low

ESR, ESL and high ripple current ratings.

V_O+ V_D

I_RMS(C1)= I_O(MAX)

•

SEPIC Converter: Input Capacitor Selection

V

IN(MIN)

The input capacitor of a SEPIC converter is less critical

than the output capacitor due to the fact that an inductor

is in series with the input and the input current waveform

istriangularinshape. Theinputvoltagesourceimpedance

determinesthesizeoftheinputcapacitorwhichistypically

in the range of 10μF to 100μF. A low ESR capacitor is

recommended, although it is not as critical as for the

output capacitor.

The value chosen for the DC coupling capacitor normally

starts with the minimum value that will satisfy 1) the RMS

current requirement and 2) the peak voltage requirement

(typically close to V_IN). Low ESR ceramic and tantalum

capacitors work well here.

SEPIC Converter Design Example

Thedesignexamplegivenherewillbeforthecircuitshown

in Figure 18. The input voltage is 5V to 15V and the output

is 12V at a maximum load current of 1.5A (2A peak).

The RMS input capacitor ripple current for a SEPIC con-

verter is:

1

1. The duty cycle range is:

I_RMS(CIN)

=

• ΔI_L

12

⎛

⎜

V_O+ V_D

⎞

⎟

D =

= 45.5% to 71.4%

Please note that the input capacitor can see a very high

surge current when a battery is suddenly connected to the

input of the converter and solid tantalum capacitors can

fail catastrophically under these conditions. Be sure to

specify surge-tested capacitors!

⎝ V + V_O+ V_D⎠

IN

2. The operating mode chosen is pulse skipping, so the

MODE/SYNC pin is shorted to INTV_CC.

3. The operating frequency is chosen to be 300kHz to

reduce the size of the inductors; the resistor from the

FREQ pin to ground is 80k.

SEPIC Converter: Selecting the DC Coupling Capacitor

The coupling capacitor C1 in Figure 16 sees nearly a

rectangular current waveform as shown in Figure 17.

Duringtheswitchoff-timethecurrentthroughC1isI_O(V_O/

V_IN) while approximately –I_Oflows during the on-time.

This current waveform creates a triangular ripple voltage

on C1:

4. Aninductorripplecurrentof40%ischosen,sothepeak

input current (which is also the minimum saturation

current) is:

χ

V_O+ V_D

⎛

⎞

⎟

⎠

I_L1(PEAK)= 1+

•I

O(MAX)

•

⎜

⎝

2

V

IN(MIN)

I_O(MAX)

V_O

0.4

2

12 + 0.5

⎛

⎝

⎞

⎟

⎠

ΔV_C1(P−P)

=

•

= 1+

•1.5 •

= 4.5A

⎜

C1• f V + V_O+ V_D

IN

5

The maximum voltage on C1 is then:

The inductor ripple current is:

D_MAX

ΔV_C1(P−P)

V_C1(MAX)= V +

ΔI_L= χ •I_O(MAX)

•

IN

1–D_MAX

2

0.714

1– 0.714

= 0.4 •1.5 •

= 1.5A

18711fa

28

LTC1871-1

W U U

APPLICATIO S I FOR ATIO

U

And so the inductor value is:

V_SENSE(MAX)

1

R_DS(ON)

≤

•

χ

I_O(MAX)

⎛

⎜

⎝

⎞

⎠

⎛

⎞

V

V_O+ V_D

5

IN(MIN)

1+

• ρ

T

⎟

+ 1

L =

•D_MAX

=

• 0.714 = 4μH

⎜

⎟

2

V

2 • ΔI_L• f

2 •1.5 • 300k

⎝

⎠

IN(MIN)

0.12

1.5 1.2 •1.5 ⎛

1

•

1

T

he component chosen is a BH Electronics BH510-

=

•

= 12.7mΩ

12.5

5

⎞

⎠

1007, which has a saturation current of 8A.

+ 1

⎟

⎜

⎝

5. With an minimum input voltage of 5V, only logic-level

power MOSFETs should be considered. Because the

maximum duty cycle is 71.4%, the maximum SENSE

pin threshold voltage is reduced from its low duty cycle

typical value of 150mV to approximately 120mV.

Assuming a MOSFET junction temperature of 125°C,

the room temperature MOSFET R_DS(ON)should be less

than:

For a SEPIC converter, the switch BV_DSSrating must be

greater than V_IN(MAX)+ V_O, or 27V. This comes close to

an IRF7811W, which is rated to 30V, and has a maxi-

mumroomtemperatureR_DS(ON)of12mΩatV_GS= 4.5V.

V

IN

4.5V to 15V

•

R3

1M

C

DC

L1*

10μF

25V

1

2

10

9

X5R

RUN

SENSE

D1

V

OUT

12V

I

V

IN

TH

1.5A

C

OUT1

(2A PEAK)

R

+

LTC1871-1

INTV

C

47μF

20V

×2

33k

3

4

5

8

7

6

C

OUT2

FB

CC

C

10μF

25V

X5R

×2

R1

12.1k

1%

C1

FREQ

GATE

GND

M1

6.8nF

L2*

+

C

R2

105k

1%

R

T

80.6k

1%

VCC

MODE/SYNC

C

IN

47μF

•

C

4.7μF

C2

47pF

X5R

GND

1871 F018a

C

, C

:

KEMET T495X476K020AS

L1, L2: BH ELECTRONICS BH510-1007 (*COUPLED INDUCTORS)

M1: INTERNATIONAL RECTIFIER IRF7811W

IN OUT1

, C

: TAIYO YUDEN TMK432BJ106MM

DC OUT2

D1:

INTERNATIONAL RECTIFIER 30BQ040

Figure 18a. 4.5V to 15V Input, 12V/2A Output SEPIC Converter

100

95

V

= 12V

IN

90

85

80

75

70

65

60

55

50

45

V

= 4.5V

IN

V

= 15V

IN

V

= 12V

O

MODE = INTV

CC

0.001

0.01

0.1

1 10

OUTPUT CURRENT (A)

1871 F18b

Figure 18b. SEPIC Efficiency vs Output Current

18711fa

29

LTC1871-1

W U U

U

APPLICATIO S I FOR ATIO

V_IN= 4.5V

V_IN= 15V

V_OUT= 12V

V

_OUT= 12V

V_OUT(AC)

200mV/DIV

V_OUT(AC)

200mV/DIV

I_OUT

0.5A/DIV

I_OUT

0.5A/DIV

50μs/DIV

1871 F19a

50μs/DIV

1871 F19b

Figure 19. LTC1871-1 SEPIC Converter Load Step Response

6. The diode for this design must handle a maximum DC

output current of 2A and be rated for a minimum

reverse voltage of V_IN+ V_OUT, or 27V. A 3A, 40V diode

from International Rectifier (30BQ040) is chosen for its

small size, relatively low forward drop and acceptable

reverse leakage at high temp.

Checktheoutputripplewithasingleoscilloscopeprobe

connected directly across the output capacitor termi-

nals, where the HF switching currents flow.

8. The choice of an input capacitor for a SEPIC converter

dependsontheimpedanceofthesourcesupplyandthe

amount of input ripple the converter will safely tolerate.

For this particular design and lab setup, a single 47μF

Kemet tantalum capacitor (T495X476K020AS) is ad-

equate. As with the output node, check the input ripple

with a single oscilloscope probe connected across the

input capacitor terminals. If any HF switching noise is

observed it is a good idea to decouple the input with a

low ESR, X5R ceramic capacitor as close to the V_INand

GND pins as possible.

7. The output capacitor usually consists of a high valued

bulk C connected in parallel with a lower valued, low

ESR ceramic. Based on a maximum output ripple

voltage of 1%, or 120mV, the bulk C needs to be greater

than:

I_OUT(MAX)

0.01• V_OUT• f

1.5A

C_OUT

≥

=

9. The DC coupling capacitor in a SEPIC converter is

chosen based on its RMS current requirement and

must be rated for a minimum voltage of V_INplus the AC

ripple voltage. Start with the minimum value which

satisfies the RMS current requirement and then check

theripplevoltagetoensurethatitdoesn’texceedtheDC

rating.

= 41μF

0.01•12V • 300kHz

The RMS ripple current rating for this capacitor needs

to exceed:

V_O

I_RMS(COUT)≥I_O(MAX)

•

=

V

IN(MIN)

12V

5V

V_O+ V_D

1.5A •

= 2.3A

I_RMS(CI)≥I_O(MAX)

•

V

IN(MIN)

12V + 0.5V

To satisfy this high RMS current demand, two 47μF

Kemet capacitors (T495X476K020AS) are required. As

a result, the output ripple voltage is a low 50mV to

60mV. In parallel with these tantalums, two 10μF, low

ESR (X5R) Taiyo Yuden ceramic capacitors

(TMK432BJ106MM) are added for HF noise reduction.

= 1.5A •

= 2.4A

5V

For this design a single 10μF, low ESR (X5R) Taiyo

Yuden ceramic capacitor (TMK432BJ106MM) is

adequate.

18711fa

30

LTC1871-1

U

TYPICAL APPLICATIO S

2.5V to 3.3V Input, 5V/2A Output Boost Converter

V

IN

2.5V to 3.3V

L1

1.8μH

D1

1

10

9

RUN

SENSE

V

5V

2A

OUT

2

I

V

IN

TH

C

OUT1

R

+

LTC1871-1

INTV

C

150μF

6.3V

×2

22k

3

4

5

8

7

6

C

OUT2

FB

CC

C

6.8nF

10μF

6.3V

X5R

×2

R1

12.1k

1%

C1

FREQ

GATE

GND

M1

C

R2

37.4k

1%

R

80.6k

1%

+

VCC

C

MODE/SYNC

T

IN

C

C2

47pF

4.7μF

47μF

X5R

6.3V

GND

1871 TA01a

C

:

SANYO POSCAP 6TPA47M

: SANYO POSCAP 6TPB150M

: TAIYO YUDEN JMK316BJ106ML

TAIYO YUDEN LMK316BJ475ML

D1: INTERNATIONAL RECTIFIER 30BQ015

L1: TOKO DS104C2 B952AS-1R8N

M1: SILICONIX/VISHAY Si9426

IN

OUT1

OUT2

VCC

:

Output Efficiency at 2.5V and 3.3V Input

100

95

90

85

80

75

70

65

60

55

50

0.001

0.01

0.1

1

10

OUTPUT CURRENT (A)

1871 TA01b

18711fa

31

LTC1871-1

TYPICAL APPLICATIO S

U

18V to 27V Input, 28V Output, 400W 2-Phase, Low Ripple, Synchronized RF Base Station Power Supply (Boost)

V

IN

18V to 27V

R1

93.1k

1%

L1

5.6μH

L2

R2

8.45k

1%

5.6μH

C

+

IN1

330μF

1

2

10

9

50V

RUN

SENSE

D1

I

TH

V

IN

C

C1

47pF

LTC1871-1

INTV

C

OUT1

3

4

5

8

7

6

2.2μF

35V

X5R

×3

C

+

FB

OUT2

CC

330μF

FREQ

GATE

GND

M1

50V

C

IN2

R

150k

5%

C

VCC1

MODE/SYNC

T1

2.2μF

35V

C

R

FB1

S1

4.7μF

47pF

0.007Ω

X5R

1W

GND

C

*

OUT5

330μF

50V

+

EXT CLOCK

C

*

OUT6

×4

L3

5.6μH

L4

INPUT (200kHz)

2.2μF

35V

5.6μH

X5R

1

2

10

9

RUN

SENSE

D2

V

OUT

28V

14A

I

TH

V

IN

L5*

0.3μH

LTC1871-1

INTV

C

OUT3

R

C

C2

3

4

5

8

7

6

2.2μF

35V

X5R

×3

C

+

*L5, C

OUT6

AND

FB

22k

OUT4

OUT5

ARE AN

CC

47pF

330μF

C

FB2

C

FREQ

GATE

GND

M2

50V

47pF

R3

OPTIONAL SECONDARY

FILTER TO REDUCE

C

IN3

R4

261k

1%

R

150k

5%

MODE/SYNC

C

T2

VCC2

2.2μF

35V

C

6.8nF

R

S2

OUTPUT RIPPLE FROM

<500mV TO <100mV

C3

12.1k

1%

4.7μF

0.007Ω

P-P P-P

X5R

1W

1871 TA04

C

:

SANYO 50MV330AX

TAIYO YUDEN GMK325BJ225MN

SANYO 50MV330AX

TAIYO YUDEN GMK325BJ225MN

TAIYO YUDEN LMK316BJ475ML

L1 TO L4: SUMIDA CEP125-5R6MC-HD

L5: SUMIDA CEP125-0R3NC-ND

D1, D2: ON SEMICONDUCTOR MBR2045CT

M1, M2: INTERNATIONAL RECTIFIER IRLZ44NS

IN1

:

IN2, 3

OUT2, 4, 5

OUT1, 3, 6

:

VCC1, 2

5V to 12V Input, ±12V/0.2A Output SEPIC Converter with Undervoltage Lockout

V

IN

5V to 12V

•

R1

127k

1%

C

DC1

R2

54.9k

1%

L1*

4.7μF

16V

1

2

10

9

X5R

RUN

SENSE

D1

V

OUT1

12V

I

V

IN

TH

0.4A

R

C

22k

LTC1871-1

INTV

C

OUT1

3

4

5

8

7

6

4.7μF

16V

X5R

×3

FB

CC

C

R4

127Ω

1%

C1

L2*

FREQ

GATE

GND

M1

6.8nF

C

IN2

C

IN1

VCC

MODE/SYNC

+

R3

1.10k

1%

R

T

60.4k

1%

1μF

16V

X5R

47μF

16V

•

4.7μF

10V

C

C2

100pF

R

S

0.02Ω

AVX

X5R

GND

V

C

OUT2

C

DC2

4.7μF

16V

X5R

×3

NOTE:

D1, D2: MBS120T3

L1 TO L3: COILTRONICS VP1-0076 (*COUPLED INDUCTORS)

M1: SILICONIX/VISHAY Si4840

4.7μF

+

–

D2

L3*

1. V UVLO = 4.47V

IN

16V

X5R

V

UVLO = 4.14V

IN

OUT2

•

–12V

0.4A

1871 TA03

18711fa

32

LTC1871-1

U

TYPICAL APPLICATIO S

4.5V to 28V Input, 5V/2A Output SEPIC Converter with Undervoltage Lockout and Soft-Start

V

IN

4.5V to 28V

R1

115k

1%

•

C

DC

2.2μF

25V

X5R

×3

R2

54.9k

1%

L1*

C1

4.7nF

1

2

10

9

RUN

SENSE

D1

V

OUT

5V

I

TH

V

IN

2A

(3A TO 4A PEAK)

R

+

LTC1871-1

INTV

C

OUT1

12k

3

4

5

8

7

6

330μF

FB

CC

C

6.3V

OUT2

R4

49.9k

1%

C

C1

22μF

6.3V

X5R

FREQ

GATE

GND

M1

L2*

8.2nF

C

IN1

VCC

+

C

IN2

R3

154k

1%

R

T

162k

1%

MODE/SYNC

4.7μF

10V

2.2μF

35V

•

C

47pF

22μF

C2

35V

X5R

GND

1871 TA02a

R5

100Ω

C2

1μF

NOTES:

1. V UVLO = 4.17V

+

–

Q1

X5R

IN

V

R6

750Ω

UVLO = 3.86V

IN

2. SOFT-START dV /dt = 5V/6ms

OUT

C

, C : TAIYO YUDEN GMK325BJ225MN

D1:

INTERNATIONAL RECTIFIER 30BQ040

IN1 DC

:

AVX TPSE226M035R0300

SANYO 6TPB330M

TAIYO YUDEN JMK325BJ226MN

LMK316BJ475ML

L1, L2: BH ELECTRONICS BH510-1007 (*COUPLED INDUCTORS)

IN2

OUT1

OUT2

:

M1:

Q1:

SILICONIX/VISHAY Si4840

PHILIPS BC847BF

:

VCC

Soft-Start

Load Step Response at V_IN= 4.5V

V_OUT

100mV/DIV

(AC)

V_OUT

1V/DIV

2.2A

I_OUT

1A/DIV

(DC)

0.5A

1ms/DIV

1871 TA02b

250μs/DIV

1871 TA02c

V_OUT

100mV/DIV

(AC)

2.2A

I_OUT

1A/DIV

(DC)

0.5A

250μs/DIV

1871 TA02d

18711fa

33

LTC1871-1

U

TYPICAL APPLICATIO S

5V to 15V Input, –5V/5A Output Positive-to-Negative Converter with Undervoltage Lockout and Level-Shifted Feedback

V

IN

5V to 15V

V

–5V

5A

OUT

•

R1

154k

1%

R2

68.1k

1%

L1*

L2*

C1

1nF

1

2

10

9

RUN

SENSE

C

OUT

I

V

IN

TH

100μF

6.3V

X5R

×2

C

22μF

25V

X7R

M1

DC

LTC1871-1

INTV

3

4

5

8

7

6

R

C

FB

CC

10k

FREQ

GATE

GND

C

C2

MODE/SYNC

330pF

D1

C

IN

VCC

R

80.6k

1%

T

4.7μF

10V

47μF

16V

C

10nF

C1

X5R

GND

R4

10k

1%

C2

10nF

R5

40.2k

1%

R3

10k

1%

6

–

4

1

LT1783

2

+

3

1871 TA05

C

:

TDK C5750X5R1C476M

TDK C5750X7R1E226M

: TDK C5750X5R0J107M

: TAIYO YUDEN LMK316BJ475ML

D1:

ON SEMICONDUCTOR MBRB2035CT

IN

C

:

L1, L2: COILTRONICS VP5-0053 (*3 WINDINGS IN PARALLEL

FOR THE PRIMARY, 3 IN PARALLEL FOR SECONDARY)

DC

OUT

VCC

M1:

INTERNATIONAL RECTIFIER IRF7822

18711fa

34

LTC1871-1

U

PACKAGE DESCRIPTIO

MS Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661)

0.889 ± 0.127

(.035 ± .005)

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

0.497 ± 0.076

(.0196 ± .003)

REF

0.50

0.305 ± 0.038

(.0120 ± .0015)

TYP

(.0197)

10 9

8

7 6

BSC

RECOMMENDED SOLDER PAD LAYOUT

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

4.90 ± 0.152

(.193 ± .006)

DETAIL “A”

0.254

(.010)

0° – 6° TYP

GAUGE PLANE

1

2

3

4 5

0.53 ± 0.152

(.021 ± .006)

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 ± 0.0508

(.004 ± .002)

0.50

(.0197)

BSC

MSOP (MS) 0307 REV E

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

18711fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection ofits circuits as described herein will notinfringe onexisting patent rights.

35

LTC1871-1

TYPICAL APPLICATIO S

U

High Power SLIC Supply with Undervoltage Lockout

(Also See the LTC3704 Data Sheet)

GND

•

4

C3

D2

10BQ060

10μF

25V

X5R

V

IN

7V TO 12V

R1

49.9k

1%

R2

150k

1%

V

OUT1

–24V

200mA

C

R

1nF

IN

•

5

+

C4

D3

10BQ060

220μF

16V

C

OUT

10μF

25V

X5R

T1*

3.3μF

1, 2, 3

TPS

100V

C

•

C2

100pF

RUN

SENSE

I

V

IN

TH

•

6

D4

C5

LTC1871-1

C2

10BQ060

10μF

25V

X5R

R

C

FB

INTV

CC

4.7μF

50V

82k

FREQ

GATE

GND

IRL2910

V

OUT2

X5R

–72V

C

C1

+

C1

4.7μF

X5R

MODE/SYNC

R

200mA

1nF

R

F2

196k

1%

T

F1

10k

1%

R

120k

S

f = 200kHz

0.012Ω

6

–

4

*COILTRONICS VP5-0155

(PRIMARY = 3 WINDINGS IN PARALLEL)

10k

1

LT1783

2

+

3

C8

0.1μF

1871 TA06

RELATED PARTS

PART NUMBER

LT^®1619

DESCRIPTION

COMMENTS

Current Mode PWM Controller

Current Mode DC/DC Controller

300kHz Fixed Frequency, Boost, SEPIC, Flyback Topology

LTC1624

SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC Design;

V

Up to 36V

IN

LTC1700

LTC1871

LTC1871-7

LTC1872

LT1930

No R

Synchronous Step-Up Controller

Up to 95% Efficiency, Operation as Low as 0.9V Input

SENSE

Wide Input Range Controller

No R

, 5V Gate Drive, Current Mode Control

SENSE

, 7V Gate Drive, Current Mode Control

SENSE

Wide Input Range Controller

SOT-23 Boost Controller

Delivers Up to 5A, 550kHz Fixed Frequency, Current Mode

1.2MHz, SOT-23 Boost Converter

Inverting 1.2MHz, SOT-23 Converter

1A/2A 3MHz Synchronous Boost Converters

Positive-to-Negative DC/DC Controller

2-Phase Step-Up DC/DC Controller

Up to 34V Output, 2.6V ≤ V ≤ 16V, Miniature Design

IN

LT1931

Positive-to-Negative DC/DC Conversion, Miniature Design

LTC3401/LTC3402

LTC3704

LT3782

Up to 97% Efficiency, Very Small Solution, 0.5V ≤ V ≤ 5V

IN

No R

, Current Mode Control, 50kHz to 1MHz

SENSE

6V ≤ V ≤ 40V; 4A Gate Drive, 150kHz to 500kHz

IN

18711fa

LT 0807 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

36

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1871IMS#TR-1
厂家：	Linear
描述：	IC SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO10, PLASTIC, MSOP-10, Switching Regulator or Controller 开关光电二极管
文件：	总36页 (文件大小：354K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1871IMS#TR-1 [Linear]

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