LTC1875EGN_技术文档

LTC1875

15µA Quiescent Current

1.5A Monolithic Synchronous

Step-Down Regulator

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FEATURES

DESCRIPTIO

■

High Efficiency: Up to 95%

The LTC^®1875 is a high efficiency 1.5A monolithic syn-

chronous buck regulator using a constant frequency,

current mode architecture. Operating supply current is

only 15µA with no load and drops to <1µA in shutdown.

The input supply voltage range of 2.65V to 6V makes the

LTC1875 ideally suited for single Li-Ion battery-powered

applications. 100% duty cycle provides low dropout op-

eration, extending battery life in portable systems.

■

Low Quiescent Current: Only 15µA with No Load

■

550kHz Constant Frequency Operation

■

2.65V to 6V Input Voltage Range

■

V_OUTfrom 0.8V to V_IN, I_OUTto 1.5A

■

True PLL Frequency Locking from 350kHz to 750kHz

■

Power Good Output Voltage Monitor

■

Low Dropout Operation: 100% Duty Cycle

Burst Mode^®or Pulse Skipping Operation

■

The switching frequency is internally set to 550kHz, allow-

ing the use of small surface mount inductors and capaci-

tors. For noise sensitive applications, the LTC1875 can be

externally synchronized from 350kHz to 750kHz. Burst

Mode operation is inhibited during synchronization or

when the SYNC/MODE pin is pulled low.

■

Current Mode Operation for Excellent Line and Load

Transient Response

■

Shutdown Mode Draws <1µA Supply Current

■

±2% Output Voltage Accuracy

■

Overcurrent and Overtemperature Protected

■

Available in 16-Lead SSOP Package

The internal synchronous switch increases efficiency and

eliminates the need for an external Schottky diode. Low

output voltages are easily supported with a 0.8V feedback

reference voltage. The LTC1875 is available in a 16-lead

SSOP package.

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APPLICATIO S

■

Portable Computers

■

Portable Instruments

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

Wireless Modems

Burst Mode is a registered trademark of Linear Technology Corporation.

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TYPICAL APPLICATIO

High Efficiency Step-Down Converter

Efficiency vs Output Load Current

V

IN

2.65V TO 6V

100

C

IN

V

= 3.6V

IN

22µF

95

90

85

80

75

70

65

60

55

SV

RUN/SS

IN

PV

IN

L1

V

= 4.2V

IN

SYNC/MODE SWP

LTC1875

6.8µH

V

*

V

IN

= 6V

OUT

3.3V

PGOOD

SWN

+

C

OUT

47µF

150k

I

PGND

TH

88.7k

47pF

220pF

V

FB

Burst Mode OPERATION

= 3.3V

SGND

V

OUT

28.0k

L = 6.8µH

10 100

OUPUT CURRENT (mA)

1875 TA01

0.1

1

1000

C

: TAIYO YUDEN CERAMIC JMK325BJ226MM

IN

: SANYO POSCAP 6TPA47M

OUT

1875 TA01a

L1: TOKO 646CY-6R8M

*V

CONNECTED TO V (MINUS SWITCH AND L1 VOLTAGE DROP) FOR 2.65V < V < 3.3V

OUT

I

N

I

N

1875f

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LTC1875

W W U W

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ABSOLUTE MAXIMUM RATINGS

PACKAGE/ORDER INFORMATION

(Note 1)

ORDER PART

Input Supply Voltage .................................. –0.3V to 7V

I_TH, PLL_LPF Voltages............................. –0.3V to 2.7V

RUN/SS, V_FBVoltages ............................... –0.3V to V_IN

SYNC/MODE Voltage ................................. –0.3V to V_IN

(V_PVIN– V_SWP) Voltage............................... –0.3V to 7V

V_SWNVoltage .............................................. –0.3V to 7V

P-Channel Switch Source Current (DC) .................... 2A

N-Channel Switch Sink Current (DC) ........................ 2A

Peak Switching Sink and Source Current ................. 3A

Operating Ambient Temperature Range

(Note 2) ............................................. –40°C to 85°C

Junction Temperature (Note 3, 6)........................ 125°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

TOP VIEW

NUMBER

SGND

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

PLL_LPF

SYNC/MODE

PGOOD

RUN/SS

LTC1875EGN

V

FB

I

SV

IN

TH

SWP1

SWN1

SWP2

SWN2

PGND2

GN PART

MARKING

PGND1

PV

IN1

PV

IN2

1875

GN PACKAGE

16-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 110°C/ W, θ_JC= 40°C/ W

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are T_A= 25°C. V_IN= 3.6V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I

Feedback Current

Regulated Output Voltage

(Note 4)

●

8

60

nA

VFB

V

(Note 4) 0°C ≤ T ≤ 85°C

(Note 4) –40°C ≤ T ≤ 85°C

0.784

0.740

0.80

0.816

0.840

V

FB

A

●

A

∆V

Overvoltage Trip Limit with Respect to V

∆V

OVL

∆V

UVL

= V

– V

20

60

110

0.25

mV

OVL

FB

OVL

FB

Undervoltage Trip Limit with Respect to V

Reference Voltage Line Regulation

Output Voltage Load Regulation

= V – V

FB UVL

UVL

FB

∆V /V

V

= 2.65V to 6V (Note 4)

IN

0.05

%/V

FB FB

V

Measured in Servo Loop, V

= 0.9V to 1.2V

= 1.6V to 1.2V

●

0.1

–0.1

0.6

–0.6

%

LOADREG

ITH

V

Input Voltage Range

●

2.65

6

V

IN

I

Input DC Bias Current

Pulse Skipping Mode

Burst Mode Operation

Shutdown

(Note 5)

2.65V < V < 6V, V

Q

= 0V, I = 0A

OUT

270

15

0

365

22

1

µA

IN

SYNC/MODE

V

= V , I

IN

= 0A

SYNC/MODE

IN OUT

= 0V, V = 6V

RUN

f

SYNC Capture Range

Oscillator Frequency

350

495

750

605

kHz

SYNC

OSC

V

≥ 0.7V

= 0V

550

80

kHz

FB

I

Phase Detector Output Current

Sinking Capability

Sourcing Capability

PLLLPF

f

< f

> f

●

3

–3

10

–10

20

–20

µA

PLLIN

PPLIN

OSC

SOC

R

of P-Channel FET

of N-Channel FET

I

= 100mA, V = 5V

0.28

0.35

0.4

Ω

A

PFET

DS(ON)

SW

IN

= –100mA, V = 5V

NFET

IN

I

Peak Inductor Current

SW Leakage

V

= 0.7V, Duty Cycle < 35%, V = 3V

1.6

0.2

2.15

2.75

±2.5

1.5

PK

LSW

FB

IN

= 0V, V = 0V or 6V, V = 6V

±0.01

1.0

µA

V

RUN

SW

IN

V

SYNC/MODE Threshold

SYNC/MODE Leakage Current

●

SYNC/MODE

I

±0.01

±1

µA

1875f

2

LTC1875

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are T_A= 25°C. V_IN= 3.6V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

0.7

MAX

1.5

UNITS

V

RUN Threshold

RUN Input Current

V

Ramping Up

= 0V

●

0.2

RUN

I

±0.01

±1

µA

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 4: The LTC1875 is tested in a feedback loop which servos V to the

FB

balance point for the error amplifier (V = 1.2V)

ITH

Note 2: The LTC1875E is guaranteed to meet specified performance from

0°C to 70°C. Specifications over the –40°C to 85°C operating temperature

range are assured by design, characterization and correlation with

statistical process controls.

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency.

Note 6: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 3: T is calculated from the ambient temperature T and power

J

A

dissipation P according to the following formula:

D

LTC1875: T = T + (P • 110°C/W)

J

A

D

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TYPICAL PERFOR A CE CHARACTERISTICS

Oscillator Frequency

vs Supply Voltage

Oscillator Frequency

R_DS(ON)vs Temperature

vs Temperature

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

595

575

555

535

515

495

580

570

560

550

540

530

V

= 3.6V

SYNCHRONOUS SWITCH

MAIN SWITCH

IN

V

= 3V

IN

V

= 5V

IN

V

= 3V

50

V

= 5V

IN

–50 –25

0

25

75 100 125

–50 –25

0

25

50

75 100 125

0

2

4

6

8

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

1875 G01

1875 G02

1875 G03

Switch Leakage Current

vs Temperature

DC Supply Current

vs Temperature

R_DS(ON)vs Input Voltage

10

9

8

7

6

5

4

3

2

1

0

300

250

200

150

100

50

0.6

0.5

0.4

0.3

0.2

0.1

0

V

= 7V

V

= 3.6V

IN

RUN = 0V

SYNCHRONOUS SWITCH

PULSE SKIPPING MODE

MAIN SWITCH

SYNCHRONOUS SWITCH

BURST MODE

0

–50

0

50

100 125

–50

0

50

100 125

0

2

4

6

8

TEMPERATURE (°C)

INPUT VOLTAGE (V)

1875 G06

1875 G04

1875 G05

1875f

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LTC1875

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TYPICAL PERFOR A CE CHARACTERISTICS

Reference Voltage vs

Temperature

Output Voltage vs Load Current

1.84

805

804

803

802

801

800

799

798

797

796

795

V

= 6V

IN

1.82

1.80

1.78

1.76

1.74

Burst Mode OPERATION

1.72

V

= 3.6V

IN

L = 4.7µH

500

LOAD CURRENT (mA)

1.70

0

1000

1500

2000

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

1875 G07

1875 G13

Efficiency vs Output Current

95

90

85

80

75

70

65

60

55

50

100

90

80

70

60

50

40

30

20

10

0

V

= 4.2V

IN

V

= 3.6V

V

= 3V

IN

V

= 3.6V

IN

V

= 4.2V

IN

V

= 3.6V

IN

V

= 6V

IN

V

= 4.2V

V

IN

= 1.8V

OUT

L = 4.7µH

Burst Mode OPERATION

PULSE SKIPPING MODE

V

= 1.8V

OUT

L = 4.7µH

Burst Mode OPERATION

0.1

1

10

100

1000

0.1

1

10

100

1000

OUTPUT CURRENT (mA)

1875 G14

1875 G15

Efficiency vs Input Voltage

Load Step (Burst Mode Operation)

100

95

90

85

80

75

70

65

60

55

50

10mA

100mA

V_OUT

100mV/DIV

1mA

I_L

1A/DIV

I_TH

1V/DIV

0.1mA

V

= 2.5V

L = 6.8µH

Burst Mode OPERATION

OUT

50µs/DIV

C_IN= 22µF

C_OUT= 47µF

1875 G08

V_IN= 3.6V

_OUT= 1.5V

L = 6.8µH

V

I_LOAD= 200mA to 1700mA

2

3

4

5

6

INPUT VOLTAGE (V)

1875 G16

1875f

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LTC1875

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TYPICAL PERFOR A CE CHARACTERISTICS

Load Step Response (Pulse

Skipping Mode)

Pulse Skipping Mode Operation

I_L

V_OUT

100mV/DIV

200mA/DIV

V_OUT

100mV/DIV

I_L

1A/DIV

I_TH

1V/DIV

SW

5V/DIV

1µs/DIV

C_IN= 22µF

C_OUT= 47µF

_LOAD= 50mA

1875 G10

100µs/DIV

C_IN= 22µF

C_OUT= 47µF

1875 G09

V_IN= 4.2V

V_OUT= 2.5V

L = 6.8µH

V_IN= 3.6V

_OUT= 1.5V

L = 6.8µH

V

I

I_LOAD= 200mA to 1700mA

Soft-Start with Shorted Output

Burst Mode Operation

I_L

200mA/DIV

I_VIN

500mA/DIV

V_OUT

100mV/DIV

RUN/SS

1V/DIV

SW

5V/DIV

5ms/DIV

1875 G12

25µs/DIV

C_IN= 22µF

C_OUT= 47µF

I_LOAD= 50mA

1875 G11

V_IN= 3.6V

V_OUT= 0V

L = 6.8µH

C_IN= 22µF

C_OUT= 47µF

I_LOAD= 0A

V_IN= 4.2V

V_OUT= 2.5V

L = 6.8µH

1875f

5

LTC1875

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PI FU CTIO S

PV_IN1, PV_IN2(Pins 8, 9): Power Supply Pins for the

Internal Drivers and Switches. These pins should always

be tied together.

SGND (Pin 1): Signal Ground Pin.

RUN/SS (Pin 2): Combination of Soft-Start and Run

ControlInputs.Forcingthispinbelow0.7Vshutsdownthe

device. In shutdown all functions are disabled and device

draws zero supply current. For the proper operation of the

part, force this pin above 2.5V. Do not leave this pin

floating. Soft-start can be accomplished by raising the

voltage on this pin gradually with an RC circuit.

SV_IN(Pin 13): Signal Power Supply Pin.

PGOOD (Pin 14): Power Good Indicator Pin. Power good

is an open-drain logic output. The PGOOD pin is pulled to

ground when the voltage on the V_FBpin is not within

±7.5% of its nominally regulated potential. This pin re-

quires a pull-up resistor for power good indication. Power

good indication works in all modes of operation.

V

_FB(Pin 3): Feedback Pin. Receives the feedback voltage

from an external resistor divider across the output.

SYNC/MODE (Pin 15): External Clock Synchronization

and Mode Select Input. To synchronize, apply an external

clock with a frequency between 350kHz and 750kHz. To

select Burst Mode operation, tie pin to SV_IN. Grounding

this pin selects pulse skipping mode. Do not leave this pin

floating.

I_TH(Pin 4): Error Amplifier Compensation Point. The

current output increases with this control voltage. Nomi-

nal voltage range for this pin is 0.5V to 1.8V.

SWP1, SWP2 (Pins 5, 12): Upper Switch Nodes. These

pins connect to the drains of the internal main PMOS

switches and should always be connected together

externally.

PLL_LPF (Pin 16): Output of the Phase Detector and

Control Input of Oscillator. Connect a series RC lowpass

networkfromthispintogroundifexternallysynchronized.

If unused, this pin may be left open.

SWN1, SWN2 (Pins 6, 11): Lower Switch Nodes. These

pins connect to the drains of the internal synchronous

NMOS switches and should always be connected together

externally.

PGND1,PGND2(Pins7,10):PowerGroundPins.Ground

pins for the internal drivers and switches. These pins

should always be tied together.

1875f

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LTC1875

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BLOCK DIAGRA

1875f

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LTC1875

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OPERATIO

(Refer to Block Diagram)

Main Control Loop

the I_THvoltage drops below approximately 0.45V, the

BURSTcomparatortrips,turningoffbothpowerMOSFETs.

The I_THpin is then disconnected from the output of the EA

amplifier and held 0.65V above ground.

The LTC1875 uses a constant frequency, current mode

step-down architecture. Both the top MOSFET and syn-

chronous bottom MOSFET switches are internal. During

normal operation, the internal top power MOSFET is

turned on each cycle when the oscillator sets the RS latch,

andturnedoffwhenthecurrentcomparator, I_COMP, resets

the RS latch. The peak inductor current at which I_COMP

turns the top MOSFET off is controlled by the voltage on

the I_THpin, which is the output of error amplifier EA. When

the load current increases, it causes a slight decrease in

the feedback voltage, V_FB, relative to the 0.8V internal

reference, which, in turn, causes the I_THvoltage to in-

crease until the average inductor current matches the new

load current. While the top MOSFET is off, the bottom

MOSFET is turned on until either the inductor current

starts to reverse direction or the next clock cycle begins.

In sleep mode, both power MOSFETs are held off and the

internal circuitry is partially turned off, reducing the quies-

cent current to 15µA. The load current is now being

supplied from the output capacitor. When the output

voltage drops, the I_THpin reconnects to the output of the

EA amplifier and the top MOSFET is again turned on and

this process repeats.

Soft-Start/Run Function

The RUN/SS pin provides a soft-start function and a

means to shut down the LTC1875. Soft-start reduces the

inputcurrentsurgebygraduallyincreasingtheregulator’s

maximum output current. This pin can also be used for

power supply sequencing.

Comparator OVDET guards against transient overshoots

>7.5% by turning the main switch off and keeping it off

until the fault is removed.

Pulling the RUN/SS pin below 0.7V shuts down the

LTC1875, which then draws <1µA current from the sup-

ply. This pin can be driven directly from logic circuits as

showninFigure1.Itisrecommendedthatthispinisdriven

to V_INduring normal operation. Note that there is no

current flowing out of this pin. Soft-start action is accom-

plished by connecting an external RC network to the RUN/

SS pin as shown in Figure 1. The LTC1875 actively pulls

the RUN/SS pin to ground under low input supply voltage

conditions.

Burst Mode Operation

The LTC1875 is capable of Burst Mode operation in which

the internal power MOSFETs operate intermittently based

on load demand. To enable Burst Mode operation, simply

tie the SYNC/MODE pin to SV_INor connect it to a logic high

(V_SYNC/MODE> 1.5V). To disable Burst Mode operation

andenablePWMpulseskippingmode, connecttheSYNC/

MODE pin to SGND. In this mode, the efficiency is lower at

lightloadsbutbecomescomparabletoBurstModeopera-

tion when the output load exceeds 100mA. The advantage

of pulse skipping mode is lower output ripple.

V

IN

3.3V OR 5V

D1*

0.32V

R

SS

When the converter is in Burst Mode operation, the peak

current of the inductor is set to approximately 400mA,

even though the voltage at the I_THpin indicates a lower

value. The voltage at the I_THpin drops when the inductor’s

average current is greater than the load requirement. As

RUN/SS

C

SS

*ZETEX BAT54

1875 F01

Figure 1. RUN/SS Pin Interfacing

1875f

8

LTC1875

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OPERATIO

Power Good Indicator

(Refer to Block Diagram)

Low Dropout Operation

Thepowergoodfunctionmonitorstheoutputvoltageinall

modes of operation. Its open-drain output is pulled low

when the output voltage is not within ±7.5% of its nomi-

nally regulated voltage. The feedback voltage is filtered

before it is fed to a power good window comparator in

order to prevent false tripping of the power good signal

during fast transients. The window comparator monitors

the output voltage even in Burst Mode operation. In

shutdown mode, open drain is actively pulled low to

indicate that the output voltage is invalid.

When the input supply voltage decreases toward the

output voltage in a buck regulator, the duty cycle in-

creases toward the maximum on-time. Further reduction

of the supply voltage forces the main switch to remain on

for more than one cycle until it reaches 100% duty cycle.

The output voltage will then be determined by the input

voltage minus the voltage drop across the top MOSFET

and the inductor.

Low Supply Operation

The LTC1875 is designed to operate down to an input

supply voltage of 2.65V although the maximum allowable

output current is reduced at this low voltage. Figure 2

shows the reduction in the maximum output current as a

function of input voltage.

Short-Circuit Protection

When the output is shorted to ground, the frequency of

the oscillator is reduced to about 80kHz, 1/7 the nominal

frequency. This frequency foldback ensures that the in-

ductorcurrenthasmoretimetodecay, therebypreventing

runaway. The oscillator’s frequency will progressively

increase to 550kHz (or to the synchronized frequency)

when V_FBrises above 0.3V.

Another important detail to remember is that at low input

supply voltages, the R_DS(ON)of the P-channel switch

increases. Therefore, the user should calculate the power

dissipation when the LTC1875 is used at 100% duty cycle

with low supply voltage (see Thermal Considerations in

the Applications Information section).

Frequency Synchronization

The LTC1875 can be synchronized to an external clock

source connected to the SYNC/MODE pin. The turn-on of

the top MOSFET is synchronized to the rising edge of the

external clock.

2000

V

= 1.5V

OUT

1500

1000

500

When the LTC1875 is clocked by an external source, Burst

Mode operation is disabled. In this synchronized mode,

whentheoutputloadcurrentisverylow,currentcompara-

tor, I_COMP, mayremaintrippedforseveralcyclesandforce

the main switch to stay off for the same number of cycles.

Increasing the output load slightly allows constant fre-

quency PWM operation to resume.

V

= 3.3V

OUT

V

= 2.5V

OUT

0

2.5

3.5

4.5

5.5

6.5

7.5

Frequency synchronization is inhibited when the feedback

voltage V_FBis below 0.6V. This prevents the external clock

from interfering with the frequency foldback for short-

circuit protection.

INPUT VOLTAGE (V)

1875 F02

Figure 2. Maximum Output Current vs Input Voltage

1875f

9

LTC1875

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OPERATIO

2200

2000

1800

1600

1400

1200

1000

800

Slope Compensation and Inductor Peak Current

V

= 3V

IN

Slope compensation is required in order to prevent sub-

harmonic oscillation at high duty cycles. It is accom-

plished by internally adding a compensating ramp to the

inductor current signal at duty cycles in excess of 40%. As

aresult,themaximuminductorpeakcurrentisreducedfor

duty cycles >40%. This is shown in the decrease of the

inductor peak current as a function of duty cycle graph in

Figure 3.

0

20

40

60

80

100

DUTY CYCLE (%)

1875 F03

Figure 3. Maximum Inductor Peak Current vs Duty Cycle

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APPLICATIO S I FOR ATIO

A reasonable starting point for setting ripple current is

ThebasicLTC1875applicationcircuitisshownonthefirst

page of this data sheet. External component selection is

driven by the load requirement and begins with the selec-

∆I_L= 0.3(I_MAX).

The inductor value also has an effect on Burst Mode

operation. The transition to low current operation begins

when the inductor current peaks fall to approximately

500mA. Lower inductor values (higher ∆I_L) will cause this

to occur at lower load currents, which can cause a dip in

efficiency in the upper range of low current operation. In

Burst Mode operation, lower inductance values will cause

the burst frequency to increase.

tion of L followed by C_INand C_OUT

.

Inductor Value Calculation

The inductor selection will depend on the operating fre-

quency of the LTC1875. The internal nominal frequency is

550kHz, but can be externally synchronized from 350kHz

to 750kHz.

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. However, oper-

ating at a higher frequency results in lower efficiency

because of increased switching losses.

Inductor Selection

The inductor should have a saturation current rating

greater than the peak inductor current set by the current

comparator of LTC1875. Also, consideration should be

given to the resistance of the inductor. Inductor conduc-

tion losses are directly proportional to the DC resistance

of the inductor. Manufacturers sometimes provide maxi-

mum current ratings based on the allowable losses in the

inductor.

Theinductorvaluehasadirecteffectonripplecurrent.The

ripple current ∆I_Ldecreases with higher inductance or

frequency and increases with higher input voltages.

1

V_OUT

V

IN

∆I_L=

V_OUT1–

(1)

f L

( )( )

Suitable inductors are available from Coilcraft, Coiltron-

ics, Dale, Sumida, Toko, Murata, Panasonic and other

manufacturers.

Accepting larger values of ∆I_Lallows the use of smaller

inductors, but results in higher output voltage ripple.

1875f

10

LTC1875

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APPLICATIO S I FOR ATIO

U

C_INand C_OUTSelection

The selection of C_OUTis driven by the required effective

series resistance (ESR). Typically, once the ESR require-

ment is satisfied, the capacitance is adequate for filtering.

The output ripple ∆V_OUTis determined by:

Incontinuousmode,thesourcecurrentofthetopMOSFET

is a trapezoidal waveform of duty cycle V_OUT/V_IN. To

preventlargevoltagetransients, alowESRinputcapacitor

sized for the maximum RMS current must be used. The

maximum RMS input capacitor current is given by:

1

∆V_OUT∆I_LESR +

8fC_OUT

1/2

V

_OUT(V – V_OUT)

[

]

IN

where f = operating frequency, C_OUT= output capacitance

and ∆I_L= ripple current in the inductor. The output ripple

is highest at maximum input voltage since ∆I_Lincreases

with input voltage. For the LTC1875, the general rule for

proper operation is:

I_RMS(CIN)I_OMAX

V

IN

This formula has a maximum at V_IN= 2V_OUT, where

I_RMS= I_OUT/2. This simple worst-case condition is com-

monly used for design because even significant devia-

tions do not offer much relief. Note that the capacitor

manufacturer’s ripple current ratings are often based on

2000 hours of life. This makes it advisable to further

derate the capacitor, or choose a capacitor rated at a

highertemperaturethanrequired.Severalcapacitorsmay

also be paralleled to meet size or height requirements in

the design. Always consult the manufacturer if there are

any questions.

ESR_COUT< 0.125Ω

The choice of using a smaller output capacitance in-

creases the output ripple voltage due to the frequency

dependent term but can be compensated for by using

capacitor(s) of very low ESR to maintain low ripple volt-

age. The I_THpin compensation components can be opti-

mized to provide stable high performance transient

response regardless of the output capacitor selected.

Depending on how the LTC1875 circuit is powered up,

you may need to check for input voltage transients. Input

voltage transients may be caused by input voltage steps

or by connecting the circuit to an already powered up

source such as a wall adapter. The sudden application of

input voltage will cause a large surge of current in the

input leads that will store energy in the parasitic induc-

tanceoftheleads. Thisenergywillcausetheinputvoltage

to swing above the DC level of the input power source and

it may exceed the maximum voltage rating of the input

capacitor and LTC1875.

Manufacturers such as Taiyo Yuden, AVX, Kemet and

Sanyo should be considered for low ESR, high perfor-

mance capacitors. The POSCAP solid electrolytic chip

capacitor available from Sanyo is an excellent choice for

output bulk capacitors due to its low ESR/size ratio. Once

the ESR requirement for C_OUThas been met, the RMS

current rating generally far exceeds the I_RIPPLE(P-P)

requirement.

Output Voltage Programming

The output voltage is set by a resistor divider according to

the following formula:

The easiest way to suppress input voltage transients is to

add a small aluminum electrolytic capacitor in parallel

with the low ESR input capacitor. The selected capacitor

needstohavetherightamountofESRinordertocritically

dampen the resonant circuit formed by the input lead

inductance and the input capacitor. The typical values of

ESR will fall in the range of 0.5Ω to 2Ω and capacitance

will fall in the range of 5µF to 50µF.

R1

R2

V_OUT= 0.8V 1+

(2)

The external resistor divider is connected to the output,

allowing remote voltage sensing as shown in Figure 4.

1875f

11

LTC1875

APPLICATIO S I FOR ATIO

W U U

U

0.8V ≤ V

≤ 6V

R

LP

OUT

2.4V

C

LP

R1

V

FB

PLL_LPF

VCO

R2

LTC1875

SGND

SYNC/

MODE

DIGITAL

PHASE/

FREQUENCY

DETECTOR

1875 F04

Figure 4. Setting the LTC1875 Output Voltage

1875 F06

Phase-Locked Loop and Frequency Synchronization

The LTC1875 has an internal voltage-controlled oscillator

and phase detector comprising a phase-locked loop. This

allows the MOSFET turn-on to be locked to the rising edge

of an external frequency source. The frequency range of

the voltage-controlled oscillator is 350kHz to 750kHz. The

phase detector used is an edge sensitive digital type that

provides zero degrees phase shift between the external

andinternaloscillators.Thistypeofphasedetectorwillnot

lock up on input frequencies close to the harmonics of the

VCO center frequency. The PLL hold-in range ∆f_His equal

to the capture range, ∆f_H= ∆f_C= ±200kHz.

Figure 6. Phase-Locked Loop Block Diagram

filter network on the PLL_LPF pin. The relationship be-

tween the voltage on the PLL_LPF pin and operating

frequencyisshowninFigure5. Asimplifiedblockdiagram

is shown in Figure 6.

If the external frequency (V_SYNC/MODE) is greater than

550kHz, the center frequency, current is sourced continu-

ously, pulling up the PLL_LPF pin. When the external

frequency is less than 550kHz, current is sunk continu-

ously, pulling down the PLL_LPF pin. If the external and

internal frequencies are the same but exhibit a phase

difference, the current sources turn on for an amount of

time corresponding to the phase difference. Thus the

voltage on the PLL_LPF pin is adjusted until the phase and

frequency of the external and internal oscillators are

identical. At this stable operating point the phase com-

paratoroutputisopenandthefiltercapacitorC_LPholdsthe

voltage.

The output of the phase detector is a pair of complemen-

tary current sources charging or discharging the external

1000

900

800

700

600

500

400

300

200

100

0

The loop filter components C_LPand R_LPsmooth out the

current pulses from the phase detector and provide a

stable input to the voltage controlled oscillator. The filter

components C_LPand R_LPdetermine how fast the loop

acquires lock. Typically R_LP= 10k and C_LPis 2200pF to

0.01µF. When not synchronized to an external clock, the

internal connection to the VCO is disconnected. This

disallowssettingtheinternaloscillationfrequencybyaDC

voltage on the V_PLLLPFpin.

0

0.5

1

1.5

2

V

(V)

PLLLPF

1875 F05

Figure 5. Relationship Between Oscillator Frequency

and Voltage at PLL_LPF Pin

1875f

12

LTC1875

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APPLICATIO S I FOR ATIO

U

Efficiency Considerations

the internal power MOSFET switches. Each time the

gate is switched from high to low to high again, a

packet of charge dQ moves from PV_INto ground. The

resultingdQ/dtisthecurrentoutofPV_INthatistypically

larger than the DC bias current. In continuous mode,

The efficiency of a switching regulator is equal to the

output power divided by the input power times 100%. It is

oftenusefultoanalyzeindividuallossestodeterminewhat

is limiting the efficiency and which change would produce

the most improvement. Efficiency can be expressed as:

I

_GATECHG= f(Q_T+ Q_B) where Q_Tand Q_Bare the gate

charges of the internal top and bottom switches. Both

the DC bias and gate charge losses are proportional to

supply voltage and thus their effects will be more

pronounced at higher supply voltages.

Efficiency = 100% – (L1 + L2 + L3 + ...)

WhereL1,L2,etc.aretheindividuallossesasapercentage

of input power.

2. I²R losses are calculated from the resistances of the

internal switches R_SWand external inductor R_L. In

continuous mode the average output current flowing

through inductor L is “chopped” between the main

switch and the synchronous switch. Thus, the series

resistancelookingintoSWpinsisafunctionofbothtop

andbottomMOSFETR_DS(ON)andthedutycycle(DC)as

follows:

Although all dissipative elements in the circuit produce

losses, two main sources usually account for most of the

losses in LTC1875 circuits: supply quiescent currents and

I²R losses. The supply quiescent current loss dominates

theefficiencylossatverylowloadcurrentwhereastheI²R

loss dominates the efficiency loss at medium to high load

currents. In a typical efficiency plot, the efficiency curve at

very low load currents can be misleading since the actual

power lost is of no consequence as illustrated in Figure 7.

R_SW= (R_DS(ON)TOP)(DC) + R_DS(ON)BOT)(1 – DC)

1. The supply quiescent current is due to two compo-

nents: the DC bias current as given in the Electrical

Characteristics and the internal main switch and syn-

chronousswitchgatechargecurrents.Thegatecharge

current results from switching the gate capacitance of

The R_DS(ON)for both the top and bottom MOSFETs can

be obtained from the Typical Performance Characteris-

tics curves. Thus, to obtain I²R losses, simply add R_SW

to R_Land multiply by the square of the average output

current.

Other losses including C_INand C_OUTESR dissipative

losses,MOSFETswitchinglossesandinductorcorelosses

generally account for less than 2% total additional loss.

1

V

= 6V

IN

OUT

= 3.3V

L = 6.8µH

Burst Mode

OPERATION

0.1

Thermal Considerations

0.01

In most applications, the LTC1875 does not dissipate

much heat due to its high efficiency. But, in applications

where the LTC1875 is running at high ambient tempera-

ture with low supply voltage and high duty cycles, such as

in dropout, the heat dissipated may exceed the maximum

junction temperature of the part. If the junction tempera-

ture reaches approximately 150°C, both power switches

will be turned off and the SW nodes will become high

impedance.

0.001

0.0001

0.1

1

10

100

1000

LOAD CURRENT (mA)

1875 F07

Figure 7. Power Lost vs Load Current

1875f

13

LTC1875

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APPLICATIO S I FOR ATIO

To avoid the LTC1875 from exceeding the maximum

junction temperature, the user will need to do some

thermal analysis. The goal of the thermal analysis is to

determine whether the power dissipated exceeds the

maximum junction temperature of the part. Normally,

some iterative calculation is required to determine a rea-

sonably accurate value. The temperature rise is given by:

Therefore:

T_J= 70°C + (0.256)(140) = 98°C

which is below the maximum junction temperature of

125°C.

Note that at higher supply voltages, the junction tempera-

ture is lower due to reduced switch resistance (R_DS(ON)).

T_R= P • θ_JA

Checking Transient Response

where P is the power dissipated by the regulator and θ_JA

is the thermal resistance from the junction of the die to the

ambient temperature.

The regulator loop response can be checked by looking at

the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

a load step occurs, V_OUTimmediately shifts by an amount

equal to (∆I_LOAD• ESR), where ESR is the effective series

resistance of C_OUT. ∆I_LOADalso begins to charge or

discharge C_OUT, generating a feedback error signal. The

regulator loop then acts to return V_OUTto its steady-state

value. During this recovery time, V_OUTcan be monitored

for overshoot or ringing that would indicate a stability

problem. The I_THpin can be used for external compensa-

tion as shown in Figure 9. (The capacitor, C_C2, is typically

needed for noise decoupling.)

The junction temperature is given by:

T_J= T_A+ T_R

where T_Ais the ambient temperature. Because the power

transistor R_DS(ON)is a function of temperature, it is

usually necessary to iterate 2 to 3 times through the

equations to achieve a reasonably accurate value for the

junction temperature.

As an example, consider the LTC1875 in dropout at an

input voltage of 3V, a load current of 0.8A and an ambient

temperature of 70°C. From the typical performance graph

of switch resistance, the R_DS(ON)of the P-channel switch

at 70°C is 0.35Ω. Therefore, power dissipated by the IC is:

A second, more severe transient is caused by switching in

loads with large (>1µF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C_OUT, causing a rapid drop in V_OUT. No regulator can

deliver enough current to prevent this problem if the load

switch resistance is low and it is driven quickly. The only

solution is to limit the rise time of the switch drive so that

the load rise time is limited to approximately (25 • C_LOAD).

Thus, a 10µF capacitor charging to 3.3V would require a

250µs rise time, limiting the charging current to about

130mA.

P = I²• R_DS(ON)= 0.224W

For the SSOP package, the θ_JAis 110°C/W. Thus the

junction temperature of the regulator is:

T_J= 70°C + (0.224)(110) = 95°C

However,atthistemperature,theR_DS(ON)isactually0.4Ω.

1875f

14

LTC1875

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APPLICATIO S I FOR ATIO

U

PC Board Layout Checklist

2. BewareofgroundloopsinmultiplelayerPCboards. Try

to maintain one central ground node on the board and

use the input capacitor to avoid excess input ripple for

high output current power supplies. If the ground is to

be used for high DC currents, choose a path away from

the small-signal components.

As with all high frequency switchers, when considering

layout, care must be taken in order to achieve optimal

electrical, thermal and noise performance. Figure 8 is a

sample of PC board layout for the design example shown

in Figure 9. A 4-layer PC board is used in this design.

Several guidelines are followed in this layout:

3. The high di/dt loop from the top terminal of the input

capacitor, through the power MOSFETs and back to the

input capacitor should be kept as tight as possible to

reduce inductive ringing. Excess inductance can cause

increased stress on the power MOSFET and increase

noise on the input. If low ESR ceramic capacitors are

usedtoreduceinputnoise,placethesecapacitorsclose

to the DUT in order to keep the series inductance to a

minimum.

1. In order to minimize switching noise and improve

output load regulation, the PGND pins of the LTC1875

shouldbeconnecteddirectlyto1)thenegativeterminal

of the output decoupling capacitors, 2) the negative

terminal of the input capacitor and 3) vias to the ground

plane immediately adjacent to Pins 1, 7 and 10. The

ground trace on the top layer of the PC board should be

as wide and short as possible to minimize series resis-

tance and inductance.

VIA CONNECTION TO V

IN

VIAS TO GND PLANE

R

SVIN

C

C2

C

PL

R

PL

C

C1

VIA CONNECTION TO R

FB1

C

SS

R

PG

R

SS

R

FB2

FB1

R

DUT

L1

C

IN1

C

IN2

C

OUT

V

IN

PGND

V

OUT

1875 F08

VIAS TO GND PLANE

Figure 8. Typical Application and Suggested Layout (Topside Only)

1875f

15

LTC1875

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U

APPLICATIO S I FOR ATIO

4. Place the small-signal components away from high

frequency switching nodes. In the layout shown in

Figure 8, all of the small-signal components have been

placed on one side of the IC and all of the power

components have been placed on the other.

Substituting V_OUT= 2.5V, V_IN= 4.2V, ∆I_L= 450mA and

f = 550kHz in equation (3) gives:

2.5V

4.2V

L =

1–

= 4.09µH

550kHz •450mA

5. For optimum load regulation and true sensing, the top

of the output resistor divider should connect indepen-

dentlytothetopoftheoutputcapacitor(Kelvinconnec-

tion), staying away from any high dV/dt traces. Place

the divider resistors near the LTC1875 in order to keep

the high impedance FB node short.

A 4.7µH inductor works well for this application. For good

efficiency choose a 2A inductor with less than 0.125Ω

series resistance.

C_INwill require an RMS current rating of at least 0.75A at

temperature and C_OUTwill require an ESR of less than

0.125Ω. In most applications, the requirements for these

capacitors are fairly similar.

Design Example

For the feedback resistors, choose R2 = 412k. R1 can then

be calculated from equation (2) to be:

As a design example, assume the LTC1875 is used in a

singlelithium-ionbattery-poweredcellularphoneapplica-

tion. The V_INwill be operating from a maximum of 4.2V

down to about 2.65V. The load current requirement is a

maximumof1.5Abutmostofthetimeitwillbeonstandby

mode, requiring only 2mA. Efficiency at both low and high

load currents is important. Output voltage is 2.5V. With

this information we can calculate L using equation (1),

V_OUT

0.8

R1=

– 1 •R2 = 875.5k, use 887k

Figure 9 shows the complete circuit along with its effi-

ciency curve.

1

f ∆I

V_OUT

V

IN

L =

V_OUT1–

(3)

( )(

)

L

1875f

16

LTC1875

W U U

APPLICATIO S I FOR ATIO

U

R

SVIN

10Ω

C

SVIN

0.1µF

13

IN

15

R

PG

SV

SYNC/MODE

100k

14

2

8

9

POWER

GOOD

V

IN

PGOOD

PV

IN

2.65V TO 4.2V

C

IN2

C

IN1

R

SS

10µF

IN

10µF

1M

GND

7

PGND

RUN/SS

10

C

SS

0.1µF

C

OUT

47µF

5

LTC1875

L1

SWP

SWN

12

6

4.7µH

16

4

V

*

OUT

PLL_LPF

2.5V/1.5A

11

R1 887k

3

I

V

FB

TH

R2

C

C1

412k

47pF

1

C

1875 F09a

C2

220pF

SGND

R

C

150k

BOLD LINES INDICATE HIGH CURRENT PATHS

C

OUT

, C : TAIYO-YUDEN CERAMIC JMK316BJ106ML

IN1 IN2

C

: TDK CERAMIC C4532X5R0J476M

L1: TOKO A921CY-4R7M

*1.5A IS THE MAXIMUM OUTPUT CURRENT

Figure 9a. Single Lithium-Ion to 2.5V/1.5A Regulator from Design Example

100

V

= 2.5V

OUT

L = 4.7µH

95

90

85

80

75

70

65

60

V

= 3V

IN

V

= 3.6V

IN

V

= 4.2V

IN

0.1

1

10

100

1000

OUTPUT CURRENT (mA)

1875 F09b

Figure 9b. Efficiency vs Output Current for Design Example

1875f

17

LTC1875

U

TYPICAL APPLICATIO

Single Li-Ion to 1.8V/1.5A Regulator Using All Ceramic Capacitors

R

SVIN

10Ω

C

SVIN

13

IN

15

0.1µF

R

PG

SV

SYNC/MODE

100k

14

2

8

9

POWER

GOOD

PGOOD

PV

IN

V

3V TO 4.2V

IN

C

IN2

C

IN1

R

PV

IN

SS

10µF

1M

GND

7

PGND

RUN/SS

10

C

SS

0.1µF

C

OUT

47µF

5

LTC1875

L1

SWP

SWN

4.7µH

12

6

16

4

V

*

OUT

PLL_LPF

1.8V/1.5A

11

R1 523k

3

I

TH

V

FB

R2

C

C1

412k

1

47pF

C

C2

1875 TA02

SGND

220pF

R

C

150k

BOLD LINES INDICATE HIGH CURRENT PATHS

C

, C : TAIYO YUDEN CERAMIC JMK316BJ106ML

IN1 IN2

: TDK CERAMIC C4532X5R0J476M

OUT

L1: TOKO A921CY-4R7M

*1.5A IS THE MAXIMUM OUTPUT CURRENT

Efficiency vs Output Current

100

90

80

70

60

50

40

V

= 1.8V

OUT

V

= 3.3V

IN

L = 4.7µH

V

= 4.2V

IN

0.1

1

10

100

1000

OUPUT CURRENT (mA)

1875 TA02a

1875f

18

LTC1875

U

PACKAGE DESCRIPTION

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.189 – .196*

(4.801 – 4.978)

.045 ±.005

.009

(0.229)

REF

16 15 14 13 12 11 10 9

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 ±.0015

.0250 TYP

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

8

.015 ± .004

(0.38 ± 0.10)

× 45°

.053 – .068

(1.351 – 1.727)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

(0.203 – 0.305)

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

GN16 (SSOP) 0502

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

1875f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.

19

LTC1875

U

TYPICAL APPLICATIO

Single Li-Ion to 3.3V/1A Regulator Using All Ceramic Capacitors

R

SVIN

10Ω

C

SVIN

0.1µF

13

IN

15

R

PG

SV

SYNC/MODE

100k

14

2

8

9

POWER

GOOD

PGOOD

PV

IN

V

3V TO 4.2V

IN

C

IN2

10µF

C

IN1

R

PV

IN

SS

10µF

1M

GND

7

PGND

RUN/SS

10

C

SS

0.1µF

C

OUT

47µF

5

LTC1875

L1

4.7µH

SWP

SWN

12

6

V

16

4

OUT

PLL_LPF

3.3V*

1A**

11

R1

1.29M

3

BOLD LINES INDICATE HIGH CURRENT PATHS

I

TH

V

FB

C

R2

412k

C1

47pF

C

, C : TAIYO YUDEN CERAMIC JMK316BJ106ML

IN1 IN2

: TDK CERAMIC C4532X5R0J476M

OUT

1

C

C2

220pF

SGND

L1: TOKO A921CY-4R7M

*V CONNECTED TO V FOR 3V < V < 3.3V

R

C

1875 TA03

150k

OUT

IN IN

**1A IS THE MAXIMUM OUTPUT CURRENT

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OUT(MIN)

DC/DC Converters

I : <1µA, ThinSOT

SD

LTC3411

LTC3412

LTC3430

LTC3440

1.25A (I ), 4MHz Synchronous Step-Down DC/DC Converter

95% Efficiency, V : 2.5V to 5.5V, V

: 0.8V, I : 60µA,

Q

OUT

IN

I

: <1µA, 10-Lead MS

SD

2.5A (I ), 4MHz Synchronous Step-Down DC/DC Converter

95% Efficiency, V : 2.5V to 5.5V, V

: 0.8V, I : 60µA,

Q

OUT

IN

I

: <1µA, TSSOP16E

SD

60V, 2.75A (I ), 200kHz High Efficiency Step-Down

90% Efficiency, V : 5.5V to 60V, V

SD

: 1.2V, I : 2.5mA,

OUT(MIN) Q

OUT

IN

DC/DC Converter

I : 25µA, TSSOP16E

600mA (I ), 2MHz Synchronous Buck-Boost

95% Efficiency, V : 2.5V to 5.5V, V

: 2.5V, I : 25µA,

OUT(MIN) Q

OUT

IN

DC/DC Converter

I : <1µA, 10-Lead MS

SD

ThinSOT is a trademark of Linear Technology Corporation.

1875f

LT/TP 0403 2K • PRINTED IN USA

20 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

LINEAR TECHNOLOGY CORPORATION 2001


型号：	LTC1875EGN
厂家：	Linear
描述：	15mA Quiescent Current 1.5A Monolithic Synchronous Step-Down Regulator 15毫安静态电流1.5A单片同步降压型稳压器稳压器
文件：	总20页 (文件大小：258K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1875EGN [Linear]

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