LTC1879EGN#PBF [Linear]
LTC1879 - 1.2A Synchronous Step-Down Regulator with 15µA Quiescent Current; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LTC1879EGN#PBF |
| 厂家： | 
Linear |
| 描述： | LTC1879 - 1.2A Synchronous Step-Down Regulator with 15µA Quiescent Current; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总20页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1879
1.2A Synchronous
Step-Down Regulator with
15µA Quiescent Current
U
FEATURES
DESCRIPTIO
■
High Efficiency: Up to 95%
The LTC®1879 is a high efficiency monolithic synchro-
nous buck regulator using a constant frequency, current
mode architecture. Operating supply current is only 15µA
with no load and drops to <1µA in shutdown. The input
supply voltage range of 2.65V to 10V makes the LTC1879
ideally suited for both single and dual Li-Ion battery-pow-
ered applications. 100% duty cycle provides low dropout
operation, extending battery life in portable systems.
■
Low Quiescent Current: Only 15µA with No Load
■
550kHz Constant Frequency Operation
■
2.65V to 10V Input Voltage Range
■
VOUT from 0.8V to VIN, IOUT to 1.2A
■
True PLL Frequency Locking from 350kHz to 750kHz
■
Power Good Output Voltage Monitor
■
Low Dropout Operation: 100% Duty Cycle
Burst Mode® or Pulse Skipping Operation
■
The switching frequency is internally set to 550kHz, allow-
ing the use of small surface mount inductors and capaci-
tors. For noise sensitive applications, the LTC1879 can be
externally synchronized from 350kHz to 750kHz. Burst
Mode operation is inhibited during synchronization or
when the SYNC/MODE pin is pulled low.
■
Current Mode Operation for Excellent Line and Load
Transient Response
■
Shutdown Mode Draws <1µA Supply Current
■
±2% Output Voltage Accuracy
■
Overcurrent and Overtemperature Protected
■
Available in 16-Lead SSOP Package
The internal synchronous rectifier switch increases effi-
ciency and eliminates the need for an external Schottky
diode. Low output voltages are easily supported with a
0.8Vfeedbackreferencevoltage. TheLTC1879isavailable
in a 16-lead SSOP package.
U
APPLICATIO S
■
Cellular Telephones
■
Portable Computers
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Wireless Modems
Burst Mode is a registered trademark of Linear Technology Corporation.
U
TYPICAL APPLICATIO
High Efficiency Step-Down Converter
Efficiency vs Output Load Current
V
IN
2.65V TO 10V
100
13
V
IN
= 3.6V
C
IN
10µF
90
80
70
60
50
40
30
SV
IN
2
15
14
4
8, 9
5, 12
6, 11
7, 10
3
RUN/SS
PV
IN
V
= 7.2V
IN
L1
SYNC/MODE
LTC1879
PGOOD
SWP
SWN
6.2µH
V
*
OUT
V
IN
= 10V
3.1V
C
OUT
47µF
150k
I
TH
PGND
Burst Mode OPERATION
= 3.1V
47pF
220pF
V
V
OUT
L = 6.2µH
FB
80.6k
SGND
1
28.0k
0.1
1
10 100
OUPUT CURRENT (mA)
1000
1879 TA01a
1879 TA01b
C
C
: TAIYO YUDEN CERAMIC LMK325BJ106MN
IN
: TDK CERAMIC C4532X5ROJ476M
OUT
L1: TOKO A921CY6R2M
*V
CONNECTED TO V (MINUS SWITCH AND L1 VOLTAGE DROP) FOR 2.65V < V < 3.1V
OUT
I
N
I
N
1879f
1
LTC1879
W W
U W
U
W U
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
ORDER PART
Input Supply Voltage ................................ –0.3V to 11V
ITH, PLL_LPF Voltages............................. –0.3V to 2.7V
RUN/SS, VFB Voltages ............................... –0.3V to VIN
SYNC/MODE Voltage ................................. –0.3V to VIN
(VPVIN – VSWP) Voltage............................. –0.3V to 11V
VSWN Voltage ............................................ –0.3V to 11V
P-Channel Switch Source Current (DC) .................... 2A
N-Channel Switch Sink Current (DC) ........................ 2A
Peak Switching Sink and Source Current ................. 3A
Operating Ambient Temperature Range
(Note 2) ............................................. –40°C to 85°C
Junction Temperature (Notes 3, 6) ...................... 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
TOP VIEW
NUMBER
SGND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PLL_LPF
SYNC/MODE
PGOOD
RUN/SS
LTC1879EGN
V
FB
I
SV
IN
TH
SWP1
SWN1
SWP2
SWN2
PGND2
GN PART
MARKING
PGND1
PV
IN1
PV
IN2
1879
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 140°C/ W, θJC = 40°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Feedback Current
Regulated Output Voltage
(Note 4)
●
8
60
nA
VFB
V
(Note 4) 0°C ≤ T ≤ 85°C
(Note 4) –40°C ≤ T ≤ 85°C
0.784
0.740
0.80
0.80
0.816
0.840
V
V
FB
A
●
●
●
A
∆V
∆V
Overvoltage Trip Limit with Respect to V
∆V
∆V
= V
– V
20
20
60
60
110
110
0.25
mV
mV
OVL
FB
OVL
UVL
OVL
FB
Undervoltage Trip Limit with Respect to V
Reference Voltage Line Regulation
Output Voltage Load Regulation
= V – V
FB UVL
UVL
FB
∆V /V
V
IN
= 2.65V to 10V (Note 4)
0.05
%/V
FB FB
V
Measured in Servo Loop, V
Measured in Servo Loop, V
= 0.9V to 1.2V
= 1.6V to 1.2V
●
●
0.1
–0.1
0.6
–0.6
%
%
LOADREG
ITH
ITH
V
Input Voltage Range
●
2.65
10
V
IN
I
Input DC Bias Current
Pulse Skipping Mode
Burst Mode Operation
Shutdown
(Note 5)
Q
2.65V < V < 10V, V
= 0V, I = 0A
OUT
270
15
0
365
22
1
µA
µA
µA
IN
SYNC/MODE
= 0A
V
V
= V , I
SYNC/MODE
IN OUT
= 0V, V = 10V
RUN
IN
f
f
SYNC Capture Range
Oscillator Frequency
350
495
750
605
kHz
SYNC
OSC
V
FB
V
FB
≥ 0.7V
= 0V
550
80
kHz
kHz
I
Phase Detector Output Current
Sinking Capability
Sourcing Capability
PLLLPF
f
f
< f
OSC
> f
SOC
●
●
3
–3
10
–10
20
–20
µA
µA
PLLIN
PPLIN
R
R
R
R
of P-Channel FET
of N-Channel FET
I
I
= 100mA, V = 5V
0.35
0.37
2.2
0.45
0.5
Ω
Ω
A
PFET
DS(ON)
DS(ON)
SW
SW
IN
= –100mA, V = 5V
NFET
IN
I
I
Peak Inductor Current
SW Leakage
V
V
= 0.7V, Duty Cycle < 35%, V = 5V
1.8
0.2
2.7
PK
LSW
FB
IN
= 0V, V = 0V or 10V, V = 10V
±0.01
1.0
±2.5
1.5
µA
V
RUN
SW
IN
V
SYNC/MODE Threshold
SYNC/MODE Leakage Current
●
SYNC/MODE
SYNC/MODE
I
±0.01
±1
µA
1879f
2
LTC1879
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
0.7
MAX
1.5
UNITS
V
V
RUN Threshold
RUN Input Current
V
V
Ramping Up
= 0V
●
0.2
RUN
RUN
RUN
RUN
I
±0.01
±1
µA
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 4: The LTC1879 is tested in a feedback loop which servos V to the
FB
balance point for the error amplifier (V = 1.2V)
ITH
Note 2: The LTC1879E is guaranteed to meet specified performance from
0°C to 70°C. Specifications over the –40°C to 85°C operating ambient
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 6: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formula:
D
LTC1879: T = T + (P × 140°C/W)
J
A
D
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Oscillator Frequency
vs Supply Voltage
Oscillator Frequency
RDS(ON) vs Temperature
vs Temperature
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
595
575
555
535
515
495
600
590
580
570
560
550
540
530
520
510
500
V
= 5V
SYNCHRONOUS SWITCH
MAIN SWITCH
IN
V
= 5V
IN
V
= 10V
IN
V
= 5V
IN
V
= 10V
25
IN
–50 –25
0
50
75 100 125
–50 –25
0
25
50
75 100 125
2
4
6
8
10
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
1879 G01
1879 G02
1879 G03
DC Supply Current
vs Temperature
DC Supply Current
vs Input Voltage
RDS(ON) vs Input Voltage
300
250
200
150
100
50
300
250
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 5V
IN
PULSE SKIPPING MODE
SYNCHRONOUS
SWITCH
PULSE SKIPPING MODE
200
150
MAIN
SWITCH
100
50
0
Burst Mode OPERATION
Burst Mode OPERATON
0
–50
0
50
100 125
0
2
4
6
8
10
7
8
2
3
4
5
6
9
10
TEMPERATURE (°C)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
1879 G04
1879 G05
1879 G06
1879f
3
LTC1879
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Switch Leakage vs Temperature
Switch Leakage vs Input Voltage
Output Voltage vs Load Current
2.51
2.50
2.49
2.48
2.47
2.46
2.45
2.44
2.43
2.42
2.41
20
18
16
14
12
10
8
50
45
40
35
30
25
20
15
10
5
V
IN
= 10V
RUN = 0V
T
= 25°C
A
MAIN SWITCH
MAIN SWITCH
6
SYNCHRONOUS
SWITCH
4
PULSE SKIPPING MODE
V
= 5V
IN
L = 6.2µH
2
SYNCHRONOUS SWITCH
0
0
50
75 100 125
0
200 400 600
800
1000 1600
1200 1400
–50
0
25
–25
0
2
4
6
8
10
LOAD CURRENT (mA)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
1879 G09
1879 G07
1879 G08
Reference Voltage
vs Temperature
Efficiency vs Output Current
Efficiency vs Output Current
804
803
802
801
800
799
798
797
796
795
794
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
V
= 6V
IN
V
= 3.6V
IN
V
= 3.6V
IN
V
= 5V
IN
V
= 5V
IN
V
= 7.2V
V
= 7.2V
IN
IN
V
= 10V
IN
V
= 10V
IN
V
= 1.8V
V
= 2.5V
OUT
L = 6.2µH
Burst Mode OPERATION
OUT
L = 6.2µH
Burst Mode OPERATION
–50 –25
0
25
50
75 100 125
0.1
1
10 100 1000
0.1
1
10
100
1000
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
1879 G11
1879 G12
1879 G10
Efficiency vs Output Current
Efficiency vs Input Voltage
100
90
80
70
60
50
40
30
20
10
0
100
V
= 4.2V
IN
V
= 7.2V
IN
100mA
10mA
90
80
1mA
V
= 4.2V
IN
70
60
50
40
30
V
= 7.2V
IN
0.1mA
V
= 3.1V
OUT
V
OUT
= 2.5V
L = 6.2µH
L = 6.2µH
Burst Mode OPERATION
Burst Mode OPERATION
PULSE SKIPPING MODE
0.1
1
10
100
1000
4
6
10
2
8
OUTPUT CURRENT (mA)
INPUT VOLTAGE (V)
1879 G13
1879 G14
1879f
4
LTC1879
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Load Step
(Pulse Skipping Mode)
Load Step (Burst Mode Operation)
Soft-Start with Shorted Output
IL
IL
1A/DIV
1A/DIV
IVIN
500mA/DIV
RUN/SS
1V/DIV
VOUT
100mV/DIV
VOUT
100mV/DIV
50µs/DIV
CIN = 20µF
COUT = 47µF
LOAD = 50mA to 1200mA
1879 G15
50µs/DIV
CIN = 20µF
COUT = 47µF
1879 G16
5ms/DIV
CIN = 20µF
COUT = 47µF
LOAD = 0A
1879 G19
VIN = 5V
VOUT = 2.5V
L = 4.7µH
VIN = 5V
VOUT = 2.5V
L = 4.7µH
VIN = 5V
VOUT = 0V
L = 4.7µH
I
I
LOAD = 50mA to 1200mA
I
Burst Mode Operation
Pulse Skipping Mode Operation
IL
IL
200mA/DIV
200mA/DIV
VOUT
50mV/DIV
VOUT
20mV/DIV
SW
5V/DIV
SW
5V/DIV
25µs/DIV
1879 G18
2.5µs/DIV
1879 G17
VIN = 5V
VOUT = 2.5V
L = 4.7µH
CIN = 20µF
VIN = 5V
OUT = 2.5V
L = 4.7µH
CIN = 20µF
COUT = 47µF
V
COUT = 47µF
I
LOAD = 15mA
ILOAD = 15mA
1879f
5
LTC1879
U
U
U
PI FU CTIO S
PVIN1, PVIN2 (Pins 8, 9): Power Supply Pins for the
Internal Drivers and Switches. These pins should always
be tied together.
SGND (Pin 1): Signal Ground Pin.
RUN/SS (Pin 2): Combination of Soft-Start and Run
ControlInputs.Forcingthispinbelow0.7Vshutsdownthe
device. In shutdown all functions are disabled and device
draws zero supply current. For the proper operation of the
part, force this pin above 2.5V. Do not leave this pin
floating. Soft-start can be accomplished by raising the
voltage on this pin gradually with an RC circuit.
SVIN (Pin 13): Signal Power Supply Pin.
PGOOD (Pin 14): Power Good Indicator Pin. Power good
is an open-drain logic output. The PGOOD pin is pulled to
ground when the voltage on the VFB pin is not within
±7.5% of its nominally regulated potential. This pin re-
quires a pull-up resistor for power good indication. Power
good indication works in all modes of operation.
V
FB (Pin 3): Feedback Pin. Receives the feedback voltage
from an external resistor divider across the output.
SYNC/MODE (Pin 15): External Clock Synchronization
and Mode Select Input. To synchronize, apply an external
clock with a frequency between 350kHz and 750kHz. To
select Burst Mode operation, tie pin to SVIN. Grounding
this pin selects pulse skipping mode. Do not leave this pin
floating.
ITH (Pin 4): Error Amplifier Compensation Point. The
current output increases with this control voltage. Nomi-
nal voltage range for this pin is 0.5V to 1.8V.
SWP1, SWP2 (Pins 5, 12): Upper Switch Nodes. These
pins connect to the drains of the internal main PMOS
switches and should always be connected together
externally.
PLL_LPF (Pin 16): Output of the Phase Detector and
Control Input of Oscillator. Connect a series RC lowpass
networkfromthispintogroundifexternallysynchronized.
If unused, this pin may be left open.
SWN1, SWN2 (Pins 6, 11): Lower Switch Nodes. These
pins connect to the drains of the internal synchronous
NMOS switches and should always be connected together
externally.
PGND1,PGND2(Pins7,10):PowerGroundPins.Ground
pins for the internal drivers and switches. These pins
should always be tied together.
1879f
6
LTC1879
W
BLOCK DIAGRA
1879f
7
LTC1879
U
OPERATIO
(Refer to Block Diagram)
Main Control Loop
the ITH voltage drops below approximately 0.45V, the
BURSTcomparatortrips,turningoffbothpowerMOSFETs.
The ITH pin is then disconnected from the output of the EA
amplifier and held 0.65V above ground.
The LTC1879 uses a constant frequency, current mode
step-down architecture. Both the top MOSFET and syn-
chronous bottom MOSFET switches are internal. During
normal operation, the internal top power MOSFET is
turned on each cycle when the oscillator sets the RS latch,
andturnedoffwhenthecurrentcomparator, ICOMP, resets
the RS latch. The peak inductor current at which ICOMP
turns the top MOSFET off is controlled by the voltage on
the ITH pin, which is the output of error amplifier EA. When
the load current increases, it causes a slight decrease in
the feedback voltage, VFB, relative to the 0.8V internal
reference, which, in turn, causes the ITH voltage to in-
crease until the average inductor current matches the new
load current. While the top MOSFET is off, the bottom
MOSFET is turned on until either the inductor current
starts to reverse direction or the next clock cycle begins.
In sleep mode, both power MOSFETs are held off and the
internal circuitry is partially turned off, reducing the quies-
cent current to 15µA. The load current is now being
supplied from the output capacitor. When the output
voltage drops, the ITH pin reconnects to the output of the
EA amplifier and the top MOSFET is again turned on and
this process repeats.
Soft-Start/Run Function
The RUN/SS pin provides a soft-start function and a
means to shut down the LTC1879. Soft-start reduces the
inputcurrentsurgebygraduallyincreasingtheregulator’s
maximum output current. This pin can also be used for
power supply sequencing.
Comparator OVDET guards against transient overshoots
>7.5% by turning the main switch off and keeping it off
until the fault is removed.
Pulling the RUN/SS pin below 0.7V shuts down the
LTC1879, which then draws <1µA current from the sup-
ply. This pin can be driven directly from logic circuits as
showninFigure1.Itisrecommendedthatthispinisdriven
to VIN during normal operation. Note that there is no
current flowing out of this pin. Soft-start action is accom-
plished by connecting an external RC network to the RUN/
SS pin as shown in Figure 1. The LTC1879 actively pulls
the RUN/SS pin to ground under low input supply voltage
conditions.
Burst Mode Operation
The LTC1879 is capable of Burst Mode operation in which
the internal power MOSFETs operate intermittently based
on load demand. To enable Burst Mode operation, simply
tie the SYNC/MODE pin to SVIN or connect it to a logic high
(VSYNC/MODE > 1.5V). To disable Burst Mode operation
andenablePWMpulseskippingmode, connecttheSYNC/
MODE pin to SGND. In this mode, the efficiency is lower at
lightloadsbutbecomescomparabletoBurstModeopera-
tion when the output load exceeds 100mA. The advantage
of pulse skipping mode is lower output ripple.
V
IN
3.3V OR 5V
D1*
0.32V
R
SS
When the converter is in Burst Mode operation, the peak
current of the inductor is set to approximately 400mA,
even though the voltage at the ITH pin indicates a lower
value. The voltage at the ITH pin drops when the inductor’s
average current is greater than the load requirement. As
RUN/SS
C
SS
*ZETEX BAT54
1879 F01
Figure 1. RUN/SS Pin Interfacing
1879f
8
LTC1879
U
OPERATIO
Power Good Indicator
(Refer to Block Diagram)
Low Dropout Operation
Thepowergoodfunctionmonitorstheoutputvoltageinall
modes of operation. Its open-drain output is pulled low
when the output voltage is not within ±7.5% of its nomi-
nally regulated voltage. The feedback voltage is filtered
before it is fed to a power good window comparator in
order to prevent false tripping of the power good signal
during fast transients. The window comparator monitors
the output voltage even in Burst Mode operation. In
shutdown mode, open drain is actively pulled low to
indicate that the output voltage is invalid.
When the input supply voltage decreases toward the
output voltage in a buck regulator, the duty cycle in-
creases toward the maximum on-time. Further reduction
of the supply voltage forces the main switch to remain on
for more than one cycle until it reaches 100% duty cycle.
The output voltage will then be determined by the input
voltage minus the voltage drop across the top MOSFET
and the inductor.
Low Supply Operation
The LTC1879 is designed to operate down to an input
supply voltage of 2.65V although the maximum allowable
output current is reduced at this low voltage. Figure 2
shows the reduction in the maximum output current as a
function of input voltage.
Short-Circuit Protection
When the output is shorted to ground, the frequency of
the oscillator is reduced to about 80kHz, 1/7 the nominal
frequency. This frequency foldback ensures that the in-
ductorcurrenthasmoretimetodecay, therebypreventing
runaway. The oscillator’s frequency will progressively
increase to 550kHz (or to the synchronized frequency)
when VFB rises above 0.3V.
Another important detail to remember is that at low input
supply voltages, the RDS(ON) of the P-channel switch
increases. Therefore, the user should calculate the power
dissipation when the LTC1879 is used at 100% duty cycle
with low supply voltage (see Thermal Considerations in
the Applications Information section).
Frequency Synchronization
The LTC1879 can be synchronized to an external clock
source connected to the SYNC/MODE pin. The turn-on of
the top MOSFET is synchronized to the rising edge of the
external clock.
1800
1600
V
= 2.5V
OUT
When the LTC1879 is clocked by an external source, Burst
Mode operation is disabled. In this synchronized mode,
whentheoutputloadcurrentisverylow,currentcompara-
tor, ICOMP, mayremaintrippedforseveralcyclesandforce
the main switch to stay off for the same number of cycles.
Increasing the output load slightly allows constant fre-
quency PWM operation to resume.
1400
V
OUT
= 1.8V
1200
1000
800
V
OUT
= 3.1V
600
400
3
4
5
6
7
10
2
8
9
Frequency synchronization is inhibited when the feedback
voltage VFB is below 0.6V. This prevents the external clock
from interfering with the frequency foldback for short-
circuit protection.
INPUT VOLTAGE (V)
1879 F02
Figure 2. Maximum Output Current vs Input Voltage
1879f
9
LTC1879
U
OPERATIO
2400
2200
2000
1800
1600
1400
1200
1000
Slope Compensation and Inductor Peak Current
V
= 5V
IN
Slope compensation is required in order to prevent sub-
harmonic oscillation at high duty cycles. It is accom-
plished by internally adding a compensating ramp to the
inductor current signal at duty cycles in excess of 40%. As
aresult,themaximuminductorpeakcurrentisreducedfor
duty cycles >40%. This is shown in the decrease of the
inductor peak current as a function of duty cycle graph in
Figure 3.
0
20
40
60
80
100
DUTY CYCLE (%)
1879 F03
Figure 3. Maximum Inductor Peak Current vs Duty Cycle
W U U
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APPLICATIO S I FOR ATIO
A reasonable starting point for setting ripple current is
ThebasicLTC1879applicationcircuitisshownonthefirst
page of this data sheet. External component selection is
driven by the load requirement and begins with the selec-
∆IL = 0.3(IMAX).
The inductor value also has an effect on Burst Mode
operation. The transition to low current operation begins
when the inductor current peaks fall to approximately
500mA. Lower inductor values (higher ∆IL) will cause this
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to increase.
tion of L followed by CIN and COUT
.
Inductor Value Calculation
The inductor selection will depend on the operating fre-
quency of the LTC1879. The internal nominal frequency is
550kHz, but can be externally synchronized from 350kHz
to 750kHz.
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. However, oper-
ating at a higher frequency results in lower efficiency
because of increased switching losses.
Inductor Selection
The inductor should have a saturation current rating
greater than the peak inductor current set by the current
comparator of LTC1879. Also, consideration should be
given to the resistance of the inductor. Inductor conduc-
tion losses are directly proportional to the DC resistance
of the inductor. Manufacturers sometimes provide maxi-
mum current ratings based on the allowable losses in the
inductor.
Theinductorvaluehasadirecteffectonripplecurrent.The
ripple current ∆IL decreases with higher inductance or
frequency and increases with higher input voltages.
1
VOUT
V
IN
∆IL =
VOUT 1–
(1)
f L
( )( )
Suitable inductors are available from Coilcraft, Cooper,
Dale, Sumida, Toko, Murata, Panasonic and other manu-
facturers.
Accepting larger values of ∆IL allows the use of smaller
inductors, but results in higher output voltage ripple.
1879f
10
LTC1879
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APPLICATIO S I FOR ATIO
U
CIN and COUT Selection
The selection of COUT is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment is satisfied, the capacitance is adequate for filtering.
The output ripple ∆VOUT is determined by:
Incontinuousmode,thesourcecurrentofthetopMOSFET
is a trapezoidal waveform of duty cycle VOUT/VIN. To
preventlargevoltagetransients, alowESRinputcapacitor
sized for the maximum RMS current must be used. The
maximum RMS input capacitor current is given by:
1
∆VOUT ∆IL ESR +
8fCOUT
1/2
V
OUT(V – VOUT)
[
]
IN
where f = operating frequency, COUT = output capacitance
and ∆IL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. For the LTC1879, the general rule for
proper operation is:
IRMS(CIN) IOMAX
V
IN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is com-
monly used for design because even significant devia-
tions do not offer much relief. Note that the capacitor
manufacturer’s ripple current ratings are often based on
2000 hours of life. This makes it advisable to further
derate the capacitor, or choose a capacitor rated at a
highertemperaturethanrequired.Severalcapacitorsmay
also be paralleled to meet size or height requirements in
the design. Always consult the manufacturer if there are
any questions.
ESRCOUT < 0.125Ω
The choice of using a smaller output capacitance in-
creases the output ripple voltage due to the frequency
dependent term but can be compensated for by using
capacitor(s) of very low ESR to maintain low ripple volt-
age. The ITH pin compensation components can be opti-
mized to provide stable high performance transient
response regardless of the output capacitor selected.
Depending on how the LTC1879 circuit is powered up,
you may need to check for input voltage transients. Input
voltage transients may be caused by input voltage steps
or by connecting the circuit to an already powered up
source such as a wall adapter. The sudden application of
input voltage will cause a large surge of current in the
input leads that will store energy in the parasitic induc-
tanceoftheleads. Thisenergywillcausetheinputvoltage
to swing above the DC level of the input power source and
it may exceed the maximum voltage rating of the input
capacitor and LTC1879.
Manufacturers such as Taiyo Yuden, AVX, Kemet and
Sanyo should be considered for low ESR, high perfor-
mance capacitors. The POSCAP solid electrolytic chip
capacitor available from Sanyo is an excellent choice for
output bulk capacitors due to its low ESR/size ratio. Once
the ESR requirement for COUT has been met, the RMS
current rating generally far exceeds the IRIPPLE(P-P)
requirement.
Output Voltage Programming
The output voltage is set by a resistor divider according to
the following formula:
The easiest way to suppress input voltage transients is to
add a small aluminum electrolytic capacitor in parallel
with the low ESR input capacitor. The selected capacitor
needstohavetherightamountofESRinordertocritically
dampen the resonant circuit formed by the input lead
inductance and the input capacitor. The typical values of
ESR will fall in the range of 0.5Ω to 2Ω and capacitance
will fall in the range of 5µF to 50µF.
R1
R2
VOUT = 0.8V 1+
(2)
The external resistor divider is connected to the output,
allowing remote voltage sensing as shown in Figure 4.
1879f
11
LTC1879
APPLICATIO S I FOR ATIO
W U U
U
R
0.8V ≤ V
≤ 10V
LP
OUT
2.4V
C
LP
R1
V
FB
PLL_LPF
VCO
R2
SYNC/
MODE
LTC1879
SGND
DIGITAL
PHASE/
FREQUENCY
DETECTOR
1879 F04
Figure 4. Setting the LTC1879 Output Voltage
1879 F06
Phase-Locked Loop and Frequency Synchronization
The LTC1879 has an internal voltage-controlled oscillator
and phase detector comprising a phase-locked loop. This
allows the MOSFET turn-on to be locked to the rising edge
of an external frequency source. The frequency range of
the voltage-controlled oscillator is 350kHz to 750kHz. The
phase detector used is an edge sensitive digital type that
provides zero degrees phase shift between the external
andinternaloscillators.Thistypeofphasedetectorwillnot
lock up on input frequencies close to the harmonics of the
VCO center frequency. The PLL hold-in range ∆fH is equal
to the capture range, ∆fH = ∆fC = ±200kHz.
Figure 6. Phase-Locked Loop Block Diagram
If the external frequency (VSYNC/MODE) is greater than
550kHz, the center frequency, current is sourced continu-
ously, pulling up the PLL_LPF pin. When the external
frequency is less than 550kHz, current is sunk continu-
ously, pulling down the PLL_LPF pin. If the external and
internal frequencies are the same but exhibit a phase
difference, the current sources turn on for an amount of
time corresponding to the phase difference. Thus the
voltage on the PLL_LPF pin is adjusted until the phase and
frequency of the external and internal oscillators are
identical. At this stable operating point the phase com-
paratoroutputisopenandthefiltercapacitorCLP holdsthe
voltage.
The output of the phase detector is a pair of complemen-
tary current sources charging or discharging the external
filter network on the PLL_LPF pin. The relationship be-
tween the voltage on the PLL_LPF pin and operating
frequency is shown in Figure 5. A simplified block diagram
is shown in Figure 6.
The loop filter components CLP and RLP smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10k and CLP is 2200pF to
0.01µF. When not synchronized to an external clock, the
internal connection to the VCO is disconnected. This
disallowssettingtheinternaloscillationfrequencybyaDC
voltage on the VPLLLPF pin.
1000
900
800
700
600
500
400
300
200
100
0
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
oftenusefultoanalyzeindividuallossestodeterminewhat
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
0
0.5
1
1.5
2
V
(V)
PLLLPF
1879 F05
Figure 5. Relationship Between Oscillator Frequency
and Voltage at PLL_LPF Pin
Efficiency = 100% – (ρ1 + ρ2 + ρ3 + ...)
1879f
12
LTC1879
W U U
APPLICATIO S I FOR ATIO
U
2. I2R losses are calculated from the resistances of the
internal switches RSW and external inductor RL. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistancelookingintoSWpinsisafunctionofbothtop
andbottomMOSFETRDS(ON) andthedutycycle(DC)as
follows:
Where ρ1, ρ2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC1879 circuits: supply quiescent currents and
I2R losses. The supply quiescent current loss dominates
theefficiencylossatverylowloadcurrentwhereastheI2R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 7.
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain I2R losses, simply add RSW
to RL and multiply by the square of the average output
current.
1. The supply quiescent current is due to two compo-
nents: the DC bias current as given in the Electrical
Characteristics and the internal main switch and syn-
chronousswitchgatechargecurrents.Thegatecharge
current results from switching the gate capacitance of
the internal power MOSFET switches. Each time the
gate is switched from high to low to high again, a
packet of charge dQ moves from PVIN to ground. The
resultingdQ/dtisthecurrentoutofPVINthatistypically
larger than the DC bias current. In continuous mode,
IGATECHG = f(QT + QB) where QT and QB are the gate
charges of the internal top and bottom switches. Both
the DC bias and gate charge losses are proportional to
supply voltage and thus their effects will be more
pronounced at higher supply voltages.
Other losses including CIN and COUT ESR dissipative
losses,MOSFETswitchinglossesandinductorcorelosses
generally account for less than 2% total additional loss.
Thermal Considerations
In most applications, the LTC1879 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC1879 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction tempera-
ture reaches approximately 150°C, both power switches
will be turned off and the SW nodes will become high
impedance.
1
V
V
= 6V
IN
OUT
= 3.3V
L = 6.8µH
To avoid the LTC1879 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. Normally,
some iterative calculation is required to determine a rea-
sonably accurate value. The temperature rise is given by:
Burst Mode OPERATION
0.1
0.01
0.001
TR = P • θJA
0.0001
0.1
1
10
100
1000
LOAD CURRENT (mA)
where P is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to the
ambient temperature.
1879 F07
Figure 7. Power Lost vs Load Current
The junction temperature is given by:
TJ = TA + TR
1879f
13
LTC1879
W U U
U
APPLICATIO S I FOR ATIO
where TA is the ambient temperature. Because the power
transistor RDS(ON) is a function of temperature, it is
usually necessary to iterate 2 to 3 times through the
equations to achieve a reasonably accurate value for the
junction temperature.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (∆ILOAD • ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT, generating a feedback error signal. The
regulator loop then acts to return VOUT to its steady-state
value. During this recovery time, VOUT can be monitored
for overshoot or ringing that would indicate a stability
problem. The ITH pin can be used for external compensa-
tion as shown in Figure 9. (The capacitor, CC2, is typically
needed for noise decoupling.)
As an example, consider the LTC1879 in dropout at an
input voltage of 5V, a load current of 0.8A and an ambient
temperature of 70°C. From the typical performance graph
of switch resistance, the RDS(ON) of the P-channel switch
at 70°C is 0.38Ω. Therefore, power dissipated by the IC is:
P = I2 • RDS(ON) = 0.243W
For the SSOP package, the θJA is 140°C/W. Thus the
junction temperature of the regulator is:
TJ = 70°C + (0.243)(140) = 104°C
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • CLOAD).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
However, at this temperature, the RDS(ON) is actually
0.42Ω.
Therefore:
TJ = 70°C + (0.269)(140) = 108°C
which is below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (RDS(ON)).
1879f
14
LTC1879
W U U
APPLICATIO S I FOR ATIO
U
PC Board Layout Checklist
3. The high di/dt loop from the top terminal of the input
capacitor, through the power MOSFETs and back to the
input capacitor should be kept as tight as possible to
reduce inductive ringing. Excess inductance can cause
increased stress on the power MOSFET and increase
noise on the input. If low ESR ceramic capacitors are
usedtoreduceinputnoise,placethesecapacitorsclose
to the DUT in order to keep the series inductance to a
minimum.
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. Figure 8 is a
sample of PC board layout for the design example shown
in Figure 9. A 4-layer PC board is used in this design.
Several guidelines are followed in this layout:
1. In order to minimize switching noise and improve
output load regulation, the PGND pins of the LTC1879
shouldbeconnecteddirectlyto1)thenegativeterminal
of the output decoupling capacitors, 2) the negative
terminal of the input capacitor and 3) vias to the ground
plane immediately adjacent to Pins 1, 7 and 10. The
ground trace on the top layer of the PC board should be
as wide and short as possible to minimize series resis-
tance and inductance.
4. Place the small-signal components away from high
frequency switching nodes. In the layout shown in
Figure 8, all of the small-signal components have been
placed on one side of the IC and all of the power
components have been placed on the other.
5. For optimum load regulation and true sensing, the top
of the output resistor divider should connect indepen-
dentlytothetopoftheoutputcapacitor(Kelvinconnec-
tion), staying away from any high dV/dt traces. Place
the divider resistors near the LTC1879 in order to keep
the high impedance FB node short.
2. BewareofgroundloopsinmultiplelayerPCboards. Try
to maintain one central ground node on the board and
use the input capacitor to avoid excess input ripple for
high output current power supplies. If the ground is to
be used for high DC currents, choose a path away from
the small-signal components.
VIAS TO GND PLANE
R
R
SVIN
C
C
C
R
PL
C2
PL
C
C1
VIA CONNECTION TO R
FB1
C
SS
R
PG
R
SS
R
R
FB2
FB1
DUT
L1
C
IN1
C
C
OUT
IN2
V
IN
PGND
V
OUT
1879 F08
VIAS TO GND PLANE
Figure 8. Typical Application and Suggested Layout (Topside Only)
1879f
15
LTC1879
W U U
U
APPLICATIO S I FOR ATIO
Design Example
An 15µH inductor works well for this application. For good
efficiency choose a 1.5A inductor with less than 0.125Ω
series resistance.
As a design example, assume the LTC1879 is used in a
dual lithium-ion battery-powered cellular phone applica-
tion. The VIN will be operating from a maximum of 8.4V
down to about 2.65V. The load current requirement is a
maximumof0.7Abutmostofthetimeitwillbeonstandby
mode, requiring only 2mA. Efficiency at both low and high
load currents is important. Output voltage is 2.5V. With
this information we can calculate L using equation (1),
CIN will require an RMS current rating of at least 0.35A at
temperature and COUT will require an ESR of less than
0.125Ω. In most applications, the requirements for these
capacitors are fairly similar.
For the feedback resistors, choose R2 = 412k. R1 can then
be calculated from equation (2) to be:
1
f ∆I
VOUT
V
IN
VOUT
0.8
L =
VOUT 1–
(3)
R1=
– 1 •R2 = 875.5k,use 887k
( )(
)
L
Substituting VOUT = 2.5V, VIN = 8.4V, ∆IL = 210mA and
f = 550kHz in equation (3) gives:
Figure 9 shows the complete circuit along with its effi-
ciency curve.
2.5V
550kHz • 210mA
2.5V
8.4V
L =
1–
= 15.2µH
1879f
16
LTC1879
W U U
APPLICATIO S I FOR ATIO
U
R
SVIN
10Ω
C
SVIN
13
IN
15
0.1µF
R
PG
SV
SYNC/MODE
100k
14
2
8
9
V
IN
PGOOD
PV
PV
IN
IN
2.65V TO 8.4V
C
IN2
C
IN1
R
SS
10µF
10µF
1M
GND
7
PGND
PGND
RUN/SS
10
C
SS
0.1µF
C
OUT
5
47µF
LTC1879
L1
SWP
SWP
SWN
SWN
15µH
12
6
V
2.5V
0.7A
OUT
16
4
PLL_LPF
11
R1
887k
3
I
V
FB
TH
R2
412k
C
C1
47pF
1
C
1879 F09a
C2
SGND
220pF
R
150k
C
BOLD LINES INDICATE HIGH CURRENT PATHS
C
C
, C : TAIYO YUDEN CERAMIC JMK316BJ106ML
OUT
IN1 IN2
: TDK CERAMIC C4532X5R0J476M
L1: TOKO A921CY-150M
: 0.7A IS THE MAXIMUM OUTPUT CURRENT
V
OUT
Figure 9a. Dual Lithium-Ion/8V Wall Adapter to 2.5V/0.7A Regulator from Design Example
100
V
V
= 3.6V
IN
OUT
= 2.5V
L = 15µH
90
80
70
60
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
1879 F09b
Figure 9b. Efficiency vs Output Current for Design Example
1879f
17
LTC1879
U
TYPICAL APPLICATIO
Dual Li-Ion to 1.8V/1A Regulator Using All Ceramic Capacitors
R
SVIN
10Ω
C
SVIN
13
IN
15
0.1µF
R
PG
SV
SYNC/MODE
100k
14
2
8
9
V
IN
PGOOD
PV
PV
IN
IN
3V TO 8.4V
C
IN2
C
IN1
R
SS
10µF
10µF
1M
GND
7
PGND
PGND
RUN/SS
10
C
SS
0.1µF
C
OUT
47µF
5
LTC1879
L1
SWP
SWP
SWN
SWN
8.2µH
12
6
V
1.8V
1A
OUT
16
4
PLL_LPF
11
R1
523k
3
I
V
FB
TH
R2
412k
C
C1
1
47pF
C
1879 TA02
C2
SGND
220pF
R
C
150k
BOLD LINES INDICATE HIGH CURRENT PATHS
C
C
, C : TAIYO YUDEN CERAMIC LMK325BJ106MN
OUT
IN1 IN2
: TDK CERAMIC C4532X5R0J476M
L1: TOKO A916CY-8R2M
: 1A IS THE MAXIMUM OUTPUT CURRENT
V
OUT
Efficiency vs Output Current
100
V
= 3.6V
IN
90
80
V
= 5V
IN
70
60
V
= 7.2V
IN
50
40
V
= 1.8V
OUT
Burst Mode OPERATION
0.1
1
10 100 1000
OUTPUT CURRENT (mA)
1879 TA04
1879f
18
LTC1879
U
PACKAGE DESCRIPTION
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.053 – .068
(1.351 – 1.727)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
(0.203 – 0.305)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
GN16 (SSOP) 0502
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1879f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.
19
LTC1879
U
TYPICAL APPLICATIO
5-Cell NiMH to 3.3V/0.25A ZETA Regulator Using All Ceramic Capacitors
R
SVIN
10Ω
C
SVIN
13
IN
15
0.1µF
R
PG
SV
SYNC/MODE
100k
14
2
8
9
V
IN
PGOOD
PV
PV
IN
2.8V TO 7.5V
C
IN2
10µF
C
IN1
10µF
R
SS
IN
1M
GND
7
PGND
PGND
RUN/SS
10
C
SS
0.1µF
L1
C
OUT
47µF
•
5
LTC1879
SWP
SWP
SWN
SWN
12
6
L1
4.7µH
C
C
16
4
10µF
V
OUT
PLL_LPF
3.3V
11
0.25A
R1
1.3M
3
I
TH
V
FB
SGND
R2
C
C1
47pF
412k
1
C
1879 TA03
C2
220pF
R
C
150k
BOLD LINES INDICATE HIGH CURRENT PATHS
C : TAIYO YUDEN CERAMIC LMK325BJ106MN
C
C
, C : TAIYO YUDEN CERAMIC LMK325BJ106MN
IN1 IN2
OUT
C
: TDK CERAMIC C4532X5R0J476M
L1: COILTRONICS CTX5-4
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25V, 2.75A (I ), 1.25MHz, High Efficiency
= 3V to 25V, V
= 1.20V, I = 1mA, I = 15µA, SO-8, TSSOP16E
OUT(MIN) O SD
OUT
Step-Down DC/DC Converter
LT1766/LT1956
LT1767
60V, 1.2A (I ), 200kHz/500kHz, High Efficiency
= 5.5V to 60V, V
= 1.20V, I = 2.5mA, I = 25µA, TSSOP16/E
OUT
OUT(MIN) O SD
Step-Down DC/DC Converter
25V, 1.2A (I ), 1.25kHz, High Efficiency
= 3V to 25V, V
= 1.20V, I = 1mA, I = 6µA, SO-8, MS8/E
OUT
OUT(MIN) O SD
Step-Down DC/DC Converter
LTC®1875
LTC1877
LT1940
1.5A, (I ), 550kHz, Synchronous Step-Down
= 2.7V to 6V, V
= 0.8V, I = 15µA, I = <1µA, TSSOP-16
OUT(MIN) O SD
OUT
DC/DC Converter
600mA, (I ), 550kHz, Synchronous
= 2.7V to 10V, V
= 0.8V, I = 10µA, I = <1µA, MS8
OUT(MIN) O SD
OUT
Step-Down DC/DC Converter
Dual Output 1.4A (I ), Constant 1.1MHz,
= 3V to 25V, V
= 1.2V, I = 2.5µA, I = <1µA, TSSOP-16E
OUT
OUT(MIN) O SD
High Efficiency Step-Down DC/DC Converter
LTC3405/LTC3405A 300mA (I ), 1.5MHz, Synchronous
= 2.7V to 6V, V
= 0.8V, I = 20µA, I = <1µA, ThinSOT
OUT(MIN) O SD
OUT
Step-Down DC/DC Converters
LTC3406/LTC3406B 600mA (I ), 1.5MHz, Synchronous
= 2.5V to 5.5V, V
= 2.5V to 5.5V, V
= 2.5V to 5.5V, V
= 2.5V to 5.5V, V
= 0.6V, I = 20µA, I = <1µA, ThinSOT
O SD
OUT
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
Step-Down DC/DC Converters
LTC3411
LTC3412
LTC3430
1.25A (I ), 4MHz, Synchronous
= 0.8V, I = 60µA, I = <1µA, 10-Pin MS
O SD
OUT
Step-Down DC/DC Converter
2.5A (I ), 4MHz, Synchronous
= 0.8V, I = 60µA, I = <1µA, TSSOP16E
O SD
OUT
Step-Down DC/DC Converter
2.5A (I ), 4MHz Synchronous
= 0.8V, I = 60µA, I = <1µA, TSSOP16E
O SD
OUT
Step-Down DC/DC Converter
ThinSOT is a trademark of Linear Technology Corporation.
1879f
LT/TP 0303 2K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
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