LTC1929_15_技术文档

LTC1929/LTC1929-PG

2-Phase, High Efficiency,

Synchronous Step-Down

Switching Regulators

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FEATURES

DESCRIPTIO

The LTC^®1929/LTC1929-PG are 2-phase, single output,

synchronous step-down current mode switching regula-

torcontrollersthatdriveN-channelexternalpowerMOSFET

stages in a phase-lockable fixed frequency architecture.

The 2-phase controllers drive their two output stages out

of phase at frequencies up to 300kHz to minimize the RMS

ripple currents in both input and output capacitors. The

2-phase technique effectively multiplies the fundamental

frequency by two, improving transient response while

operating each channel at an optimum frequency for

efficiency. Thermal design is also simplified.

■

2-Phase Single Output Controller

■

Reduces Required Input Capacitance and Power

Supply Induced Noise

■

Current Mode Control Ensures Current Sharing

■

Phase-Lockable Fixed Frequency: 150kHz to 300kHz

■

True Remote Sensing Differential Amplifier

OPTI-LOOP^TMCompensation Improves Transient

■

Response

■

±

1% Output Voltage Accuracy

■

Power Good Output Voltage Monitor (LTC1929-PG)

Wide V_INRange: 4V to 36V Operation

Very Low Dropout Operation: 99% Duty Cycle

Adjustable Soft-Start Current Ramping

Internal Current Foldback

Short-Circuit Shutdown Timer with Defeat Option

Overvoltage Soft-Latch Eliminates Nuisance Trips

An internal differential amplifier provides true remote

sensing of the regulated supply’s positive and negative

output terminals as required by high current applications.

The RUN/SS pin provides soft-start and a defeatable,

timed, latched short-circuit shutdown to shut down both

channels. Internal foldback current limit provides protec-

tion for the external synchronous MOSFETs in the event of

an output fault. OPTI-LOOP compensation allows the

transient response to be optimized over a wide range of

output capacitance and ESR values.

^{Available in 28-L}U^{ead SSOP Package}

APPLICATIO S

■

Desktop Computers

■

Internet/Network Servers

■

Large Memory Arrays

, LTC and LT are registered trademarks of Linear Technology Corporation.

OPTI-LOOP is a trademark of Linear Technology Corporation.

■

DC Power Distribution Systems

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TYPICAL APPLICATIO

10Ω

V

IN

5V TO 28V

10µF

35V

0.1µF

CERAMIC

×4

V

TG1

BOOST1

SW1

IN

0.1µF

0.47µF

LTC1929

L1

1µH

0.002Ω

RUN/SS

BG1

D1

PGND

+

1000pF

SENSE1

I

TH

–

10k

100pF

16k

TG2

BOOST2

SW2

SGND

V

OUT

0.47µF

1.6V/40A

L2

1µH

0.002Ω

V

BG2

D2

DIFFOUT

EAIN

–

INTV

CC

+

C

10µF

OUT

+

V

SENSE2

1000µF

4V

OS

16k

+

–

V

OS

×2

C

OUT

: T510E108K004AS L1, L2: CEPH149-1ROMC

1929 F01

Figure 1. High Current 2-Phase Step-Down Converter

1

LTC1929/LTC1929-PG

W W

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ABSOLUTE AXI U RATI GS

(Note 1)

PACKAGE/ORDER I FOR ATIO

TOP VIEW

ORDER PART

NUMBER

Input Supply Voltage (V_IN).........................36V to –0.3V

Topside Driver Voltages (BOOST1,2).........42V to –0.3V

Switch Voltage (SW1, 2) .............................36V to –5 V

SENSE1⁺, SENSE2⁺, SENSE1^–,

1

2

NC

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RUN/SS

+

TG1

SENSE1

LTC1929CG

–

3

SW1

BOOST1

SENSE1

LTC1929CG-PG

LTC1929IG

4

EAIN

PLLFLTR

PLLIN

SENSE2^–Voltages........................ (1.1)INTV_CCto –0.3V

5

V

IN

EAIN, V_OS⁺, V_OS^–, EXTV_CC, INTV_CC,

6

BG1

LTC1929IG-PG

RUN/SS, AMPMD Voltages..........................7V to –0.3V

Boosted Driver Voltage (BOOST-SW) ..........7V to –0.3V

PLLFLTR, PLLIN, V_DIFFOUTVoltages .... INTV_CCto –0.3V

I_THVoltage................................................2.7V to –0.3V

Peak Output Current <1µs(TGL1,2, BG1,2)................ 3A

INTV_CCRMS Output Current................................ 50mA

Operating Ambient Temperature Range

LTC1929C.................................................. 0°C to 85°C

LTC1929I .............................................. –40°C to 85°C

Junction Temperature (Note 2)............................. 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

7

EXTV

CC

NC

8

INTV

CC

I

TH

9

PGND

BG2

SGND

10

11

12

13

14

V

DIFFOUT

–

BOOST2

SW2

V

OS

+

–

TG2

SENSE2

+

AMPMD*

G PACKAGE

28-LEAD PLASTIC SSOP

*PGOOD ON LTC1929-PG

T_JMAX= 125°C, θ_JA= 95°C/W

Consult factory for Military grade parts.

The ● denotes the specifications which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V, V_RUN/SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loop

V

Regulated Feedback Voltage

(Note 3); I Voltage = 1.2V

●

0.792

0.800

0.808

V

EAIN

TH

–

Maximum Current Sense Threshold

V

= 5V

62

65

75

88

85

mV

SENSEMAX

SENSE

= 5V, LTC1929 Only

SENSE1, 2

I

Feedback Current

(Note 3)

–5

–50

nA

INEAIN

V

Output Voltage Load Regulation

(Note 3)

LOADREG

Measured in Servo Loop; I Voltage = 0.7V

Measured in Servo Loop; I Voltage = 2V

●

0.05

–0.1

0.5

–0.5

%

TH

V

Reference Voltage Line Regulation

Output Overvoltage Threshold

Undervoltage Lockout

V

= 3.6V to 30V (Note 3)

IN

0.002

0.86

3.5

0.02

0.88

4

%/V

V

REFLNREG

OVL

Measured at V

0.84

3

EAIN

UVLO

V

Ramping Down

V

IN

TH

g

Transconductance Amplifier g

I

= 1.2V; Sink/Source 5µA; (Note 3)

3

mmho

V/mV

m

Transconductance Amplifier Gain

= 1.2V; (g xZ ; No Ext Load); (Note 3)

1.5

mOL

m

L

I

Input DC Supply Current

Normal Mode

Shutdown

(Note 4)

Q

EXTV Tied to V ; V

= 5V

470

20

µA

CC

OUT OUT

V

= 0V

40

RUN/SS

I

Soft-Start Charge Current

RUN/SS Pin ON Threshold

RUN/SS Pin Latchoff Arming

= 1.9V

–0.5

1.0

–1.2

1.5

µA

V

RUN/SS

V

Rising

1.9

4.5

RUN/SS

Rising from 3V

4.1

V

RUN/SSLO

2

LTC1929/LTC1929-PG

The ● denotes the specifications which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V, V_RUN/SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I

RUN/SS Discharge Current

Soft Short Condition V

= 0.5V;

0.5

2.0

4.0

µA

SCL

EAIN

V

= 4.5V

RUN/SS

I

Shutdown Latch Disable Current

Total Sense Pins Source Current

Maximum Duty Factor

V

= 0.5V

EAIN

1.6

–60

99.5

5

µA

%

SDLHO

SENSE

Each Channel: V

In Dropout

–

– = V + + = 0V

SENSE1 , 2

–85

98

SENSE1 , 2

DF

MAX

Top Gate Transition Time:

Rise Time

Fall Time

TG1, 2 t

C

= 3300pF

30

40

90

ns

r

f

LOAD

Bottom Gate Transition Time:

Rise Time

Fall Time

BG1, 2 t

C

= 3300pF

30

20

90

ns

r

f

LOAD

TG/BG t

Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

1D

C

= 3300pF Each Driver

90

ns

LOAD

BG/TG t

Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

2D

90

ns

LOAD

t

Minimum On-Time

Tested with a Square Wave (Note 6)

180

ON(MIN)

Internal V Regulator

CC

V

Internal V Voltage

6V < V < 30V; V = 4V

EXTVCC

4.8

4.5

5.0

0.2

120

80

5.2

1.0

V

%

INTVCC

CC

IN

INT

INTV Load Regulation

I

= 0 to 20mA; V

= 4V

EXTVCC

LDO

CC

EXT

EXTV Voltage Drop

= 20mA; V

= 20mA, V

= 5V

240

160

mV

V

CC

EXTVCC

= 5V, LTC1929-PG

EXTVCC

EXT-PG

EXTV Voltage Drop

CC

EXTV Switchover Voltage

= 20mA, EXTV Ramping Positive

●

4.7

0.2

EXTVCC

LDOHYS

CC

EXTV Switchover Hysteresis

= 20mA, EXTV Ramping Negative

V

CC

Oscillator and Phase-Locked Loop

f

Nominal Frequency

Lowest Frequency

Highest Frequency

PLLIN Input Resistance

V

= 1.2V

= 0V

190

120

280

220

140

310

50

250

160

360

kHz

kΩ

NOM

LOW

HIGH

PLLFLTR

≥ 2.4V

R

PLLIN

I

Phase Detector Output Current

Sinking Capability

Sourcing Capability

PLLFLTR

f

< f

> f

–15

15

µA

PLLIN

OSC

R

Controller 2-Controller 1 Phase

180

Deg

RELPHS

PGOOD Output (LTC1929-PG Only)

V

PGOOD Voltage Low

PGOOD Leakage Current

PGOOD Trip Level

I

= 2mA

= 5V

0.1

0.3

V

PGL

PGOOD

I

V

±1

µA

PGOOD

V

with Respect to Set Output Voltage

EAIN

PG

V

Ramping Negative

Ramping Positive

–6

6

–7.5

7.5

–9.5

9.5

%

EAIN

Differential Amplifier/Op Amp Gain Block (Note 5)

A

Gain

Differential Amp Mode

Differential Amp Mode; 0V < V < 5V

0.995

46

1

1.005

6

V/V

dB

DA

CMRR

Common Mode Rejection Ratio

Input Resistance

Input Offset Voltage

55

80

DA

CM

R

Differential Amp Mode; Measured at V + Input

kΩ

mV

IN

OS

V

Op Amp Mode; V = 2.5V; V

= 5V;

OS

CM

DIFFOUT

I

= 1mA (LTC1929 Only)

DIFFOUT

3

LTC1929/LTC1929-PG

The ● denotes the specifications which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V, V_RUN/SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

30

MAX

UNITS

nA

I

Input Bias Current

Open Loop DC Gain

Op Amp Mode (LTC1929 Only)

200

B

A

Op Amp Mode; 0.7V ≤ V

< 10V

5000

V/mV

OL

DIFFOUT

(LTC1929 Only)

V

Common Mode Input Voltage Range

Common Mode Rejection Ratio

Power Supply Rejection Ratio

Maximum Output Current

Maximum Output Voltage

Gain-Bandwidth Product

Slew Rate

Op Amp Mode (LTC1929 Only)

Op Amp Mode; 0V < V < 3V (LTC1929 Only)

0

3

V

dB

CM

CMRR

70

10

90

35

11

2

OA

CM

PSRR

Op Amp Mode; 6V < V < 30V (LTC1929 Only)

dB

OA

IN

I

Op Amp Mode; V

= 0V (LTC1929 Only)

= 1mA (LTC1929 Only)

mA

V

CL

DIFFOUT

V

Op Amp Mode; I

O(MAX)

GBW

SR

MHz

V/µs

Op Amp Mode; R = 2k (LTC1929 Only)

5

L

Note 1: Absolute Maximum Ratings are those values beyond which the

life of a device may be impaired.

Note 5: When the AMPMD pin is high (default for the LTC1929-PG), the

LTC1929 IC pins are connected directly to the internal op amp inputs.

When the AMPMD pin is low, internal MOSFET switches connect four

40k resistors around the op amp to create a standard unity-gain

differential amp.

Note 2: T is calculated from the ambient temperature T and power

J

A

dissipation P according to the following formulas:

D

LTC1929CG: T = T + (P • 95°C/W)

J

A

D

Note 6: Minimum on-time condition corresponds to the on inductor

Note 3: The LTC1929 is tested in a feedback loop that servos V to a

ITH

peak-to-peak ripple current ≥40% of I

(see minimum on-time

MAX

specified voltage and measures the resultant V

.

EAIN

considerations in the Applications Information section).

Note 4: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

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TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Output Current

(Figure 13)

Efficiency vs Output Current

(Figure 13)

Efficiency vs V_IN

(Figure 13)

100

80

60

40

20

0

100

90

80

70

60

50

100

80

60

40

20

0

V

OUT

= 5V

EXTVCC

I

= 20A

V

= 5V

EXTVCC

V

OUT

= 2V

V

= 5V

IN

V

= 0V

EXTVCC

= 8V

V

= 1.6V

OUT

= 12V

= 20V

V

= 12V

= 2V

V

= 2V

EXTVCC

IN

OUT

= 0V

FREQ = 200kHz

10 100

OUTPUT CURRENT (A)

FREQ = 200kHz

10 100

OUTPUT CURRENT (A)

0.1

1

0.1

1

5

10

15

20

V

IN

(V)

1929 G01

1929 G02

1929 G03

4

LTC1929/LTC1929-PG

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TYPICAL PERFOR A CE CHARACTERISTICS

Supply Current vs Input Voltage

and Mode

INTV_CCand EXTV_CCSwitch

Voltage vs Temperature

EXTV_CCVoltage Drop

1000

800

600

400

200

0

5.05

250

200

150

100

50

V

= 5V

OUT

EXTVCC

INTV VOLTAGE

CC

= V

OUT

5.00

4.95

4.90

4.85

4.80

4.75

4.70

LTC1929

LTC1929-PG

ON

EXTV SWITCHOVER THRESHOLD

CC

SHUTDOWN

10 15

INPUT VOLTAGE (V)

0

5

20

25

30

35

0

10

20

30

40

50

–50 –25

0

25

50

TEMPERATURE (°C)

75

100 125

CURRENT (mA)

1929 G04

1929 G05

1929 G06

Maximum Current Sense Threshold

vs Percent on Nominal Output

Voltage (Foldback)

Maximum Current Sense Threshold

vs Duty Factor

Internal 5V LDO Line Reg

75

50

25

0

5.1

5.0

80

70

60

50

40

30

20

10

0

I

= 1mA

LOAD

4.9

4.8

4.7

4.6

4.5

4.4

0

20

40

60

80

100

20

INPUT VOLTAGE (V)

30

35

50

0

5

10

15

25

0

25

75

100

DUTY FACTOR (%)

PERCENT ON NOMINAL OUTPUT VOLTAGE (%)

1929 G08

1929 G07

1929 G09

Maximum Current Sense Threshold

vs V_RUN/SS(Soft-Start)

Maximum Current Sense Threshold

vs Sense Common Mode Voltage

Current Sense Threshold

vs I_THVoltage

80

76

72

68

64

60

90

80

60

40

20

V

= 1.6V

SENSE(CM)

70

60

50

40

30

20

10

0

–10

–20

–30

0

1

2

3

4

5

6

0

1

2

3

4

5

0

0.5

1

1.5

(V)

2

2.5

V

(V)

COMMON MODE VOLTAGE (V)

V

ITH

RUN/SS

1929 G10

1929 G11

1929 G12

5

LTC1929/LTC1929-PG

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Load Regulation

V_ITHvs V_RUN/SS

SENSE Pins Total Source Current

0.0

–0.1

–0.2

–0.3

–0.4

2.5

2.0

1.5

1.0

100

50

V

= 0.7V

V

= 15V

OSENSE

IN

FIGURE 1

0

–50

–100

0.5

0

1

2

3

4

5

0

1

2

3

4

5

6

0

2

4

6

V

(V)

LOAD CURRENT (A)

V

COMMON MODE VOLTAGE (V)

RUN/SS

SENSE

1629 G13

1629 G14

1629 G15

Maximum Current Sense

Threshold vs Temperature

RUN/SS Current vs Temperature

80

78

76

74

72

70

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

–

V

= 5V

SENSE

0

–50 –25

0

25

50

75 100 125

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

1929 G16

1929 G17

Soft-Start (Figure 13)

Load Step (Figure 13)

V_ITH

1V/DIV

V_OUT

50mV/DIV

V_OUT

2V/DIV

20A

I_OUT

V_RUN/SS

2V/DIV

10A/DIV

0A

100ms/DIV

1929 G18

20µs/DIV

1929 G19

6

LTC1929/LTC1929-PG

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TYPICAL PERFOR A CE CHARACTERISTICS

Current SENSE Pin Input Current

vs Temperature

EXTV_CCSwitch Resistance

vs Temperature

Oscillator Frequency

vs Temperature

35

33

31

29

27

25

10

8

350

V

OUT

= 5V

V

= 5V

FREQSET

300

250

200

150

100

50

V

= OPEN

= 0V

FREQSET

6

V

FREQSET

4

2

0

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

TEMPERATURE (°C)

1929 G20

1929 G21

1929 G22

Undervoltage Lockout

vs Temperature

V_RUN/SSShutdown Latch

Thresholds vs Temperature

4.5

4.0

3.5

3.50

3.45

3.40

3.35

LATCH ARMING

3.0

2.5

2.0

1.5

1.0

0.5

LATCHOFF

THRESHOLD

3.30

3.25

3.20

0

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

1929 G23

1929 G24

7

LTC1929/LTC1929-PG

U

PI FU CTIO S

RUN/SS (Pin 1): Combination of Soft-Start, Run Control

Input and Short-Circuit Detection Timer. A capacitor to

groundatthispinsetstheramptimetofullcurrentoutput.

Forcing this pin below 0.8V causes the IC to shut down all

internal circuitry. All functions are disabled in shutdown.

SENSE1⁺, SENSE2⁺(Pins 2,14): The (+) Input to the

Differential Current Comparators. The I_THpin voltage and

built-in offsets between SENSE^–and SENSE⁺pins in

conjunction with R_SENSEset the current trip threshold.

differential amplifier (default for the LTC1929-PG) or an

uncommitted Op Amp.

AMPMD (Pin 15): (LTC1929 Only) This Logic Input pin

controls the connections of internal precision resistors

that configure the operational amplifier as a unity-gain

differential amplifier.

PGOOD (Pin 15): (LTC1929-PG Only) Open-Drain Logic

Output. PGOOD is pulled to ground when the voltage on

the EAIN pin is not within ±7.5% of its set point.

SENSE1^–, SENSE2^–(Pins 3, 13): The (–) Input to the

Differential Current Comparators.

TG2, TG1 (Pins 16, 27): High Current Gate Drives for Top

N-Channel MOSFETS. These are the outputs of floating

drivers with a voltage swing equal to INTV_CCsuperim-

posed on the switch node voltage SW.

EAIN (Pin 4): Input to the Error Amplifier that compares

thefeedbackvoltagetotheinternal0.8Vreferencevoltage.

This pin is normally connected to a resistive divider from

the output of the differential amplifier (DIFFOUT).

SW2, SW1 (Pins 17, 26): Switch Node Connections to

Inductors. Voltage swing at these pins is from a Schottky

diode (external) voltage drop below ground to V_IN.

PLLFLTR (Pin 5): The Phase-Locked Loop’s Low Pass

Filter is tied to this pin. Alternatively, this pin can be driven

with an AC or DC voltage source to vary the frequency of

the internal oscillator.

BOOST2, BOOST1 (Pins 18, 25): Bootstrapped Supplies

to the Topside Floating Drivers. Capacitors are connected

between the Boost and Switch pins, and Schottky diodes

are tied between the Boost and INTV_CCpins.

PLLIN (Pin 6): External Synchronization Input to Phase

Detector. This pin is internally terminated to SGND with

50kΩ. The phase-locked loop will force the rising top gate

signal of controller 1 to be synchronized with the rising

edge of the PLLIN signal.

BG2, BG1 (Pins 19, 23): Voltage Swing High Current Gate

Drives for Bottom Synchronous N-Channel MOSFETS.

Voltage swing at these pins is from ground to INTV_CC.

PGND(Pin20):DriverPowerGround.Connectstosources

of bottom N-channel MOSFETS and the (–) terminals of

C_IN.

NC (Pins 7, 28): Not connected.

I_TH(Pin 8): Error Amplifier Output and Switching Regula-

torCompensationPoint.Bothcurrentcomparator’sthresh-

oldsincreasewiththiscontrolvoltage. Thenormalvoltage

range of this pin is from 0V to 2.4V

INTV_CC(Pin 21): Output of the Internal 5V Linear Low

Dropout Regulator and the EXTV_CCSwitch. The driver and

control circuits are powered from this voltage source.

Decouple to power ground with a 1µF ceramic capacitor

placed directly adjacent to the IC and minimum of 4.7µF

additional tantalum or other low ESR capacitor.

SGND (Pin 9): Signal Ground, common to both control-

lers, must be routed separately from the input switched

current ground path to the common (–) terminal(s) of the

C_OUTcapacitor(s).

EXTV_CC(Pin 22): External Power Input to an Internal

Switch . This switch closes and supplies INTV_CC,bypass-

ing the internallow dropout regulator whenever EXTV_CCis

higher than 4.7V. See EXTV_CCConnection in the Applica-

tions Information section. Do not exceed 7V on this pin

and ensure V_EXTVCC≤ V_IN.

V_DIFFOUT(Pin 10): Output of a Differential Amplifier that

provides true remote output voltage sensing. This pin

normally drives an external resistive divider that sets the

output voltage.

+

V_OS^–, V_OS(Pins 11, 12): Inputs to an Operational

Amplifier. Internal precision resistors capable of being

electronically switched in or out can configure it as a

V_IN(Pin24):MainSupplyPin.Shouldbecloselydecoupled

to the IC’s signal ground pin.

8

LTC1929/LTC1929-PG

U

U W

FU CTIO AL DIAGRA

LTC1929-PG OPTIONAL PGOOD HOOKUP

DIFFOUT

PGOOD

–

+

0.86V

–

V

OS

EAIN

A1

–

+

–

+

0.74V

OS

INTV

CC

V

IN

PLLIN

PHASE DET

F

IN

D

C

DUPLICATE FOR SECOND

CONTROLLER CHANNEL

B

BOOST

TG

50k

PLLFLTR

R

C

LP

B

DROP

OUT

DET

+

CLK1

CLK2

TOP

BOT

C

IN

OSCILLATOR

BOT

FORCE BOT

LP

SW

S

Q

SWITCH

LOGIC

INTV

CC

R

BG

PGND

LTC1929 ONLY

–

V

OS

SHDN

A1

+

–

+

OS

INTV

CC

I

1

–

L

–

+

SENSE

30k

4(V

)

FB

–

C

OUT

R

SENSE

AMPMD

DIFFOUT

SLOPE

COMP

0V POSITION

45k

2.4V

V

OUT

EAIN

R1

V

FB

–

+

EA

OV

V

0.8V

REF

0.80V

0.86V

V

IN

R2

V

IN

+

–

+

–

4.7V

5V

LDO

REG

C

V

IN

I

TH

EXTV

INTV

CC

1.2µA

SHDN

RUN

SOFT-

START

R

C

CC

5V

4(V

FB

)

+

6V

RUN/SS

INTERNAL

SUPPLY

SGND

C

SS

1929 FBD

9

LTC1929/LTC1929-PG

U

(Refer to Functional Diagram)

OPERATIO

Main Control Loop

Low Current Operation

The LTC1929 uses a constant frequency, current mode

step-down architecture with inherent current sharing.

During normal operation, the top MOSFET is turned on

each cycle when the oscillator sets the RS latch, and

turned off when the main current comparator, I₁, resets

the RS latch. The peak inductor current at which I₁resets

the RS latch is controlled by the voltage on the I_THpin,

which is the output of the error amplifier EA. The differen-

tialamplifier,A1,producesasignalequaltothedifferential

voltage sensed across the output capacitor but re-refer-

ences it to the internal signal ground (SGND) reference.

The EAIN pin receives a portion of this voltage feedback

signal at the DIFFOUT pin which is compared to the

internalreferencevoltagebytheEA.Whentheloadcurrent

increases, it causes a slight decrease in the EAIN pin

voltagerelative to the 0.8V reference, which in turn causes

the I_THvoltage to increase until the average inductor

current matches the new load current. After the top

MOSFET has turned off, the bottom MOSFET is turned on

for the rest of the period.

The LTC1929 operates in a continuous, PWM control

mode. The resulting operation at low output currents

optimizes transient response at the expense of substantial

negative inductor current during the latter part of the

period. The level of ripple current is determined by the

inductor value, input voltage, output voltage, and fre-

quency of operation.

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be

synchronized to an external source via the PLLIN pin. The

output of the phase detector at the PLLFLTR pin is also the

DC frequency control input of the oscillator that operates

over a 140kHz to 310kHz range corresponding to a DC

voltageinputfrom0Vto2.4V.Whenlocked,thePLLaligns

the turn on of the top MOSFET to the rising edge of the

synchronizingsignal.WhenPLLINisleftopen,thePLLFLTR

pingoeslow,forcingtheoscillatortominimumfrequency.

InputcapacitanceESRrequirementsandefficiencylosses

are substantially reduced because the peak current drawn

from the input capacitor is effectively divided by two and

power loss is proportional to the RMS current squared. A

two stage, single output voltage implementation can re-

duce input path power loss by 75% and radically reduce

the required RMS current rating of the input capacitor(s).

The top MOSFET drivers are biased from floating boot-

strap capacitor C_B, which normally is recharged during

each off cycle through an external Schottky diode. When

V_INdecreasestoavoltageclosetoV_OUT,however,theloop

may enter dropout and attempt to turn on the top MOSFET

continuously. A dropout detector detects this condition

and forces the top MOSFET to turn off for about 400ns

every 10th cycle to recharge the bootstrap capacitor.

INTV_CC/EXTV_CCPower

Power for the top and bottom MOSFET drivers and most

of the IC circuitry is derived from INTV_CC. When the

EXTV_CCpin is left open, an internal 5V low dropout

regulator supplies INTV_CCpower. If the EXTV_CCpin is

taken above 4.7V, the 5V regulator is turned off and an

internalswitchisturnedonconnectingEXTV_CCtoINTV_CC.

This allows the INTV_CCpower to be derived from a high

efficiency external source such as the output of the regu-

lator itself or a secondary winding, as described in the

Applications Information section. An external Schottky

diode can be used to minimize the voltage drop from

EXTV_CCto INTV_CCin applications requiring greater than

the specified INTV_CCcurrent. Voltages up to 7V can be

applied to EXTV_CCfor additional gate drive capability.

The main control loop is shut down by pulling Pin 1 (RUN/

SS) low. Releasing RUN/SS allows an internal 1.2µA

current source to charge soft-start capacitor C_SS. When

C_SSreaches1.5V,themaincontrolloopisenabledwiththe

I_THvoltageclampedatapproximately30%ofitsmaximum

value. As C_SScontinues to charge, I_THis gradually re-

leased allowing normal operation to resume. When the

RUN/SS pin is low, all LTC1929 functions are shut down.

IfV_OUThasnotreached70%ofitsnominalvaluewhenC_SS

has charged to 4.1V, an overcurrent latchoff can be

invoked as described in the Applications Information

section.

10

LTC1929/LTC1929-PG

U

(Refer to Functional Diagram)

OPERATIO

Differential Amplifier

output meets the ±7.5% requirement, the MOSFET is

turned off within 10µs and the pin is allowed to be pulled

up by an external source.

This amplifier provides true differential output voltage

sensing. Sensing both V_OUT⁺and V_OUT^–benefits regula-

tion in high current applications and/or applications hav-

ing electrical interconnection losses. The AMPMD pin

(LTC1929only)allowsselectionofinternal,precisionfeed-

backresistorsforhighcommonmoderejectiondifferencing

applications, or direct access to the actual amplifier inputs

withouttheseinternalfeedbackresistorsforotherapplica-

tions. The AMPMD pin is grounded to connect the internal

precision resistors in a unity-gain differencing application

(default for the LTC1929-PG), or tied to the INTV_CCpin to

bypasstheinternalresistorsandmaketheamplifierinputs

directlyavailable.Theamplifierisaunity-gainstable,2MHz

gain-bandwidth, >120dB open-loop gain design. The am-

plifier has an output slew rate of 5V/µs and is capable of

driving capacitive loads with an output RMS current typi-

cally up to 25mA. The amplifier is not capable of sinking

current and therefore must be resistively loaded to do so.

Short-Circuit Detection

The RUN/SS capacitor is used initially to limit the inrush

current from the input power source. Once the controllers

have been given time, as determined by the capacitor on

the RUN/SS pin, to charge up the output capacitors and

provide full load current, the RUN/SS capacitor is then

usedasashort-circuittimeoutcircuit.Iftheoutputvoltage

falls to less than 70% of its nominal output voltage the

RUN/SS capacitor begins discharging assuming that the

output is in a severe overcurrent and/or short-circuit

condition. If the condition lasts for a long enough period

as determined by the size of the RUN/SS capacitor, the

controller will be shut down until the RUN/SS pin voltage

is recycled. This built-in latchoff can be overidden by

providing a current >5µA at a compliance of 5V to the

RUN/SS pin. This current shortens the soft-start period

but also prevents net discharge of the RUN/SS capacitor

during a severe overcurrent and/or short-circuit condi-

tion.Foldbackcurrentlimitingisactivatedwhentheoutput

voltage falls below 70% of its nominal level whether or not

the short-circuit latchoff circuit is enabled.

Power Good (PGOOD) Pin (LTC1929-PG Only)

The PGOOD pin is connected to an open drain of a

MOSFET.TheMOSFETturnsonandpullsthepinlowwhen

the output is not within ±7.5% of its nominal output level

as determined by its resistive feedback divider. When the

U

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APPLICATIO S I FOR ATIO

ThebasicLTC1929applicationcircuitisshowninFigure 1

on the first page. External component selection is driven

by the load requirement, and begins with the selection of

R_{SENSE1, 2}. Once R_{SENSE1, 2}are known, L1 and L2 can be

chosen. Next, the power MOSFETs and D1 and D2 are

selected. The operating frequency and the inductor are

chosen based mainly on the amount of ripple current.

Finally, C_INis selected for its ability to handle the input

ripple current (that PolyPhase^TMoperation minimizes) and

C_OUTis chosen with low enough ESR to meet the output

ripplevoltageandloadstepspecifications(alsominimized

with PolyPhase). Current mode architecture provides in-

herent current sharing between output stages. The circuit

showninFigure 1canbeconfiguredforoperationuptoan

input voltage of 28V (limited by the external MOSFETs).

R_SENSESelection For Output Current

R_{SENSE1, 2}are chosen based on the required output

current. The LTC1929 current comparator has a maxi-

mum threshold of 75mV/R_SENSEand an input common

mode range of SGND to 1.1( INTV_CC). The current com-

parator threshold sets the peak inductor current, yielding

a maximum average output current I_MAXequal to the peak

value less half the peak-to-peak ripple current, ∆I_L.

Allowing a margin for variations in the LTC1929 and

external component values yields:

R_SENSE= 2(50mV/I_MAX

)

PolyPhase is a trademark of Linear Technology Corporation.

11

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APPLICATIO S I FOR ATIO

When using the controller in very low dropout conditions,

the maximum output current level will be reduced due to

internal compensation required to meet stability criterion

for buck regulators operating at greater than 50% duty

factor. A curve is provided to estimate this reduction in

peak output current level depending upon the operating

duty factor.

MOSFET gate charge and transition losses. In addition to

this basic tradeoff, the effect of inductor value on ripple

currentandlowcurrentoperationmustalsobeconsidered.

The PolyPhase approach reduces both input and output

ripplecurrentswhileoptimizingindividualoutputstagesto

runatalowerfundamentalfrequency,enhancingefficiency.

Theinductorvaluehasadirecteffectonripplecurrent.The

inductor ripple current ∆I_Lper individual section, N,

decreases with higher inductance or frequency and in-

Operating Frequency

The LTC1929 uses a constant frequency, phase-lockable

architecture with the frequency determined by an internal

capacitor. This capacitor is charged by a fixed current plus

an additional current which is proportional to the voltage

applied to the PLLFLTR pin. Refer to Phase-Locked Loop

and Frequency Synchronization in the Applications Infor-

mation section for additional information.

creases with higher V_INor V_OUT

:

V_OUT

fL

V_OUT

V

IN

∆I_L=

1−

where f is the individual output stage operating frequency.

In a 2-phase converter, the net ripple current seen by the

output capacitor is much smaller than the individual

inductor ripple currents due to the ripple cancellation. The

details on how to calculate the net output ripple current

can be found in Application Note 77.

A graph for the voltage applied to the PLLFLTR pin vs

frequency is given in Figure 2. As the operating frequency

isincreasedthegatechargelosseswillbehigher,reducing

efficiency (see Efficiency Considerations). The maximum

switching frequency is approximately 310kHz.

Figure 3 shows the net ripple current seen by the output

capacitors for the 1- and 2-phase configurations. The

outputripplecurrentisplottedforafixedoutputvoltageas

the duty factor is varied between 10% and 90% on the

x-axis. The output ripple current is normalized against the

inductor ripple current at zero duty factor. The graph can

be used in place of tedious calculations, simplifying the

design process.

2.5

2.0

1.5

1.0

0.5

0

1.0

1-PHASE

2-PHASE

0.9

0.8

120

170

220

270

320

OPERATING FREQUENCY (kHz)

0.7

0.6

0.5

0.4

0.3

0.2

0.1

1929 F02

Figure 2. Operating Frequency vs V_PLLFLTR

Inductor Value Calculation and Output Ripple Current

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because of

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

1929 F03

Figure 3. Normalized Output Ripple Current

vs Duty Factor [I_RMS≈ 0.3 (∆I_O(P–P))]

12

LTC1929/LTC1929-PG

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APPLICATIO S I FOR ATIO

Accepting larger values of ∆I_Lallows the use of low

inductances, butcanresultinhigheroutputvoltageripple.

A reasonable starting point for setting ripple current is ∆I_L

=0.4(I_OUT)/2,whereI_OUTisthetotalloadcurrent.Remem-

ber, the maximum ∆I_Loccurs at the maximum input

voltage. The individual inductor ripple currents are deter-

mined by the inductor, input and output voltages.

EXTV_CCPinConnection).Consequently,logic-levelthresh-

old MOSFETs must be used in most applications. The only

exception is if low input voltage is expected (V_IN< 5V);

then, sublogic-level threshold MOSFETs (V_GS(TH)< 3V)

should be used. Pay close attention to the BV_DSSspecifi-

cation for the MOSFETs as well; most of the logic-level

MOSFETs are limited to 30V or less.

SelectioncriteriaforthepowerMOSFETsincludethe“ON”

Inductor Core Selection

resistance R_DS(ON), reverse transfer capacitance C_RSS

,

Once the values for L1 and L2 are known, the type of

inductor must be selected. High efficiency converters

generally cannot afford the core loss found in low cost

powdered iron cores, forcing the use of more expensive

ferrite, molypermalloy, or Kool Mµ^®cores. Actual core

loss is independent of core size for a fixed inductor value,

but it is very dependent on inductance selected. As induc-

tance increases, core losses go down. Unfortunately,

increased inductance requires more turns of wire and

therefore copper losses will increase.

input voltage, and maximum output current. When the

LTC1929isoperatingincontinuousmodethedutyfactors

for the top and bottom MOSFETs of each output stage are

given by:

V_OUT

V

IN

Main SwitchDuty Cycle =

V – V_OUT

IN

Synchronous SwitchDuty Cycle =

V

IN

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

The MOSFET power dissipations at maximum output

current are given by:

2

V_OUTI_MAX

P_MAIN

=

1+ δ R_DS(ON)

+

(

)

V

IN

2

)

I_MAX

2

k V

C_RSS

(

f

(

IN

)( )

Molypermalloy (from Magnetics, Inc.) is a very good, low

losscorematerialfortoroids,butitismoreexpensivethan

ferrite. A reasonable compromise from the same manu-

facturer is Kool Mµ. Toroids are very space efficient,

especially when you can use several layers of wire. Be-

cause they lack a bobbin, mounting is more difficult.

However, designs for surface mount are available which

do not increase the height significantly.

2

V – V_OUTI_MAX

IN

P_SYNC

=

1+ δ R_DS(ON)

(

)

V

IN

2

where δ is the temperature dependency of R_DS(ON)and k

is a constant inversely related to the gate drive current.

Both MOSFETs have I²R losses but the topside N-channel

equation includes an additional term for transition losses,

which peak at the highest input voltage. For V_IN< 20V the

high current efficiency generally improves with larger

MOSFETs, while for V_IN> 20V the transition losses rapidly

increasetothepointthattheuseofahigherR_DS(ON)device

with lower C_RSSactual provides higher efficiency. The

Power MOSFET, D1 and D2 Selection

Two external power MOSFETs must be selected for each

output stage with the LTC1929: One N-channel MOSFET

for the top (main) switch, and one N-channel MOSFET for

the bottom (synchronous) switch.

The peak-to-peak drive levels are set by the INTV_CCvolt-

age. This voltage is typically 5V during start-up (see

Kool Mµ is a registered trademark of Magnetics, Inc.

13

LTC1929/LTC1929-PG

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APPLICATIO S I FOR ATIO

0.6

0.5

0.4

0.3

0.2

0.1

0

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during a

short-circuit when the synchronous switch is on close to

100% of the period.

1-PHASE

2-PHASE

The term (1 + δ) is generally given for a MOSFET in the

form of a normalized R_DS(ON)vs. Temperature curve, but

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs. C_RSSis usually specified in the MOS-

FET characteristics. The constant k = 1.7 can be used to

estimate the contributions of the two terms in the main

switch dissipation equation.

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

1929 F04

TheSchottkydiodes,D1andD2showninFigure1conduct

during the dead-time between the conduction of the two

large power MOSFETs. This helps prevent the body diode

of the bottom MOSFET from turning on, storing charge

during the dead-time, and requiring a reverse recovery

periodwhichwouldreduceefficiency. A1Ato3A(depend-

ing on output current) Schottky diode is generally a good

compromise for both regions of operation due to the

relatively small average current. Larger diodes result in

additional transition losses due to their larger junction

capacitance.

Figure 4. Normalized RMS Input Ripple Current

vs Duty Factor for 1 and 2 Output Stages

These worst-case conditions are commonly used for de-

signbecauseevensignificantdeviationsdonotoffermuch

relief. Note that capacitor manufacturer’s ripple current

ratings are often based on only 2000 hours of life. This

makes it advisable to further derate the capacitor, or to

choose a capacitor rated at a higher temperature than

required.Severalcapacitorsmayalsobeparalleledtomeet

size or height requirements in the design. Always consult

the capacitor manufacturer if there is any question.

C_INand C_OUTSelection

It is important to note that the efficiency loss is propor-

tional to the input RMS current squared and therefore a

2-stage implementation results in 75% less power loss

when compared to a single phase design. Battery/input

protection fuse resistance (if used), PC board trace and

connector resistance losses are also reduced by the re-

ductionoftheinputripplecurrentina2-phasesystem.The

requiredamountofinputcapacitanceisfurtherreducedby

the factor, 2, due to the effective increase in the frequency

of the current pulses.

In continuous mode, the source current of each top

N-channel MOSFET is a square wave of duty cycle V_OUT

/

V_IN. A low ESR input capacitor sized for the maximum

RMS current must be used. The details of a close form

equation can be found in Application Note 77. Figure 4

shows the input capacitor ripple current for a 2-phase

configuration with the output voltage fixed and input

voltage varied. The input ripple current is normalized

against the DC output current. The graph can be used in

place of tedious calculations. The minimum input ripple

currentcanbeachievedwhentheinputvoltageistwicethe

output voltage. The minimum is not quite zero due to

inductor ripple current.

The selection of C_OUTis driven by the required effective

series resistance (ESR). Typically once the ESR require-

ment has been met, the RMS current rating generally far

exceeds the I_RIPPLE(P-P)requirements. The steady state

output ripple (∆V_OUT) is determined by:

In the graph of Figure 4, the local maximum input RMS

capacitor currents are reached when:

V_OUT2k − 1

1

=

∆V_OUT≈ ∆I_RIPPLEESR +

where k = 1, 2.

V

4

16fC_OUT

IN

14

LTC1929/LTC1929-PG

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APPLICATIO S I FOR ATIO

Where f = operating frequency of each stage, C_OUT

output capacitance and ∆I_RIPPLE= combined inductor

=

series. Consultthemanufacturerforotherspecificrecom-

mendations. A combination of capacitors will often result

in maximizing performance and minimizing overall cost

and size.

ripple currents.

The output ripple varies with input voltage since ∆I_Lis a

functionofinputvoltage.Theoutputripplewillbelessthan

50mV at max V_INwith ∆I_L= 0.4I_OUT(MAX)/2 assuming:

INTV_CCRegulator

An internal P-channel low dropout regulator produces 5V

at the INTV_CCpin from the V_INsupply pin. The INTV_CC

regulator powers the drivers and internal circuitry of the

LTC1929.TheINTV_CCpinregulatorcansupplyupto50mA

peak and must be bypassed to power ground with a

minimum of 4.7µF tantalum or electrolytic capacitor. An

additional 1µF ceramic capacitor placed very close to the

IC is recommended due to the extremely high instanta-

neous currents required by the MOSFET gate drivers.

C_OUTrequired ESR < 4(R_SENSE) and

C_OUT> 1/(16f)(R_SENSE)

The emergence of very low ESR capacitors in small,

surface mount packages makes very physically small

implementations possible. The ability to externally com-

pensate the switching regulator loop using the I_THpin

(OPTI-LOOP compensation) allows a much wider selec-

tion of output capacitor types. OPTI-LOOP compensation

effectively removes constraints on output capacitor ESR.

The impedance characteristics of each capacitor type are

significantlydifferentthananidealcapacitorandtherefore

require accurate modeling or bench evaluation during

design.

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC1929 to be

exceeded. The supply current is dominated by the gate

charge supply current, in addition to the current drawn

from the differential amplifier output. The gate charge is

dependent on operating frequency as discussed in the

Efficiency Considerations section. The supply current can

either be supplied by the internal 5V regulator or via the

EXTV_CCpin. When the voltage applied to the EXTV_CCpin

is less than 4.7V, all of the INTV_CCload current is supplied

by the internal 5V linear regulator. Power dissipation for

the IC is higher in this case by (I_IN)(V_IN– INTV_CC) and

efficiency is lowered. The junction temperature can be

estimated by using the equations given in Note 1 of the

Electrical Characteristics. For example, the LTC1929 V_IN

current is limited to less than 24mA from a 24V supply:

Manufacturers such as Nichicon, United Chemicon and

Sanyoshouldbeconsideredforhighperformancethrough-

hole capacitors. The OS-CON semiconductor dielectric

capacitor available from Sanyo and the Panasonic SP

surface mount types have the lowest (ESR)(size) product

of any aluminum electrolytic at a somewhat higher price.

An additional ceramic capacitor in parallel with OS-CON

type capacitors is recommended to reduce the inductance

effects.

In surface mount applications, multiple capacitors may

have to be paralleled to meet the ESR or RMS current

handling requirements of the application. Aluminum elec-

trolytic and dry tantalum capacitors are both available in

surface mount configurations. New special polymer sur-

face mount capacitors offer very low ESR also but have

muchlowercapacitivedensityperunitvolume. Inthecase

oftantalum,itiscriticalthatthecapacitorsaresurgetested

for use in switching power supplies. Several excellent

choices are the AVX TPS, AVX TPSV or the KEMET T510

seriesofsurfacemounttantalums,availableincaseheights

ranging from 2mm to 4mm. Other capacitor types include

Sanyo OS-CON, Nichicon PL series and Sprague 595D

T_J= 70°C + (24mA)(24V)(95°C/W) = 125°C

Use of the EXTV_CCpin reduces the junction temperature

to:

T_J= 70°C + (24mA)(5V)(95°C/W) = 81.4°C

The input supply current should be measured while the

controller is operating in continuous mode at maximum

V_INand the power dissipation calculated in order to pre-

vent the maximum junction temperature from being

exceeded.

15

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EXTV_CCConnection

1. EXTV_CCleft open (or grounded). This will cause INTV_CC

to be powered from the internal 5V regulator resulting in

a significant efficiency penalty at high input voltages.

The LTC1929 contains an internal P-channel MOSFET

switch connected between the EXTV_CCand INTV_CCpins.

When the voltage applied to EXTV_CCrises above 4.7V, the

internal regulator is turned off and the switch closes,

connecting the EXTV_CCpin to the INTV_CCpin thereby

supplying internal and MOSFET gate driving power. The

switch remains closed as long as the voltage applied to

EXTV_CCremains above 4.5V. This allows the MOSFET

driver and control power to be derived from the output

during normal operation (4.7V < V_EXTVCC< 7V) and from

the internal regulator when the output is out of regulation

(start-up, short-circuit). Do not apply greater than 7V to

the EXTV_CCpin and ensure that EXTV_CC< V_IN+ 0.3V when

using the application circuits shown.If an external voltage

source is applied to the EXTV_CCpin when the V_INsupply is

not present, a diode can be placed in series with the

LTC1929’s V_INpin and a Schottky diode between the

EXTV_CCandtheV_INpin,topreventcurrentfrombackfeeding

V_IN.

2. EXTV_CCconnected directly to V_OUT. This is the normal

connection for a 5V regulator and provides the highest

efficiency.

3. EXTV_CCconnected to an external supply. If an external

supply is available in the 5V to 7V range, it may be used to

powerEXTV_CCprovidingitiscompatiblewiththeMOSFET

gate drive requirements.

4. EXTV_CCconnected to an output-derived boost network.

For 3.3V and other low voltage regulators, efficiency gains

can still be realized by connecting EXTV_CCto an output-

derived voltage which has been boosted to greater than

4.7V but less than 7V. This can be done with either the

inductive boost winding as shown in Figure 5a or the

capacitive charge pump shown in Figure 5b. The charge

pump has the advantage of simple magnetics.

Topside MOSFET Driver Supply (C_B,D_B) (Refer to

Functional Diagram)

Significant efficiency gains can be realized by powering

INTV_CCfrom the output, since the V_INcurrent resulting

from the driver and control currents will be scaled by the

ratio: (Duty Factor)/(Efficiency). For 5V regulators this

means connecting the EXTV_CCpin directly to V_OUT. How-

ever, for 3.3V and other lower voltage regulators, addi-

tionalcircuitryisrequiredtoderiveINTV_CCpowerfromthe

output.

External bootstrap capacitors C_B1and C_B2connected to

the BOOST1 and BOOST2 pins supply the gate drive

voltages for the topside MOSFETs. Capacitor C_Bin the

Functional Diagram is charged though diode D_Bfrom

INTV_CCwhentheSWpinislow.WhenthetopsideMOSFET

turns on, the driver places the C_Bvoltage across the gate-

sourceofthedesiredMOSFET.ThisenhancestheMOSFET

and turns on the topside switch. The switch node voltage,

The following list summarizes the four possible connec-

tions for EXTV_CC:

+

V

OPTIONAL EXTV CONNECTION

CC

+

IN

C

IN

5V < V

< 7V

V

SEC

+

IN

C

IN

V

IN

BAT85

0.22µF

BAT85

V

IN

1N4148

TG1

V

SEC

TG1

+

N-CH

VN2222LL

LTC1929

1µF

N-CH

LTC1929

R

SENSE

R

SENSE

V

SW1

BG1

EXTV

OUT

CC

V

SW1

BG1

OUT

L1

T1

+

C

OUT

C

OUT

N-CH

PGND

1929 F05b

1929 F05a

Figure 5a. Secondary Output Loop with EXTV_CCConnection

Figure 5b. Capacitive Charge Pump for EXTV_CC

16

LTC1929/LTC1929-PG

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SW, rises to V_INand the BOOST pin rises to V_IN+ V_INTVCC

.

currents by gradually increasing the controller’s current

limit I_TH(MAX). The latchoff timer prevents very short,

extreme load transients from tripping the overcurrent

latch. A small pull-up current (>5µA) supplied to the RUN/

SS pin will prevent the overcurrent latch from operating.

The following explanation describes how the functions

operate.

The value of the boost capacitor C_Bneeds to be 30 to 100

times that of the total input capacitance of the topside

MOSFET(s). ThereversebreakdownofD_Bmustbegreater

than V_IN(MAX).

The final arbiter when defining the best gate drive ampli-

tude level will be the input supply current. If a change is

made that decreases input current, the efficiency has

improved. If the input current does not change then the

efficiency has not changed either.

An internal 1.2µA current source charges up the C_SS

capacitor_.When the voltage on RUN/SS reaches 1.5V, the

controllerispermittedtostartoperating.Asthevoltageon

RUN/SS increases from 1.5V to 3.0V, the internal current

Output Voltage

limit is increased from 25mV/R_SENSEto 75mV/R_SENSE

.

The output current limit ramps up slowly, taking an

additional 1.4s/µF to reach full current. The output current

thus ramps up slowly, reducing the starting surge current

required from the input power supply. If RUN/SS has been

pulled all the way to ground there is a delay before starting

of approximately:

The LTC1929 has a true remote voltage sense capability.

Thesensingconnectionsshouldbereturnedfromtheload

back to the differential amplifier’s inputs through a com-

mon, tightly coupled pair of PC traces. The differential

amplifier rejects common mode signals capacitively or

inductively radiated into the feedback PC traces as well as

ground loop disturbances. The differential amplifier out-

put signal is divided down and compared with the internal

precision 0.8V voltage reference by the error amplifier.

1.5V

t_DELAY

=

C

_SS= 1.25s / µF C_SS

(

)

1.2µA

The differential amplifier can be used in either of two

configurations according to the voltage applied to the

AMPMD pin (LTC1929 only). The first configuration, with

the connections illustrated in the Functional Diagram,

utilizes a set of internal precision resistors to enable

precision instrumentation-type measurement of the out-

put voltage. This configuration is activated when the

AMPMD pin is tied to ground and is the default for the

LTC1929-PG. When the AMPMD pin is tied to INTV_CC, the

resistors are disconnected and the amplifier inputs are

made directly available. The amplifier can then be used as

a general purpose op amp. The amplifier has a 0V to 3V

common mode input range limitation due to the internal

switching of its inputs. The output is an NPN emitter

follower without any internal pull-down current. A DC

resistiveloadtogroundisrequiredinordertosinkcurrent.

Theoutputwillswingfrom0Vto10V(V_IN≥V_DIFFOUT+2V).

The time for the output current to ramp up is then:

3V − 1.5V

1.2µA

t_IRAMP

=

C

_SS= 1.25s / µF C_SS

(

)

By pulling both RUN/SS controller pins below 0.8V the

LTC1929isputintolowcurrentshutdown(I_Q<40µA).The

RUN/SS pins can be driven directly from logic as shown in

Figure 6. Diode D1 in Figure 6 reduces the start delay but

allows C_SSto ramp up slowly providing the soft-start

function. The RUN/SS pin has an internal 6V zener clamp

(see Functional Diagram).

Fault Conditions: Overcurrent Latchoff

The RUN/SS pin also provides the ability to latch off the

controllers when an overcurrent condition is detected.

The RUN/SS capacitor, C_SS, is used initially to limit the

inrush current of both controllers. After the controllers

havebeenstartedandbeengivenadequatetimetocharge

up the output capacitors and provide full load current, the

RUN/SS capacitor is used for a short-circuit timer. If the

output voltage falls to less than 70% of its nominal value,

Soft-Start/Run Function

The RUN/SS pin provides three functions: 1) Run/Shut-

down,2)soft-startand3)adefeatableshort-circuitlatchoff

timer. Soft-start reduces the input power sources’ surge

17

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after C_SSreaches 4.1V, C_SSbegins discharging on the

assumption that the output is in an overcurrent condition.

If the condition lasts for a long enough period as deter-

mined by the size of C_SS, the controller will be shut down

until the RUN/SS pin voltage is recycled. If the overload

occurs during start-up, the time can be approximated by:

The value of the soft-start capacitor C_SSmay need to be

scaled with output voltage, output capacitance and load

current characteristics. The minimum soft-start capaci-

tance is given by:

C

_SS> (C_OUT)(V_OUT)(10^-4)(R_SENSE

)

The minimum recommended soft-start capacitor of C_SS

0.1µF will be sufficient for most applications.

=

t

_LO1≈ (C_SS• 0.6V)/(1.2µA) = 5 • 10⁵(C_SS)

If the overload occurs after start-up the voltage on the

RUN/SS capacitor will continue charging and will provide

additional time before latching off:

Phase-Locked Loop and Frequency Synchronization

The LTC1929 has a phase-locked loop comprised of an

internal voltage controlled oscillator and phase detector.

This allows the top MOSFET turn-on to be locked to the

rising edge of an external source. The frequency range of

the voltage controlled oscillator is ±50% around the

center frequency f_O. A voltage applied to the PLLFLTR pin

of 1.2V corresponds to a frequency of approximately

220kHz. The nominal operating frequency range of the

LTC1929 is 140kHz to 310kHz.

t

_LO2≈ (C_SS• 3V)/(1.2µA) = 2.5 • 10⁶(C_SS)

This built-in overcurrent latchoff can be overridden by

providing a pull-up resistor, R_SS, to the RUN/SS pin as

shown in Figure 6. This resistance shortens the soft-start

period and prevents the discharge of the RUN/SS capaci-

tor during a severe overcurrent and/or short-circuit con-

dition. When deriving the 5µA current from V_INas in the

figure, current latchoff is always defeated. The diode

connecting of this pull-up resistor to INTV_CC, as in

Figure 6, eliminates any extra supply current during shut-

down while eliminating the INTV_CCloading from prevent-

ing controller start-up.

The phase detector used is an edge sensitive digital type

which provides zero degrees phase shift between the

external and internal oscillators. This type of phase detec-

tor will not lock up on input frequencies close to the

harmonics of the VCO center frequency. The PLL hold-in

range, ∆f_H, is equal to the capture range, ∆f_C:

Why should you defeat current latchoff? During the

prototypingstageofadesign,theremaybeaproblemwith

noise pickup or poor layout causing the protection circuit

to latch off the controller. Defeating this feature allows

troubleshooting of the circuit and PC layout. The internal

short-circuit and foldback current limiting still remains

active, thereby protecting the power supply system from

failure. A decision can be made after the design is com-

plete whether to rely solely on foldback current limiting or

to enable the latchoff feature by removing the pull-up

resistor.

∆f_H= ∆f_C= ±0.5 f_O(150kHz-300kHz)

The output of the phase detector is a complementary pair

of current sources charging or discharging the external

filter network on the PLLFLTR pin. A simplified block

diagram is shown in Figure 7.

2.4V

R

10k

LP

PHASE

DETECTOR

C

LP

EXTERNAL

OSC

V

INTV

IN

CC

3.3V OR 5V

RUN/SS

*

PLLFLTR

R

*

SS

PLLIN

DIGITAL

PHASE/

FREQUENCY

DETECTOR

D1

RUN/SS

OSC

D1*

C

SS

50k

C

SS

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

1929 F06

1929 F07

Figure 6. RUN/SS Pin Interfacing

Figure 7. Phase-Locked Loop Block Diagram

18

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If the external frequency (f_PLLIN) is greater than the oscil-

lator frequency f_0SC, current is sourced continuously,

pulling up the PLLFLTR pin. When the external frequency

is less than f_0SC, current is sunk continuously, pulling

down the PLLFLTR pin. If the external and internal fre-

quencies are the same but exhibit a phase difference, the

currentsourcesturnonforanamountoftimecorrespond-

ing to the phase difference. Thus the voltage on the

PLLFLTR pin is adjusted until the phase and frequency of

the external and internal oscillators are identical. At this

stable operating point the phase comparator output is

open and the filter capacitor C_LPholds the voltage. The

LTC1929 PLLIN pin must be driven from a low impedance

source such as a logic gate located close to the pin.

significant amount of cycle skipping can occur with corre-

spondingly larger current and voltage ripple.

If an application can operate close to the minimum on-

time limit, an inductor must be chosen that has a low

enough inductance to provide sufficient ripple amplitude

to meet the minimum on-time requirement. As a general

rule, keep the inductor ripple current of each phase equal

to or greater than 15% of I_OUT(MAX)at V_IN(MAX)

.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can be

expressed as:

The loop filter components (C_LP, R_LP) smooth out the

current pulses from the phase detector and provide a

stable input to the voltage controlled oscillator. The filter

components C_LPand R_LPdetermine how fast the loop

acquires lock. Typically R_LP=10kΩ and C_LPis 0.01µF to

0.1µF.

%Efficiency = 100% – (L1 + L2 + L3 + ...)

whereL1, L2, etc. aretheindividuallossesasapercentage

of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC1929 circuits: 1) LTC1929 V_INcurrent (in-

cluding loading on the differential amplifier output),

2) INTV_CCregulator current, 3) I²R losses and 4) Topside

MOSFET transition losses.

Minimum On-Time Considerations

Minimum on-time t_ON(MIN)is the smallest time duration

thattheLTC1929iscapableofturningonthetopMOSFET.

It is determined by internal timing delays and the gate

chargerequiredtoturnonthetopMOSFET.Lowdutycycle

applications may approach this minimum on-time limit

and care should be taken to ensure that

1) The V_INcurrent has two components: the first is the

DC supply current given in the Electrical Characteristics

table, which excludes MOSFET driver and control cur-

rents; the second is the current drawn from the differential

amplifier output. V_INcurrent typically results in a small

(<0.1%) loss.

V_OUT

t_{ON MIN}

<

(

)

V f

^IN( )

Ifthedutycyclefallsbelowwhatcanbeaccommodatedby

the minimum on-time, the LTC1929 will begin to skip

cycles resulting in nonconstant frequency operation. The

output voltage will continue to be regulated, but the ripple

current and ripple voltage will increase.

2) INTV_CCcurrent is the sum of the MOSFET driver and

control currents. The MOSFET driver current results from

switching the gate capacitance of the power MOSFETs.

Each time a MOSFET gate is switched from low to high to

low again, a packet of charge dQ moves from INTV_CCto

ground. The resulting dQ/dt is a current out of INTV_CCthat

is typically much larger than the control circuit current. In

continuous mode, I_GATECHG= (Q_T+ Q_B), where Q_Tand Q_B

are the gate charges of the topside and bottom side

MOSFETs.

The minimum on-time for the LTC1929 is generally less

than200ns.However,asthepeaksensevoltagedecreases

the minimum on-time gradually increases. This is of

particular concern in forced continuous applications with

low ripple current at light loads. If the duty cycle drops

below the minimum on-time limit in this situation, a

19

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SupplyingINTV_CCpowerthroughtheEXTV_CCswitchinput

from an output-derived source will scale the V_INcurrent

required for the driver and control circuits by the ratio

(Duty Factor)/(Efficiency). For example, in a 20V to 5V

application, 10mA of INTV_CCcurrent results in approxi-

mately 3mA of V_INcurrent. This reduces the mid-current

loss from 10% or more (if the driver was powered directly

from V_IN) to only a few percent.

minimum of 200µF to 300µF of output capacitance having

a maximum of 10mΩ to 20mΩ of ESR. The LTC1929

2-phase architecture typically halves the input and output

capacitancerequirementsovercompetingsolutions.Other

lossesincludingSchottkyconductionlossesduringdead-

time and inductor core losses generally account for less

than 2% total additional loss.

Checking Transient Response

3) I²R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resistor,

and input and output capacitor ESR. In continuous mode

The regulator loop response can be checked by looking at

the load transient response. Switching regulators take

several cycles to respond to a step in DC (resistive) load

current. When a load step occurs, V_OUTshifts by an

amount equal to ∆I_LOAD(ESR), where ESR is the effective

seriesresistanceofC_OUT(∆I_LOAD)alsobeginstochargeor

discharge C_OUTgenerating the feedback error signal that

forces the regulator to adapt to the current change and

return V_OUTto its steady-state value. During this recovery

time V_OUTcan be monitored for excessive overshoot or

ringing, which would indicate a stability problem. The

availability of the I_THpin not only allows optimization of

control loop behavior but also provides a DC coupled and

AC filtered closed loop response test point. The DC step,

rise time, and settling at this test point truly reflects the

closed loop response. Assuming a predominantly second

order system, phase margin and/or damping factor can be

estimated using the percentage of overshoot seen at this

pin. The bandwidth can also be estimated by examining

the rise time at the pin. The I_THexternal components

shown in the Figure 1 circuit will provide an adequate

starting point for most applications.

the average output current flows through L and R_SENSE

,

but is “chopped” between the topside MOSFET and the

synchronous MOSFET. If the two MOSFETs have approxi-

mately the same R_DS(ON), then the resistance of one

MOSFET can simply be summed with the resistances of L,

R_SENSEand ESR to obtain I²R losses. For example, if each

R_DS(ON)=10mΩ, R_L=10mΩ, and R_SENSE=5mΩ, then the

total resistance is 25mΩ. This results in losses ranging

from 2% to 8% as the output current increases from 3A to

15A per output stage for a 5V output, or a 3% to 12% loss

per output stage for a 3.3V output. Efficiency varies as the

inverse square of V_OUTfor the same external components

and output power level. The combined effects of increas-

ingly lower output voltages and higher currents required

by high performance digital systems is not doubling but

quadrupling the importance of loss terms in the switching

regulator system!

4) Transition losses apply only to the topside MOSFET(s),

and only when operating at high input voltages (typically

20V or greater). Transition losses can be estimated from:

The I_THseries R_C-C_Cfilter sets the dominant pole-zero

loop compensation. The values can be modified slightly

(from 0.2 to 5 times their suggested values) to maximize

transient response once the final PC layout is done and the

particular output capacitor type and value have been

determined. The output capacitors need to be decided

upon because the various types and values determine the

loop feedback factor gain and phase. An output current

pulse of 20% to 80% of full-load current having a rise time

of<2µswillproduceoutputvoltageandI_THpinwaveforms

2

Transition Loss = (1.7) V_INI_O(MAX)C_RSS

f

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efficiency degradation in portable systems. It is very

important to include these “system” level losses in the

design of a system. The internal battery and input fuse

resistance losses can be minimized by making sure that

C_INhas adequate charge storage and a very low ESR at the

switching frequency. A 50W supply will typically require a

20

LTC1929/LTC1929-PG

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that will give a sense of the overall loop stability without

breaking the feedback loop. The initial output voltage step

resulting from the step change in output current may not

bewithinthebandwidthofthefeedbackloop,sothissignal

cannot be used to determine phase margin. This is why it

isbettertolookattheIthpinsignalwhichisinthefeedback

loop and is the filtered and compensated control loop

response. The gain of the loop will be increased by

increasing R_Cand the bandwidth of the loop will be

increased by decreasing C_C. If R_Cis increased by the same

factor that C_Cis decreased, the zero frequency will be kept

the same, thereby keeping the phase the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loop system and will demonstrate the actual over-

all supply performance.

Automotive Considerations: Plugging into the

Cigarette Lighter

As battery-powered devices go mobile, there is a natural

interest in plugging into the cigarette lighter in order to

conserveorevenrechargebatterypacksduringoperation.

But before you connect, be advised: you are plugging into

the supply from hell. The main battery line in an automo-

bileisthesourceofanumberofnastypotentialtransients,

including load-dump, reverse-battery, and double-bat-

tery.

Load-dump is the result of a loose battery cable. When the

cablebreaksconnection,thefieldcollapseinthealternator

can cause a positive spike as high as 60V which takes

several hundred milliseconds to decay. Reverse-battery is

just what it says, while double-battery is a consequence of

tow truck operators finding that a 24V jump start cranks

cold engines faster than 12V.

A second, more severe transient is caused by switching in

loads with large (>1µF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C_OUT, causing a rapid drop in V_OUT. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

C_LOADto C_OUTis greater than 1:50, the switch rise time

should be controlled so that the load rise time is limited to

approximately 25 • C_LOAD. Thus a 10µF capacitor would

require a 250µs rise time, limiting the charging current to

about 200mA.

ThenetworkshowninFigure8isthemoststraightforward

approach to protect a DC/DC converter from the ravages

of an automotive battery line. The series diode prevents

current from flowing during reverse-battery, while the

transient suppressor clamps the input voltage during

load-dump. Note that the transient suppressor should not

conduct during double-battery operation, but must still

clamptheinputvoltagebelowbreakdownoftheconverter.

AlthoughtheLT1929hasamaximuminputvoltageof36V,

most applications will be limited to 30V by the MOSFET

BV_DSS

.

50A I RATING

PK

V

IN

12V

LTC1929

TRANSIENT VOLTAGE

SUPPRESSOR

GENERAL INSTRUMENT

1.5KA24A

1929 F08

Figure 8. Automotive Application Protection

21

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Design Example

The worst-case power disipated by the synchronous

MOSFET under normal operating conditions at elevated

ambient temperature and estimated 50°C junction tem-

perature rise is:

Asadesignexample,assumeV_IN=5V(nominal),V_IN= 5.5V

(max), V_OUT=1.8V, I_MAX=20A, T_A=70°Candf = 300kHz.

Theinductancevalueischosenfirstbasedona30%ripple

current assumption. The highest value of ripple current

occursatthemaximuminputvoltage.TietheFREQSETpin

to the INTV_CCpin for 300kHz operation. The minimum

inductance for 30% ripple current is:

2

5.5V − 1.8V

P_SYNC

=

10A 1.48 0.013Ω

(

) (

)(

)

5.5V

= 1.29W

Ashort-circuittogroundwillresultinafoldedbackcurrent

of about:

V_OUT

V

IN

L ≥

1−

f ∆I

( )

200ns 5.5V

(

)

25mV

0.004Ω

1

2

I_SC

=

+

= 6.6A

1.8V

5.5V

1.5µH

≥

1−

300kHz 30% 10A

(

)(

)

The worst-case power disipated by the synchronous

MOSFET under short-circuit conditions at elevated ambi-

ent temperature and estimated 50°C junction temperature

rise is:

≥ 1.35µH

A 1.5µH inductor will produce 27% ripple current. The

peak inductor current will be the maximum DC value plus

one half the ripple current, or 11.4A. The minimum on-

time occurs at maximum V_IN:

2

) (

5.5V − 1.8V

5.5V

= 564mW

P_SYNC

=

6.6A 1.48 0.013Ω

(

)(

)

V_OUT

V f

IN

1.8V

t_{ON MIN}

=

= 1.1µs

(

)

5.5V 300kHz

(

)(

)

which is less than half of the normal, full-load dissipation.

Incidentally, since the load no longer dissipates power in

the shorted condition, total system power dissipation is

decreased by over 99%.

The R_SENSEresistors value can be calculated by using the

maximum current sense voltage specification with some

accomodation for tolerances:

The duty factor for this application is:

50mV

11.4A

R_SENSE

=

≈ 0.004Ω

V_O1.8V

DF =

=

= 0.36

V

5V

IN

The power dissipation on the topside MOSFET can be

easily estimated. Using a Siliconix Si4420DY for example;

R_DS(ON)= 0.013Ω, C_RSS= 300pF. At maximum input

voltagewithT_J(estimated)=110°Catanelevatedambient

temperature:

Using Figure 4, the RMS ripple current will be:

I_INRMS= (20A)(0.23) = 4.6A_RMS

An input capacitor(s) with a 4.6A_RMSripple current rating

is required.

2

1.8V

5.5V

P_MAIN

=

10 1+ 0.005 110°C − 25°C

( )

(

)(

)

]

The output capacitor ripple current is calculated by using

the inductor ripple already calculated for each inductor

and multiplying by the factor obtained from Figure 3

along with the calculated duty factor. The output ripple in

[

2

) (

0.013Ω + 1.7 5.5V 10A 300pF

(

)(

)

300kHz = 0.65W

(

)

22

LTC1929/LTC1929-PG

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continuous mode will be highest at the maximum input

voltage since the duty factor is <50%. The maximum

output current ripple is:

provides the AC current to the MOSFETs. Keep the input

currentpathformedbytheinputcapacitor,topandbottom

MOSFETs, and the Schottky diode on the same side of the

PC board in a tight loop to minimize conducted and

radiated EMI.

V_OUT

fL

∆I_COUT

=

0.3 at 33%DF

(

)

5) Is the INTV_CC1µF ceramic decoupling capacitor con-

nectedcloselybetweenINTV_CCandthepowergroundpin?

This capacitor carries the MOSFET driver peak currents. A

small value is used to allow placement immediately adja-

cent to the IC.

1.8V

∆I_COUTMAX

=

0.3

300kHz 1.5µH

(

)(

)

= 1.2A_RMS

6) Keep the switching nodes, SW1 (SW2), away from

sensitive small-signal nodes. Ideally the switch nodes

should be placed at the furthest point from the LTC1929.

V

_OUTRIPPLE= 20mΩ 1.2A_RMS= 24mV_RMS

(

)

PC Board Layout Checklist

7)Usealowimpedancesourcesuchasalogicgatetodrive

the PLLIN pin and keep the lead as short as possible.

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1929. These items are also illustrated graphically in

the layout diagram of Figure 11. Check the following in

your layout:

The diagram in Figure 9 illustrates all branch currents in

a2-phaseswitchingregulator.Itbecomesveryclearafter

studying the current waveforms why it is critical to keep

thehigh-switching-currentpathstoasmallphysicalsize.

High electric and magnetic fields will radiate from these

“loops” just as radio stations transmit signals. The out-

put capacitor ground should return to the negative termi-

nal of the input capacitor and not share a common

groundpathwithanyswitchedcurrentpaths.Thelefthalf

of the circuit gives rise to the “noise” generated by a

switching regulator. The ground terminations of the

synchronous MOSFETs and Schottky diodes should re-

turn to the bottom plate(s) of the input capacitor(s) with

a short isolated PC trace since very high switched cur-

rents are present. A separate isolated path from the

bottom plate(s) of the input capacitor(s) should be used

to tie in the IC power ground pin (PGND) and the signal

ground pin (SGND). This technique keeps inherent sig-

nals generated by high current pulses from taking alter-

nate current paths that have finite impedances during the

total period of the switching regulator. External OPTI-

LOOP compensation allows overcompensation for PC

layouts which are not optimized but this is not the

recommended design procedure.

1) Are the signal and power grounds segregated? The

LTC1929 signal ground pin should return to the (–) plate

of C_OUTseparately. The power ground returns to the

sources of the bottom N-channel MOSFETs, anodes of the

Schottky diodes, and (–) plates of C_IN, which should have

as short lead lengths as possible.

2) Does the LTC1929 V_OS⁺pin connect to the (+) plate(s)

of C_OUT? Does the LTC1929 V_OS^–pin connect to the (–)

plate(s) of C_OUT? The resistive divider R1, R2 must be

connected between the V_DIFFOUTand signal ground and

anyfeedforwardcapacitoracrossR1shouldbeascloseas

possible to the LTC1929.

3)AretheSENSE^–andSENSE⁺leadsroutedtogetherwith

minimum PC trace spacing? The filter capacitors between

SENSE⁺and SENSE^–pin pairs should be as close as

possible to the LTC1929. Ensure accurate current sensing

with Kelvin connections.

4) Do the (+) plates of C_INconnect to the drains of the

topside MOSFETs as closely as possible? This capacitor

23

LTC1929/LTC1929-PG

U

W

U U

APPLICATIO S I FOR ATIO

Simplified Visual Explanation of How a 2-Phase

Controller Reduces Both Input and Output RMS Ripple

Current

Figure 4 illustrates the RMS input current drawn from the

input capacitance vs the duty cycle as determined by the

ratio of input and output voltage. The peak input RMS

currentlevelofthesinglephasesystemisreducedby50%

in a 2-phase solution due to the current splitting between

the two stages.

A multiphase power supply significantly reduces the

amount of ripple current in both the input and output

capacitors.TheRMSinputripplecurrentisdividedby,and

the effective ripple frequency is multiplied up by the

number of phases used (assuming that the input voltage

isgreaterthanthenumberofphasesusedtimestheoutput

voltage). The output ripple amplitude is also reduced by,

and the effective ripple frequency is increased by the

number of phases used. Figure 10 graphically illustrates

the principle.

An interesting result of the 2-phase solution is that the V_IN

which produces worst-case ripple current for the input

capacitor, V_OUT= V_IN/2, in the single phase design pro-

duces zero input current ripple in the 2-phase design.

The output ripple current is reduced significantly when

compared to the single phase solution using the same

inductance value because the V_OUT/L discharge current

term from the stage that has its bottom MOSFET on

subtracts current from the (V_IN- V_OUT)/L charging current

resultingfromthestagewhichhasitstopMOSFETon. The

output ripple current is:

The worst-case RMS ripple current for a single stage

design peaks at twice the value of the output voltage . The

worst-case RMS ripple current for a two stage design

results in peaks at 1/4 and 3/4 of input voltage. When the

RMS current is calculated, higher effective duty factor

results and the peak current levels are divided as long as

the currents in each stage are balanced. Refer to Applica-

tion Note 19 for a detailed description of how to calculate

RMS current for the single stage switching regulator.

Figures 3 and 4 illustrate how the input and output

currents are reduced by using an additional phase. The

input current peaks drop in half and the frequency is

doubled for this 2-phase converter. The input capacity

requirement is thus reduced theoretically by a factor of

four! Ceramic input capacitors with their unbeatably low

ESR characteristics can be used.

1− 2D 1−D

(

)

2V_OUT

fL

∆I_RIPPLE

=

1− 2D +1

where D is duty factor.

The input and output ripple frequency is increased by the

number of stages used, reducing the output capacity

requirements.WhenV_INisapproximatelyequalto2(V_OUT

)

as illustrated in Figures 3 and 4, very low input and output

ripple currents result.

24

LTC1929/LTC1929-PG

U

W U U

APPLICATIO S I FOR ATIO

L1

SW1

R

SENSE1

D1

V

OUT

IN

R

IN

C

+

OUT

+

C

IN

R

L

L2

SW2

R

SENSE2

D2

BOLD LINES INDICATE

HIGH, SWITCHING

CURRENT LINES.

KEEP LINES TO A

MINIMUM LENGTH.

1929 F09

Figure 9. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator

SINGLE PHASE

DUAL PHASE

SW V

SW1 V

SW2 V

I

CIN

I

L1

L2

I

COUT

I

CIN

I

COUT

RIPPLE

1929 F10

Figure 10. Single and 2-Phase Current Waveforms

25

LTC1929/LTC1929-PG

U

TYPICAL APPLICATIO S

26

LTC1929/LTC1929-PG

U

TYPICAL APPLICATIO S

100

90

80

70

60

50

V

= 5V

OUT

IN

= 1.6V

0

5

10 15 20 25 30 35 40

LOAD CURRENT (A)

1929 F12

Figure 12. Efficiency Plot for Circuit of Figure 11

U

PACKAGE DESCRIPTIO

Dimensions in inches (millimeters) unless otherwise noted.

G Package

28-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

10.07 – 10.33*

(0.397 – 0.407)

28 27 26 25 24 23 22 21 20 19 18

16 15

17

7.65 – 7.90

(0.301 – 0.311)

5

7

8

1

2

3

4

6

9 10 11 12 13 14

5.20 – 5.38**

(0.205 – 0.212)

1.73 – 1.99

(0.068 – 0.078)

0° – 8°

0.65

(0.0256)

BSC

0.13 – 0.22

0.55 – 0.95

(0.005 – 0.009)

(0.022 – 0.037)

0.05 – 0.21

(0.002 – 0.008)

0.25 – 0.38

(0.010 – 0.015)

NOTE: DIMENSIONS ARE IN MILLIMETERS

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.152mm (0.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

G28 SSOP 1098

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

27

LTC1929/LTC1929-PG

U

TYPICAL APPLICATIO

LTC1929-PG

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RUN/SS

NC

TG1

L1

2

+

0.1µF

SENSE1

EAIN

1000pF

0.004Ω

3

4

–

SW1

2.7k

0.22µF

BOOST1

M1

M2

10k

51k

5

D1

INTV

47k

PLLFLTR

PLLIN

NC

V

IN

CC

MBRS140T3

6

BG1

15k

C

IN

7

10Ω

47µF 35V

EXTV

5V (OPT)

CC

+

8

+

I

INTV

TH

3.3nF

10k

0.1µF

10µF

100pF

9

C

OUT

SGND

PGND

BG2

V

IN

10

11

12

13

14

5V TO 28V

V

470pF

15k

DIFFOUT

D2

MBRS140T3

–

BOOST2

SW2

M3

M4

OS

0.22µF

+

OS

V

0.004Ω

OUT

–

+

SENSE2

TG2

2V

1000pF

100k

20A

L2

PGOOD

SWITCHING FREQUENCY = 200kHz

PGOOD

C

: 5A RIPPLE CURRENT RATING REQUIRED

IN

OUT

: 4 × 180µF/4V PANASONIC SP

L1 TO L2: 1.5µH SUMIDA CEP125-1R5MC

1929 F13

M1 TO M4: FAIRCHILD FDS7760A

Figure 13. 2V/20A CPU Power Supply with Active Voltage Positioning

RELATED PARTS

PART NUMBER

DESCRIPTION

Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulators POR, Auxiliary Regulator

Dual Synchronous Controller with Auxiliary Regulator POR, External Feedback Divider

COMMENTS

LTC1438/LTC1439

LTC1438-ADJ

LTC1538-AUX

LTC1539

Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulator Auxiliary Regulator, 5V Standby

Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulator 5V Standby, POR, Low-Battery, Aux Regulator

LTC1435/LTC1435A

LTC1436A-PLL

High Efficiency Synchronous Step-Down Switching Regulator

Burst Mode^TMOperation, 16-Pin Narrow SO

Adaptive Power^TMMode, 24-Pin SSOP

Constant Frequency, Standby, 5V and 3.3V LDOs

Expandable Up to 12 Phases, G-28, Up to 120A

500kHz, 25MHz GBW

High Efficiency Low Noise Synchronous Step-Down Switching Regulator

LTC1628/LTC1628-PG Dual High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator

LTC1629/LTC1629-PG PolyPhase High Efficiency Controller

LTC1702/LTC1703

LTC1735

Dual High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator

High Efficiency Synchronous Step-Down Controller

Burst Mode Operation, 16-Pin Narrow SSOP,

Fault Protection, 3.5V ≤ V ≤ 36V

IN

LTC1736

High Efficiency Synchronous Step-Down Controller with 5-Bit VID

Output Fault Protection, Power Good, GN-24,

3.5V ≤ V ≤ 36V, 0.8V ≤ V

≤ 6V

IN

OUT

Adaptive Power and Burst Mode are trademarks of Linear Technology Corporation.

1929f LT/TP 0500 4K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

LINEAR TECHNOLOGY CORPORATION 1999

●

(408)432-1900 FAX:(408)434-0507 www.linear-tech.com


型号：	LTC1929_15
厂家：	Linear
描述：	2-Phase, High Efficiency, Synchronous Step-Down Switching Regulators
文件：	总28页 (文件大小：321K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1929_15 [Linear]

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