LTC1955EUH#TR [Linear]
LTC1955 - Dual Smart Card Interface with Serial Control; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C;
| 型号： | LTC1955EUH#TR |
| 厂家： | 
Linear |
| 描述： | LTC1955 - Dual Smart Card Interface with Serial Control; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C |
| 文件： | 总20页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1955
Dual Smart Card Interface
with Serial Control
U
FEATURES
DESCRIPTIO
The LTC®1955 provides all necessary supervisory and
power control functions for two smart cards, two S.A.M.
cards or a combination of S.A.M. and smart cards. It
provides a charge pump for battery powered applications
as well as all necessary level shifting circuitry.
■
Compatible with ISO7816-3 and EMV Electrical
Specifications
■
Power Management and Control for Two Smart
Cards
■
Control/Status Serial Port May be Daisy-Chained
for Multicard Applications
The card voltages can be independently set to 1.8V, 3V or
5V. Both card interfaces include a card detection channel
withautomaticdebouncecircuitry.Toreducewiringcosts,
the LTC1955 interfaces to a microcontroller via a simple
4-wire serial interface. Multiple devices may be connected
in daisy-chain fashion so that the number of wires to the
card socket board is independent of the number of sock-
ets. Status data is returned over the same interface.
■
Automatic Shutdown on Electrical Faults
■
Buck/Boost Charge Pump Generates 5V, 3V or 1.8V
Outputs (Smart Card Classes A, B and C)*
■
Independent 5V/3V/1.8V Level Control for Both Cards
■
Automatic Level Translation
■
Supervisory Functions Prevent Smart Card Faults
■
Low Operating Current: 250µA Typical
Ultralow Shutdown Current
>10kV ESD on Smart Card Pins
Small 32-Pin 5mUm × 5mm QFN Package
■
■
■
Extensive security features ensure proper deactivation
sequencing in the event of a supply fault or a smart card
electrical fault. The smart card pins can withstand greater
than 10kV ESD in-situ with no additional components.
The LTC1955 is available in a low profile (0.75mm) 5mm
× 5mm QFN package.
APPLICATIO S
■
Handheld Payment Terminals
■
Pay Telephones
, LTC and LT are registered trademarks of Linear Technology Corporation.
*Protected by U.S. Patents including 6356140, 6411531.
■
ATM Machines
■
POS Terminals
■
Computer Keyboards
■
Multiple S.A.M. Sockets
U
240k
180k
TYPICAL APPLICATIO
23
CARD
DETECT
UNDERV
1
2
DV
PRES A
CC
12,13
Deactivation Sequence
V
BATT
INPUT
POWER
0.1µF
4.7µF
LTC1955
3
4
5
6
7
8
9, 10
24
C8A
C4A
GND
RST A
5V/DIV
I/O A
FAULT
RST A
CLK A
27
28
26
25
D
D
IN
SMART CARD
CLK A
5V/DIV
4-WIRE
COMMAND
INTERFACE
V
OUT
CCA
SCLK
LD
1µF
21
PRES B
I/O A
5V/DIV
29
30
32
31
22
20
19
18
17
DATA
I/O B
RST B
CLK B
V
CCA
5V/DIV
4-WIRE
CARD
INTERFACE
R
IN
SYNC
VENDOR CARD
10µs/DIV
1955 G11.eps
ASYNC
NC/NO
V
CCB
1µF
+
–
C
C
CPO
15
1955 TA01
14
11
4.7µF
1µF
1955fa
1
LTC1955
W W
U W
ABSOLUTE AXI U RATI GS
(Note 1)
VBATT, DVCC, CPO, FAULT,
UNDERV to GND.......................................–0.3V to 6.0V
PRES A/PRES B, DATA, RIN, SYNC, ASYNC,
IVCCA/IVCCB ........................................................................... 80mA
VCCA/VCCB Short-Circuit Duration .................... Indefinite
Operating Ambient Temperature Range
LD, DIN, SCLK to GND ............... –0.3V to (DVCC + 0.3V)
I/O A .......................................... –0.3V to (VCCA + 0.3V)
I/O B .......................................... –0.3V to (VCCB + 0.3V)
(Note 4) .............................................. –40°C to 85°C
Storage Temperature Range ................. –65°C to 125°C
U
W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
32 31 30 29 28 27 26 25
LTC1955EUH
DV
CC
1
2
3
4
5
6
7
8
24 FAULT
23 UNDERV
PRES A
C8A
NC/NO
22
21
C4A
PRES B
33
I/O A
20 I/O B
RST B
RST A
CLK A
19
18 CLK B
17
UH PART MARKING
1955
V
CCA
V
CCB
9
10 11 12 13 14 15 16
UH PACKAGE
32-LEAD PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD IS SGND
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VPVBATT = VSVBATT = 3.3V, DVCC = 3.3V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Power Supply
V
Operating Voltage
●
2.7
5.5
V
BATT
I
+ I
SVBATT
Operating Current
V
V
= 5V, V
= 0V, I = 0µA
CCA
●
●
250
350
400
500
µA
µA
PVBATT
CCA
CCA
CCB
= V
= 5V, I
= I
CCB
= 0µA
CCB
CCA
I
+ I
Shutdown Current
No Cards Present, V
= 0V
●
●
●
●
0.75
1.75
5.5
25
µA
V
PVBATT
SVBATT
CPO
DV Operating Voltage
1.7
CC
I
I
Operating Current
Shutdown Current
10
µA
µA
DVCC
DVCC
0.5
1.5
Charge Pump
5V Mode Open-Loop
Output Resistance
R
OLCP
V
= 3.075V, I
= I
+ I = 120mA (Note 3)
CCB
●
●
5.7
0.6
8.5
1.5
Ω
BATT
CPO
CCA
CPO Turn On Time
I
= 0mA, 10% to 90%
ms
CCA/B
1955fa
2
LTC1955
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VPVBATT = VSVBATT = 3.3V, DVCC = 3.3V unless otherwise noted.
SYMBOL
Smart Card Supplies V , V
CONDITIONS
MIN
TYP
MAX
UNITS
CCA CCB
V
Output Voltage
5V Mode, 0 < I
3V Mode, 0 < I
1.8V Mode, 0 < I
< 60mA
< 50mA
●
●
●
4.65
2.75
1.65
5.0
3.0
1.8
5.35
3.25
1.95
V
V
V
CCA/B
CCA/B
CCA/B
< 30mA
CCA/B
V
Turn On-Time
I
= 0mA, 10% to 90%
●
●
●
0.8
–5
1.5
–2.5
135
ms
%
CCA/B
CCA/B
Undervoltage Detection
Overcurrent Detection
Smart Card Detection
Relative to Nominal Output
5V Mode
–9
65
100
mA
Debounce Time ( PRES A/B to
PRES A, PRES B Pull-Up Current
D15/D7)
V
V
= 0V
●
●
●
20
35
1.25
20
60
2.5
250
ms
µA
µs
NC/NO
= 0
PRESA/B
Deactivation Time ( RST to V = 0.4V)
I
= 0mA, C
= 1µF
VCCA/B
CC
CCA/B
CLK A, CLK B
Low Level Output Voltage (V ), (Note 2)
Sink Current = –200µA
●
●
●
●
0.2
16
V
V
OL
High Level Output Voltage (V ), (Note 2)
Source Current = 200µA
Loaded with 50pF, 10% to 90%
V
– 0.2
CCA/B
OH
Rise/Fall Time (Note 2)
ns
CLK A, CLK B Frequency (Note 2)
RST A, RST B, C4A, C8A
10
MHz
Low Level Output Voltage (V ), (Note 2)
Sink Current = –200µA
●
●
●
0.2
100
0.3
V
V
OL
High Level Output Voltage (V ), (Note 2)
Source Current = 200µA
Loaded with 50pF, 10% to 90%
V
– 0.2
CCA/B
OH
Rise/Fall Time (Note 2)
ns
I/O A, I/O B
Low Level Output Voltage (V ), (Note 2)
Sink Current = –1mA (V
= 0V)
DATA
●
●
●
●
V
V
OL
High Level Output Voltage (V ), (Note 2)
Source Current = 20µA (V
= V
)
0.85 • V
CCA/B
OH
DATA
DVCC
Rise/Fall Time (Note 2)
Short Circuit Current (Note 2)
DATA
Loaded with 50pF, 10% to 90%
= 0V
500
10
ns
V
DATA
5
mA
Low Level Output Voltage (V
)
Sink Current = –500µA (V
Source Current = 20µA (V
= 0V)
●
●
●
0.3
500
V
V
OL
I/OA/B
High Level Output Voltage (V
Rise/Fall Time
)
= V
)
0.8 • DV
CC
OH
I/OA/B
CCA/B
Loaded with 50pF, 10% to 90%
ns
R , D , SCLK, LD, SYNC, ASYNC, NC/NO
IN IN
Low Input Threshold (V )
●
●
●
0.15 • DV
1
V
V
IL
CC
High Input Threshold (V )
0.85 • DV
–1
IH
CC
Input Current (I /I )
µA
IH IL
D
OUT
Low Level Output Voltage (V
)
Sink Current = –200µA
Source Current = 200µA
●
●
0.3
V
V
OL
High Level Output Voltage (V
UNDERV
)
DV – 0.3
CC
OH
Threshold
●
●
1.17
1.23
1.29
50
V
Leakage Current
V
= 3.3V
nA
UNDERV
1955fa
3
LTC1955
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VPVBATT = VSVBATT = 3.3V, DVCC = 3.3V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
FAULT
Low Level Output Voltage (V
Leakage Current
)
Sink Current = –200µA
●
●
0.005
0.3
1
V
OL
V
= 5.5V
µA
FAULT
SYMBOL PARAMETER
Serial Port Timing
CONDITIONS
MIN
TYP
MAX
UNITS
t
D
D
D
Valid to SCLK Setup
Valid to SCLK Hold
●
●
●
●
●
●
●
●
8
ns
ns
ns
ns
ns
ns
ns
ns
DS
IN
t
t
t
t
8
DH
DD
L
IN
Output Delay
C
= 15pF
LOAD
15
50
50
50
50
0
60
OUT
SCLK Low Time
SCLK High Time
LD Pulse Width
SCLK to LD
H
t
LW
CL
LC
t
t
LD to SCLK
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: This specification applies to all three smart card voltage classes:
1.8V, 3V and 5V.
Note 4: The LTC1955E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
ambient temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 3: R
≡ (2V
– V )/I ; V
will depend upon total load
OLCP
BATT
CPO CPO CPO
(I
CCA
+ I ) and minimum supply voltage V
CCB
. See Figure 6.
BATT
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Charge Pump Open-Loop Output
Resistance vs Temperature
(2VIN – VCPO) / ILOAD(MAX)
I/O X Short-Circuit Current vs
No Load Supply Current vs VBATT
Temperature
600
500
400
300
200
100
0
6.0
5.5
5.0
4.5
4.0
3.5
7.0
6.5
6.0
5.5
5.0
4.5
T
I
= 25°C
CCA CCB
DV = V
CCX
= 5.5V
V
V
= 2.7V
A
CC
BATT
IN
CPO
= I
= 0µA
V
= 5V
= 4.9V
V
= V
= 5V
CCB
CCA
V
= 1.8V, V
= 0V
CCA
CCB
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
–40
–15
10
35
60
85
–40
–15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
1955 G01
1955 G02
1955 G03
1955fa
4
LTC1955
U W
TYPICAL PERFOR A CE CHARACTERISTICS
VCCX Overcurrent Shutdown
Threshold vs Temperature
Card Detection Debounce Time vs
BATT Supply Voltage
Bidirectional Channel (I/O A, I/O B)
Low Output Level vs Temperature
V
0.16
0.14
0.12
0.10
0.08
0.06
180
160
140
120
100
80
60
55
50
45
40
35
30
25
V
I
BATT
= 0V
V
V
= 3.3V
DATA
= –1mA
BATT
CPO
V
= 1.8V
CCX
= 5.75V
OL
V
= 2.7V
T
= 85°C
= 25°C
A
A
V
V
= 1.8V
= 3V
CCX
CCX
V
CCX
V
CCX
= 3V
= 5V
T
T
= –40°C
A
V
= 5V
35
CCX
–40
–15
10
35
60
85
–40
–15
10
60
85
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
V
BATT
1955 G06
1955 G04
1955 G05
VBATT Quiescent Current
[IBATT – 2 (ICCA + ICCB)]
vs Load Current
VBATT Shutdown Current vs
Supply Voltage
DVCC Shutdown Current vs Supply
Voltage
1.0
0.8
0.6
0.4
0.2
0
3.0
2.5
2.0
1.5
1.0
0.5
0
10
V
A
= 3.1V
BATT
V
= V
BATT
V
= V
BATT
DVCC
DVCC
9
8
7
6
5
4
3
2
1
0
T
= 25°C
T
T
= –40°C
A
A
T
= –40°C
A
A
T
= 25°C
A
T
= 25°C, 85°C
= 85°C
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
10µ
100µ
1m
10m
100m
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
V
DVCC
LOAD CURRENT (A)
V
BATT
1955 G07
1955 G09
1955 G08
Charge Pump and LDO Activation
Deactivation Sequence
Data – I/O Channel, CL = 50pF
RST A
5V/DIV
VCPO
5V/DIV
I/O A
2V/DIV
CLK A
5V/DIV
VCCA
5V/DIV
I/O A
5V/DIV
DATA
2V/DIV
I/O A
5V/DIV
V
CCA
5V/DIV
1ms/DIV
1955 G10
10µs/DIV
1955 G11.eps
100ns/DIV
1955 G12
1955fa
5
LTC1955
U
U
U
PI FU CTIO S
SVBATT: Power. Supply voltage for analog sections of the
LTC1955.
synchronous card is deselected, the CLK A/CLK B pin for
that channel is latched at its current state.
PVBATT: Power. Supply voltage for the charge pump.
DVCC: Power. Reference voltage for the control logic.
ASYNC: Input. The ASYNC pin provides the clock input for
asynchronous cards and should be connected to a free
running clock. The clock signal to the smart card can be a
÷1,÷2,÷4or÷8versionofthesignalonASYNC.Asynchro-
nous cards can also be placed in clock stop mode with the
clock stopped either high or low.
SGND: Ground. Signal ground for analog sections of the
LTC1955. The exposed pad must be soldered to PCB
ground.
PGND: Ground. Power ground for the charge pump. This
pin should be connected directly to a low impedance
ground plane.
DIN: Input. Input for the serial port. Command data is
shifted into DIN synchronously with SCLK. DIN can be
connected directly to a microcontroller or the DOUT pin of
another LTC1955 for daisy chained operation.
CPO:ChargePump. CPOistheoutputofthechargepump.
When one or both of the smart cards requires power, the
charge pump will charge CPO to either 3.7V or 5.35V
dependingonwhatsmartcardvoltagesarerequired.Alow
impedance 4.7µF X5R or X7R ceramic capacitor is re-
quired on CPO.
C+, C–: Charge Pump. Charge pump flying capacitor pins.
A 1µF X5R or X7R ceramic capacitor should be connected
from C+ to C–.
DOUT: Output. Output for the serial port. Smart card status
dataisshiftedoutofDOUT synchronouslywithSCLK.DOUT
can be connected directly to a microcontroller or the DIN
pin of another LTC1955 for daisy chained operation.
SCLK:Input.TheSCLKpinclockstheserialport.Eachnew
data bit is received on the rising edge of SCLK. SCLK
should be left high during idle times and should not be
clocked when LD is low.
DATA:Input/Output.MicrocontrollersidedataI/Opin.The
DATA pin provides the bidirectional communication path
to both smart cards. One, both or neither of the cards may
be selected to communicate via the DATA pin. If several
LTC1955s are connected in parallel, the DATA pin can be
made high impedance by selecting neither card. The C4A
and C8A synchronous card pins can be selected to con-
nect to the DATA pin via the serial port (see Table 4).
LD: Input. The falling edge of this pin loads the current
state of the shift register into the command register.
Command changes to both smart card channels will be
updated on the falling edge of LD. The rising edge of LD
latches status information from the smart card channels
into the shift register for the next read/write cycle.
NC/NO: Input. This pin controls the activation level of the
PRES A/PRES B pins. When it is high (DVCC), the PRES
pins are active high. When it is low (GND), the PRES pins
areactivelow.WhenagroundsideN.O.switchisused,the
NC/NO pin should be grounded. When a ground side N.C.
switch is used, the NC/NO pin should be connected to
DVCC.
RIN: Input. The RIN pin supplies the RST signal to both
smart cards. It is level shifted and transmitted directly to
the RST pin of a selected card socket. When a card is
deselected,theRSTA/RSTBpinforthatchannelislatched
at its current state.
SYNC: Input. The SYNC pin provides the clock input for
synchronous smart cards. When a synchronous card is
selected, its CLK pin follows SYNC directly. When a
Note: If an N.C. switch is used, a small current (several
microamperes) will flow through the switch whenever a
smart card is not present. For ultralow power consump-
tion in shutdown, an N.O. switch is optimum.
1955fa
6
LTC1955
U
U
U
PI FU CTIO S
PRES A/PRES B: Card Socket. The PRES A/PRES B pins
are used to detect the presence of the smart cards. They
can be connected to either normally open or normally
closed detection switches on the smart card acceptor’s
sockets.TheNC/NOpinshouldbesetappropriately.These
pins have a pull-up current source on-chip so no external
components are required.
CLK A/CLK B: Card Socket. The CLK A/CLK B pins should
be connected to the CLK pins of the respective smart card
sockets. The CLK A/CLK B signals can be derived from
either the SYNC input or the ASYNC input depending on
which type of card is being accessed. The card type is
selected via the serial port (see Tables 1 and 3).
V
CCA, VCCB: Card Socket. The VCCA/VCCB pins should be
C4A/C8A: Card Socket. These pins connect to the C4 and
C8 pins of synchronous memory cards on smart card
socketA.Thesignalforthesepinsisunidirectionalandcan
only be sent to the card. Data for C4A and C8A is transmit-
ted via the DATA pin and may be selected in place of I/OA
via the serial port (see Table 4). When either C4A or C8A
is selected, it will follow the DATA pin. When it is dese-
lected, it will remain latched at its current state.
connected to the VCC pins of the respective smart card
sockets. The activation of a VCCA/VCCB pin is controlled by
the serial port (see Tables 1 and 2) and can be set to 0V,
1.8V, 3V or 5V. The voltage levels of the two card sockets
are controlled independently for maximum flexibility.
FAULT: Output. The FAULT pin can be used as an interrupt
to a microcontroller to indicate when a fault has occurred.
It is an open drain output, which is logically equivalent to
D4 + D5 + D12 + D13. (See Table 1)
I/O A/I/O B: Card Socket. The I/O A/I/O B pins connect to
the I/O pins of the respective smart card sockets. When a
smartcardisselected,itsI/OpinconnectstotheDATApin.
Whenasmartcardisdeselected, itsI/OA/I/OBpinreturns
to the idle state (H).
UNDERV: Input. The UNDERV pin provides security by
supplying a precision undervoltage threshold for external
supply monitoring. An external resistive voltage divider
programs the desired undervoltage threshold. Once
UNDERV falls below 1.23V, the LTC1955 automatically
begins the deactivation sequence on any channel that is
active.
RST A/RST B: Card Socket. These pins should be con-
nected to the RST pins of the respective smart card
sockets. TheRSTA/RSTBsignalsarederivedfromtheRIN
pin. Whenacardisselected, itsRSTpinfollowsRIN. When
a card is deselected, the RST A/RST B pin for that channel
holds the current value on RIN.
If external supply monitoring is not required, the UNDERV
pin should be connected to either SVBATT or DVCC.
1955fa
7
LTC1955
W
BLOCK DIAGRA
CHARGE PUMP
PGND SV
+
–
C
C
PV
CPO
15
BATT
BATT
14
11
10
12
13
CHARGE
PUMP
17
LDO B
8
5
4
3
7
6
V
LDO A
V
CCA
CCB
20
18
19
21
I/O B
CLK B
I/O A
C4A
CLOCK
CONTROL
LOGIC
SMART
CARD
SOCKET B
SMART
CARD
SOCKET A
RST B
C8A
RESET
CONTROL
LOGIC
τ
PRES B
CLK A
RST A
29
31
32
30
DATA
ASYNC
SYNC
SMART
CARD
COMMUNICATIONS
τ
2
PRES A
NC/NO
22
R
IN
24
9
FAULT
SGND
STATUS DATA
27
28
26
25
DIGITAL
SUPPLY
D
IN
SERIAL PORT
COMMAND/STATUS
DATA
D
OUT
1
DV
CC
SHIFT REGISTER
SCLK
LD
23
UNDERV
–
+
COMMAND LATCH
+
1.23V
–
1955 BD
1955fa
8
LTC1955
U
OPERATIO
Serial Port
• Operating mode of asynchronous cards (clock stop
high, low, ÷1, ÷2, ÷4 or ÷8)
The microcontroller compatible serial port provides all of
the command and control inputs for the LTC1955 as well
as the status of the two smart cards. Data on the DIN input
is loaded on the rising edge of SCLK. D15 is loaded first
and D0 last. At the same time the command bits are being
shifted into the DIN input, the status bits are being shifted
out of the DOUT output. The status bits are presented to
• Selection of the I/O, C4 or C8 pins for card socket A
The serial port provides the following status data:
• It indicates the presence or absence of the smart cards.
• It indicates the readiness of the smart card VCC sup-
plies. Communication with a smart card is disabled
until its power supply voltage has reached the final
value.
DOUT on the rising edge of SCLK. Once all bits have been
clockedintotheshiftregister, thecommanddataisloaded
into the command latch by bringing LD low. At this time
the command latch is updated and the LTC1955 will begin
to act on the new command set. When LD is low, the shift
register is transparent to the status data of the two smart
card channels. The status data is latched into the shift
register on the rising edge of LD. SCLK should be held in
the high state when idle and should only be clocked when
LD is high. Likewise LD should only be brought high when
SCLK is high. Figure 2 shows the operation of the serial
port.
• It indicates fault status. In the event of an electrical or
ATR fault, the fault is reported. For electrical faults, the
LTC1955 will automatically deactivate the smart card.
Table 1 illustrates the command inputs and status outputs
associated with each bit of the serial data word.
Three voltage options are available from the LTC1955: 5V,
3V and 1.8V. Bits D0, D1 (card B) and D8, D9 (card A)
determine which voltage is selected. Setting both control
bits of a channel to 0 deactivates that channel and sets the
smart card supply voltage to 0V. If both channels are
deactivated, the LTC1955 is in shutdown. Table 2 shows
the operation of the supply control bits.
Multiple LTC1955s may be daisy-chained together by
connecting the DOUT pin of one LTC1955 to the DIN pin of
another. Figure7showsanexampleofmultipleLTC1955s
daisy chained together.
The CLK A/CLK B pins to the smart cards can be pro-
grammedforvariousmodes.Bothsynchronousandasyn-
chronous cards are supported. There are several options
available with asynchronous cards. Table 3 shows how all
clock options are obtained using bits D5–D7 (card B) and
D13–D15 (card A). The default state of the LTC1955 on
power up is synchronous mode.
The maximum clock rate for the serial port is 10MHz.
The serial port controls the following parameters of each
smart card socket:
• Selection/deselection of a smart card
• VCC voltage level of each card (5V/3V/1.8V/0V)
• Clock mode of each card (synchronous or asynchro-
nous)
t
LC
t
DS
t
DH
t
H
t
L
t
CL
t
LW
t
DD
SCLK
D
IN
X
D15
D14
D2
D1
D0
X
LD
D15 FROM
INPUT
D
OUT
D15
D14
D13
D1
D0
D15
1955 F02
Figure 2. Serial Port Timing Diagram
1955fa
9
LTC1955
U
OPERATIO
Table 1. Serial Port Commands
STATUS OUTPUT
To receive status data from the serial port, a read/write
operation must be performed. When polling for the pres-
ence of a smart card on both channels, the input word
should be set to $0000 since this is the shutdown com-
mand for the LTC1955. However, consider the example
where some operation is already being performed on
channel A. If, for example, the previous command was
$BE00 (VCCA set to 3V, card selected, I/O A connected to
DATAandCLKAsettoASYNC÷2), thenthecommandsfor
this channel must be rewritten to the serial port each time.
To poll for the presence of a card on channel B, or even the
VCCA READY status, then $BE00 should be rewritten on
each new read/write cycle. Once a card is detected on
channel B, the commands for channel B can be changed
but the $BExx should continue to be rewritten for
channel A.
BIT COMMAND INPUT
D0 Options
CARD B
0
0
0
0
V
CCB
D1 (See Table 2)
D2 Card B Select/Deselect
D3 Data Pull-Up Defeat
Card B Electrical Fault D4 Reserved (Always Set to “0”)
Card B ATR Fault
D5 Card B Clock Options
D6 (See Table 3)
D7
Card B V Ready
CC
Card B Present
CARD A
0
0
0
0
D8
V
Options
CCA
D9 (See Table 2)
D10 Card A Select/Deselect
D11 Card A Communications
Card A Electrical Fault D12 Options (See Table 4)
Card A ATR Fault
D13 Card A Clock Options
D14 (See Table 3)
D15
Card A V Ready
CC
Bidirectional Channels
Card A Present
Thebidirectionalchannelsarelevelshiftedtotheappropri-
ate VCCA/B voltages at the I/O A/I/O B pins.
Table 2. VCC and Shutdown Options
An NMOS pass transistor performs the level shifting. The
gate of the NMOS transistor is biased such that the
transistor is completely off when both sides have relin-
quished the channel. If one side of the channel asserts an
L, then the transistor will convey the L to the other side.
Note that current passes from the receiving side of the
channel to the transmitting side. The low output voltage of
thereceivingsidewillbedependentuponthevoltageatthe
transmitting side plus the I • R drop of the pass transistor.
D9
D1
D8 Status (Card A)
D0 Status (Card B)
0
0
1
1
0
1
0
1
V
CC
V
CC
V
CC
V
CC
= 0V (Shutdown)
= 1.8V
= 3V
= 5V
Table 3. Clock Options
D7
D15
D6
D14
D5
D13
Clock Mode Card B
Clock Mode Card A
When a card socket is selected, it becomes a candidate to
drive data on the DATA pin and likewise receive data from
the DATA pin. When a card socket is deselected, the
voltage on its I/O A/I/O B pin will return to the idle state (H)
and the DATA side of that channel will become high
impedance. If both cards are deselected, the DATA pin will
be high impedance.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Synchronous Mode
Unused
Asynchronous Stop Low
Asynchronous Stop High
Asynchronous ÷1
Asynchronous ÷2
Asynchronous ÷4
Asynchronous ÷8
Both cards may be deselected at the same time to allow
communication with a second LTC1955.
Card channel A includes provision for unidirectional com-
munication with the C4 and C8 pins of the smart card. The
C4, C8 and I/O pins of card A are individually multiplexed
to the DATA pin using bits D11 and D12 as shown in
Table 4.
1955fa
10
LTC1955
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OPERATIO
Table 4. Card A Communications Options
D12 D11 Card A Communication Mode
In asynchronous mode the CLK A/CLK B pins follow either
the ASYNC pin (÷1 mode) or a divided version of this pin.
TheCLKA/CLKBpinscanalsobestoppedhighorlow.The
available divider ratios include ÷2, ÷4 and ÷8. When
switching between divider ratios, the internal selection
circuitry ensures that no spikes or glitches appear on the
CLK A/CLK B pins. Consequently, it may take up to 8 clock
pulses for the clock frequency change command to take
affect. Synchronization circuitry ensures that no glitches
occur when entering or exiting one of the stop modes. For
example, when entering stop low mode, the selection
circuitry waits for the next falling edge of the respective
CLK A/CLK B signal to make the change. Likewise if stop
high is selected it will occur on the next rising edge.
0
0
1
1
0
1
0
1
Nothing Selected
C4A Connected to DATA Pin
C8A Connected to DATA Pin
I/O A Connected to DATA Pin
Note that if a reset is initiated with both cards selected,
then both may give an answer to reset and collide on the
DATA line. No damage will occur but data could be lost or
corrupted.
Dynamic Pull-Up Current Sources
Thecurrentsourcesonthebidirectionalpins(DATA,I/OA/
I/O B) are dynamically activated to achieve a fast rise time
with a relatively small static current*. Once a bidirectional
pin is relinquished, a small start up current begins to
charge the node. An edge rate detector determines if the
pin is released by comparing its slew rate with an internal
reference value. If a valid transition is detected, a large
pull-up current enhances the edge rate on the node. The
higher slew rate corroborates the decision to charge the
node thereby affecting a dynamic form of hysteresis.
Deselection of an asynchronous card does not affect its
CLK A/CLK B pin. Its clock can be started, stopped or its
divider ratio changed at any time.
To clean up the duty cycle of the incoming clock in
asynchronousapplications,anyoftheclockdividermodes
÷2, ÷4 or ÷8 will yield a very nearly 50% duty cycle.
Additionalsynchronizationcircuitrypreventsglitchesfrom
occurring when switching between synchronous mode
and asynchronous mode. Because of this circuitry, two
edges (a falling edge followed by a rising edge) are
necessary at the CLK pin to switch modes from asynchro-
nous to synchronous. For example, if clock stop mode is
engaged, the clock channel will not change modes until
clock stop mode is disengaged.
LOCAL
SUPPLY
V
REF
+
–
I
START
dv
dt
BIDIRECTIONAL
PIN
Anycombinationofcards,synchronousorasynchronous,
can be used as both channels can be set to any of the clock
modes or divider ratios independently.
1955 F03
Figure 3. Dynamic Pull-Up Current Sources
Clock Channels
Both SYNC and ASYNC inputs are independently level
shifted to the appropriate voltage for the CLK A/CLK B pins
(5V, 3V, 1.8V).
As described in the section Serial Port, the LTC1955
supports both synchronous and asynchronous smart
cards. On start-up, or when bits D13-D15 for card A and
bits D5-D7 for card B are set to 0s, the clock channel is in
synchronous mode. The remaining modes are used for
asynchronous cards.
Reset Channels
When a card is selected, the reset channels provide a level
shifted path from the RIN pin to the RST A/RST B pins.
When a card is deselected its RST A/RST B pin is latched
at the current value of RIN.
In synchronous mode the CLK A/CLK B pins follow the
SYNC pin for a channel that is selected. If a channel is
deselected(viatheserialport)theCLKA/CLKBlineforthat
channel is latched at its current value.
*U.S. Patent No. 6,356,140
1955fa
11
LTC1955
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OPERATIO
Smart Card Detection Circuits
Manual deactivation may be performed under software
control by setting the smart card pins to 0V in the desired
sequence via the control pins (SYNC, ASYNC, RIN, DATA
and the serial port). For most applications this will be
cumbersome and the built-in deactivation will be used
instead.
The PRES A/PRES B pins are used to detect the presence
of a smart card. An automatic debounce circuit waits until
a smart card has been present for a continuous period of
typically 35ms. Once a valid card indication exists, the
status bit for that channel is updated and may be polled by
cycling data through the serial port. The DOUT pin (equiva-
lent to D15) of the serial port can be used to indicate the
presence of a card on channel A in real time if LD is held
low.
Automatic Deactivation
The built-in deactivation sequence can be executed via the
serial port simply by setting the appropriate control bits
(D0 and D1 or D8 and D9) to 0. The deactivation sequence
is outlined below.
The PRES A/PRES B pins have built-in pull-up current
sources so no external components are required for
switch detection. The pull-up current sources are de-
signed to have a small current when the pin voltage is
below approximately 1V but somewhat higher current
when the pin voltage reaches 1V. This helps maintain low
power dissipation when a card is present and yet fast
response time to a card removal.
1. The RST A/RST B pin for that channel is immediately
brought low.
2. ThedeactivationoftheCLKA/CLKBpinsdependsupon
which type of card is used:
If the smart card was set to asynchronous mode then
theCLKA/CLKBpinwillbelatchedlowonitsnextfalling
edge. Ifnofallingedgesoccurwithin5µs(min)thenthe
CLK A/CLK B line is forced low.
The PRES A/PRES B pins can be configured to respond to
either normally open or normally closed switches via the
NC/NO pin.
If the smart card was set to synchronous mode then the
CLK A/CLK B pin is immediately latched at its current
value (either high or low) and then forced low after a
duration of 5µs (min). During the 5µs timeout period
changes on SYNC will be ignored.
Activation/Deactivation
For maximum flexibility, the activation sequencing of the
smart card is left to the application programmer. Upon
activation, to comply with relevant smart card standards,
none of the smart card signal pins will be allowed to go
highbeforethesmartcardsupplyvoltage(VCCA/VCCB)has
reached its final value. Deactivation can be achieved either
manuallyorautomatically. Anelectricalfaultconditionwill
trigger the automatic deactivation.
3. The I/O A/I/O B, C4A and C8A pins for that channel are
brought low.
4. The VCCA/VCCB pin is brought low.
Ifanerroroccursononesmartcard, operationoftheother
card is unaffected.
1955fa
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LTC1955
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OPERATIO
Short circuits on the I/O A/I/O B lines will not be detected
by the fault detection hardware; however, a short circuit
from these lines to their respective VCCA/VCCB pins will be
compliant with the maximum current limits set by appli-
cable standards (<15mA).
Electrical Fault Detection
Several types of faults are detected by the LTC1955. They
include VCCA/VCCB undervoltage, VCCA/VCCB overcurrent,
CLK A/CLK B, RST A/RST B, C8A, C4A short circuit, card
removalduringatransaction,failedanswertoreset(ATR),
supplyundervoltageorUNDERVandchipovertemperature.
To prevent false errors from plaguing the microcontroller,
the electrical faults are acted upon only after a 5µs (min)
timeout period. Card removal during transaction faults
initiate the deactivation sequence immediately.
An electrical fault can be cleared on either channel by
setting the voltage of that channel to 0V. Set D0 and D1 to
OO to clear channel B and set D8 and D9 to 00 to clear
channel A. It is not necessary to set all four bits to zeros.
Answer to Reset (ATR) Fault Detection
V
CCA/VCCB under voltage faults are determined by com-
Answer to Reset faults are detected by an internal counter
that is started once the RST A/B line goes high. If the DATA
pin remains high for 40,000 clock cycles, the ATR fault bit
for a given channel is set in the serial port’s status register
(see Table 1) and the FAULT pin is brought low.
paringtheactualoutputvoltagewiththeinternalreference
voltage. If the output is more than ~5% below its set point
for the entire timeout period, the fault is reported and the
deactivation sequence is initiated.
V
CCA/VCCB overcurrent faults are detected by comparing
An ATR fault can not occur if the clock mode of a channel
is set to synchronous. ATR faults will only occur for
asynchronous smart cards.
the output current of the LDOs with an internal reference
level. IfthecurrentofanLDOismorethan100mA(typ)for
the entire timeout period, the fault is reported and the
deactivation sequence is initiated.
ATR faults are cleared by bringing the RST A/B pin low for
the faulted channel. This will also clear the FAULT pin to
the Hi-Z state (assuming no other errors are causing
FAULT to be low).
CLK A/CLK B and RST A/RST B faults are detected by
comparing the outputs of these pins with their expected
signals. If the signal on a pin is incorrect for the entire
timeout period, the fault is reported and the deactivation
sequence is initiated.
An ATR fault will not automatically deactivate a card
channel. It is the application programmer’s responsibility
to check the status register for ATR faults and deactivate
the smart card channel in accordance with smart card
standards. Generally the application has 50ms (EMV
2.1.3.1, 2.1.3.2) from the 40,000th clock pulse to deacti-
vate the card. Once the LTC1955 receives the deactivation
command, it will shut down a card channel in less than
250µs.
The clock channels are a special case. Since they can have
a free running clock, the error indication is accumulated
over a longer period of time without being cleared. Even
though the clock may be running, an error will still be
detected.
An overtemperature fault is detected by sensing the junc-
tion temperature of the IC. If the junction temperature
exceeds approximately 150°C for the entire timeout
period, the fault is reported by setting both fault bits (D4
and D12) and the deactivation sequence is initiated.
Using the FAULT Pin
The FAULT pin can be used as an interrupt to a
microcontroller. It is an open-drain output and generally
requiresapull-upresistor.TheFAULTpinwillgolowwhen
either an electrical fault or an answer to reset fault occurs
on either channel. Thus there are four possible faults that
can cause it to indicate a problem. The serial port’s status
register must be polled to find out what type of fault
occured and on which channel. The FAULT pin is logically
equivalent to D4+D5+D12+D13 (see Table 1).
A card removal fault is determined as soon as the PRES A/
PRES B pin is high (for NC/NO = 0). Once this occurs the
fault is reported and the deactivation sequence is initiated.
Ifnocardispresent,andtheapplicationsoftwareattempts
to power up a card socket, an automatic fault will result on
that channel.
1955fa
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APPLICATIO S I FOR ATIO
10kV ESD Protection
(i.e., minimum inductance). The PVBATT/SVBATT nodes
should be especially well bypassed. The capacitor for this
node should be directly adjacent to the QFN package. The
All smart card pins (CLK A/CLK B, RST A/RST B, I/O A/
I/O B, C4A, C8A and VCCA/VCCB) can withstand over 10kV
of human body model ESD in-situ. In order to ensure
proper ESD protection, careful board layout is required.
The PGND and SGND pins should be tied directly to a
groundplane.TheVCCA/VCCB capacitorsshouldbelocated
very close to the VCCA/VCCB pins and tied immediately to
the ground plane.
C
PO andflyingcapacitorsshouldbeverycloseaswell. The
LTC1955 can tolerate more distance between the LDO
capacitors and the VCCA/B pins.
Figure 4 shows an example of a tight printed circuit board
using single layer copper. For best performance a multi-
layerboardcanbeusedandshouldemployasolid ground
plane on at least one layer.
Capacitor Selection
The following capacitors are recommended for use with
the LTC1955:
Warning: A polarized capacitor such as tantalum or alumi-
num should never be used for the flying capacitor since its
voltage can reverse upon start up of the LTC1955. Low
ESR ceramic capacitors should always be used for the
flying capacitor.
Type
Value
Case Size Murata P/N
C
CPO
X5R
4.7µF
0805
0603
0402
GRM40-034 X5R 475K 6.3
IN
C
V
X5R
X5R
1µF
GRM39 X5R 105K 6.3
GRM36 X5R 104K 10
FLY
A total of six capacitors are required to operate the
LTC1955. AninputbypasscapacitorisrequiredatPVBATT
CCA/B
CDV
0.1µF
,
CC
SVBATT and DVCC. Output bypass capacitors are required
on each of the smart card VCCA/VCCB pins. A charge pump
flying capacitor is required from C+ to C– and a charge
storage capacitor is required on the charge pump out pin
CPO.
To prevent excessive noise spikes due to charge pump
operation, low ESR (equivalent series resistance) multi-
layer ceramic capacitors are strongly recommended.
V
There are several types of ceramic capacitors available
each having considerably different characteristics. For
example,X7R/X5Rceramiccapacitorshaveexcellentvolt-
age and temperature stability but relatively low packing
density. Y5V ceramic capacitors have apparently higher
packing density but poor performance over their rated
voltage or temperature ranges. Under certain voltage and
temperature conditions, Y5V and X7R/X5R ceramic ca-
pacitors can be compared directly by case size rather than
specified value for a desired minimum capacitance.
CCA
Placementofthecapacitorsiscriticalforcorrectoperation
oftheLTC1955.Becausethechargepumpgenerateslarge
current steps, all of the capacitors should be placed as
close to the LTC1955 as possible. The low impedance
nature of multilayer ceramic chip capacitors will minimize
voltage spikes but only if the power path is kept very short
GND
V
V
CCB
BATT
1955 F04
Figure 4. Optimum Single Layer PCB Layout
1955fa
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APPLICATIO S I FOR ATIO
Interfacing to a Microcontroller
Daisy-Chained Operation
The serial port of the LTC1955 can be connected directly
to a 68HC11 style microcontroller’s serial port. The
microcontrollershouldbeconfiguredasthemasterdevice
and its clock’s idle state should be set to high (MSTR = 1,
CPOL = 1 and CPHA = 0 for the MC68HC11 family).
Figure 4 shows the recommended configuration and di-
rection of data flow. Note that an additional I/O line is
necessaryforLDtoloadthedataonceithasshiftedaround
the loop. Command data is latched into the command
register on the falling edge of the LD signal. The LTC1955
willbegintoactonnewcommanddataassoonasLDgoes
low. Any general purpose microcontroller I/O line can be
configured to control the LD pin.
Forapplicationsrequiringmorethantwocardsockets, the
serial port of the LTC1955 is designed to be easily daisy-
chained. The DOUT pin of one LTC1955 can be connected
directly to the DIN pin of another LTC1955. Rather than
sending two 8-bit bytes before asserting LD, the
microcontroller should send two 8-bit bytes per device.
LD should only be asserted after all devices have been
updated. Figure 7 shows three LTC1955s cascaded in
daisychainfashion. Inthiscasethemicrocontrollerwould
write six 8-bit bytes before asserting the LD pin. Alterna-
tively,iftwoserialportsareavailableonthemicrocontroller,
then two LTC1955s can be controlled independently.
If the DATA lines of two or more LTC1955s are connected
together, the static pull-up current will be the sum of the
devices. Thestaticcurrentcanbebroughtbacktothelevel
of a single LTC1955 by setting bit D3 on all but one of the
LTC1955s to 1 (see Table 1). Bit D3 disables the pull-up
current source on the DATA pin. This will help prevent VOL
problems in multiple LTC1955 applications when driving
the DATA or I/O pins low.
The status of the LTC1955 is returned over the serial port.
Status data is latched into the shift register on the rising
edge of the LD pin. Whenever the system is waiting for
status data from the LTC1955, its LD pin should be held
low.
µCONTROLLER
LTC1955
MOSI
D
D
IN
CARD A
MISO
SCK
I/O
OUT
SCLK
LD
CARD B
1955 F05
Figure 5. Microcontroller Interface
1955fa
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LTC1955
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APPLICATIO S I FOR ATIO
Using S.A.M. Cards
Using the UNDERV Pin
For applications using one or more installed S.A.M. cards,
the PRES A/PRES B pins for those sockets must be
grounded before operation of the card can occur (assum-
ing NC/NO is grounded). The PRES A/PRES B pull-up
currentisdesignedforverylowconsumption,butultralow
current can be achieved in shutdown by using a
microcontroller output to pull down on the PRES A/PRES
B pins only when communication is necessary. The fault
detection circuitry will not allow a card socket to be
operated unless a card is detected.
The UNDERV pin can be used to add protection against a
supplyundervoltagefault. Byusingtwoexternalprogram-
mingresistors, theundervoltagedetectioncanbesettoan
arbitrary level (Figure 8). To ensure that the smart cards
are properly shut down, there must be sufficient energy
available in the input bypass capacitor to run one or both
smart cards until the deactivation cycle begins. It can take
approximately 30µs from the detection of a fault until the
deactivation sequence begins. It is desirable to maintain
the VBATT supply at 2.7V or greater during this period.
Consider the following (worst-case) example:
Asynchronous Channel A Card Detection
1) The UNDERV pin is programmed to trip below 3.1V.
Since the shift register is transparent when LD is held low,
DOUT is the same as D15. Recall from Table 1 that D15
indicates the status of the card detection channel for
channel A. Thus, it is not necessary to perform an entire
read/write operation to determine the card detection sta-
tus of channel A. With LD low, DOUT can be used to
generate a real time card detection interrupt. This could be
useful for one S.A.M. card, one smart card application.
2) It is possible to have both cards activated at 5V and
drawing 60mA.
Since the output voltage is programmed to 5V, the charge
pump will be acting as a voltage doubler. With two cards
drawing 60mA each, the input current will be 2 • (60mA +
60mA) or about 240mA. Allowing the VBATT supply to
droop from 3.1V to 2.7V during the 30µs timeout period,
the input capacitance would need to be at least
240mA / [(3.1V – 2.7V) / 30µs] or 18µF.
Inter Card Communication
Communication is possible directly from one card socket
totheotherwhenbothcardsareselectedatthesametime.
Thiscanbeachievedbythefollowingsequenceofactions.
Thermal Management
To minimize power dissipation, the LTC1955 will actively
decide whether to step up or down depending on the
requiredoutputvoltagesandavailableinputvoltage. How-
ever, for optimum efficiency, the LTC1955 should be
powered from a 3.3V supply.
1) Start with both cards off and deselected
2) Activate the supply of the slave card
3) Select the slave card only
4) Initiate a reset on the slave card
5) Deselect the slave card
If the input voltage is above 3.6V, and both cards are
drawingmaximumcurrent,therecanbesubstantialpower
dissipation in the LTC1955. If the junction temperature
increases above approximately 150°C, the thermal shut-
down circuitry will automatically deactivate both chan-
nels. To reduce the maximum junction temperature, a
good thermal connection to the PC board is recom-
mended.
6) Activate the supply of the master card
7) Select the master card only
8) Initiate a reset on the master card
9) Select both cards
Zero Shutdown Current
Although the LTC1955 is designed to have very low
shutdown current, it can still draw over a microampere on
1955fa
16
LTC1955
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APPLICATIO S I FOR ATIO
both DVCC and VBATT when in shutdown. For applications
that require virtually zero shutdown current, the DVCC pin
canbegrounded. ThiswillreducetheVBATT currenttowell
under a single microampere. Internal logic ensures that
the LTC1955 is in shutdown when DVCC is grounded.
Note, however, that all of the logic signals that are refer-
enced to DVCC (DIN, SCLK, LD, DATA, RIN, SYNC, ASYNC
and NC/NO) will have to be at 0V as well to prevent ESD
diodes to DVCC from being forward biased.
ROLCP is dependent on a number of factors including the
switching term, 1/(fOSC • CFLY), internal switch resis-
tances and the nonoverlap period of the switching circuit.
However,foragivenROLCP,theminimumCPOvoltagecan
be determined from the following expression:
VCPO ≥ 2VBATT – (ICCA + ICCB)ROLCP
The LDOs have been designed to meet all applicable smart
card standards for VCC with VCPO as low as 5.13V. Given
this information, trade-offs can be made by the user with
regard to total consumption (ICCA + ICCB) and minimum
supply voltage.
Operation at Higher Supplies
If a 5.5V to 6V supply voltage is available, it is possible to
achieve some power savings by bypassing the charge
pump. The higher supply can be connected directly to the
CPO pin. As long as the voltage on CPO is higher than that
at which it ordinarily regulates (5.35V or 3.7V depending
on voltage selections) the charge pump’s oscillator will
not run. This configuration can give considerable power
savings since the charge pump is not being used.
R
OLCP
CPO
+
2V
BATT
LDO A
V
CCA
LDO B
V
CCB
–
1955 F06
Figure 6. Equivalent Open-Loop Circuit
A voltage source is still needed on both DVCC and SVBATT
/
PVBATT in this configuration. Recall that DVCC sets the
logic reference level for all the control and smart card
communication pins. The voltage on SVBATT/PVBATT can
be any convenient level that meets the parameters in the
Electrical Characteristics table.
Changing the Smart Card Supply Voltage
Although the LTC1955 control system will allow the smart
card voltage to be changed from one value to the next
without an interim power down, this is not recommended.
When changing from a higher voltage to a lower voltage
there will generally not be a problem; however, changing
from a lower voltage to a higher voltage will result in both
an undervoltage condition and an overcurrent condition
on that channel. The likely result is that the channel will
automatically deactivate. Applicable smart card standards
specify that the smart card supply be powered to zero
before applying a new voltage.
The 5.5V to 6V supply can be left permanently connected
to CPO but there will be approximately 5µA of current flow
into CPO when the LTC1955 is in shutdown.
Charge Pump Strength
Under low VBATT conditions, the amount of current avail-
able to the smart cards is limited by the charge pump.
Figure 6 shows how the LTC1955 can be modeled as a
Thevenin equivalent circuit to determine the amount of
current available given the effective input voltage, 2VBATT
Compliance Testing
Inductance due to long leads on type approval equipment
can cause ringing and overshoot that leads to testing
problems. Small amounts of capacitance and damping
resistors can be included in the application without com-
promising the normal electrical performance of the
LTC1955 or smart card system. Generally a 100Ω resistor
and a 20pF capacitor will accomplish this as shown in
Figure 9.
and the effective open-loop output resistance, ROLCP
.
From Figure 6, the available current is given by:
2VBATT – VCPO
ICCA + ICCB ≤
ROLCP
1955fa
17
LTC1955
U
W U U
APPLICATIO S I FOR ATIO
1µF
4.7µF
11
14
21
2
–
+
C
C
C
C
PRES B PRES A
12, 13
9, 10
1
V
BATT
INPUT
SMART CARD
VENDOR CARD
GND
DV
POWER
CC
23
UNDERV
24
FAULT
FAULT
27
28
26
25
LTC1955
D
D
IN
4-WIRE
COMMAND
INTERFACE
OUT
SCLK
LD
29
30
32
31
15
15
15
DATA
CPO
4-WIRE
CARD
INTERFACE
4.7µF
4.7µF
4.7µF
R
IN
SYNC
ASYNC
1µF
4.7µF
11
–
14
+
21
2
C
PRES B PRES A
12, 13
9, 10
1
V
BATT
SMART CARD
VENDOR CARD
GND
DV
CC
23
UNDERV
24
FAULT
27
28
26
25
LTC1955
D
D
IN
OUT
SCLK
LD
29
30
32
31
DATA
CPO
R
IN
SYNC
ASYNC
1µF
4.7µF
11
–
14
+
21
2
C
PRES B PRES A
12, 13
9, 10
1
V
BATT
VENDOR CARD
VENDOR CARD
GND
DV
CC
23
UNDERV
24
FAULT
27
28
26
25
LTC1955
D
D
IN
OUT
SCLK
LD
29
30
32
31
DATA
CPO
R
IN
SYNC
ASYNC
1955 F07
Figure 7. Multiple LTC1955s Daisy Chained Together
1955fa
18
LTC1955
U
W
U U
APPLICATIO S I FOR ATIO
MAIN SUPPLY
100Ω
100Ω
100Ω
V
= 1.23V (1 + R1/R2)
I/O X
CLK X
RST X
C7
TRIP
R1
R2
20pF
SMART
23
C3
CARD
UNDERV
LTC1955
LTC1955
20pF
SOCKET
C2
20pF
1µF
V
CCX
C1
C5
0.1µF
1955 F08
1955 F09
Figure 8. Setting the Undervoltage Trip Point
Figure 9. Additional Components for
Improved Compliance Testing
U
PACKAGE DESCRIPTIO
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.45 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
BOTTOM VIEW—EXPOSED PAD
0.23 TYP
R = 0.115
TYP
(4 SIDES)
0.75 ± 0.05
5.00 ± 0.10
(4 SIDES)
31 32
0.00 – 0.05
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.45 ± 0.10
(4-SIDES)
(UH) QFN 0603
0.200 REF
0.25 ± 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
1955fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC1955
U
TYPICAL APPLICATIO
0.1µF
FAULT
0.1µF
180k
262k
+
0.1µF
4.7µF
47k
37
47k
RESET
Li-ION
16
17
4
21
45 19
1
23
UNDERV
12, 13
1k
RXEN DREN
V
CC
MOD B
V
DD
V
XIRQ
DV
V
BATT
4
5
3
RH
CC
V
CC18
V
CC3
V
CCA
36
1
24
RST
RST
FAULT
LTC1728ES5-1.8
GND
LTC1348CG
MC68L11E9PB2
LTC1955EUH
3
4
5
6
7
8
C8
C4
C7
C2
C3
C1
2
DB9
C8A
C4A
RD
TD
2
3
7
8
25
24
40
39
38
42
41
43
44
DR1OUT
DR1IN
PD1 (TXD)
PD0 (RXD)
IRQ
I/O A
CARD A
C5
27
28
26
25
RX1IN
RX1OUT
(MOSI) PD3
(MISO) PD2
(SCK) PD4
(SS) PD5
D
D
RST A
CLK A
IN
OUT
GND
5
SCLK
LD
V
CCA
1µF
0.1µF
2
5
27
26
+
+
PRES A
C1
C3
0.1µF
0.1µF
0.1µF
6
2
–
–
C1
C3
+
C2
24
8
31
32
30
29
20
19
18
17
C7
C2
C3
C1
(2MHz) E
PB1
ASYNC
SYNC
I/O B
RST B
CLK B
CARD B
C5
3
–
C2
9
PB0
R
IN
1
(IC3) PA0
PC0
DATA
V
CCB
28
1µF
0.1µF
21
PRES B
+
–
–
+
GND
15
V
V
MODA EXTAL XTAL
V
V
C
C
CPO
15
GND NC/NO
RL SS
1
28
18 20
22
26
27
11
14
9, 10
22
0.1µF
0.1µF
4.7µF
10M
1µF
8.000MHz
27pF
27pF
1955 TA02
Battery Powered RS232 to Dual Smart Card Interface
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V = 3V/5V, V = 2.7V to 6V,
OUT
SSOP-16/-24 Package
LTC1755/LTC1756
ISO 7816-3 and EMV Compatible Smart Card Interface
SIM Power Supply and Level Translator Step-Up/Step-Down Charge Pump
SIM Power Supply and Level Translator Step-Up/Step-Down Charge Pump
SIM Power Supply and Level Translator
IN
LTC1555
V
OUT
= 3V/5V, V = 2.7V to 10V,
IN
SSOP-16/-20 Package
LTC1555L-1.8
LTC4555
V
OUT
= 1.8V/3V/5V, V = 2.6V to 6V,
IN
SSOP-16 Package
V
OUT
= 1.8V/3V, V = 3V to 6V, 3mm × 3mm
IN
QFN Package
LTC4556
SIM Power Supply and Level Translator
V
OUT
QFN Package
= 1.8V/3V, V = 3V to 6V, 3mm × 3mm
IN
LTC4557
SIM Power Supply and Level Translator
V
OUT
QFN Package
= 1.8V/3V, V = 3V to 6V, 3mm × 3mm
IN
1955fa
LT/TP 1004 1K REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2002
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