LTC1955IUH#TRPBF_技术文档

LTC1955

Dual Smart Card Interface

with Serial Control

FeaTures

DescripTion

The LTC^®1955 provides all necessary supervisory and

power control functions for two smart cards, two S.A.M.

cards or a combination of S.A.M. and smart cards. It

provides a charge pump for battery-powered applications

as well as all necessary level shifting circuitry.

n

Compatible with ISO7816-3 and EMV Electrical

Speciﬁcations

n

Power Management and Control for Two Smart Cards

n

Control/Status Serial Port May Be Daisychained for

Multicard Applications

Automatic Shutdown on Electrical Faults

n

The card voltages can be independently set to 1.8V, 3V or

5V. Both card interfaces include a card detection channel

withautomaticdebouncecircuitry.Toreducewiringcosts,

the LTC1955 interfaces to a microcontroller via a simple

4-wire serial interface. Multiple devices may be connected

in daisychain fashion so that the number of wires to the

cardsocketboardisindependentofthenumberofsockets.

Status data is returned over the same interface.

n

Buck/Boost Charge Pump Generates 5V, 3V or 1.8V

Outputs (Smart Card Classes A, B and C)

n

Independent 5V/3V/1.8V Level Control for Both Cards

n

Automatic Level Translation

n

Supervisory Functions Prevent Smart Card Faults

n

Low Operating Current: 250µA Typical

n

Ultralow Shutdown Current

>10kV ESD on Smart Card Pins

n

Extensive security features ensure proper deactivation

sequencing in the event of a supply fault or a smart card

electrical fault. The smart card pins can withstand greater

than 10kV ESD in-situ with no additional components.

Small 32-Lead 5mm × 5mm QFN Package

applicaTions

n

Handheld Payment Terminals

n

Pay Telephones

The LTC1955 is available in a low proﬁle (0.75mm) 5mm

× 5mm QFN package.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 6356140, 6411531.

n

ATM Machines

POS Terminals

Computer Keyboards

Multiple S.A.M. Sockets

n

240k

180k

Typical applicaTion

23

CARD

DETECT

UNDERV

1

2

DV

PRES A

CC

12,13

V

BATT

INPUT

POWER

0.1µF

4.7µF

LTC1955

Deactivation Sequence

3

4

5

6

7

8

9, 10

24

C8A

C4A

GND

I/O A

FAULT

RST A

5V/DIV

RST A

CLK A

27

28

26

25

D

IN

SMART CARD

CLK A

5V/DIV

4-WIRE

COMMAND

INTERFACE

V

OUT

CCA

SCLK

1µF

21

LD

PRES B

I/O A

5V/DIV

V

CCA

5V/DIV

29

30

32

31

22

20

19

18

17

DATA

I/O B

RST B

CLK B

4-WIRE

CARD

INTERFACE

1955 TA01a

R

IN

SYNC

10µs/DIV

VENDOR CARD

ASYNC

NC/NO

V

CCB

1µF

+

–

C

CPO

15

1955 TA01b

14

11

1µF

4.7µF

1955fd

1

For more information www.linear.com/LTC1955

LTC1955

absoluTe MaxiMuM raTings

pin conFiguraTion

(Note 1)

TOP VIEW

V

, DV , CPO, FAULT,

BATT CC

UNDERV to GND ....................................... –0.3V to 6.0V

PRES A/PRES B, DATA, R , SYNC, ASYNC,

IN

LD, D , SCLK to GND.................–0.3V to (DV + 0.3V)

IN

CC

CCA

CCB

32 31 30 29 28 27 26 25

I/O A............................................ –0.3V to (V

+ 0.3V)

DV

1

2

3

4

5

6

7

8

24 FAULT

CC

PRES A

C8A

23 UNDERV

I/O B............................................ –0.3V to (V

VCCA CCB

NC/NO

22

21

I

/IV .............................................................80mA

C4A

PRES B

33

SGND

V

/V

Short-Circuit Duration..................... Indeﬁnite

CCA CCB

I/O A

20 I/O B

RST B

Operating Temperature Range (Note 4).... –40°C to 85°C

Junction Temperature ........................................... 125°C

Storage Temperature Range................... –65°C to 125°C

RST A

CLK A

19

18 CLK B

17

V

CCA

CCB

9

10 11 12 13 14 15 16

UH PACKAGE

32-LEAD (5mm × 5mm) PLASTIC QFN

T

= 125°C, θ = 34°C/W

JA

JMAX

EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH

LTC1955EUH#PBF

LTC1955IUH#PBF

LEAD BASED FINISH

LTC1955EUH

TAPE AND REEL

PART MARKING*

1955

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC1955EUH#TRPBF

LTC1955IUH#TRPBF

TAPE AND REEL

–40°C to 85°C

32-Lead (5mm × 5mm) Plastic QFN

PACKAGE DESCRIPTION

1955

–40°C to 85°C

PART MARKING*

1955

TEMPERATURE RANGE

–40°C to 85°C

LTC1955EUH#TR

LTC1955IUH#TR

32-Lead (5mm × 5mm) Plastic QFN

LTC1955IUH

1955

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

elecTrical characTerisTics ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_PVBATT= V_SVBATT= 3.3V, DV_CC= 3.3V, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Input Power Supply

l

V

Operating Voltage

2.7

5.5

V

BATT

l

I

+ I

SVBATT

Operating Current

V

CCA

V

CCA

= 5V, V

= 0V, I = 0µA

CCA

250

350

400

500

µA

PVBATT

CCB

= V

= 5V, I

= I

= 0µA

CCB

CCA

CCB

l

I

+ I

Shutdown Current

No Cards Present. V

= 0V

0.75

1.75

5.5

µA

V

PVBATT

SVBATT

CPO

DV Operating Voltage

1.7

CC

1955fd

2

For more information www.linear.com/LTC1955

LTC1955

elecTrical characTerisTics ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_PVBATT= V_SVBATT= 3.3V, DV_CC= 3.3V, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

10

MAX

25

UNITS

µA

l

I

Operating Current

Shutdown Current

DVCC

0.5

1.5

µA

Charge Pump

5V Mode Open-Loop Output Resistance

l

R

V

= 3.075V, I

= I

+ I = 120mA (Note 3)

CCB

5.7

0.6

8.5

1.5

Ω

OLCP

BATT

CPO

CCA

CPO Turn-On Time

Smart Card Supplies V , V

I

= 0mA, 10% to 90%

ms

CCA/B

CCA CCB

l

V

Output Voltage

5V Mode, 0 < I

3V Mode, 0 < I

< 60mA

4.65

2.75

1.65

5

3

1.8

5.35

3.25

1.95

V

CCA/B

< 50mA

< 30mA

1.8V Mode, 0 < I

CCA/B

l

V

Turn-On Time

I

= 0mA, 10% to 90%

0.8

–5

1.5

–2.5

135

ms

%

CCA/B

Undervoltage Detection

Overcurrent Detection

Smart Card Detection

Relative to Nominal Output

5V Mode

–9

65

100

mA

l

V

I

= 0V

20

35

1.25

20

60

2.5

250

ms

µA

µs

Debounce Time ( PRES A/B to

PRES A, PRES B Pull-Up Current

D15/D7)

NC/NO

= 0

PRESA/B

= 0mA, C

= 1µF

VCCA/B

Deactivation Time ( RST to V = 0.4V)

CCA/B

CC

CLK A, CLK B

l

Low Level Output Voltage (V ), (Note 2)

Sink Current = –200µA

0.2

16

V

OL

High Level Output Voltage (V ), (Note 2)

Source Current = 200µA

V

– 0.2

CCA/B

OH

Rise/Fall Time (Note 2)

Loaded with 50pF, 10% to 90%

ns

CLK A, CLK B Frequency (Note 2)

RST A, RST B, C4A, C8A

10

MHz

l

Low Level Output Voltage (V ), (Note 2)

Sink Current = –200µA

0.2

100

0.3

V

OL

High Level Output Voltage (V ), (Note 2)

Source Current = 200µA

Loaded with 50pF, 10% to 90%

V

– 0.2

CCA/B

OH

Rise/Fall Time (Note 2)

ns

I/O A, I/O B

l

Low Level Output Voltage (V ), (Note 2)

Sink Current = –1mA (V

= 0V)

V

OL

DATA

High Level Output Voltage (V ), (Note 2)

Source Current = 20µA (V

= V

)

0.85 • V

CCA/B

OH

DATA

DVCC

Rise/Fall Time (Note 2)

Short-Circuit Current (Note 2)

DATA

Loaded with 50pF, 10% to 90%

= 0V

500

10

ns

V

5

mA

DATA

l

Low Level Output Voltage (V

)

Sink Current = –500µA (V

Source Current = 20µA (V

= 0V)

0.3

500

V

OL

I/OA/B

High Level Output Voltage (V

Rise/Fall Time

)

OH

= V

)

0.8 • DV

CC

I/OA/B

CCA/B

Loaded with 50pF, 10% to 90%

ns

R , D , SCLK, LD, SYNC, ASYNC, NC/NO

IN IN

l

Low Input Threshold (V )

0.15 • DV

1

V

IL

CC

High Input Threshold (V )

0.85 • DV

–1

IH

CC

Input Current (I /I )

µA

IH IL

1955fd

3

For more information www.linear.com/LTC1955

LTC1955

elecTrical characTerisTics ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_PVBATT= V_SVBATT= 3.3V, DV_CC= 3.3V, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

D

OUT

l

Low Level Output Voltage (V

)

Sink Current = –200µA

Source Current = 200µA

0.3

V

OL

High Level Output Voltage (V

UNDERV

)

OH

DV – 0.3

CC

l

Threshold

1.17

1.23

0.005

TYP

1.29

50

V

Leakage Current

FAULT

V

= 3.3V

nA

UNDERV

l

Low Level Output Voltage (V

Leakage Current

)

Sink Current = –200µA

= 5.5V

0.3

1

V

OL

V

µA

FAULT

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNITS

Serial Port Timing

l

t

D

Valid to SCLK Setup

Valid to SCLK Hold

8

ns

DS

DH

DD

L

IN

8

IN

Output Delay

C

= 15pF

LOAD

15

50

0

60

OUT

SCLK Low Time

SCLK High Time

SCLK to LD

H

CL

LC

LFC

LD to SCLK

LD Falling to SCLK

50

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: This speciﬁcation applies to all three smart card voltage classes:

1.8V, 3V and 5V.

Note 4: The LTC1955E is guaranteed to meet performance speciﬁcations

from 0°C to 85°C. Speciﬁcations over the –40°C to 85°C operating

ambient temperature range are assured by design, characterization and

correlation with statistical process controls. The LTC1955I is guaranteed to

meet performance speciﬁcations over the full –40°C to 85°C temperature

range.

Note 3: R

@ (2V

– V )/I ; V

will depend upon total load

OLCP

BATT

CPO CPO CPO

(I

+ I ) and minimum supply voltage V

CCB

. See Figure 5.

BATT

CCA

1955fd

4

For more information www.linear.com/LTC1955

LTC1955

Typical perForMance characTerisTics

Charge Pump Open-Loop Output

Resistance vs Temperature

(2V_IN– V_CPO) / I_LOAD(MAX)

I/O X Short-Circuit Current

No Load Supply Current vs V_BATT

vs Temperature

600

500

400

300

200

100

0

7.0

6.5

6.0

5.5

5.0

4.5

6.0

5.5

5.0

4.5

4.0

3.5

T

I

= 25°C

= I

DV = V

CCX

= 5.5V

V

= 2.7V

A

CC

BATT

= 5V

IN

CPO

= 0µA

V

= 4.9V

CCA CCB

V

= V

= 5V

CCB

CCA

= 1.8V, V

= 0V

CCB

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

SUPPLY VOLTAGE (V)

–40

–15

10

35

60

85

–40

–15

10

35

60

85

TEMPERATURE (°C)

1955 G01

1955 G03

1955 G02

V_CCXOvercurrent Shutdown

Threshold vs Temperature

Card Detection Debounce Time

vs V_BATTSupply Voltage

Bidirectional Channel (I/O A, I/O B)

Low Output Level vs Temperature

180

160

140

120

100

80

60

55

50

45

40

35

30

25

0.16

0.14

0.12

0.10

0.08

0.06

V

I

= 0V

V = 3.3V

BATT

V = 5.75V

CPO

DATA

= –1mA

OL

V

= 1.8V

CCX

V

BATT

= 2.7V

T

= 85°C

= 25°C

A

V

= 1.8V

= 3V

CCX

V

= 3V

= 5V

CCX

T

= –40°C

A

V

= 5V

35

CCX

–40

–15

10

60

85

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

SUPPLY VOLTAGE (V)

–40

–15

10

35

60

85

TEMPERATURE (°C)

V

BATT

TEMPERATURE (°C)

1955 G04

1955 G05

1955 G06

V_BATTQuiescent Current

[I_BATT– 2 (I_CCA+ I_CCB)]

vs Load Current

V_BATTShutdown Current

vs Supply Voltage

DV_CCShutdown Current

vs Supply Voltage

3.0

2.5

2.0

1.5

1.0

0.5

0

1.0

0.8

0.6

0.4

0.2

0

10

9

8

7

6

5

4

3

2

1

0

V

A

= 3.1V

V

= V

V

= V

BATT

DVCC

BATT

DVCC

T

= 25°C

T

= –40°C

= 85°C

A

T

= –40°C

A

T

= 25°C

A

= 25°C, 85°C

10µ

100µ

1m

10m

100m

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

SUPPLY VOLTAGE (V)

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

SUPPLY VOLTAGE (V)

LOAD CURRENT (A)

V

BATT

DVCC

1955 G07

1955 G08

1955 G09

1955fd

5

For more information www.linear.com/LTC1955

LTC1955

Typical perForMance characTerisTics

Charge Pump and LDO Activation

Deactivation Sequence

Data – I/O Channel, C_L= 50pF

RST A

5V/DIV

I/O A

2V/DIV

V

CPO

CLK A

5V/DIV

V

CCA

I/O A

5V/DIV

DATA

2V/DIV

I/O A

5V/DIV

V

CCA

5V/DIV

1955 G11

1955 G10

1955 G12

10µs/DIV

1ms/DIV

100ns/DIV

pin FuncTions

SV : Power. Supply voltage for analog sections of the

BATT

andC8Asynchronouscardpinscanbeselectedtoconnect

to the DATA pin via the serial port (see Table 4).

LTC1955.

PV : Power. Supply voltage for the charge pump.

R : Input. The R pin supplies the RST signal to both

BATT

IN

smart cards. It is level shifted and transmitted directly

to the RST pin of a selected card socket. When a card is

deselected,theRSTA/RSTBpinforthatchannelislatched

at its current state.

DV : Power. Reference voltage for the control logic.

CC

SGND: Ground. Signal ground for analog sections of the

LTC1955. The Exposed Pad must be soldered to PCB

ground.

SYNC: Input. The SYNC pin provides the clock input for

synchronous smart cards. When a synchronous card

is selected, its CLK pin follows SYNC directly. When a

synchronous card is deselected, the CLK A/CLK B pin for

that channel is latched at its current state.

PGND: Ground. Power ground for the charge pump. This

pin should be connected directly to a low impedance

ground plane.

CPO:ChargePump. CPOistheoutputofthechargepump.

When one or both of the smart cards requires power, the

charge pump will charge CPO to either 3.7V or 5.35V

depending on what smart card voltages are required. A

low impedance 4.7µF X5R or X7R ceramic capacitor is

required on CPO.

ASYNC: Input. The ASYNC pin provides the clock input

for asynchronous cards and should be connected to a free

running clock. The clock signal to the smart card can be

a ÷1, ÷2, ÷4 or ÷8 version of the signal on ASYNC. Asyn-

chronous cards can also be placed in clock stop mode

with the clock stopped either high or low.

+

–

C , C : Charge Pump. Charge pump ﬂying capacitor pins.

A 1µF X5R or X7R ceramic capacitor should be connected

D : Input. Input for the serial port. Command data is

IN

+

–

from C to C .

shifted into D synchronously with SCLK. D can be

IN

OUT

connected directly to a microcontroller or the D

another LTC1955 for daisychained operation.

pin of

DATA: Input/Output. Microcontroller side data I/O pin. The

DATA pin provides the bidirectional communication path

to both smart cards. One, both or neither of the cards may

be selected to communicate via the DATA pin. If several

LTC1955s are connected in parallel, the DATA pin can be

made high impedance by selecting neither card. The C4A

D

: Output. Output for the serial port. Smart card status

OUT

dataisshiftedoutofD

synchronouslywithSCLK.D

OUT

can be connected directly to a microcontroller or the D

pin of another LTC1955 for daisychained operation.

IN

1955fd

6

For more information www.linear.com/LTC1955

LTC1955

pin FuncTions

SCLK: Input. The SCLK pin clocks the serial port. Each

new data bit is received on the rising edge of SCLK. SCLK

should be left high during idle times and should not be

clocked when LD is low.

I/O A/I/O B: Card Socket. The I/O A/I/O B pins connect to

the I/O pins of the respective smart card sockets. When

a smart card is selected, its I/O pin connects to the DATA

pin. When a smart card is deselected, its I/O A/I/O B pin

returns to the idle state (H).

LD: Input. The falling edge of this pin loads the current

state of the shift register into the command register.

Command changes to both smart card channels will be

updated on the falling edge of LD. The rising edge of LD

latches status information from the smart card channels

into the shift register for the next read/write cycle.

RSTA/RSTB:CardSocket.Thesepinsshouldbeconnected

to the RST pins of the respective smart card sockets. The

RST A/RST B signals are derived from the R pin. When

IN

a card is selected, its RST pin follows R . When a card

IN

is deselected, the RST A/RST B pin for that channel holds

the current value on R .

IN

NC/NO: Input. This pin controls the activation level of the

PRES A/PRES B pins. When it is high (DV ), the PRES

CLK A/CLK B: Card Socket. The CLK A/CLK B pins should

be connected to the CLK pins of the respective smart card

sockets. The CLK A/CLK B signals can be derived from

either the SYNC input or the ASYNC input depending on

which type of card is being accessed. The card type is

selected via the serial port (see Tables 1 and 3).

CC

pins are active high. When it is low (GND), the PRES pins

are active low. When a ground side N.O. switch is used,

the NC/NO pin should be grounded. When a ground side

N.C. switch is used, the NC/NO pin should be connected

to DV .

CC

Note: If an N.C. switch is used, a small current (several

microamperes) will ﬂow through the switch whenever a

smartcardisnotpresent.Forultralowpowerconsumption

in shutdown, an N.O. switch is optimum.

V

, V : Card Socket. The V /V

pins should be

CCA CCB

connected to the V pins of the respective smart card

CC

sockets. The activation of a V /V

pin is controlled by

CCA CCB

the serial port (see Tables 1 and 2) and can be set to 0V,

1.8V, 3V or 5V. The voltage levels of the two card sockets

are controlled independently for maximum ﬂexibility.

PRES A/PRES B: Card Socket. The PRES A/PRES B pins

are used to detect the presence of the smart cards. They

can be connected to either normally open or normally

closed detection switches on the smart card acceptor’s

sockets.TheNC/NOpinshouldbesetappropriately.These

pins have a pull-up current source on-chip so no external

components are required.

FAULT: Output. The FAULT pin can be used as an interrupt

to a microcontroller to indicate when a fault has occurred.

It is an open-drain output, which is logically equivalent to

D4 + D5 + D12 + D13. (See Table 1)

UNDERV: Input. The UNDERV pin provides security by

supplying a precision undervoltage threshold for ex-

ternal supply monitoring. An external resistive voltage

divider programs the desired undervoltage threshold.

Once UNDERV falls below 1.23V, the LTC1955 automati-

cally begins the deactivation sequence on any channel

that is active.

C4A/C8A: Card Socket. These pins connect to the C4

and C8 pins of synchronous memory cards on smart

card socket A. The signal for these pins is unidirectional

and can only be sent to the card. Data for C4A and C8A

is transmitted via the DATA pin and may be selected

in place of I/OA via the serial port (see Table 4). When

either C4A or C8A is selected, it will follow the DATA

pin. When it is deselected, it will remain latched at its

current state.

If external supply monitoring is not required, the UNDERV

pin should be connected to either SV

or DV .

BATT

CC

1955fd

7

For more information www.linear.com/LTC1955

LTC1955

block DiagraM

CHARGE PUMP

PGND SV

+

–

C

PV

CPO

15

BATT

14

11

10

12

13

CHARGE

PUMP

17

20

18

19

21

LDO B

8

5

4

3

7

6

V

LDO A

V

CCA

CCB

I/O B

CLK B

I/O A

C4A

CLOCK

CONTROL

LOGIC

SMART

CARD

SOCKET B

SMART

CARD

SOCKET A

RST B

C8A

RESET

CONTROL

LOGIC

τ

PRES B

CLK A

RST A

29

31

32

30

DATA

ASYNC

SYNC

SMART

CARD

COMMUNICATIONS

τ

2

PRES A

NC/NO

22

R

IN

24

9

FAULT

STATUS DATA

SGND

27

28

26

25

DIGITAL

SUPPLY

D

IN

SERIAL PORT

COMMAND/STATUS

DATA

D

OUT

1

DV

CC

SHIFT REGISTER

SCLK

LD

23

UNDERV

–

+

COMMAND LATCH

+

1.23V

–

1955 BD

1955fd

8

For more information www.linear.com/LTC1955

LTC1955

operaTion

Serial Port

• Operating mode of asynchronous cards (clock stop

high, low, ÷1, ÷2, ÷4 or ÷8)

The microcontroller compatible serial port provides all

of the command and control inputs for the LTC1955, as

• Selection of the I/O, C4 or C8 pins for card socket A

The serial port provides the following status data:

well as the status of the two smart cards. Data on the D

IN

input is loaded on the rising edge of SCLK. D15 is loaded

• It indicates the presence or absence of the smart

cards.

ﬁrst and D0 last. At the same time, the command bits are

being shifted into the D input, the status bits are being

IN

shiftedoutoftheD output.Thestatusbitsarepresented

OUT

• ItindicatesthereadinessofthesmartcardV supplies.

CC

to D

on the rising edge of SCLK. Once all bits have

OUT

Communication with a smart card is disabled until its

been clocked into the shift register, the command data is

loaded into the command latch by bringing LD low. At this

time, the command latch is updated and the LTC1955 will

begin to act on the new command set. The status data

is latched into the shift register on the rising edge of LD.

SCLK should be low when LD is brought low and should

be high when LD is brought high. This requires a 9th clock

cycle per transaction. Figure 1 shows the recommended

operation of the serial port.

power supply voltage has reached the ﬁnal value.

• It indicates fault status. In the event of an electrical or

ATR fault, the fault is reported. For electrical faults, the

LTC1955 will automatically deactivate the smart card.

Table 1 illustrates the command inputs and status outputs

associated with each bit of the serial data word.

Three voltage options are available from the LTC1955: 5V,

3V and 1.8V. Bits D0, D1 (card B) and D8, D9 (card A)

determine which voltage is selected. Setting both control

bits of a channel to 0 deactivates that channel and sets

the smart card supply voltage to 0V. If both channels are

deactivated, the LTC1955 is in shutdown. Table 2 shows

the operation of the supply control bits.

Multiple LTC1955s may be daisychained together by

connecting the D

pin of one LTC1955 to the D pin of

OUT

IN

another. Figure 6 shows an example of multiple LTC1955s

daisychained together.

The maximum clock rate for the serial port is 10MHz.

The CLK A/CLK B pins to the smart cards can be pro-

grammedforvariousmodes.Bothsynchronousandasyn-

chronous cards are supported. There are several options

available with asynchronous cards. Table 3 shows how

all clock options are obtained using bits D5–D7 (card B)

and D13–D15 (card A). The default state of the LTC1955

on power up is synchronous mode.

The serial port controls the following parameters of each

smart card socket:

• Selection/deselection of a smart card

• V voltage level of each card (5V/3V/1.8V/0V)

CC

• Clock mode of each card (synchronous or asynchronous)

READ/WRITE CYCLE

t

H

t

CL

LC

X

DS

DH

L

CL

LFC

t

DD

SCLK

D

IN

D15

D14

D2

D1

D0

X

LD

D15 FROM

INPUT

D

D15

D14

D5

D1

D0

D15

OUT

1955 F01

Figure 1. Serial Port Timing Diagram

1955fd

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LTC1955

operaTion

Table 1. Serial Port Comand

Toreceivestatusdatafromtheserialport, aread/writeop-

erationmustbeperformed. Whenpollingforthepresence

of a smart card on both channels, the input word should

be set to $0000 since this is the shutdown command for

the LTC1955. However, consider the example where some

operation is already being performed on channel A. If, for

STATUS OUTPUT

BIT COMMAND INPUT

CARD B

0

D0

D1

V

Options

CCB

(See Table 2)

0

D2 Card B Select/Deselect

D3 Data Pull-Up Defeat

0

example, the previous command was $BE00 (V

set to

Card B Electrical Fault

Card B ATR Fault

D4 Reserved (Always Set to “0”)

D5 Card B Clock Options

CCA

3V, card selected, I/O A connected to DATA and CLK A set

to ASYNC÷2), then the commands for this channel must

be rewritten to the serial port each time. To poll for the

(See Table 3)

Card B V Ready

D6

CC

Card B Present

D7

presence of a card on channel B, or even the V

ready

CCA

CARD A

0

D8

D9

V

Options

CCA

(See Table 2)

status, then $BE00 should be rewritten on each new read/

write cycle. Once a card is detected on channel B, the

commands for channel B can be changed but the $BExx

should continue to be rewritten for channel A.

D10 Card A Select/Deselect

D11 Card A Communications

Options (See Table 4)

Card A Electrical Fault D12

Card A ATR Fault

D13 Card A Clock Options

Bidirectional Channels

(See Table 3)

Card A V Ready

D14

D15

CC

Thebidirectionalchannelsarelevelshiftedtotheappropri-

Card A Present

ate V

voltages at the I/O A/I/O B pins.

CCA/B

An NMOS pass transistor performs the level shifting. The

gateoftheNMOStransistorisbiasedsuchthatthetransis-

tor is completely off when both sides have relinquished

the channel. If one side of the channel asserts an L, then

the transistor will convey the L to the other side. Note that

currentpassesfromthereceivingsideofthechanneltothe

transmitting side. The low output voltage of the receiving

sidewillbedependentuponthevoltageatthetransmitting

side plus the I • R drop of the pass transistor.

Table 2. V_CCand Shutdown Options

D9

D1

D8

D0

STATUS (CARD A)

STATUS (CARD B)

0

1

0

1

0

1

V

CC

V

CC

V

CC

V

CC

= 0V (Shutdown)

= 1.8V

= 3V

= 5V

Table 3. Clock Options

When a card socket is selected, it becomes a candidate

to drive data on the DATA pin, and likewise, receive data

from the DATA pin. When a card socket is deselected, the

voltage on its I/O A/I/O B pin will return to the idle state

(H), and the DATA side of that channel will become high

impedance. If both cards are deselected, the DATA pin

will be high impedance.

D7

D6

D5

CLOCK MODE (CARD B)

D15

D14

D13 CLOCK MODE (CARD A)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Synchronous Mode

Unused

Asynchronous Stop Low

Asynchronous Stop High

Asynchronous ÷1

Asynchronous ÷2

Asynchronous ÷4

Asynchronous ÷8

Both cards may be deselected at the same time to allow

communication with a second LTC1955.

Card channel A includes provision for unidirectional

communication with the C4 and C8 pins of the smart

card. The C4, C8 and I/O pins of card A are individually

multiplexed to the DATA pin using bits D11 and D12, as

shown in Table 4.

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Inasynchronousmode,theCLKA/CLKBpinsfolloweither

the ASYNC pin (÷1 mode) or a divided version of this pin.

The CLK A/CLK B pins can also be stopped high or low.

The available divider ratios include ÷2, ÷4 and ÷8. When

switching between divider ratios, the internal selection

circuitry ensures that no spikes or glitches appear on the

CLK A/CLK B pins. Consequently, it may take up to 8 clock

pulses for the clock frequency change command to take

affect. Synchronization circuitry ensures that no glitches

occur when entering or exiting one of the stop modes.

For example, when entering stop low mode, the selection

circuitry waits for the next falling edge of the respective

CLK A/CLK B signal to make the change. Likewise, if stop

high is selected, it will occur on the next rising edge.

operaTion

Table 4. Card A Communications Options

D12

0

1

D11 CARD A COMMUNICATION MODE

0

1

0

1

Nothing Selected

C4A Connected to DATA Pin

C8A Connected to DATA Pin

I/O A Connected to DATA Pin

Note that if a reset is initiated with both cards selected,

then both may give an answer to reset and collide on the

DATA line. No damage will occur but data could be lost

or corrupted.

Dynamic Pull-Up Current Sources

The current sources on the bidirectional pins (DATA, I/O

A/I/OB)aredynamicallyactivatedtoachieveafastrisetime

with a relatively small static current.* Once a bidirectional

pin is relinquished, a small start-up current begins to

charge the node. An edge rate detector determines if the

pin is released by comparing its slew rate with an internal

reference value. If a valid transition is detected, a large

pull-up current enhances the edge rate on the node. The

higher slew rate corroborates the decision to charge the

node thereby affecting a dynamic form of hysteresis.

Deselection of an asynchronous card does not affect its

CLK A/CLK B pin. Its clock can be started, stopped or its

divider ratio changed at any time.

To clean up the duty cycle of the incoming clock in asyn-

chronous applications, any of the clock divider modes ÷2,

÷4 or ÷8 will yield a very nearly 50% duty cycle.

Additionalsynchronizationcircuitrypreventsglitchesfrom

occurringwhenswitchingbetweensynchronousmodeand

asynchronous mode. Because of this circuitry, two edges

(a falling edge followed by a rising edge) are necessary

at the CLK pin to switch modes from asynchronous to

synchronous. Forexample, ifclockstopmodeisengaged,

the clock channel will not change modes until clock stop

mode is disengaged.

LOCAL

SUPPLY

V

+

–

REF

I

START

dv

dt

Anycombinationofcards,synchronousorasynchronous,

can be used as both channels can be set to any of the

clock modes or divider ratios independently.

BIDIRECTIONAL

1955 F02

Figure 2. Dynamic Pull-Up Current Sources

Both SYNC and ASYNC inputs are independently level

shifted to the appropriate voltage for the CLK A/CLK B

pins (5V, 3V, 1.8V).

Clock Channels

As described in the section Serial Port, the LTC1955 sup-

ports both synchronous and asynchronous smart cards.

On start-up, or when bits D13-D15 for card A and bits

D5-D7 for card B are set to 0s, the clock channel is in

synchronous mode. The remaining modes are used for

asynchronous cards.

Reset Channels

When a card is selected, the reset channels provide a level

shifted path from the R pin to the RST A/RST B pins.

IN

When a card is deselected, its RST A/RST B pin is latched

at the current value of R .

IN

In synchronous mode, the CLK A/CLK B pins follow the

SYNC pin for a channel that is selected. If a channel is

deselected (via the serial port), the CLK A/CLK B line for

that channel is latched at its current value.

* U.S. Patent No. 6,356,140

1955fd

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Smart Card Detection Circuits

Automatic Deactivation

The PRES A/PRES B pins are used to detect the presence

of a smart card. An automatic debounce circuit waits until

a smart card has been present for a continuous period

of typically 35ms. Once a valid card indication exists,

the status bit for that channel is updated and may be

The built-in deactivation sequence can be executed via the

serial port simply by setting the appropriate control bits

(D0 and D1 or D8 and D9) to 0. The deactivation sequence

is outlined below.

1. The RST A/RST B pin for that channel is immediately

brought low.

polled by cycling data through the serial port. The D

OUT

pin (equivalent to D15) of the serial port can be used to

indicate the presence of a card on channel A in real time

if LD is held low.

2. ThedeactivationoftheCLKA/CLKBpinsdependsupon

which type of card is used:

If the smart card was set to asynchronous mode, then

the CLK A/CLK B pin will be latched low on its next

falling edge. If no falling edges occur within 5µs (min),

then the CLK A/CLK B line is forced low.

The PRES A/PRES B pins have built-in pull-up current

sources, so no external components are required for

switchdetection.Thepull-upcurrentsourcesaredesigned

to have a small current when the pin voltage is below ap-

proximately 1V, but somewhat higher current when the

pin voltage reaches 1V. This helps maintain low power

dissipation when a card is present and yet fast response

time to a card removal.

Ifthesmartcardwassettosynchronousmode,thenthe

CLK A/CLK B pin is immediately latched at its current

value (either high or low) and then forced low after a

duration of 5µs (min). During the 5µs timeout period,

changes on SYNC will be ignored.

The PRES A/PRES B pins can be conﬁgured to respond

to either normally open or normally closed switches via

the NC/NO pin.

3. The I/O A/I/O B, C4A and C8A pins for that channel are

brought low.

4. The V /V

pin is brought low.

Activation/Deactivation

CCA CCB

If an error occurs on one smart card, operation of the

other card is unaffected.

For maximum ﬂexibility, the activation sequencing of the

smart card is left to the application programmer. Upon

activation, to comply with relevant smart card standards,

none of the smart card signal pins will be allowed to go

Electrical Fault Detection

highbeforethesmartcardsupplyvoltage(V /V )has

CCA CCB

Several types of faults are detected by the LTC1955. They

reacheditsﬁnalvalue. Deactivationcanbeachievedeither

manuallyorautomatically.Anelectricalfaultconditionwill

trigger the automatic deactivation.

include V /V

undervoltage, V /V

overcurrent,

CCA CCB

CLK A/CLK B, RST A/RST B, C8A, C4A short-circuit, card

removalduringatransaction,failedanswertoreset(ATR),

supplyundervoltageorUNDERVandchipovertemperature.

To prevent false errors from plaguing the microcontroller,

the electrical faults are acted upon only after a 5µs (min)

timeout period. Card removal during transaction faults

initiate the deactivation sequence immediately.

Manual deactivation may be performed under software

control by setting the smart card pins to 0V in the desired

sequence via the control pins (SYNC, ASYNC, R , DATA

IN

and the serial port). For most applications, this will be

cumbersome and the built-in deactivation will be used

instead.

1955fd

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operaTion

V /V undervoltagefaultsaredeterminedbycompar-

CCA CCB

An electrical fault can be cleared on either channel by

setting the voltage of that channel to 0V. Set D0 and D1

to OO to clear channel B and set D8 and D9 to 00 to clear

channel A. It is not necessary to set all four bits to zeros.

ing the actual output voltage with the internal reference

voltage. If the output is more than ~5% below its set point

for the entire timeout period, the fault is reported and the

deactivation sequence is initiated.

Answer to Reset (ATR) Fault Detection

V

/V

overcurrent faults are detected by comparing

CCA CCB

Answer to reset faults are detected by an internal counter

thatisstartedoncetheRSTA/Blinegoeshigh. IftheDATA

pin remains high for 40,000 clock cycles, the ATR fault bit

for a given channel is set in the serial port’s status register

(see Table 1) and the FAULT pin is brought low.

the output current of the LDOs with an internal reference

level. If the current of an LDO is more than 100mA (typ)

for the entire timeout period, the fault is reported and the

deactivation sequence is initiated.

CLK A/CLK B and RST A/RST B faults are detected by

comparing the outputs of these pins with their expected

signals. If the signal on a pin is incorrect for the entire

timeout period, the fault is reported and the deactivation

sequence is initiated.

An ATR fault cannot occur if the clock mode of a chan-

nel is set to synchronous. ATR faults will only occur for

asynchronous smart cards.

ATR faults are cleared by bringing the RST A/B pin low

for the faulted channel. This will also clear the FAULT pin

to the Hi-Z state (assuming no other errors are causing

FAULT to be low).

The clock channels are a special case. Since they can have

a free running clock, the error indication is accumulated

over a longer period of time without being cleared. Even

though the clock may be running, an error will still be

detected.

An ATR fault will not automatically deactivate a card

channel. It is the application programmer’s responsibility

to check the status register for ATR faults and deacti-

vate the smart card channel in accordance with smart

card standards. Generally, the application has 50ms

(EMV 2.1.3.1, 2.1.3.2) from the 40,000th clock pulse to

deactivate the card. Once the LTC1955 receives the de-

activation command, it will shut down a card channel in

less than 250µs.

Anovertemperaturefaultisdetectedbysensingthejunction

temperature of the IC. If the junction temperature exceeds

approximately 150°C for the entire timeout period, the

fault is reported by setting both fault bits (D4 and D12)

and the deactivation sequence is initiated.

A card removal fault is determined as soon as the PRES A/

PRES B pin is high (for NC/NO = 0). Once this occurs,

the fault is reported and the deactivation sequence is

initiated.

Using the FAULT Pin

The FAULT pin can be used as an interrupt to a microcon-

troller. It is an open-drain output and generally requires

a pull-up resistor. The FAULT pin will go low when either

an electrical fault, or an answer to reset fault, occurs on

either channel. Thus, there are four possible faults that

can cause it to indicate a problem. The serial port’s status

register must be polled to ﬁnd out what type of fault oc-

curred and on which channel. The FAULT pin is logically

equivalent to D4 + D5 + D12 + D13 (see Table 1).

Ifnocardispresent,andtheapplicationsoftwareattempts

to power-up a card socket, an automatic fault will result

on that channel.

Short-circuits on the I/O A/I/O B lines will not be detected

by the fault detection hardware; however, a short-circuit

from these lines to their respective V /V

pins will

CCA CCB

be compliant with the maximum current limits set by ap-

plicable standards (<15mA).

1955fd

13

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LTC1955

applicaTions inForMaTion

10kV ESD Protection

be especially well bypassed. The capacitor for this node

should be directly adjacent to the QFN package. The CPO

and ﬂying capacitors should be very close as well. The

LTC1955 can tolerate more distance between the LDO

Allsmartcardpins(CLKA/CLKB,RSTA/RSTB,I/OA/I/OB,

C4A, C8A and V /V ) can withstand over 10kV of

CCA CCB

human body model ESD in-situ. In order to ensure proper

ESD protection, careful board layout is required. The

PGND and SGND pins should be tied directly to a ground

capacitors and the V

pins.

CCA/B

Figure 3 shows an example of a tight printed circuit

board using single-layer copper. For best performance, a

multilayer board can be used and should employ a solid

ground plane on at least one layer.

plane. The V /V

capacitors should be located very

CCA CCB

close to the V /V

pins and tied immediately to the

CCA CCB

ground plane.

The following capacitors are recommended for use with

the LTC1955.

Capacitor Selection

Warning: A polarized capacitor such as tantalum or alumi-

num should never be used for the ﬂying capacitor since

its voltage can reverse upon start-up of the LTC1955.

Low ESR ceramic capacitors should always be used for

the ﬂying capacitor.

TYPE

VALUE CASE SIZE MURATA P/N

C

X5R

4.7µF

0805

0603

0402

GRM40-034 X5R 475K 6.3

GRM39 X5R 105K 6.3

GRM36 X5R 104K 10

IN

CPO

C

V

X5R

1µF

FLY

CCA/B

CDV

0.1µF

CC

AtotalofsixcapacitorsarerequiredtooperatetheLTC1955.

An input bypass capacitor is required at PV

, SV

BATT

and DV . Output bypass capacitors are required on each

CC

of the smart card V /V

pins. A charge pump ﬂying

CCA CCB

+

–

capacitor is required from C to C and a charge storage

capacitor is required on the charge pump out pin CPO.

To prevent excessive noise spikes due to charge pump

operation, low ESR (equivalent series resistance) multi-

layer ceramic capacitors are strongly recommended.

V

CCA

Thereareseveraltypesofceramiccapacitorsavailable,each

havingconsiderablydifferentcharacteristics.Forexample,

X7R/X5R ceramic capacitors have excellent voltage and

temperature stability but relatively low packing density.

Y5V ceramic capacitors have apparently higher packing

density but poor performance over their rated voltage or

temperatureranges.Undercertainvoltageandtemperature

conditions, Y5V and X7R/X5R ceramic capacitors can be

compared directly by case size rather than speciﬁed value

for a desired minimum capacitance.

Placementofthecapacitorsiscriticalforcorrectoperation

of the LTC1955. Because the charge pump generates large

currentsteps,allofthecapacitorsshouldbeplacedasclose

to the LTC1955 as possible. The low impedance nature of

multilayer ceramic chip capacitors will minimize voltage

spikes but only if the power path is kept very short (i.e.,

GND

V

CCB

BATT

1955 F03

Figure 3. Optimum Single-Layer PCB Layout

minimum inductance). The PV

/SV

nodes should

BATT

1955fd

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LTC1955

applicaTions inForMaTion

Interfacing to a Microcontroller

Daisychained Operation

The serial port of the LTC1955 can be connected directly

to a 68HC11 style microcontroller’s serial port. The mcro-

controller should be conﬁgured as the master device and

its clock’s idle state should be set to high (MSTR = 1,

CPOL = 1 and CPHA = 0 for the MC68HC11 family).

Figure 4 shows the recommended conﬁguration and

direction of data ﬂow. Note that an additional I/O line

is necessary for LD to load the data once it has shifted

around the loop. Command data is latched into the com-

mand register on the falling edge of the LD signal. The

LTC1955 will begin to act on new command data as soon

as LD goes low. Any general purpose microcontroller I/O

line can be conﬁgured to control the LD pin.

For applications requiring more than two card sockets,

the serial port of the LTC1955 is designed to be easily

daisychained. The D

pin of one LTC1955 can be con-

OUT

nected directly to the D pin of another LTC1955. Rather

IN

than sending two 8-bit bytes before asserting LD, the

microcontrollershouldsendtwo8-bitbytesperdevice.LD

shouldonlybeassertedafteralldeviceshavebeenupdated.

Figure 6 shows three LTC1955s cascaded in daisychain

fashion. In this case, the microcontroller would write six

8-bit bytes before asserting the LD pin. Alternatively, if

two serial ports are available on the microcontroller, then

two LTC1955s can be controlled independently.

If the DATA lines of two or more LTC1955s are connected

together, the static pull-up current will be the sum of the

devices. Thestaticcurrentcanbebroughtbacktothelevel

of a single LTC1955 by setting bit D3 on all but one of the

LTC1955s to 1 (see Table 1). Bit D3 disables the pull-up

The status of the LTC1955 is returned over the serial

port. Status data is latched into the shift register on the

rising edge of the LD pin. Whenever the system is wait-

ing for status data from the LTC1955, its LD pin should

be held low.

current source on the DATA pin. This will help prevent V

OL

problems in multiple LTC1955 applications when driving

the DATA or I/O pins low.

µCONTROLLER

MOSI

LTC1955

D

IN

CARD A

MISO

SCK

I/O

OUT

SCLK

CARD B

LD

1955 F04

Figure 4. Microcontroller Interface

1955fd

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LTC1955

applicaTions inForMaTion

Using S.A.M. Cards

Using the UNDERV Pin

For applications using one or more installed S.A.M.

cards, the PRES A/PRES B pins for those sockets must

be grounded before operation of the card can occur

(assuming NC/NO is grounded). The PRES A/PRES B

pull-up current is designed for very low consumption,

but ultralow current can be achieved in shutdown by us-

ing a microcontroller output to pull down on the PRES

A/PRES B pins only when communication is necessary.

The fault detection circuitry will not allow a card socket

to be operated unless a card is detected.

The UNDERV pin can be used to add protection against a

supplyundervoltagefault.Byusingtwoexternalprogram-

mingresistors,theundervoltagedetectioncanbesettoan

arbitrary level (Figure 7). To ensure that the smart cards

are properly shut down, there must be sufﬁcient energy

available in the input bypass capacitor to run one or both

smart cards until the deactivation cycle begins. It can take

approximately 30µs from the detection of a fault until the

deactivation sequence begins. It is desirable to maintain

the V

supply at 2.7V or greater during this period.

BATT

Consider the following (worst-case) example:

Asynchronous Channel A Card Detection

1. The UNDERV pin is programmed to trip below 3.1V.

Since the shift register is transparent when LD is held

low, D

is the same as D15. Recall from Table 1 that

2. It is possible to have both cards activated at 5V and

drawing 60mA.

OUT

D15 indicates the status of the card detection channel for

channel A. Thus, it is not necessary to perform an entire

read/write operation to determine the card detection

Since the output voltage is programmed to 5V, the charge

pump will be acting as a voltage doubler. With two cards

drawing 60mA each, the input current will be 2 • (60mA

status of channel A. With LD low, D

can be used to

OUT

generatearealtimecarddetectioninterrupt. Thiscouldbe

useful for one S.A.M. card, one smart card application.

+ 60mA), or about 240mA. Allowing the V

supply to

BATT

droop from 3.1V to 2.7V during the 30µs timeout period,

the input capacitance would need to be at least:

Inter Card Communication

240mA / [(3.1V – 2.7V) / 30µs] or 18µF.

Communication is possible directly from one card socket

to the other when both cards are selected at the same

time. This can be achieved by the following sequence of

actions.

Thermal Management

To minimize power dissipation, the LTC1955 will actively

decide whether to step up or down depending on the

required output voltages and available input voltage.

However, for optimum efﬁciency, the LTC1955 should be

powered from a 3.3V supply.

1. Start with both cards off and deselected

2. Activate the supply of the slave card

3. Select the slave card only

If the input voltage is above 3.6V, and both cards are

drawingmaximumcurrent,therecanbesubstantialpower

dissipation in the LTC1955. If the junction temperature in-

creasesaboveapproximately150°C,thethermalshutdown

circuitry will automatically deactivate both channels. To

reducethemaximumjunctiontemperature,agoodthermal

connection to the PC board is recommended.

4. Initiate a reset on the slave card

5. Deselect the slave card

6. Activate the supply of the master card

7. Select the master card only

8. Initiate a reset on the master card

9. Select both cards

Zero Shutdown Current

Although the LTC1955 is designed to have very low shut-

downcurrent, itcanstilldrawoveramicroampereonboth

1955fd

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applicaTions inForMaTion

DV and V

when in shutdown. For applications that

R is dependent on a number of factors including the

OLCP

CC

BATT

require virtually zero shutdown current, the DV pin can

switchingterm,1/(f

•C ),internalswitchresistances

CC

OSC FLY

be grounded. This will reduce the V

current to well

and the nonoverlap period of the switching circuit. How-

ever, for a given R , the minimum CPO voltage can be

BATT

under a single microampere. Internal logic ensures that

OLCP

theLTC1955isinshutdownwhenDV isgrounded.Note,

determined from the following expression:

CC

however, that all of the logic signals that are referenced

V

CPO

≥ 2V – (I + I )R

BATT

CCA

CCB OLCP

to DV (D , SCLK, LD, DATA, R , SYNC, ASYNC and

CC

IN

TheLDOshavebeendesignedtomeetallapplicablesmart

card standards for V with V as low as 5.13V. Given

NC/NO)willhavetobeat0Vaswell, topreventESDdiodes

to DV from being forward-biased.

CC

CPO

CC

this information, trade-offs can be made by the user with

Operation at Higher Supplies

regard to total consumption (I

+ I ) and minimum

CCA CCB

supply voltage.

If a 5.5V to 6V supply voltage is available, it is possible

to achieve some power savings by bypassing the charge

pump. The higher supply can be connected directly to the

CPO pin. As long as the voltage on CPO is higher than that

at which it ordinarily regulates (5.35V or 3.7V depending

on voltage selections), the charge pump’s oscillator will

not run. This conﬁguration can give considerable power

savings since the charge pump is not being used.

R

OLCP

CPO

+

2V

BATT

LDO A

V

LDO B

V

CCB

CCA

–

1955 F05

A voltage source is still needed on both DV and SV

/

BATT

CC

Figure 5. Equivalent Open-Loop Circuit

PV

in this conﬁguration. Recall that DV sets the

BATT

CC

logic reference level for all the control and smart card

communication pins. The voltage on SV /PV can

Changing the Smart Card Supply Voltage

BATT

Although the LTC1955 control system will allow the smart

card voltage to be changed from one value to the next

withoutaninterimpower-down,thisisnotrecommended.

When changing from a higher voltage to a lower voltage

there will generally not be a problem; however, changing

from a lower voltage to a higher voltage will result in both

an undervoltage condition and an overcurrent condition

on that channel. The likely result is that the channel will

automaticallydeactivate.Applicablesmartcardstandards

specify that the smart card supply be powered to zero

before applying a new voltage.

be any convenient level that meets the parameters in the

Electrical Characteristics table.

The 5.5V to 6V supply can be left permanently connected

toCPO,buttherewillbeapproximately5µAofcurrentﬂow

into CPO when the LTC1955 is in shutdown.

Charge Pump Strength

UnderlowV

conditions,theamountofcurrentavailable

BATT

to the smart cards is limited by the charge pump.

Figure 5 shows how the LTC1955 can be modeled as a

Thevenin equivalent circuit to determine the amount of

Compliance Testing

current available given the effective input voltage, 2V

and the effective open-loop output resistance, R

BATT

.

Inductance due to long leads on type approval equipment

can cause ringing and overshoot that leads to testing

problems. Small amounts of capacitance and damp-

ing resistors can be included in the application without

compromising the normal electrical performance of the

LTC1955 or smart card system. Generally, a 100Ω resis-

tor and a 20pF capacitor will accomplish this, as shown

OLCP

From Figure 5, the available current is given by:

2V_BATT– V_CPO

I_CCA+I_CCB

≤

R_OLCP

in Figure 8.

1955fd

17

For more information www.linear.com/LTC1955

LTC1955

applicaTions inForMaTion

1µF

4.7µF

11

14

21

2

–

+

C

PRES B PRES A

12, 13

9, 10

1

V

BATT

INPUT

POWER

SMART CARD

VENDOR CARD

GND

DV

CC

23

UNDERV

24

FAULT

27

28

26

25

LTC1955

D

IN

4-WIRE

COMMAND

INTERFACE

OUT

SCLK

LD

29

30

32

31

15

DATA

CPO

4-WIRE

CARD

INTERFACE

4.7µF

R

IN

SYNC

ASYNC

4.7µF

11

–

14

+

21

2

C

PRES B PRES A

12, 13

9, 10

1

V

BATT

SMART CARD

VENDOR CARD

GND

DV

CC

23

UNDERV

24

FAULT

27

28

26

25

LTC1955

D

IN

OUT

SCLK

LD

29

30

32

31

DATA

CPO

R

IN

SYNC

ASYNC

4.7µF

11

14

+

21

2

–

C

PRES B PRES A

12, 13

9, 10

1

V

BATT

VENDOR CARD

GND

DV

CC

23

UNDERV

24

FAULT

27

28

26

25

LTC1955

D

IN

OUT

SCLK

LD

29

30

32

31

DATA

CPO

R

IN

SYNC

ASYNC

1955 F07

Figure 6. Multiple LTC1955s Daisychained Together

1955fd

18

For more information www.linear.com/LTC1955

LTC1955

applicaTions inForMaTion

MAIN SUPPLY

V

= 1.23V (1 + R1/R2)

TRIP

R1

R2

23

UNDERV

LTC1955

1955 F08

Figure 7. Setting the Undervoltage Trip Point

100Ω

I/O X

CLK X

RST X

C7

100Ω

20pF

SMART

CARD

SOCKET

C3

C2

C1

LTC1955

20pF

V

CCX

C5

1µF

0.1µF

1955 F09

Figure 8. Additional Components for

Improved Compliance Testing

1955fd

19

For more information www.linear.com/LTC1955

LTC1955

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693 Rev D)

0.70 ±0.05

5.50 ±0.05

4.10 ±0.05

3.45 ±0.05

3.50 REF

(4 SIDES)

3.45 ±0.05

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.30 TYP

OR 0.35 × 45° CHAMFER

R = 0.05

TYP

0.00 – 0.05

R = 0.115

TYP

0.75 ±0.05

5.00 ±0.10

(4 SIDES)

31 32

0.40 ±0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

3.45 ±0.10

3.50 REF

(4-SIDES)

3.45 ±0.10

(UH32) QFN 0406 REV D

0.200 REF

0.25 ±0.05

0.50 BSC

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

1955fd

20

For more information www.linear.com/LTC1955

LTC1955

revision hisTory ^{(Revision history begins at Rev C)}

REV

DATE

DESCRIPTION

PAGE NUMBER

C

11/13 Remove t spec from Serial Port Timing

4

9

4

9

LW

Revised Serial Port Timing section and diagram

D

2/14

Added t parameter to Serial Port Timing electrical parameters.

LFC

Modiﬁed Figure 1.

1955fd

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC1955

21

LTC1955

Typical applicaTion

Battery-Powered RS232 to Dual Smart Card Interface

0.1µF

FAULT

4.7µF

0.1µF

180k

262k

+

0.1µF

47k

37

47k

RESET

Li-ION

16

17

4

21

45 19

V

1

23

UNDERV

12, 13

1k

RXEN DREN

V

CC

MOD B

V

XIRQ

DV

V

BATT

4

5

3

DD

RH

CC

V

CC18

V

CC3

V

CCA

36

1

24

RST

FAULT

LTC1728ES5-1.8

GND

LTC1348CG

MC68L11E9PB2

LTC1955EUH

3

4

5

6

7

8

C8

C4

C7

C2

C3

C1

2

DB9

C8A

C4A

RD

TD

2

3

7

8

25

24

40

39

38

42

41

43

44

DR1OUT

DR1IN

PD1 (TXD)

PD0 (RXD)

IRQ

I/O A

CARD A

C5

27

28

26

25

RX1IN

RX1OUT

(MOSI) PD3

(MISO) PD2

(SCK) PD4

(SS) PD5

D

RST A

CLK A

IN

OUT

GND

5

SCLK

V

CCA

1µF

0.1µF

LD

2

5

27

26

+

PRES A

C1

C3

0.1µF

6

2

–

C1

C3

+

C2

C7

C2

C3

C1

24

8

31

32

30

29

20

19

18

17

(2MHz) E

PB1

ASYNC

SYNC

I/O B

RST B

CLK B

CARD B

C5

3

–

C2

9

PB0

R

IN

1

(IC3) PA0

PC0

DATA

V

CCB

28

1µF

0.1µF

21

PRES B

+

–

+

GND

15

V

MODA EXTAL XTAL

V

C

CPO

15

GND NC/NO

RL SS

1

28

18 20

22

26

27

11

14

9, 10

22

0.1µF

4.7µF

10M

1µF

8.000MHz

27pF

1955 TA02

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

LTC1755/LTC1756 ISO 7816-3 and EMV Compatible Smart Card Interface

V

= 3V/5V, V = 2.7V to 6V, SSOP-16/-24 Package

IN

OUT

LTC1555

SIM Power Supply and Level Translator Step-Up/Step-Down

Charge Pump

V

= 3V/5V, V = 2.7V to 10V, SSOP-16/-20 Package

IN

LTC1555L-1.8

SIM Power Supply and Level Translator Step-Up/Step-Down

Charge Pump

V = 1.8V/3V/5V, V = 2.6V to 6V, SSOP-16 Package

OUT IN

LTC4555

LTC4556

LTC4557

SIM Power Supply and Level Translator

V

OUT

V

OUT

V

OUT

= 1.8V/3V, V = 3V to 6V, 3mm × 3mm QFN Package

IN

= 1.8V/3V, V = 3V to 6V, 3mm × 3mm QFN Package

IN

= 1.8V/3V, V = 3V to 6V, 3mm × 3mm QFN Package

IN

1955fd

LT 0214 REV D • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

22

For more information www.linear.com/LTC1955

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC1955

●

 LINEAR TECHNOLOGY CORPORATION 2002


型号：	LTC1955IUH#TRPBF
厂家：	Linear
描述：	LTC1955 - Dual Smart Card Interface with Serial Control; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C
文件：	总22页 (文件大小：359K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1955IUH#TRPBF [Linear]

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